| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 6 | 0 | 6 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| read_csr_after_alert_issued | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 6 | 0 | 6 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| error_code | 1321412 | 1 | T1 | 1417 | T4 | 8463 | T11 | 7800 | ||||
| status | 177991 | 1 | T1 | 122 | T4 | 674 | T11 | 580 | ||||
| direct_access_rdata | 51146 | 1 | T1 | 63 | T4 | 302 | T11 | 269 | ||||
| secret_digests | 13080 | 1 | T1 | 30 | T4 | 36 | T11 | 24 | ||||
| hw_digests | 8720 | 1 | T1 | 20 | T4 | 24 | T11 | 16 | ||||
| unbuffered_digests | 21800 | 1 | T1 | 50 | T4 | 60 | T11 | 40 | 
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |