Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
94.92 93.81 96.20 95.74 91.89 97.10 96.34 93.35


Total test records in report: 1299
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html
T1262 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.1329638152 Aug 21 07:34:49 PM UTC 24 Aug 21 07:34:52 PM UTC 24 615141057 ps
T342 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1315770920 Aug 21 07:34:49 PM UTC 24 Aug 21 07:34:52 PM UTC 24 39185793 ps
T1263 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.2437426914 Aug 21 07:34:47 PM UTC 24 Aug 21 07:34:52 PM UTC 24 110440629 ps
T1264 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.207849791 Aug 21 07:34:49 PM UTC 24 Aug 21 07:34:52 PM UTC 24 141526301 ps
T1265 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.2133558095 Aug 21 07:34:48 PM UTC 24 Aug 21 07:34:52 PM UTC 24 148721220 ps
T1266 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1110596677 Aug 21 07:34:49 PM UTC 24 Aug 21 07:34:53 PM UTC 24 101871995 ps
T1267 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.2110465017 Aug 21 07:34:50 PM UTC 24 Aug 21 07:34:53 PM UTC 24 40319097 ps
T1268 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.247757378 Aug 21 07:34:50 PM UTC 24 Aug 21 07:34:53 PM UTC 24 136488540 ps
T1269 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.1097923324 Aug 21 07:34:50 PM UTC 24 Aug 21 07:34:53 PM UTC 24 45038881 ps
T1270 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.3124909067 Aug 21 07:34:51 PM UTC 24 Aug 21 07:34:53 PM UTC 24 42927091 ps
T1271 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.882338672 Aug 21 07:34:50 PM UTC 24 Aug 21 07:34:53 PM UTC 24 40138589 ps
T1272 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.2828007399 Aug 21 07:34:45 PM UTC 24 Aug 21 07:34:53 PM UTC 24 176731531 ps
T1273 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.613488770 Aug 21 07:34:50 PM UTC 24 Aug 21 07:34:53 PM UTC 24 38771329 ps
T1274 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.1054409879 Aug 21 07:34:51 PM UTC 24 Aug 21 07:34:53 PM UTC 24 540812557 ps
T1275 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.999418790 Aug 21 07:34:50 PM UTC 24 Aug 21 07:34:53 PM UTC 24 531390310 ps
T1276 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1987881671 Aug 21 07:34:49 PM UTC 24 Aug 21 07:34:53 PM UTC 24 980311787 ps
T1277 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.2486678843 Aug 21 07:34:50 PM UTC 24 Aug 21 07:34:54 PM UTC 24 578176297 ps
T306 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1781420997 Aug 21 07:34:42 PM UTC 24 Aug 21 07:34:54 PM UTC 24 1235967165 ps
T1278 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1422134337 Aug 21 07:34:48 PM UTC 24 Aug 21 07:34:54 PM UTC 24 88146435 ps
T1279 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.811884825 Aug 21 07:34:47 PM UTC 24 Aug 21 07:34:54 PM UTC 24 137692430 ps
T391 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2038257467 Aug 21 07:34:44 PM UTC 24 Aug 21 07:34:55 PM UTC 24 1368344021 ps
T1280 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.4141298913 Aug 21 07:34:52 PM UTC 24 Aug 21 07:34:55 PM UTC 24 40072672 ps
T1281 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.3964592384 Aug 21 07:34:52 PM UTC 24 Aug 21 07:34:55 PM UTC 24 38049091 ps
T1282 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.2462509271 Aug 21 07:34:52 PM UTC 24 Aug 21 07:34:55 PM UTC 24 584579044 ps
T1283 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.35860499 Aug 21 07:34:52 PM UTC 24 Aug 21 07:34:55 PM UTC 24 48088679 ps
T1284 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.2746357870 Aug 21 07:34:53 PM UTC 24 Aug 21 07:34:55 PM UTC 24 38728183 ps
T1285 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.1774074814 Aug 21 07:34:53 PM UTC 24 Aug 21 07:34:55 PM UTC 24 147910073 ps
T1286 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.298227229 Aug 21 07:34:53 PM UTC 24 Aug 21 07:34:56 PM UTC 24 83606766 ps
T1287 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.4090474842 Aug 21 07:34:53 PM UTC 24 Aug 21 07:34:56 PM UTC 24 39082312 ps
T1288 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.877166208 Aug 21 07:34:52 PM UTC 24 Aug 21 07:34:56 PM UTC 24 76116949 ps
T1289 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.2554649500 Aug 21 07:34:52 PM UTC 24 Aug 21 07:34:56 PM UTC 24 74778268 ps
T390 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.310537612 Aug 21 07:34:34 PM UTC 24 Aug 21 07:34:57 PM UTC 24 4750052642 ps
T388 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.3424870332 Aug 21 07:34:46 PM UTC 24 Aug 21 07:34:59 PM UTC 24 873630151 ps
T394 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.26638863 Aug 21 07:34:41 PM UTC 24 Aug 21 07:34:59 PM UTC 24 1226604975 ps
T395 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.378931664 Aug 21 07:34:25 PM UTC 24 Aug 21 07:35:00 PM UTC 24 19941143076 ps
T392 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.168824011 Aug 21 07:34:39 PM UTC 24 Aug 21 07:35:01 PM UTC 24 2117554836 ps
T385 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3346002572 Aug 21 07:34:43 PM UTC 24 Aug 21 07:35:04 PM UTC 24 5042511414 ps
T386 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1732964912 Aug 21 07:34:48 PM UTC 24 Aug 21 07:35:06 PM UTC 24 1309311998 ps
T393 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.180934288 Aug 21 07:34:48 PM UTC 24 Aug 21 07:35:07 PM UTC 24 1449748058 ps
T1290 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.763537497 Aug 21 07:34:54 PM UTC 24 Aug 21 07:35:07 PM UTC 24 69052325 ps
T1291 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.678387734 Aug 21 07:34:54 PM UTC 24 Aug 21 07:35:07 PM UTC 24 154791128 ps
T1292 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.81617655 Aug 21 07:34:54 PM UTC 24 Aug 21 07:35:07 PM UTC 24 39756152 ps
T1293 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.1948935891 Aug 21 07:34:54 PM UTC 24 Aug 21 07:35:07 PM UTC 24 41195037 ps
T1294 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.3844565580 Aug 21 07:34:54 PM UTC 24 Aug 21 07:35:07 PM UTC 24 101218716 ps
T1295 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.1099580514 Aug 21 07:34:54 PM UTC 24 Aug 21 07:35:07 PM UTC 24 149496722 ps
T1296 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.1660647065 Aug 21 07:34:53 PM UTC 24 Aug 21 07:35:07 PM UTC 24 514485392 ps
T1297 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.2637965481 Aug 21 07:34:54 PM UTC 24 Aug 21 07:35:07 PM UTC 24 147900508 ps
T1298 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.3870539099 Aug 21 07:34:54 PM UTC 24 Aug 21 07:35:07 PM UTC 24 91485078 ps
T1299 /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.2994344374 Aug 21 07:34:30 PM UTC 24 Aug 21 07:35:16 PM UTC 24 20228816322 ps

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_req.295965354
Short name T7
Test name
Test status
Simulation time 1457910841 ps
CPU time 13.85 seconds
Started Aug 21 07:35:42 PM UTC 24
Finished Aug 21 07:35:57 PM UTC 24
Peak memory 257656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=295965354 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.295965354
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_esc.3768288716
Short name T12
Test name
Test status
Simulation time 16433169945 ps
CPU time 37.62 seconds
Started Aug 21 07:35:08 PM UTC 24
Finished Aug 21 07:35:47 PM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3768288716 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.3768288716
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_test_access.2456163443
Short name T18
Test name
Test status
Simulation time 1469831459 ps
CPU time 14.96 seconds
Started Aug 21 07:34:57 PM UTC 24
Finished Aug 21 07:35:14 PM UTC 24
Peak memory 253340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2456163443 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.2456163443
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.1454609556
Short name T14
Test name
Test status
Simulation time 3603069124 ps
CPU time 60.74 seconds
Started Aug 21 07:35:39 PM UTC 24
Finished Aug 21 07:36:42 PM UTC 24
Peak memory 267956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1454609556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.1454609556
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_check_fail.551067875
Short name T55
Test name
Test status
Simulation time 2455434131 ps
CPU time 20.82 seconds
Started Aug 21 07:35:08 PM UTC 24
Finished Aug 21 07:35:31 PM UTC 24
Peak memory 253524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=551067875 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.551067875
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all.1074090487
Short name T152
Test name
Test status
Simulation time 13298005849 ps
CPU time 128.85 seconds
Started Aug 21 07:34:57 PM UTC 24
Finished Aug 21 07:37:09 PM UTC 24
Peak memory 255680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1074090487
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_str
ess_all.1074090487
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_macro_errs.631713667
Short name T168
Test name
Test status
Simulation time 3596710446 ps
CPU time 44.79 seconds
Started Aug 21 07:34:56 PM UTC 24
Finished Aug 21 07:35:52 PM UTC 24
Peak memory 267992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=631713667 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.631713667
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_init_fail.58995595
Short name T109
Test name
Test status
Simulation time 251244842 ps
CPU time 4.77 seconds
Started Aug 21 07:39:27 PM UTC 24
Finished Aug 21 07:39:33 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=58995595 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.58995595
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/30.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all.3796172486
Short name T140
Test name
Test status
Simulation time 6643984420 ps
CPU time 107.5 seconds
Started Aug 21 07:35:33 PM UTC 24
Finished Aug 21 07:37:23 PM UTC 24
Peak memory 259552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3796172486
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_str
ess_all.3796172486
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_sec_cm.3927148235
Short name T216
Test name
Test status
Simulation time 154627095201 ps
CPU time 264.2 seconds
Started Aug 21 07:35:07 PM UTC 24
Finished Aug 21 07:39:36 PM UTC 24
Peak memory 285272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3927148235 -ass
ert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.3927148235
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_key_req.59737091
Short name T120
Test name
Test status
Simulation time 1584478241 ps
CPU time 34.11 seconds
Started Aug 21 07:34:56 PM UTC 24
Finished Aug 21 07:35:41 PM UTC 24
Peak memory 253540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=59737091 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.59737091
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_req.3085490736
Short name T92
Test name
Test status
Simulation time 1315836344 ps
CPU time 12.66 seconds
Started Aug 21 07:34:56 PM UTC 24
Finished Aug 21 07:35:20 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3085490736 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_
req.3085490736
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_init_fail.2215673240
Short name T99
Test name
Test status
Simulation time 507812184 ps
CPU time 4.63 seconds
Started Aug 21 07:35:08 PM UTC 24
Finished Aug 21 07:35:14 PM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2215673240 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.2215673240
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_lock.3765807887
Short name T117
Test name
Test status
Simulation time 2872248775 ps
CPU time 21.31 seconds
Started Aug 21 07:34:59 PM UTC 24
Finished Aug 21 07:35:30 PM UTC 24
Peak memory 251640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3765807887 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.3765807887
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all.702216779
Short name T139
Test name
Test status
Simulation time 6131599742 ps
CPU time 81.76 seconds
Started Aug 21 07:35:49 PM UTC 24
Finished Aug 21 07:37:13 PM UTC 24
Peak memory 255424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=702216779 -
assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stre
ss_all.702216779
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_init_fail.3855291827
Short name T39
Test name
Test status
Simulation time 661670426 ps
CPU time 7.61 seconds
Started Aug 21 07:42:46 PM UTC 24
Finished Aug 21 07:42:55 PM UTC 24
Peak memory 251264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3855291827 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.3855291827
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/67.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.2396547483
Short name T298
Test name
Test status
Simulation time 1182770403 ps
CPU time 10.75 seconds
Started Aug 21 07:34:28 PM UTC 24
Finished Aug 21 07:34:40 PM UTC 24
Peak memory 252772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2396547
483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ct
rl_tl_intg_err.2396547483
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_req.1865434368
Short name T202
Test name
Test status
Simulation time 1017266793 ps
CPU time 24.45 seconds
Started Aug 21 07:35:33 PM UTC 24
Finished Aug 21 07:35:59 PM UTC 24
Peak memory 257620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1865434368 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_
req.1865434368
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.1635583862
Short name T163
Test name
Test status
Simulation time 3569659500 ps
CPU time 122.19 seconds
Started Aug 21 07:40:11 PM UTC 24
Finished Aug 21 07:42:16 PM UTC 24
Peak memory 267936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1635583862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.1635583862
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_init_fail.1825020869
Short name T82
Test name
Test status
Simulation time 580158448 ps
CPU time 7.52 seconds
Started Aug 21 07:35:15 PM UTC 24
Finished Aug 21 07:35:24 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1825020869 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.1825020869
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_macro_errs.3090028151
Short name T191
Test name
Test status
Simulation time 1827509378 ps
CPU time 15.43 seconds
Started Aug 21 07:37:00 PM UTC 24
Finished Aug 21 07:37:16 PM UTC 24
Peak memory 253720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3090028151 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.3090028151
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all.871125088
Short name T263
Test name
Test status
Simulation time 48051718175 ps
CPU time 112.76 seconds
Started Aug 21 07:35:13 PM UTC 24
Finished Aug 21 07:37:08 PM UTC 24
Peak memory 257476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=871125088 -
assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stre
ss_all.871125088
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_check_fail.3431613557
Short name T45
Test name
Test status
Simulation time 1316277559 ps
CPU time 22.75 seconds
Started Aug 21 07:37:53 PM UTC 24
Finished Aug 21 07:38:17 PM UTC 24
Peak memory 253720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3431613557 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.3431613557
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/20.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all.2183406729
Short name T829
Test name
Test status
Simulation time 15755531396 ps
CPU time 197.34 seconds
Started Aug 21 07:39:45 PM UTC 24
Finished Aug 21 07:43:06 PM UTC 24
Peak memory 267824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2183406729
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_st
ress_all.2183406729
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_init_fail.1991752994
Short name T934
Test name
Test status
Simulation time 316031386 ps
CPU time 4.05 seconds
Started Aug 21 07:44:24 PM UTC 24
Finished Aug 21 07:44:29 PM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1991752994 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.1991752994
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/127.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.3812313824
Short name T88
Test name
Test status
Simulation time 12153888835 ps
CPU time 160.37 seconds
Started Aug 21 07:35:19 PM UTC 24
Finished Aug 21 07:38:03 PM UTC 24
Peak memory 272228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3812313824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.3812313824
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_init_fail.3147714275
Short name T2
Test name
Test status
Simulation time 1783377213 ps
CPU time 3.25 seconds
Started Aug 21 07:34:57 PM UTC 24
Finished Aug 21 07:35:03 PM UTC 24
Peak memory 253528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3147714275 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.3147714275
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_alert_test.456389205
Short name T11
Test name
Test status
Simulation time 261843048 ps
CPU time 2.37 seconds
Started Aug 21 07:35:07 PM UTC 24
Finished Aug 21 07:35:10 PM UTC 24
Peak memory 250784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=456389205 -ass
ert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.456389205
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.2797756235
Short name T291
Test name
Test status
Simulation time 90261656348 ps
CPU time 353.94 seconds
Started Aug 21 07:36:26 PM UTC 24
Finished Aug 21 07:42:25 PM UTC 24
Peak memory 302712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2797756235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.2797756235
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_check_fail.500323335
Short name T74
Test name
Test status
Simulation time 771416734 ps
CPU time 27.26 seconds
Started Aug 21 07:36:24 PM UTC 24
Finished Aug 21 07:36:52 PM UTC 24
Peak memory 257528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=500323335 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.500323335
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_lock.3242936782
Short name T114
Test name
Test status
Simulation time 950693215 ps
CPU time 19.28 seconds
Started Aug 21 07:34:56 PM UTC 24
Finished Aug 21 07:35:26 PM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3242936782 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.3242936782
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.2712880695
Short name T302
Test name
Test status
Simulation time 98206375 ps
CPU time 4.32 seconds
Started Aug 21 07:34:22 PM UTC 24
Finished Aug 21 07:34:28 PM UTC 24
Peak memory 252816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2712880695
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_
csr_aliasing.2712880695
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.342749434
Short name T30
Test name
Test status
Simulation time 176174093 ps
CPU time 3.42 seconds
Started Aug 21 07:45:26 PM UTC 24
Finished Aug 21 07:45:32 PM UTC 24
Peak memory 250924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=342749434 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.342749434
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/227.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_macro_errs.3423895047
Short name T185
Test name
Test status
Simulation time 7273861602 ps
CPU time 49.73 seconds
Started Aug 21 07:35:17 PM UTC 24
Finished Aug 21 07:36:09 PM UTC 24
Peak memory 267968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3423895047 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.3423895047
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_init_fail.4038976038
Short name T198
Test name
Test status
Simulation time 190094219 ps
CPU time 3.93 seconds
Started Aug 21 07:44:24 PM UTC 24
Finished Aug 21 07:44:29 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4038976038 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.4038976038
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/130.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_check_fail.3641806901
Short name T59
Test name
Test status
Simulation time 2623234024 ps
CPU time 20.37 seconds
Started Aug 21 07:41:57 PM UTC 24
Finished Aug 21 07:42:18 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3641806901 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.3641806901
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/47.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_regwen.1141469063
Short name T130
Test name
Test status
Simulation time 404137116 ps
CPU time 9.22 seconds
Started Aug 21 07:35:04 PM UTC 24
Finished Aug 21 07:35:14 PM UTC 24
Peak memory 251232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1141469063 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.1141469063
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_init_fail.2176187983
Short name T188
Test name
Test status
Simulation time 1580156417 ps
CPU time 3.88 seconds
Started Aug 21 07:39:57 PM UTC 24
Finished Aug 21 07:40:02 PM UTC 24
Peak memory 251324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2176187983 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.2176187983
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/34.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_init_fail.1519595076
Short name T48
Test name
Test status
Simulation time 485994916 ps
CPU time 4.62 seconds
Started Aug 21 07:36:11 PM UTC 24
Finished Aug 21 07:36:17 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1519595076 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.1519595076
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all.1244977091
Short name T154
Test name
Test status
Simulation time 18110179645 ps
CPU time 239.12 seconds
Started Aug 21 07:35:07 PM UTC 24
Finished Aug 21 07:39:11 PM UTC 24
Peak memory 300596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1244977091
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_str
ess_all.1244977091
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_init_fail.3727219270
Short name T67
Test name
Test status
Simulation time 212077359 ps
CPU time 5.42 seconds
Started Aug 21 07:38:42 PM UTC 24
Finished Aug 21 07:38:48 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3727219270 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.3727219270
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/26.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_init_fail.3546164110
Short name T37
Test name
Test status
Simulation time 396979508 ps
CPU time 6.65 seconds
Started Aug 21 07:44:14 PM UTC 24
Finished Aug 21 07:44:22 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3546164110 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.3546164110
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/114.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_init_fail.662024659
Short name T80
Test name
Test status
Simulation time 291203955 ps
CPU time 4.83 seconds
Started Aug 21 07:44:55 PM UTC 24
Finished Aug 21 07:45:01 PM UTC 24
Peak memory 253268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=662024659 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.662024659
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/169.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all_with_rand_reset.2526472379
Short name T424
Test name
Test status
Simulation time 90062690333 ps
CPU time 227.92 seconds
Started Aug 21 07:41:32 PM UTC 24
Finished Aug 21 07:45:23 PM UTC 24
Peak memory 267864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2526472379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.2526472379
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.1791639181
Short name T20
Test name
Test status
Simulation time 10452018887 ps
CPU time 110.61 seconds
Started Aug 21 07:38:40 PM UTC 24
Finished Aug 21 07:40:32 PM UTC 24
Peak memory 267960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1791639181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.1791639181
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_key_req.807684808
Short name T261
Test name
Test status
Simulation time 1236143476 ps
CPU time 24.27 seconds
Started Aug 21 07:35:56 PM UTC 24
Finished Aug 21 07:36:21 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=807684808 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.807684808
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all.3932623766
Short name T166
Test name
Test status
Simulation time 14725701149 ps
CPU time 118.05 seconds
Started Aug 21 07:42:08 PM UTC 24
Finished Aug 21 07:44:08 PM UTC 24
Peak memory 257476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3932623766
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_st
ress_all.3932623766
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_init_fail.3902646458
Short name T792
Test name
Test status
Simulation time 1395020025 ps
CPU time 3.91 seconds
Started Aug 21 07:42:23 PM UTC 24
Finished Aug 21 07:42:28 PM UTC 24
Peak memory 253336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3902646458 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.3902646458
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/52.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_parallel_lc_esc.4121116383
Short name T151
Test name
Test status
Simulation time 11888843391 ps
CPU time 30.85 seconds
Started Aug 21 07:44:31 PM UTC 24
Finished Aug 21 07:45:04 PM UTC 24
Peak memory 251308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4121116383 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.4121116383
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/138.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all.3890036188
Short name T157
Test name
Test status
Simulation time 9114273214 ps
CPU time 187.41 seconds
Started Aug 21 07:35:21 PM UTC 24
Finished Aug 21 07:38:31 PM UTC 24
Peak memory 269812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3890036188
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_str
ess_all.3890036188
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.4212195556
Short name T300
Test name
Test status
Simulation time 2576934133 ps
CPU time 18.88 seconds
Started Aug 21 07:34:21 PM UTC 24
Finished Aug 21 07:34:41 PM UTC 24
Peak memory 256940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4212195
556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ct
rl_tl_intg_err.4212195556
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_background_chks.2681403145
Short name T141
Test name
Test status
Simulation time 633777186 ps
CPU time 21.68 seconds
Started Aug 21 07:35:08 PM UTC 24
Finished Aug 21 07:35:31 PM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2681403145 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.2681403145
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_background_chks/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_esc.3821986948
Short name T136
Test name
Test status
Simulation time 185210256 ps
CPU time 4.32 seconds
Started Aug 21 07:41:47 PM UTC 24
Finished Aug 21 07:41:52 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3821986948 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.3821986948
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_check_fail.2026574237
Short name T31
Test name
Test status
Simulation time 1211926738 ps
CPU time 25.53 seconds
Started Aug 21 07:36:14 PM UTC 24
Finished Aug 21 07:36:41 PM UTC 24
Peak memory 253400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2026574237 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.2026574237
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_errs.2652918508
Short name T8
Test name
Test status
Simulation time 10161645388 ps
CPU time 21.47 seconds
Started Aug 21 07:34:56 PM UTC 24
Finished Aug 21 07:35:28 PM UTC 24
Peak memory 251324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2652918508 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.2652918508
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.764637296
Short name T1097
Test name
Test status
Simulation time 348271123 ps
CPU time 3.05 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:32 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=764637296 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.764637296
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/236.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.1556272860
Short name T283
Test name
Test status
Simulation time 4816850468 ps
CPU time 44.21 seconds
Started Aug 21 07:42:52 PM UTC 24
Finished Aug 21 07:43:38 PM UTC 24
Peak memory 267844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1556272860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.1556272860
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/70.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.3873050300
Short name T289
Test name
Test status
Simulation time 39489579325 ps
CPU time 87.45 seconds
Started Aug 21 07:42:50 PM UTC 24
Finished Aug 21 07:44:20 PM UTC 24
Peak memory 272056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3873050300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.3873050300
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/69.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.180934288
Short name T393
Test name
Test status
Simulation time 1449748058 ps
CPU time 17.53 seconds
Started Aug 21 07:34:48 PM UTC 24
Finished Aug 21 07:35:07 PM UTC 24
Peak memory 252776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1809342
88 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ct
rl_tl_intg_err.180934288
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/19.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_regwen.3191471740
Short name T272
Test name
Test status
Simulation time 483962965 ps
CPU time 6.54 seconds
Started Aug 21 07:37:58 PM UTC 24
Finished Aug 21 07:38:06 PM UTC 24
Peak memory 257436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3191471740 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.3191471740
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/20.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_check_fail.1131984882
Short name T47
Test name
Test status
Simulation time 22600609419 ps
CPU time 52.52 seconds
Started Aug 21 07:42:16 PM UTC 24
Finished Aug 21 07:43:10 PM UTC 24
Peak memory 257812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1131984882 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.1131984882
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/49.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_test_access.2227055827
Short name T145
Test name
Test status
Simulation time 757722987 ps
CPU time 14.12 seconds
Started Aug 21 07:35:19 PM UTC 24
Finished Aug 21 07:35:35 PM UTC 24
Peak memory 253428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2227055827 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.2227055827
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_background_chks.2349491014
Short name T105
Test name
Test status
Simulation time 489829769 ps
CPU time 5.23 seconds
Started Aug 21 07:35:42 PM UTC 24
Finished Aug 21 07:35:48 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2349491014 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.2349491014
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_background_chks/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_parallel_lc_esc.880293834
Short name T350
Test name
Test status
Simulation time 476128202 ps
CPU time 9.86 seconds
Started Aug 21 07:44:04 PM UTC 24
Finished Aug 21 07:44:15 PM UTC 24
Peak memory 251440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=880293834 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.880293834
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/105.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_parallel_lc_esc.1425319119
Short name T134
Test name
Test status
Simulation time 415691930 ps
CPU time 3.2 seconds
Started Aug 21 07:44:15 PM UTC 24
Finished Aug 21 07:44:19 PM UTC 24
Peak memory 253228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1425319119 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.1425319119
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/117.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_parallel_lc_esc.823402842
Short name T144
Test name
Test status
Simulation time 670472436 ps
CPU time 9.29 seconds
Started Aug 21 07:44:28 PM UTC 24
Finished Aug 21 07:44:38 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=823402842 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.823402842
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/134.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_parallel_lc_esc.3934471880
Short name T164
Test name
Test status
Simulation time 382297124 ps
CPU time 9.63 seconds
Started Aug 21 07:44:48 PM UTC 24
Finished Aug 21 07:44:59 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3934471880 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.3934471880
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/155.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_parallel_lc_esc.606791975
Short name T150
Test name
Test status
Simulation time 176239248 ps
CPU time 6.77 seconds
Started Aug 21 07:42:35 PM UTC 24
Finished Aug 21 07:42:43 PM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=606791975 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.606791975
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/57.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all.187606197
Short name T287
Test name
Test status
Simulation time 10013627646 ps
CPU time 84.43 seconds
Started Aug 21 07:36:27 PM UTC 24
Finished Aug 21 07:37:54 PM UTC 24
Peak memory 257472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=187606197 -
assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_str
ess_all.187606197
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_regwen.3913073010
Short name T112
Test name
Test status
Simulation time 309382971 ps
CPU time 5.6 seconds
Started Aug 21 07:35:18 PM UTC 24
Finished Aug 21 07:35:25 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3913073010 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.3913073010
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.4001639455
Short name T282
Test name
Test status
Simulation time 4988505345 ps
CPU time 52.49 seconds
Started Aug 21 07:38:03 PM UTC 24
Finished Aug 21 07:38:57 PM UTC 24
Peak memory 257656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4001639455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.4001639455
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1458243676
Short name T329
Test name
Test status
Simulation time 139081426 ps
CPU time 2.17 seconds
Started Aug 21 07:34:24 PM UTC 24
Finished Aug 21 07:34:27 PM UTC 24
Peak memory 252700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1458243676 -asse
rt nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.1458243676
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.419096545
Short name T330
Test name
Test status
Simulation time 264280438 ps
CPU time 2.41 seconds
Started Aug 21 07:34:24 PM UTC 24
Finished Aug 21 07:34:27 PM UTC 24
Peak memory 252760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=419096545
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_c
sr_hw_reset.419096545
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_test_access.1769481804
Short name T232
Test name
Test status
Simulation time 1489234480 ps
CPU time 15.5 seconds
Started Aug 21 07:35:29 PM UTC 24
Finished Aug 21 07:35:46 PM UTC 24
Peak memory 257264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1769481804 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.1769481804
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.423030302
Short name T1171
Test name
Test status
Simulation time 19110415936 ps
CPU time 238.84 seconds
Started Aug 21 07:42:53 PM UTC 24
Finished Aug 21 07:46:55 PM UTC 24
Peak memory 270300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=423030302 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.423030302
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/72.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_key_req.121231015
Short name T253
Test name
Test status
Simulation time 354269516 ps
CPU time 8.36 seconds
Started Aug 21 07:36:17 PM UTC 24
Finished Aug 21 07:36:27 PM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=121231015 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.121231015
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_regwen.4195015008
Short name T714
Test name
Test status
Simulation time 314691405 ps
CPU time 7.71 seconds
Started Aug 21 07:42:06 PM UTC 24
Finished Aug 21 07:42:15 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4195015008 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.4195015008
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/48.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.1442263925
Short name T474
Test name
Test status
Simulation time 7936288480 ps
CPU time 91.46 seconds
Started Aug 21 07:43:16 PM UTC 24
Finished Aug 21 07:44:49 PM UTC 24
Peak memory 267800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1442263925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.1442263925
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.1442989172
Short name T278
Test name
Test status
Simulation time 1701805785 ps
CPU time 48.26 seconds
Started Aug 21 07:42:19 PM UTC 24
Finished Aug 21 07:43:09 PM UTC 24
Peak memory 257652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1442989172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.1442989172
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_check_fail.422137933
Short name T86
Test name
Test status
Simulation time 3546985941 ps
CPU time 30.44 seconds
Started Aug 21 07:38:37 PM UTC 24
Finished Aug 21 07:39:08 PM UTC 24
Peak memory 257560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=422137933 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.422137933
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/25.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_check_fail.2854684105
Short name T35
Test name
Test status
Simulation time 10971776207 ps
CPU time 36.44 seconds
Started Aug 21 07:41:53 PM UTC 24
Finished Aug 21 07:42:31 PM UTC 24
Peak memory 253592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2854684105 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.2854684105
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/46.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_init_fail.679973338
Short name T26
Test name
Test status
Simulation time 248868691 ps
CPU time 4.08 seconds
Started Aug 21 07:43:40 PM UTC 24
Finished Aug 21 07:43:45 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=679973338 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.679973338
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/93.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all.644267261
Short name T635
Test name
Test status
Simulation time 19615404248 ps
CPU time 92.13 seconds
Started Aug 21 07:38:40 PM UTC 24
Finished Aug 21 07:40:14 PM UTC 24
Peak memory 257472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=644267261 -
assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_str
ess_all.644267261
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_init_fail.1955037885
Short name T293
Test name
Test status
Simulation time 146862350 ps
CPU time 3.4 seconds
Started Aug 21 07:44:48 PM UTC 24
Finished Aug 21 07:44:53 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1955037885 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.1955037885
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/157.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_init_fail.3001458825
Short name T132
Test name
Test status
Simulation time 185095514 ps
CPU time 3.91 seconds
Started Aug 21 07:36:20 PM UTC 24
Finished Aug 21 07:36:25 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3001458825 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.3001458825
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_init_fail.1217284419
Short name T27
Test name
Test status
Simulation time 178329729 ps
CPU time 3.65 seconds
Started Aug 21 07:44:15 PM UTC 24
Finished Aug 21 07:44:19 PM UTC 24
Peak memory 251396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1217284419 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.1217284419
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/117.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_init_fail.974226822
Short name T182
Test name
Test status
Simulation time 484118554 ps
CPU time 5.83 seconds
Started Aug 21 07:37:07 PM UTC 24
Finished Aug 21 07:37:14 PM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=974226822 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.974226822
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/15.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all.1795470762
Short name T418
Test name
Test status
Simulation time 26913789738 ps
CPU time 140.42 seconds
Started Aug 21 07:37:59 PM UTC 24
Finished Aug 21 07:40:22 PM UTC 24
Peak memory 257476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1795470762
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_st
ress_all.1795470762
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.26638863
Short name T394
Test name
Test status
Simulation time 1226604975 ps
CPU time 16.86 seconds
Started Aug 21 07:34:41 PM UTC 24
Finished Aug 21 07:34:59 PM UTC 24
Peak memory 257036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2663886
3 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctr
l_tl_intg_err.26638863
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3346002572
Short name T385
Test name
Test status
Simulation time 5042511414 ps
CPU time 18.98 seconds
Started Aug 21 07:34:43 PM UTC 24
Finished Aug 21 07:35:04 PM UTC 24
Peak memory 256988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3346002
572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_c
trl_tl_intg_err.3346002572
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all.4131358063
Short name T374
Test name
Test status
Simulation time 27269287816 ps
CPU time 91.63 seconds
Started Aug 21 07:36:07 PM UTC 24
Finished Aug 21 07:37:41 PM UTC 24
Peak memory 257472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4131358063
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_str
ess_all.4131358063
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_init_fail.810087608
Short name T40
Test name
Test status
Simulation time 125520702 ps
CPU time 3.84 seconds
Started Aug 21 07:44:06 PM UTC 24
Finished Aug 21 07:44:11 PM UTC 24
Peak memory 251440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=810087608 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.810087608
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/112.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_smoke.1230807239
Short name T176
Test name
Test status
Simulation time 629541915 ps
CPU time 14 seconds
Started Aug 21 07:35:13 PM UTC 24
Finished Aug 21 07:35:28 PM UTC 24
Peak memory 251456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1230807239 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.1230807239
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_wake_up.3562598817
Short name T5
Test name
Test status
Simulation time 780435436 ps
CPU time 2.12 seconds
Started Aug 21 07:34:54 PM UTC 24
Finished Aug 21 07:35:08 PM UTC 24
Peak memory 251128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3562598817 -assert nopostproc
+UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/ope
ntitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.3562598817
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_wake_up/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all.830245330
Short name T277
Test name
Test status
Simulation time 22089984197 ps
CPU time 188.23 seconds
Started Aug 21 07:40:46 PM UTC 24
Finished Aug 21 07:43:58 PM UTC 24
Peak memory 257728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=830245330 -
assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_str
ess_all.830245330
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all.1348809473
Short name T481
Test name
Test status
Simulation time 7059891124 ps
CPU time 23.22 seconds
Started Aug 21 07:35:39 PM UTC 24
Finished Aug 21 07:36:04 PM UTC 24
Peak memory 251332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1348809473
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_str
ess_all.1348809473
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.1781420997
Short name T306
Test name
Test status
Simulation time 1235967165 ps
CPU time 10.7 seconds
Started Aug 21 07:34:42 PM UTC 24
Finished Aug 21 07:34:54 PM UTC 24
Peak memory 256852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1781420
997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_c
trl_tl_intg_err.1781420997
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_errs.1222840131
Short name T147
Test name
Test status
Simulation time 4095610019 ps
CPU time 22.46 seconds
Started Aug 21 07:37:07 PM UTC 24
Finished Aug 21 07:37:31 PM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1222840131 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.1222840131
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/15.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_init_fail.1318073979
Short name T72
Test name
Test status
Simulation time 198379047 ps
CPU time 3.44 seconds
Started Aug 21 07:43:06 PM UTC 24
Finished Aug 21 07:43:11 PM UTC 24
Peak memory 251608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1318073979 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.1318073979
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/78.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_lock.966962906
Short name T295
Test name
Test status
Simulation time 455596937 ps
CPU time 8.41 seconds
Started Aug 21 07:36:40 PM UTC 24
Finished Aug 21 07:36:50 PM UTC 24
Peak memory 253720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=966962906 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.966962906
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all_with_rand_reset.696927099
Short name T313
Test name
Test status
Simulation time 18225447905 ps
CPU time 64.46 seconds
Started Aug 21 07:37:59 PM UTC 24
Finished Aug 21 07:39:05 PM UTC 24
Peak memory 257604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=696927099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.696927099
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_init_fail.3515703815
Short name T110
Test name
Test status
Simulation time 185525150 ps
CPU time 4.05 seconds
Started Aug 21 07:44:36 PM UTC 24
Finished Aug 21 07:44:42 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3515703815 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.3515703815
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/146.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_init_fail.4077802198
Short name T987
Test name
Test status
Simulation time 118786524 ps
CPU time 3.59 seconds
Started Aug 21 07:44:55 PM UTC 24
Finished Aug 21 07:45:00 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4077802198 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.4077802198
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/168.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_regwen.1405970009
Short name T93
Test name
Test status
Simulation time 511979257 ps
CPU time 6.86 seconds
Started Aug 21 07:34:56 PM UTC 24
Finished Aug 21 07:35:14 PM UTC 24
Peak memory 251240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1405970009 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.1405970009
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_key_req.2381132840
Short name T355
Test name
Test status
Simulation time 917504097 ps
CPU time 12.36 seconds
Started Aug 21 07:36:34 PM UTC 24
Finished Aug 21 07:36:47 PM UTC 24
Peak memory 251308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2381132840 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.2381132840
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all.665558465
Short name T378
Test name
Test status
Simulation time 7288428884 ps
CPU time 106.06 seconds
Started Aug 21 07:37:49 PM UTC 24
Finished Aug 21 07:39:37 PM UTC 24
Peak memory 267708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=665558465 -
assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_str
ess_all.665558465
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.3667986844
Short name T1068
Test name
Test status
Simulation time 476448827 ps
CPU time 5.91 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:20 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3667986844 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.3667986844
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/192.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_test_access.1113599705
Short name T409
Test name
Test status
Simulation time 1181132623 ps
CPU time 19.18 seconds
Started Aug 21 07:36:45 PM UTC 24
Finished Aug 21 07:37:05 PM UTC 24
Peak memory 257784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1113599705 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.1113599705
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2040605228
Short name T348
Test name
Test status
Simulation time 265871072 ps
CPU time 5.61 seconds
Started Aug 21 07:34:22 PM UTC 24
Finished Aug 21 07:34:29 PM UTC 24
Peak memory 252720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2040605228
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_
csr_bit_bash.2040605228
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.2946897185
Short name T304
Test name
Test status
Simulation time 389878292 ps
CPU time 3.44 seconds
Started Aug 21 07:34:22 PM UTC 24
Finished Aug 21 07:34:27 PM UTC 24
Peak memory 254796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2946897185
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_
csr_hw_reset.2946897185
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.894891805
Short name T308
Test name
Test status
Simulation time 129531172 ps
CPU time 2.43 seconds
Started Aug 21 07:34:22 PM UTC 24
Finished Aug 21 07:34:26 PM UTC 24
Peak memory 256960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=894891805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.894891805
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2286209107
Short name T307
Test name
Test status
Simulation time 80119202 ps
CPU time 2.07 seconds
Started Aug 21 07:34:22 PM UTC 24
Finished Aug 21 07:34:25 PM UTC 24
Peak memory 252784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2286209107 -asse
rt nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.2286209107
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.1251723035
Short name T1173
Test name
Test status
Simulation time 77265051 ps
CPU time 1.76 seconds
Started Aug 21 07:34:21 PM UTC 24
Finished Aug 21 07:34:24 PM UTC 24
Peak memory 242148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1251723035 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.1251723035
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.3883640413
Short name T1175
Test name
Test status
Simulation time 68970351 ps
CPU time 1.83 seconds
Started Aug 21 07:34:22 PM UTC 24
Finished Aug 21 07:34:25 PM UTC 24
Peak memory 240544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=
3883640413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.otp_ctrl_mem_partial_access.3883640413
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_mem_partial_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3060933874
Short name T1174
Test name
Test status
Simulation time 131745259 ps
CPU time 1.91 seconds
Started Aug 21 07:34:22 PM UTC 24
Finished Aug 21 07:34:25 PM UTC 24
Peak memory 240332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3060933874
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_
mem_walk.3060933874
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_mem_walk/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.2104953860
Short name T301
Test name
Test status
Simulation time 180167334 ps
CPU time 3.08 seconds
Started Aug 21 07:34:22 PM UTC 24
Finished Aug 21 07:34:26 PM UTC 24
Peak memory 252652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=2104953860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.otp_ctrl_same_csr_outstanding.2104953860
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.3128797653
Short name T1176
Test name
Test status
Simulation time 180867784 ps
CPU time 4.25 seconds
Started Aug 21 07:34:21 PM UTC 24
Finished Aug 21 07:34:26 PM UTC 24
Peak memory 258968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3128797653 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.3128797653
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.3549123867
Short name T1191
Test name
Test status
Simulation time 1816229228 ps
CPU time 6.14 seconds
Started Aug 21 07:34:25 PM UTC 24
Finished Aug 21 07:34:32 PM UTC 24
Peak memory 252864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3549123867
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_
csr_aliasing.3549123867
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.3037857264
Short name T331
Test name
Test status
Simulation time 143773443 ps
CPU time 3.58 seconds
Started Aug 21 07:34:24 PM UTC 24
Finished Aug 21 07:34:29 PM UTC 24
Peak memory 252716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3037857264
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_
csr_bit_bash.3037857264
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1058931275
Short name T406
Test name
Test status
Simulation time 380950640 ps
CPU time 3.35 seconds
Started Aug 21 07:34:25 PM UTC 24
Finished Aug 21 07:34:30 PM UTC 24
Peak memory 258964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1058931275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.1058931275
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.574303919
Short name T1177
Test name
Test status
Simulation time 56294278 ps
CPU time 1.84 seconds
Started Aug 21 07:34:24 PM UTC 24
Finished Aug 21 07:34:27 PM UTC 24
Peak memory 241700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=574303919 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.574303919
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.2001749889
Short name T1180
Test name
Test status
Simulation time 517905765 ps
CPU time 2.5 seconds
Started Aug 21 07:34:24 PM UTC 24
Finished Aug 21 07:34:27 PM UTC 24
Peak memory 241508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=
2001749889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.otp_ctrl_mem_partial_access.2001749889
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_mem_partial_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2651820105
Short name T1179
Test name
Test status
Simulation time 45853783 ps
CPU time 2.16 seconds
Started Aug 21 07:34:24 PM UTC 24
Finished Aug 21 07:34:27 PM UTC 24
Peak memory 241532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2651820105
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_
mem_walk.2651820105
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_mem_walk/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2012968168
Short name T303
Test name
Test status
Simulation time 63819470 ps
CPU time 3.15 seconds
Started Aug 21 07:34:25 PM UTC 24
Finished Aug 21 07:34:29 PM UTC 24
Peak memory 254764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=2012968168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.otp_ctrl_same_csr_outstanding.2012968168
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.2000813924
Short name T1184
Test name
Test status
Simulation time 137968944 ps
CPU time 5.97 seconds
Started Aug 21 07:34:24 PM UTC 24
Finished Aug 21 07:34:31 PM UTC 24
Peak memory 258912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2000813924 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.2000813924
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.3290213366
Short name T299
Test name
Test status
Simulation time 9834907353 ps
CPU time 13.81 seconds
Started Aug 21 07:34:24 PM UTC 24
Finished Aug 21 07:34:39 PM UTC 24
Peak memory 256936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3290213
366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ct
rl_tl_intg_err.3290213366
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3072516266
Short name T1230
Test name
Test status
Simulation time 267108323 ps
CPU time 3.55 seconds
Started Aug 21 07:34:39 PM UTC 24
Finished Aug 21 07:34:44 PM UTC 24
Peak memory 258948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=3072516266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_mem_rw_with_rand_reset.3072516266
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.857382815
Short name T1223
Test name
Test status
Simulation time 44564861 ps
CPU time 2 seconds
Started Aug 21 07:34:39 PM UTC 24
Finished Aug 21 07:34:42 PM UTC 24
Peak memory 251884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=857382815 -asser
t nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.857382815
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.3656650435
Short name T1220
Test name
Test status
Simulation time 43918140 ps
CPU time 1.76 seconds
Started Aug 21 07:34:39 PM UTC 24
Finished Aug 21 07:34:42 PM UTC 24
Peak memory 241084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3656650435 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.3656650435
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.1525046586
Short name T1224
Test name
Test status
Simulation time 127652786 ps
CPU time 2.34 seconds
Started Aug 21 07:34:39 PM UTC 24
Finished Aug 21 07:34:43 PM UTC 24
Peak memory 252764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=1525046586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
10.otp_ctrl_same_csr_outstanding.1525046586
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.866417808
Short name T1237
Test name
Test status
Simulation time 152946881 ps
CPU time 6.76 seconds
Started Aug 21 07:34:38 PM UTC 24
Finished Aug 21 07:34:46 PM UTC 24
Peak memory 259016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=866417808 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.866417808
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.3266242914
Short name T397
Test name
Test status
Simulation time 10164130874 ps
CPU time 11.37 seconds
Started Aug 21 07:34:38 PM UTC 24
Finished Aug 21 07:34:51 PM UTC 24
Peak memory 256932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3266242
914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_c
trl_tl_intg_err.3266242914
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3333647991
Short name T1231
Test name
Test status
Simulation time 72498147 ps
CPU time 2.39 seconds
Started Aug 21 07:34:41 PM UTC 24
Finished Aug 21 07:34:44 PM UTC 24
Peak memory 256920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=3333647991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_mem_rw_with_rand_reset.3333647991
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.234300003
Short name T340
Test name
Test status
Simulation time 143837569 ps
CPU time 1.76 seconds
Started Aug 21 07:34:40 PM UTC 24
Finished Aug 21 07:34:42 PM UTC 24
Peak memory 252032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=234300003 -asser
t nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.234300003
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.3037136848
Short name T1219
Test name
Test status
Simulation time 143870111 ps
CPU time 1.39 seconds
Started Aug 21 07:34:40 PM UTC 24
Finished Aug 21 07:34:42 PM UTC 24
Peak memory 241032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3037136848 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.3037136848
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2827949533
Short name T1225
Test name
Test status
Simulation time 270138327 ps
CPU time 2.24 seconds
Started Aug 21 07:34:40 PM UTC 24
Finished Aug 21 07:34:43 PM UTC 24
Peak memory 252756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=2827949533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
11.otp_ctrl_same_csr_outstanding.2827949533
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.3323277935
Short name T1228
Test name
Test status
Simulation time 789075855 ps
CPU time 3.43 seconds
Started Aug 21 07:34:39 PM UTC 24
Finished Aug 21 07:34:44 PM UTC 24
Peak memory 259008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3323277935 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.3323277935
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.168824011
Short name T392
Test name
Test status
Simulation time 2117554836 ps
CPU time 19.94 seconds
Started Aug 21 07:34:39 PM UTC 24
Finished Aug 21 07:35:01 PM UTC 24
Peak memory 256932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1688240
11 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ct
rl_tl_intg_err.168824011
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.3808319262
Short name T1232
Test name
Test status
Simulation time 75725715 ps
CPU time 2.38 seconds
Started Aug 21 07:34:41 PM UTC 24
Finished Aug 21 07:34:44 PM UTC 24
Peak memory 256828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=3808319262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_mem_rw_with_rand_reset.3808319262
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.461748177
Short name T1226
Test name
Test status
Simulation time 61587803 ps
CPU time 1.59 seconds
Started Aug 21 07:34:41 PM UTC 24
Finished Aug 21 07:34:43 PM UTC 24
Peak memory 251884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=461748177 -asser
t nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.461748177
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.762205449
Short name T1227
Test name
Test status
Simulation time 73583433 ps
CPU time 1.8 seconds
Started Aug 21 07:34:41 PM UTC 24
Finished Aug 21 07:34:44 PM UTC 24
Peak memory 240780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=762205449 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.762205449
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.1133102815
Short name T1229
Test name
Test status
Simulation time 44279366 ps
CPU time 1.98 seconds
Started Aug 21 07:34:41 PM UTC 24
Finished Aug 21 07:34:44 PM UTC 24
Peak memory 251952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=1133102815 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
12.otp_ctrl_same_csr_outstanding.1133102815
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3604076821
Short name T1243
Test name
Test status
Simulation time 532742032 ps
CPU time 5.36 seconds
Started Aug 21 07:34:41 PM UTC 24
Finished Aug 21 07:34:47 PM UTC 24
Peak memory 259080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3604076821 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.3604076821
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.3548279547
Short name T1238
Test name
Test status
Simulation time 70320282 ps
CPU time 3.02 seconds
Started Aug 21 07:34:42 PM UTC 24
Finished Aug 21 07:34:46 PM UTC 24
Peak memory 259104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=3548279547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_mem_rw_with_rand_reset.3548279547
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.3893322676
Short name T1233
Test name
Test status
Simulation time 76591489 ps
CPU time 1.85 seconds
Started Aug 21 07:34:42 PM UTC 24
Finished Aug 21 07:34:45 PM UTC 24
Peak memory 251868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3893322676 -asse
rt nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.3893322676
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.3305125151
Short name T1234
Test name
Test status
Simulation time 525125385 ps
CPU time 1.96 seconds
Started Aug 21 07:34:42 PM UTC 24
Finished Aug 21 07:34:45 PM UTC 24
Peak memory 241196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3305125151 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.3305125151
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.246767479
Short name T1235
Test name
Test status
Simulation time 45325033 ps
CPU time 2.26 seconds
Started Aug 21 07:34:42 PM UTC 24
Finished Aug 21 07:34:45 PM UTC 24
Peak memory 252684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=246767479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
13.otp_ctrl_same_csr_outstanding.246767479
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.3312851594
Short name T1253
Test name
Test status
Simulation time 600784539 ps
CPU time 7.35 seconds
Started Aug 21 07:34:41 PM UTC 24
Finished Aug 21 07:34:49 PM UTC 24
Peak memory 259036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3312851594 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.3312851594
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.4254882846
Short name T1240
Test name
Test status
Simulation time 1062199450 ps
CPU time 2.26 seconds
Started Aug 21 07:34:44 PM UTC 24
Finished Aug 21 07:34:47 PM UTC 24
Peak memory 256836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=4254882846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_mem_rw_with_rand_reset.4254882846
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.2457397931
Short name T341
Test name
Test status
Simulation time 593464361 ps
CPU time 2.18 seconds
Started Aug 21 07:34:43 PM UTC 24
Finished Aug 21 07:34:47 PM UTC 24
Peak memory 252808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2457397931 -asse
rt nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.2457397931
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.2700480630
Short name T1239
Test name
Test status
Simulation time 586800492 ps
CPU time 2.38 seconds
Started Aug 21 07:34:43 PM UTC 24
Finished Aug 21 07:34:47 PM UTC 24
Peak memory 241772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2700480630 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.2700480630
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1565661768
Short name T1244
Test name
Test status
Simulation time 75204299 ps
CPU time 2.65 seconds
Started Aug 21 07:34:43 PM UTC 24
Finished Aug 21 07:34:47 PM UTC 24
Peak memory 254860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=1565661768 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
14.otp_ctrl_same_csr_outstanding.1565661768
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.1896631231
Short name T1241
Test name
Test status
Simulation time 867911057 ps
CPU time 3.83 seconds
Started Aug 21 07:34:42 PM UTC 24
Finished Aug 21 07:34:47 PM UTC 24
Peak memory 259016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1896631231 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.1896631231
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.868845395
Short name T1256
Test name
Test status
Simulation time 391633206 ps
CPU time 4.17 seconds
Started Aug 21 07:34:45 PM UTC 24
Finished Aug 21 07:34:50 PM UTC 24
Peak memory 258932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=868845395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_mem_rw_with_rand_reset.868845395
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3372720248
Short name T1248
Test name
Test status
Simulation time 523450731 ps
CPU time 2.5 seconds
Started Aug 21 07:34:45 PM UTC 24
Finished Aug 21 07:34:48 PM UTC 24
Peak memory 252764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3372720248 -asse
rt nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.3372720248
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/15.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.317698790
Short name T1242
Test name
Test status
Simulation time 148425507 ps
CPU time 2.36 seconds
Started Aug 21 07:34:44 PM UTC 24
Finished Aug 21 07:34:47 PM UTC 24
Peak memory 241940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=317698790 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.317698790
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/15.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.366539876
Short name T1245
Test name
Test status
Simulation time 164836728 ps
CPU time 2.12 seconds
Started Aug 21 07:34:45 PM UTC 24
Finished Aug 21 07:34:48 PM UTC 24
Peak memory 252772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=366539876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
15.otp_ctrl_same_csr_outstanding.366539876
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/15.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.484737288
Short name T1251
Test name
Test status
Simulation time 919955227 ps
CPU time 4.3 seconds
Started Aug 21 07:34:44 PM UTC 24
Finished Aug 21 07:34:49 PM UTC 24
Peak memory 259004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=484737288 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.484737288
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/15.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.2038257467
Short name T391
Test name
Test status
Simulation time 1368344021 ps
CPU time 10.12 seconds
Started Aug 21 07:34:44 PM UTC 24
Finished Aug 21 07:34:55 PM UTC 24
Peak memory 256864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2038257
467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_c
trl_tl_intg_err.2038257467
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/15.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.2414527887
Short name T1252
Test name
Test status
Simulation time 275188881 ps
CPU time 2.84 seconds
Started Aug 21 07:34:45 PM UTC 24
Finished Aug 21 07:34:49 PM UTC 24
Peak memory 259140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2414527887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_mem_rw_with_rand_reset.2414527887
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.303654089
Short name T1246
Test name
Test status
Simulation time 50409385 ps
CPU time 2.25 seconds
Started Aug 21 07:34:45 PM UTC 24
Finished Aug 21 07:34:48 PM UTC 24
Peak memory 254692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=303654089 -asser
t nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.303654089
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.3484098880
Short name T1247
Test name
Test status
Simulation time 147104694 ps
CPU time 2.31 seconds
Started Aug 21 07:34:45 PM UTC 24
Finished Aug 21 07:34:48 PM UTC 24
Peak memory 242400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3484098880 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.3484098880
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.1202626213
Short name T1249
Test name
Test status
Simulation time 62903465 ps
CPU time 2.59 seconds
Started Aug 21 07:34:45 PM UTC 24
Finished Aug 21 07:34:49 PM UTC 24
Peak memory 252552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=1202626213 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.otp_ctrl_same_csr_outstanding.1202626213
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.2828007399
Short name T1272
Test name
Test status
Simulation time 176731531 ps
CPU time 7.08 seconds
Started Aug 21 07:34:45 PM UTC 24
Finished Aug 21 07:34:53 PM UTC 24
Peak memory 252812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2828007399 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.2828007399
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.1836010000
Short name T389
Test name
Test status
Simulation time 2613669213 ps
CPU time 9.92 seconds
Started Aug 21 07:34:45 PM UTC 24
Finished Aug 21 07:34:56 PM UTC 24
Peak memory 252780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1836010
000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_c
trl_tl_intg_err.1836010000
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.2437426914
Short name T1263
Test name
Test status
Simulation time 110440629 ps
CPU time 3.19 seconds
Started Aug 21 07:34:47 PM UTC 24
Finished Aug 21 07:34:52 PM UTC 24
Peak memory 258936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2437426914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_mem_rw_with_rand_reset.2437426914
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.4285343598
Short name T1254
Test name
Test status
Simulation time 680931030 ps
CPU time 2.26 seconds
Started Aug 21 07:34:46 PM UTC 24
Finished Aug 21 07:34:50 PM UTC 24
Peak memory 254800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4285343598 -asse
rt nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.4285343598
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.34234927
Short name T1250
Test name
Test status
Simulation time 40062539 ps
CPU time 1.54 seconds
Started Aug 21 07:34:46 PM UTC 24
Finished Aug 21 07:34:49 PM UTC 24
Peak memory 240904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=34234927 -assert no
postproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.34234927
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.957484890
Short name T1255
Test name
Test status
Simulation time 100389706 ps
CPU time 2.22 seconds
Started Aug 21 07:34:46 PM UTC 24
Finished Aug 21 07:34:50 PM UTC 24
Peak memory 252748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=957484890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
17.otp_ctrl_same_csr_outstanding.957484890
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.3883969215
Short name T1260
Test name
Test status
Simulation time 79089984 ps
CPU time 3.81 seconds
Started Aug 21 07:34:46 PM UTC 24
Finished Aug 21 07:34:51 PM UTC 24
Peak memory 258912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3883969215 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.3883969215
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.3424870332
Short name T388
Test name
Test status
Simulation time 873630151 ps
CPU time 11.2 seconds
Started Aug 21 07:34:46 PM UTC 24
Finished Aug 21 07:34:59 PM UTC 24
Peak memory 256860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3424870
332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_c
trl_tl_intg_err.3424870332
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.2133558095
Short name T1265
Test name
Test status
Simulation time 148721220 ps
CPU time 3.09 seconds
Started Aug 21 07:34:48 PM UTC 24
Finished Aug 21 07:34:52 PM UTC 24
Peak memory 258876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2133558095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_mem_rw_with_rand_reset.2133558095
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.30611933
Short name T1257
Test name
Test status
Simulation time 85222642 ps
CPU time 2 seconds
Started Aug 21 07:34:48 PM UTC 24
Finished Aug 21 07:34:51 PM UTC 24
Peak memory 253964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=30611933 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.30611933
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.2803156665
Short name T1259
Test name
Test status
Simulation time 141226359 ps
CPU time 2.21 seconds
Started Aug 21 07:34:48 PM UTC 24
Finished Aug 21 07:34:51 PM UTC 24
Peak memory 242604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2803156665 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.2803156665
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.533381977
Short name T1261
Test name
Test status
Simulation time 132000998 ps
CPU time 2.51 seconds
Started Aug 21 07:34:48 PM UTC 24
Finished Aug 21 07:34:51 PM UTC 24
Peak memory 254684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=533381977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
18.otp_ctrl_same_csr_outstanding.533381977
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.811884825
Short name T1279
Test name
Test status
Simulation time 137692430 ps
CPU time 5.88 seconds
Started Aug 21 07:34:47 PM UTC 24
Finished Aug 21 07:34:54 PM UTC 24
Peak memory 259136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=811884825 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.811884825
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1732964912
Short name T386
Test name
Test status
Simulation time 1309311998 ps
CPU time 16.89 seconds
Started Aug 21 07:34:48 PM UTC 24
Finished Aug 21 07:35:06 PM UTC 24
Peak memory 252712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1732964
912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_c
trl_tl_intg_err.1732964912
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1987881671
Short name T1276
Test name
Test status
Simulation time 980311787 ps
CPU time 3.35 seconds
Started Aug 21 07:34:49 PM UTC 24
Finished Aug 21 07:34:53 PM UTC 24
Peak memory 258968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1987881671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_mem_rw_with_rand_reset.1987881671
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.1315770920
Short name T342
Test name
Test status
Simulation time 39185793 ps
CPU time 1.69 seconds
Started Aug 21 07:34:49 PM UTC 24
Finished Aug 21 07:34:52 PM UTC 24
Peak memory 257948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1315770920 -asse
rt nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.1315770920
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/19.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.1329638152
Short name T1262
Test name
Test status
Simulation time 615141057 ps
CPU time 1.69 seconds
Started Aug 21 07:34:49 PM UTC 24
Finished Aug 21 07:34:52 PM UTC 24
Peak memory 241204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1329638152 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.1329638152
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/19.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.1110596677
Short name T1266
Test name
Test status
Simulation time 101871995 ps
CPU time 2.51 seconds
Started Aug 21 07:34:49 PM UTC 24
Finished Aug 21 07:34:53 PM UTC 24
Peak memory 252624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=1110596677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
19.otp_ctrl_same_csr_outstanding.1110596677
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/19.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.1422134337
Short name T1278
Test name
Test status
Simulation time 88146435 ps
CPU time 5.17 seconds
Started Aug 21 07:34:48 PM UTC 24
Finished Aug 21 07:34:54 PM UTC 24
Peak memory 259156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1422134337 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.1422134337
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/19.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.1397248273
Short name T407
Test name
Test status
Simulation time 889923992 ps
CPU time 4.07 seconds
Started Aug 21 07:34:28 PM UTC 24
Finished Aug 21 07:34:33 PM UTC 24
Peak memory 252688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1397248273
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_
csr_aliasing.1397248273
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.3497625373
Short name T349
Test name
Test status
Simulation time 78285768 ps
CPU time 4.16 seconds
Started Aug 21 07:34:26 PM UTC 24
Finished Aug 21 07:34:32 PM UTC 24
Peak memory 252688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3497625373
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_
csr_bit_bash.3497625373
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.4214537934
Short name T332
Test name
Test status
Simulation time 119061164 ps
CPU time 2.03 seconds
Started Aug 21 07:34:26 PM UTC 24
Finished Aug 21 07:34:30 PM UTC 24
Peak memory 254824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4214537934
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_
csr_hw_reset.4214537934
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.1851728555
Short name T1187
Test name
Test status
Simulation time 139230767 ps
CPU time 2.42 seconds
Started Aug 21 07:34:28 PM UTC 24
Finished Aug 21 07:34:31 PM UTC 24
Peak memory 258876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1851728555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.1851728555
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.862053033
Short name T305
Test name
Test status
Simulation time 45839408 ps
CPU time 2.06 seconds
Started Aug 21 07:34:26 PM UTC 24
Finished Aug 21 07:34:30 PM UTC 24
Peak memory 254764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=862053033 -asser
t nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.862053033
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.511822848
Short name T1181
Test name
Test status
Simulation time 579441015 ps
CPU time 1.83 seconds
Started Aug 21 07:34:26 PM UTC 24
Finished Aug 21 07:34:29 PM UTC 24
Peak memory 240688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=511822848 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.511822848
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.452975140
Short name T1183
Test name
Test status
Simulation time 139612696 ps
CPU time 2.13 seconds
Started Aug 21 07:34:26 PM UTC 24
Finished Aug 21 07:34:30 PM UTC 24
Peak memory 241520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=
452975140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
otp_ctrl_mem_partial_access.452975140
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_mem_partial_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.278615832
Short name T1182
Test name
Test status
Simulation time 37428964 ps
CPU time 1.86 seconds
Started Aug 21 07:34:26 PM UTC 24
Finished Aug 21 07:34:29 PM UTC 24
Peak memory 240332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=278615832
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_m
em_walk.278615832
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_mem_walk/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.2869144261
Short name T333
Test name
Test status
Simulation time 74925021 ps
CPU time 2.54 seconds
Started Aug 21 07:34:28 PM UTC 24
Finished Aug 21 07:34:31 PM UTC 24
Peak memory 252684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=2869144261 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.otp_ctrl_same_csr_outstanding.2869144261
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.1756958536
Short name T1186
Test name
Test status
Simulation time 90570116 ps
CPU time 4.89 seconds
Started Aug 21 07:34:25 PM UTC 24
Finished Aug 21 07:34:31 PM UTC 24
Peak memory 258976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1756958536 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.1756958536
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.378931664
Short name T395
Test name
Test status
Simulation time 19941143076 ps
CPU time 33.5 seconds
Started Aug 21 07:34:25 PM UTC 24
Finished Aug 21 07:35:00 PM UTC 24
Peak memory 256868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3789316
64 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctr
l_tl_intg_err.378931664
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.207849791
Short name T1264
Test name
Test status
Simulation time 141526301 ps
CPU time 1.67 seconds
Started Aug 21 07:34:49 PM UTC 24
Finished Aug 21 07:34:52 PM UTC 24
Peak memory 241692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=207849791 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.207849791
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/20.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.2486678843
Short name T1277
Test name
Test status
Simulation time 578176297 ps
CPU time 2.44 seconds
Started Aug 21 07:34:50 PM UTC 24
Finished Aug 21 07:34:54 PM UTC 24
Peak memory 242168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2486678843 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.2486678843
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/21.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.2110465017
Short name T1267
Test name
Test status
Simulation time 40319097 ps
CPU time 1.66 seconds
Started Aug 21 07:34:50 PM UTC 24
Finished Aug 21 07:34:53 PM UTC 24
Peak memory 241088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2110465017 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.2110465017
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/22.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.882338672
Short name T1271
Test name
Test status
Simulation time 40138589 ps
CPU time 1.84 seconds
Started Aug 21 07:34:50 PM UTC 24
Finished Aug 21 07:34:53 PM UTC 24
Peak memory 241640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=882338672 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.882338672
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/23.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.613488770
Short name T1273
Test name
Test status
Simulation time 38771329 ps
CPU time 1.87 seconds
Started Aug 21 07:34:50 PM UTC 24
Finished Aug 21 07:34:53 PM UTC 24
Peak memory 240780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=613488770 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.613488770
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/24.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.247757378
Short name T1268
Test name
Test status
Simulation time 136488540 ps
CPU time 1.56 seconds
Started Aug 21 07:34:50 PM UTC 24
Finished Aug 21 07:34:53 PM UTC 24
Peak memory 241132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=247757378 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.247757378
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/25.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.999418790
Short name T1275
Test name
Test status
Simulation time 531390310 ps
CPU time 1.87 seconds
Started Aug 21 07:34:50 PM UTC 24
Finished Aug 21 07:34:53 PM UTC 24
Peak memory 240852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=999418790 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.999418790
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/26.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.1097923324
Short name T1269
Test name
Test status
Simulation time 45038881 ps
CPU time 1.49 seconds
Started Aug 21 07:34:50 PM UTC 24
Finished Aug 21 07:34:53 PM UTC 24
Peak memory 241032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1097923324 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.1097923324
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/27.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.3124909067
Short name T1270
Test name
Test status
Simulation time 42927091 ps
CPU time 1.46 seconds
Started Aug 21 07:34:51 PM UTC 24
Finished Aug 21 07:34:53 PM UTC 24
Peak memory 241436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3124909067 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.3124909067
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/28.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.1054409879
Short name T1274
Test name
Test status
Simulation time 540812557 ps
CPU time 1.67 seconds
Started Aug 21 07:34:51 PM UTC 24
Finished Aug 21 07:34:53 PM UTC 24
Peak memory 241204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1054409879 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.1054409879
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/29.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3538772385
Short name T339
Test name
Test status
Simulation time 784041731 ps
CPU time 7.31 seconds
Started Aug 21 07:34:30 PM UTC 24
Finished Aug 21 07:34:38 PM UTC 24
Peak memory 252640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3538772385
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_
csr_aliasing.3538772385
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.3778697379
Short name T1198
Test name
Test status
Simulation time 191026124 ps
CPU time 4.88 seconds
Started Aug 21 07:34:30 PM UTC 24
Finished Aug 21 07:34:36 PM UTC 24
Peak memory 252644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3778697379
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_
csr_bit_bash.3778697379
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3899112795
Short name T1190
Test name
Test status
Simulation time 152419793 ps
CPU time 1.9 seconds
Started Aug 21 07:34:29 PM UTC 24
Finished Aug 21 07:34:32 PM UTC 24
Peak memory 251864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3899112795
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_
csr_hw_reset.3899112795
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.618895318
Short name T1195
Test name
Test status
Simulation time 123914759 ps
CPU time 2.31 seconds
Started Aug 21 07:34:30 PM UTC 24
Finished Aug 21 07:34:34 PM UTC 24
Peak memory 256892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=618895318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.618895318
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.2416072377
Short name T335
Test name
Test status
Simulation time 76971523 ps
CPU time 1.56 seconds
Started Aug 21 07:34:30 PM UTC 24
Finished Aug 21 07:34:33 PM UTC 24
Peak memory 251864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2416072377 -asse
rt nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.2416072377
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.3663749217
Short name T1185
Test name
Test status
Simulation time 576820917 ps
CPU time 2.19 seconds
Started Aug 21 07:34:28 PM UTC 24
Finished Aug 21 07:34:31 PM UTC 24
Peak memory 241712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3663749217 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.3663749217
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2334229250
Short name T1188
Test name
Test status
Simulation time 69148629 ps
CPU time 1.56 seconds
Started Aug 21 07:34:29 PM UTC 24
Finished Aug 21 07:34:32 PM UTC 24
Peak memory 239988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=
2334229250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.otp_ctrl_mem_partial_access.2334229250
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_mem_partial_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3802699613
Short name T1189
Test name
Test status
Simulation time 36825086 ps
CPU time 1.68 seconds
Started Aug 21 07:34:29 PM UTC 24
Finished Aug 21 07:34:32 PM UTC 24
Peak memory 241684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3802699613
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_
mem_walk.3802699613
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_mem_walk/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.1275503507
Short name T345
Test name
Test status
Simulation time 103138333 ps
CPU time 3.48 seconds
Started Aug 21 07:34:30 PM UTC 24
Finished Aug 21 07:34:35 PM UTC 24
Peak memory 252696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=1275503507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.otp_ctrl_same_csr_outstanding.1275503507
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.1150507284
Short name T1197
Test name
Test status
Simulation time 310771978 ps
CPU time 6.97 seconds
Started Aug 21 07:34:28 PM UTC 24
Finished Aug 21 07:34:36 PM UTC 24
Peak memory 259036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1150507284 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.1150507284
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.4141298913
Short name T1280
Test name
Test status
Simulation time 40072672 ps
CPU time 1.37 seconds
Started Aug 21 07:34:52 PM UTC 24
Finished Aug 21 07:34:55 PM UTC 24
Peak memory 241884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4141298913 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.4141298913
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/30.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.2462509271
Short name T1282
Test name
Test status
Simulation time 584579044 ps
CPU time 1.65 seconds
Started Aug 21 07:34:52 PM UTC 24
Finished Aug 21 07:34:55 PM UTC 24
Peak memory 240912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2462509271 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.2462509271
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/31.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.2554649500
Short name T1289
Test name
Test status
Simulation time 74778268 ps
CPU time 2.03 seconds
Started Aug 21 07:34:52 PM UTC 24
Finished Aug 21 07:34:56 PM UTC 24
Peak memory 242540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2554649500 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.2554649500
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/32.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.3964592384
Short name T1281
Test name
Test status
Simulation time 38049091 ps
CPU time 1.46 seconds
Started Aug 21 07:34:52 PM UTC 24
Finished Aug 21 07:34:55 PM UTC 24
Peak memory 241108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3964592384 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.3964592384
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/33.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.877166208
Short name T1288
Test name
Test status
Simulation time 76116949 ps
CPU time 1.8 seconds
Started Aug 21 07:34:52 PM UTC 24
Finished Aug 21 07:34:56 PM UTC 24
Peak memory 240852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=877166208 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.877166208
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/34.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.35860499
Short name T1283
Test name
Test status
Simulation time 48088679 ps
CPU time 1.52 seconds
Started Aug 21 07:34:52 PM UTC 24
Finished Aug 21 07:34:55 PM UTC 24
Peak memory 240856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=35860499 -assert no
postproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.35860499
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/35.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.298227229
Short name T1286
Test name
Test status
Simulation time 83606766 ps
CPU time 1.65 seconds
Started Aug 21 07:34:53 PM UTC 24
Finished Aug 21 07:34:56 PM UTC 24
Peak memory 241132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=298227229 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.298227229
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/36.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.4090474842
Short name T1287
Test name
Test status
Simulation time 39082312 ps
CPU time 1.59 seconds
Started Aug 21 07:34:53 PM UTC 24
Finished Aug 21 07:34:56 PM UTC 24
Peak memory 240916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4090474842 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.4090474842
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/37.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.1774074814
Short name T1285
Test name
Test status
Simulation time 147910073 ps
CPU time 1.48 seconds
Started Aug 21 07:34:53 PM UTC 24
Finished Aug 21 07:34:55 PM UTC 24
Peak memory 241884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1774074814 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.1774074814
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/38.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.2958960919
Short name T1258
Test name
Test status
Simulation time 142180472 ps
CPU time 1.77 seconds
Started Aug 21 07:34:53 PM UTC 24
Finished Aug 21 07:34:56 PM UTC 24
Peak memory 241808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2958960919 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.2958960919
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/39.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.1493454570
Short name T338
Test name
Test status
Simulation time 556952221 ps
CPU time 5.75 seconds
Started Aug 21 07:34:32 PM UTC 24
Finished Aug 21 07:34:38 PM UTC 24
Peak memory 252704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1493454570
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_
csr_aliasing.1493454570
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_csr_aliasing/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.2847768375
Short name T1212
Test name
Test status
Simulation time 864852672 ps
CPU time 6.8 seconds
Started Aug 21 07:34:32 PM UTC 24
Finished Aug 21 07:34:39 PM UTC 24
Peak memory 242532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2847768375
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_
csr_bit_bash.2847768375
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_csr_bit_bash/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.3123796195
Short name T336
Test name
Test status
Simulation time 236741537 ps
CPU time 2.3 seconds
Started Aug 21 07:34:30 PM UTC 24
Finished Aug 21 07:34:34 PM UTC 24
Peak memory 252764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3123796195
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_
csr_hw_reset.3123796195
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_csr_hw_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.1938728751
Short name T1204
Test name
Test status
Simulation time 125061031 ps
CPU time 4.52 seconds
Started Aug 21 07:34:32 PM UTC 24
Finished Aug 21 07:34:37 PM UTC 24
Peak memory 258940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=1938728751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.1938728751
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.921382736
Short name T1196
Test name
Test status
Simulation time 602818987 ps
CPU time 1.72 seconds
Started Aug 21 07:34:31 PM UTC 24
Finished Aug 21 07:34:34 PM UTC 24
Peak memory 251880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=921382736 -asser
t nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.921382736
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.3882304501
Short name T1193
Test name
Test status
Simulation time 38369602 ps
CPU time 1.64 seconds
Started Aug 21 07:34:30 PM UTC 24
Finished Aug 21 07:34:33 PM UTC 24
Peak memory 240856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3882304501 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.3882304501
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.2648968271
Short name T1192
Test name
Test status
Simulation time 133180497 ps
CPU time 1.54 seconds
Started Aug 21 07:34:30 PM UTC 24
Finished Aug 21 07:34:33 PM UTC 24
Peak memory 241684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=
2648968271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.otp_ctrl_mem_partial_access.2648968271
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_mem_partial_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.808971952
Short name T1194
Test name
Test status
Simulation time 41121882 ps
CPU time 1.86 seconds
Started Aug 21 07:34:30 PM UTC 24
Finished Aug 21 07:34:33 PM UTC 24
Peak memory 240336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=808971952
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_m
em_walk.808971952
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_mem_walk/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.1414741496
Short name T346
Test name
Test status
Simulation time 102382143 ps
CPU time 2.85 seconds
Started Aug 21 07:34:32 PM UTC 24
Finished Aug 21 07:34:36 PM UTC 24
Peak memory 252624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=1414741496 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.otp_ctrl_same_csr_outstanding.1414741496
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.93852075
Short name T1199
Test name
Test status
Simulation time 1393924430 ps
CPU time 4.97 seconds
Started Aug 21 07:34:30 PM UTC 24
Finished Aug 21 07:34:36 PM UTC 24
Peak memory 259028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=93852075 -assert no
postproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.93852075
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.2994344374
Short name T1299
Test name
Test status
Simulation time 20228816322 ps
CPU time 44.39 seconds
Started Aug 21 07:34:30 PM UTC 24
Finished Aug 21 07:35:16 PM UTC 24
Peak memory 252772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2994344
374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ct
rl_tl_intg_err.2994344374
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.1660647065
Short name T1296
Test name
Test status
Simulation time 514485392 ps
CPU time 1.79 seconds
Started Aug 21 07:34:53 PM UTC 24
Finished Aug 21 07:35:07 PM UTC 24
Peak memory 240964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1660647065 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.1660647065
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/40.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.2746357870
Short name T1284
Test name
Test status
Simulation time 38728183 ps
CPU time 1.41 seconds
Started Aug 21 07:34:53 PM UTC 24
Finished Aug 21 07:34:55 PM UTC 24
Peak memory 241872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2746357870 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.2746357870
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/41.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.763537497
Short name T1290
Test name
Test status
Simulation time 69052325 ps
CPU time 1.37 seconds
Started Aug 21 07:34:54 PM UTC 24
Finished Aug 21 07:35:07 PM UTC 24
Peak memory 240532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=763537497 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.763537497
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/42.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.1948935891
Short name T1293
Test name
Test status
Simulation time 41195037 ps
CPU time 1.4 seconds
Started Aug 21 07:34:54 PM UTC 24
Finished Aug 21 07:35:07 PM UTC 24
Peak memory 240844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1948935891 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.1948935891
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/43.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.678387734
Short name T1291
Test name
Test status
Simulation time 154791128 ps
CPU time 1.34 seconds
Started Aug 21 07:34:54 PM UTC 24
Finished Aug 21 07:35:07 PM UTC 24
Peak memory 241700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=678387734 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.678387734
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/44.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.2637965481
Short name T1297
Test name
Test status
Simulation time 147900508 ps
CPU time 1.58 seconds
Started Aug 21 07:34:54 PM UTC 24
Finished Aug 21 07:35:07 PM UTC 24
Peak memory 240828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2637965481 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.2637965481
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/45.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.3870539099
Short name T1298
Test name
Test status
Simulation time 91485078 ps
CPU time 1.67 seconds
Started Aug 21 07:34:54 PM UTC 24
Finished Aug 21 07:35:07 PM UTC 24
Peak memory 240768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3870539099 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.3870539099
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/46.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.3844565580
Short name T1294
Test name
Test status
Simulation time 101218716 ps
CPU time 1.37 seconds
Started Aug 21 07:34:54 PM UTC 24
Finished Aug 21 07:35:07 PM UTC 24
Peak memory 240904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3844565580 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.3844565580
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/47.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.1099580514
Short name T1295
Test name
Test status
Simulation time 149496722 ps
CPU time 1.43 seconds
Started Aug 21 07:34:54 PM UTC 24
Finished Aug 21 07:35:07 PM UTC 24
Peak memory 241204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1099580514 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.1099580514
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/48.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.81617655
Short name T1292
Test name
Test status
Simulation time 39756152 ps
CPU time 1.38 seconds
Started Aug 21 07:34:54 PM UTC 24
Finished Aug 21 07:35:07 PM UTC 24
Peak memory 240980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=81617655 -assert no
postproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/low
risc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.81617655
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/49.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.2590257928
Short name T1206
Test name
Test status
Simulation time 386585016 ps
CPU time 4.19 seconds
Started Aug 21 07:34:33 PM UTC 24
Finished Aug 21 07:34:38 PM UTC 24
Peak memory 258968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2590257928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_mem_rw_with_rand_reset.2590257928
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.4102297914
Short name T337
Test name
Test status
Simulation time 90939345 ps
CPU time 2.34 seconds
Started Aug 21 07:34:33 PM UTC 24
Finished Aug 21 07:34:36 PM UTC 24
Peak memory 252820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4102297914 -asse
rt nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.4102297914
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.2669807889
Short name T1200
Test name
Test status
Simulation time 606240579 ps
CPU time 2.68 seconds
Started Aug 21 07:34:33 PM UTC 24
Finished Aug 21 07:34:37 PM UTC 24
Peak memory 242480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2669807889 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.2669807889
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.2000322751
Short name T347
Test name
Test status
Simulation time 1092674958 ps
CPU time 4.21 seconds
Started Aug 21 07:34:33 PM UTC 24
Finished Aug 21 07:34:38 PM UTC 24
Peak memory 252764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=2000322751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
5.otp_ctrl_same_csr_outstanding.2000322751
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.1630421970
Short name T1205
Test name
Test status
Simulation time 168913882 ps
CPU time 4.37 seconds
Started Aug 21 07:34:33 PM UTC 24
Finished Aug 21 07:34:38 PM UTC 24
Peak memory 258916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1630421970 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.1630421970
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.3971215981
Short name T309
Test name
Test status
Simulation time 796599699 ps
CPU time 10 seconds
Started Aug 21 07:34:33 PM UTC 24
Finished Aug 21 07:34:44 PM UTC 24
Peak memory 256992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3971215
981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ct
rl_tl_intg_err.3971215981
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.4190853128
Short name T1208
Test name
Test status
Simulation time 187533786 ps
CPU time 3.52 seconds
Started Aug 21 07:34:34 PM UTC 24
Finished Aug 21 07:34:39 PM UTC 24
Peak memory 258964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=4190853128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_mem_rw_with_rand_reset.4190853128
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.1294035478
Short name T1203
Test name
Test status
Simulation time 48350245 ps
CPU time 2.18 seconds
Started Aug 21 07:34:34 PM UTC 24
Finished Aug 21 07:34:37 PM UTC 24
Peak memory 254760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1294035478 -asse
rt nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.1294035478
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.3334574214
Short name T1201
Test name
Test status
Simulation time 139507866 ps
CPU time 1.98 seconds
Started Aug 21 07:34:34 PM UTC 24
Finished Aug 21 07:34:37 PM UTC 24
Peak memory 241024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3334574214 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.3334574214
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1291866614
Short name T1213
Test name
Test status
Simulation time 1126168488 ps
CPU time 4.87 seconds
Started Aug 21 07:34:34 PM UTC 24
Finished Aug 21 07:34:40 PM UTC 24
Peak memory 254812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=1291866614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
6.otp_ctrl_same_csr_outstanding.1291866614
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.3237390178
Short name T1210
Test name
Test status
Simulation time 124295425 ps
CPU time 4.99 seconds
Started Aug 21 07:34:33 PM UTC 24
Finished Aug 21 07:34:39 PM UTC 24
Peak memory 259008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3237390178 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.3237390178
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.3692860141
Short name T384
Test name
Test status
Simulation time 1256782842 ps
CPU time 10.02 seconds
Started Aug 21 07:34:34 PM UTC 24
Finished Aug 21 07:34:45 PM UTC 24
Peak memory 252896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3692860
141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ct
rl_tl_intg_err.3692860141
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.2235219108
Short name T1209
Test name
Test status
Simulation time 69083727 ps
CPU time 2.29 seconds
Started Aug 21 07:34:36 PM UTC 24
Finished Aug 21 07:34:39 PM UTC 24
Peak memory 256856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2235219108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_mem_rw_with_rand_reset.2235219108
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.681260352
Short name T1207
Test name
Test status
Simulation time 155581900 ps
CPU time 1.77 seconds
Started Aug 21 07:34:35 PM UTC 24
Finished Aug 21 07:34:38 PM UTC 24
Peak memory 253960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=681260352 -asser
t nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.681260352
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.1340627942
Short name T1202
Test name
Test status
Simulation time 41222401 ps
CPU time 1.86 seconds
Started Aug 21 07:34:34 PM UTC 24
Finished Aug 21 07:34:37 PM UTC 24
Peak memory 240852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1340627942 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.1340627942
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.548510678
Short name T344
Test name
Test status
Simulation time 96139494 ps
CPU time 2.99 seconds
Started Aug 21 07:34:35 PM UTC 24
Finished Aug 21 07:34:39 PM UTC 24
Peak memory 252804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=548510678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
7.otp_ctrl_same_csr_outstanding.548510678
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.479406509
Short name T1217
Test name
Test status
Simulation time 282444012 ps
CPU time 5.87 seconds
Started Aug 21 07:34:34 PM UTC 24
Finished Aug 21 07:34:41 PM UTC 24
Peak memory 258952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=479406509 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.479406509
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.310537612
Short name T390
Test name
Test status
Simulation time 4750052642 ps
CPU time 21.89 seconds
Started Aug 21 07:34:34 PM UTC 24
Finished Aug 21 07:34:57 PM UTC 24
Peak memory 257120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3105376
12 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctr
l_tl_intg_err.310537612
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.2553810174
Short name T1216
Test name
Test status
Simulation time 118611459 ps
CPU time 3.14 seconds
Started Aug 21 07:34:37 PM UTC 24
Finished Aug 21 07:34:41 PM UTC 24
Peak memory 258968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2553810174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_mem_rw_with_rand_reset.2553810174
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3043117865
Short name T343
Test name
Test status
Simulation time 154629036 ps
CPU time 1.84 seconds
Started Aug 21 07:34:37 PM UTC 24
Finished Aug 21 07:34:40 PM UTC 24
Peak memory 254008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3043117865 -asse
rt nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.3043117865
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.1613299449
Short name T1211
Test name
Test status
Simulation time 42177416 ps
CPU time 1.51 seconds
Started Aug 21 07:34:37 PM UTC 24
Finished Aug 21 07:34:39 PM UTC 24
Peak memory 241704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1613299449 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.1613299449
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.1858844673
Short name T1218
Test name
Test status
Simulation time 192061370 ps
CPU time 3.61 seconds
Started Aug 21 07:34:37 PM UTC 24
Finished Aug 21 07:34:41 PM UTC 24
Peak memory 254880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=1858844673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
8.otp_ctrl_same_csr_outstanding.1858844673
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3009526567
Short name T1178
Test name
Test status
Simulation time 360033217 ps
CPU time 3.41 seconds
Started Aug 21 07:34:36 PM UTC 24
Finished Aug 21 07:34:40 PM UTC 24
Peak memory 258968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3009526567 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.3009526567
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2385798717
Short name T387
Test name
Test status
Simulation time 2789371251 ps
CPU time 18.39 seconds
Started Aug 21 07:34:37 PM UTC 24
Finished Aug 21 07:34:56 PM UTC 24
Peak memory 252976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2385798
717 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ct
rl_tl_intg_err.2385798717
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.2331443257
Short name T1221
Test name
Test status
Simulation time 107461244 ps
CPU time 2.98 seconds
Started Aug 21 07:34:38 PM UTC 24
Finished Aug 21 07:34:42 PM UTC 24
Peak memory 258940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_
ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/
hw/dv/tools/sim.tcl +ntb_random_seed=2331443257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_mem_rw_with_rand_reset.2331443257
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.3226181258
Short name T1215
Test name
Test status
Simulation time 70406953 ps
CPU time 1.59 seconds
Started Aug 21 07:34:38 PM UTC 24
Finished Aug 21 07:34:41 PM UTC 24
Peak memory 251800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3226181258 -asse
rt nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.3226181258
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_csr_rw/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.129537490
Short name T1214
Test name
Test status
Simulation time 39589233 ps
CPU time 1.72 seconds
Started Aug 21 07:34:38 PM UTC 24
Finished Aug 21 07:34:41 PM UTC 24
Peak memory 241200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=129537490 -assert n
opostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lo
wrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.129537490
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_intr_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.2415456489
Short name T1222
Test name
Test status
Simulation time 151919572 ps
CPU time 3.12 seconds
Started Aug 21 07:34:38 PM UTC 24
Finished Aug 21 07:34:42 PM UTC 24
Peak memory 254940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_see
d=2415456489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
9.otp_ctrl_same_csr_outstanding.2415456489
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_same_csr_outstanding/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.2704170288
Short name T1236
Test name
Test status
Simulation time 1138227824 ps
CPU time 6.66 seconds
Started Aug 21 07:34:38 PM UTC 24
Finished Aug 21 07:34:46 PM UTC 24
Peak memory 259152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2704170288 -assert
nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/l
owrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.2704170288
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_tl_errors/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.2240915965
Short name T396
Test name
Test status
Simulation time 696019068 ps
CPU time 10.83 seconds
Started Aug 21 07:34:38 PM UTC 24
Finished Aug 21 07:34:50 PM UTC 24
Peak memory 256992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2240915
965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ct
rl_tl_intg_err.2240915965
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_tl_intg_err/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_alert_test.3985508809
Short name T1
Test name
Test status
Simulation time 217387349 ps
CPU time 1.57 seconds
Started Aug 21 07:34:57 PM UTC 24
Finished Aug 21 07:35:01 PM UTC 24
Peak memory 250640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3985508809 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.3985508809
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_background_chks.2105664368
Short name T101
Test name
Test status
Simulation time 1129128010 ps
CPU time 17.23 seconds
Started Aug 21 07:34:56 PM UTC 24
Finished Aug 21 07:35:24 PM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2105664368 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.2105664368
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_check_fail.1373400435
Short name T100
Test name
Test status
Simulation time 292082286 ps
CPU time 6.4 seconds
Started Aug 21 07:34:56 PM UTC 24
Finished Aug 21 07:35:13 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1373400435 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.1373400435
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_init_fail.3698096870
Short name T4
Test name
Test status
Simulation time 106001861 ps
CPU time 3.13 seconds
Started Aug 21 07:34:55 PM UTC 24
Finished Aug 21 07:35:09 PM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3698096870 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.3698096870
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_low_freq_read.3665368977
Short name T123
Test name
Test status
Simulation time 3021698204 ps
CPU time 9.14 seconds
Started Aug 21 07:34:55 PM UTC 24
Finished Aug 21 07:35:15 PM UTC 24
Peak memory 251580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3665368977 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit
an/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.3665368977
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_esc.3311575054
Short name T94
Test name
Test status
Simulation time 263217514 ps
CPU time 5.57 seconds
Started Aug 21 07:34:56 PM UTC 24
Finished Aug 21 07:35:12 PM UTC 24
Peak memory 251212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3311575054 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.3311575054
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_partition_walk.889039345
Short name T177
Test name
Test status
Simulation time 5055646526 ps
CPU time 22.96 seconds
Started Aug 21 07:34:55 PM UTC 24
Finished Aug 21 07:35:29 PM UTC 24
Peak memory 251604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=889039345 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit
an/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.889039345
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_sec_cm.757234451
Short name T22
Test name
Test status
Simulation time 20864284693 ps
CPU time 179.11 seconds
Started Aug 21 07:34:57 PM UTC 24
Finished Aug 21 07:38:00 PM UTC 24
Peak memory 285840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=757234451 -asse
rt nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.757234451
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_smoke.3677691854
Short name T13
Test name
Test status
Simulation time 976472508 ps
CPU time 6.32 seconds
Started Aug 21 07:34:54 PM UTC 24
Finished Aug 21 07:35:12 PM UTC 24
Peak memory 257572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3677691854 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.3677691854
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_background_chks.667840061
Short name T6
Test name
Test status
Simulation time 6668708164 ps
CPU time 10.77 seconds
Started Aug 21 07:34:57 PM UTC 24
Finished Aug 21 07:35:10 PM UTC 24
Peak memory 257496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=667840061 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.667840061
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_check_fail.2102513549
Short name T96
Test name
Test status
Simulation time 1643478776 ps
CPU time 23.92 seconds
Started Aug 21 07:35:01 PM UTC 24
Finished Aug 21 07:35:29 PM UTC 24
Peak memory 253464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2102513549 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.2102513549
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_errs.820670998
Short name T172
Test name
Test status
Simulation time 4033081678 ps
CPU time 31.42 seconds
Started Aug 21 07:35:00 PM UTC 24
Finished Aug 21 07:35:42 PM UTC 24
Peak memory 257472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=820670998 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.820670998
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_macro_errs.2129766933
Short name T116
Test name
Test status
Simulation time 1385055202 ps
CPU time 21.58 seconds
Started Aug 21 07:35:02 PM UTC 24
Finished Aug 21 07:35:28 PM UTC 24
Peak memory 255508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2129766933 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.2129766933
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_key_req.189866414
Short name T129
Test name
Test status
Simulation time 1176842782 ps
CPU time 8.2 seconds
Started Aug 21 07:35:02 PM UTC 24
Finished Aug 21 07:35:14 PM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=189866414 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.189866414
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_esc.1532076492
Short name T128
Test name
Test status
Simulation time 743386602 ps
CPU time 13.23 seconds
Started Aug 21 07:34:59 PM UTC 24
Finished Aug 21 07:35:21 PM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1532076492 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.1532076492
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_req.2670927854
Short name T111
Test name
Test status
Simulation time 8764241293 ps
CPU time 17.24 seconds
Started Aug 21 07:34:58 PM UTC 24
Finished Aug 21 07:35:24 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2670927854 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_
req.2670927854
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_smoke.3686763135
Short name T3
Test name
Test status
Simulation time 254835997 ps
CPU time 6.38 seconds
Started Aug 21 07:34:57 PM UTC 24
Finished Aug 21 07:35:06 PM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3686763135 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.3686763135
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_test_access.2899701866
Short name T17
Test name
Test status
Simulation time 244085590 ps
CPU time 6.04 seconds
Started Aug 21 07:35:05 PM UTC 24
Finished Aug 21 07:35:12 PM UTC 24
Peak memory 257460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2899701866 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.2899701866
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/1.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_alert_test.3817035838
Short name T489
Test name
Test status
Simulation time 53667559 ps
CPU time 2.86 seconds
Started Aug 21 07:36:29 PM UTC 24
Finished Aug 21 07:36:33 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3817035838 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.3817035838
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_errs.4294945653
Short name T210
Test name
Test status
Simulation time 256981058 ps
CPU time 14.49 seconds
Started Aug 21 07:36:23 PM UTC 24
Finished Aug 21 07:36:38 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4294945653 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.4294945653
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_lock.2538047965
Short name T319
Test name
Test status
Simulation time 10970056495 ps
CPU time 22.86 seconds
Started Aug 21 07:36:23 PM UTC 24
Finished Aug 21 07:36:47 PM UTC 24
Peak memory 253436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2538047965 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.2538047965
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_macro_errs.135959107
Short name T488
Test name
Test status
Simulation time 448993509 ps
CPU time 5.14 seconds
Started Aug 21 07:36:26 PM UTC 24
Finished Aug 21 07:36:32 PM UTC 24
Peak memory 253732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=135959107 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.135959107
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_key_req.3072229665
Short name T211
Test name
Test status
Simulation time 1383707397 ps
CPU time 13.19 seconds
Started Aug 21 07:36:26 PM UTC 24
Finished Aug 21 07:36:40 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3072229665 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.3072229665
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_esc.2741977422
Short name T208
Test name
Test status
Simulation time 1355756168 ps
CPU time 12.62 seconds
Started Aug 21 07:36:23 PM UTC 24
Finished Aug 21 07:36:36 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2741977422 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.2741977422
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_req.2203659976
Short name T294
Test name
Test status
Simulation time 446336337 ps
CPU time 12.54 seconds
Started Aug 21 07:36:20 PM UTC 24
Finished Aug 21 07:36:34 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2203659976 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc
_req.2203659976
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_regwen.3993624523
Short name T205
Test name
Test status
Simulation time 366950055 ps
CPU time 7.04 seconds
Started Aug 21 07:36:26 PM UTC 24
Finished Aug 21 07:36:34 PM UTC 24
Peak memory 251552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3993624523 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.3993624523
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_smoke.3715583182
Short name T254
Test name
Test status
Simulation time 982136185 ps
CPU time 7.36 seconds
Started Aug 21 07:36:19 PM UTC 24
Finished Aug 21 07:36:27 PM UTC 24
Peak memory 251584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3715583182 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.3715583182
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_test_access.4070189638
Short name T320
Test name
Test status
Simulation time 1008630671 ps
CPU time 19.43 seconds
Started Aug 21 07:36:26 PM UTC 24
Finished Aug 21 07:36:47 PM UTC 24
Peak memory 251576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4070189638 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.4070189638
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/10.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_init_fail.779189408
Short name T888
Test name
Test status
Simulation time 160025824 ps
CPU time 5.42 seconds
Started Aug 21 07:43:56 PM UTC 24
Finished Aug 21 07:44:03 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=779189408 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.779189408
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/100.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_parallel_lc_esc.3565284961
Short name T899
Test name
Test status
Simulation time 4519081659 ps
CPU time 12.5 seconds
Started Aug 21 07:43:56 PM UTC 24
Finished Aug 21 07:44:10 PM UTC 24
Peak memory 251376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3565284961 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.3565284961
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/100.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_init_fail.3886660411
Short name T887
Test name
Test status
Simulation time 335699704 ps
CPU time 4.74 seconds
Started Aug 21 07:43:56 PM UTC 24
Finished Aug 21 07:44:03 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3886660411 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.3886660411
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/101.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_parallel_lc_esc.1815055813
Short name T909
Test name
Test status
Simulation time 1088829395 ps
CPU time 18.43 seconds
Started Aug 21 07:43:56 PM UTC 24
Finished Aug 21 07:44:16 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1815055813 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.1815055813
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/101.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_init_fail.307725931
Short name T889
Test name
Test status
Simulation time 160588437 ps
CPU time 6.27 seconds
Started Aug 21 07:43:56 PM UTC 24
Finished Aug 21 07:44:04 PM UTC 24
Peak memory 253248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=307725931 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.307725931
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/102.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_parallel_lc_esc.3824393900
Short name T905
Test name
Test status
Simulation time 7926330936 ps
CPU time 15.95 seconds
Started Aug 21 07:43:56 PM UTC 24
Finished Aug 21 07:44:14 PM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3824393900 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.3824393900
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/102.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_init_fail.248601607
Short name T69
Test name
Test status
Simulation time 124213851 ps
CPU time 3.36 seconds
Started Aug 21 07:43:56 PM UTC 24
Finished Aug 21 07:44:01 PM UTC 24
Peak memory 251516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=248601607 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.248601607
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/103.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_parallel_lc_esc.248447634
Short name T890
Test name
Test status
Simulation time 210709479 ps
CPU time 6.21 seconds
Started Aug 21 07:43:56 PM UTC 24
Finished Aug 21 07:44:04 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=248447634 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.248447634
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/103.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_init_fail.3334628372
Short name T885
Test name
Test status
Simulation time 84542256 ps
CPU time 3.74 seconds
Started Aug 21 07:43:57 PM UTC 24
Finished Aug 21 07:44:02 PM UTC 24
Peak memory 251232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3334628372 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.3334628372
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/104.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_parallel_lc_esc.1002399803
Short name T893
Test name
Test status
Simulation time 216578020 ps
CPU time 7.16 seconds
Started Aug 21 07:43:58 PM UTC 24
Finished Aug 21 07:44:07 PM UTC 24
Peak memory 251132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1002399803 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.1002399803
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/104.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_init_fail.829230562
Short name T892
Test name
Test status
Simulation time 2612046485 ps
CPU time 6.02 seconds
Started Aug 21 07:43:58 PM UTC 24
Finished Aug 21 07:44:06 PM UTC 24
Peak memory 253548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=829230562 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.829230562
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/105.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_init_fail.1289148117
Short name T896
Test name
Test status
Simulation time 119257830 ps
CPU time 3.71 seconds
Started Aug 21 07:44:04 PM UTC 24
Finished Aug 21 07:44:09 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1289148117 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.1289148117
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/106.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_parallel_lc_esc.680433619
Short name T920
Test name
Test status
Simulation time 6878370958 ps
CPU time 16.14 seconds
Started Aug 21 07:44:04 PM UTC 24
Finished Aug 21 07:44:22 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=680433619 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.680433619
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/106.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_init_fail.279823625
Short name T898
Test name
Test status
Simulation time 2083277472 ps
CPU time 4.62 seconds
Started Aug 21 07:44:04 PM UTC 24
Finished Aug 21 07:44:10 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=279823625 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.279823625
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/107.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_parallel_lc_esc.3247613113
Short name T897
Test name
Test status
Simulation time 97774021 ps
CPU time 4.64 seconds
Started Aug 21 07:44:04 PM UTC 24
Finished Aug 21 07:44:10 PM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3247613113 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.3247613113
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/107.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_init_fail.1192888600
Short name T180
Test name
Test status
Simulation time 270785497 ps
CPU time 3.81 seconds
Started Aug 21 07:44:04 PM UTC 24
Finished Aug 21 07:44:09 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1192888600 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.1192888600
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/108.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_parallel_lc_esc.2963768754
Short name T907
Test name
Test status
Simulation time 2464720199 ps
CPU time 10.46 seconds
Started Aug 21 07:44:04 PM UTC 24
Finished Aug 21 07:44:16 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2963768754 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.2963768754
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/108.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_init_fail.91659515
Short name T902
Test name
Test status
Simulation time 181430572 ps
CPU time 5.98 seconds
Started Aug 21 07:44:05 PM UTC 24
Finished Aug 21 07:44:12 PM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=91659515 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.91659515
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/109.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_parallel_lc_esc.3957998791
Short name T932
Test name
Test status
Simulation time 3906907864 ps
CPU time 28.87 seconds
Started Aug 21 07:44:05 PM UTC 24
Finished Aug 21 07:44:35 PM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3957998791 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.3957998791
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/109.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_alert_test.3975602505
Short name T315
Test name
Test status
Simulation time 184051368 ps
CPU time 2.6 seconds
Started Aug 21 07:36:39 PM UTC 24
Finished Aug 21 07:36:43 PM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3975602505 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.3975602505
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_check_fail.4109333486
Short name T43
Test name
Test status
Simulation time 828196134 ps
CPU time 24.25 seconds
Started Aug 21 07:36:33 PM UTC 24
Finished Aug 21 07:36:59 PM UTC 24
Peak memory 253396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4109333486 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.4109333486
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_errs.1840681417
Short name T501
Test name
Test status
Simulation time 12029513745 ps
CPU time 34.97 seconds
Started Aug 21 07:36:33 PM UTC 24
Finished Aug 21 07:37:10 PM UTC 24
Peak memory 253696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1840681417 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.1840681417
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_lock.3916423656
Short name T415
Test name
Test status
Simulation time 1025395012 ps
CPU time 15.28 seconds
Started Aug 21 07:36:32 PM UTC 24
Finished Aug 21 07:36:48 PM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3916423656 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.3916423656
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_init_fail.3158306793
Short name T107
Test name
Test status
Simulation time 155833413 ps
CPU time 4.11 seconds
Started Aug 21 07:36:29 PM UTC 24
Finished Aug 21 07:36:34 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3158306793 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.3158306793
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_macro_errs.736587708
Short name T192
Test name
Test status
Simulation time 17889951579 ps
CPU time 51.03 seconds
Started Aug 21 07:36:34 PM UTC 24
Finished Aug 21 07:37:26 PM UTC 24
Peak memory 269976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=736587708 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.736587708
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_esc.2824386779
Short name T318
Test name
Test status
Simulation time 532464765 ps
CPU time 13.41 seconds
Started Aug 21 07:36:31 PM UTC 24
Finished Aug 21 07:36:45 PM UTC 24
Peak memory 251440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2824386779 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.2824386779
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_req.1073688642
Short name T314
Test name
Test status
Simulation time 1434848651 ps
CPU time 10.35 seconds
Started Aug 21 07:36:31 PM UTC 24
Finished Aug 21 07:36:42 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1073688642 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc
_req.1073688642
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_regwen.1796228264
Short name T403
Test name
Test status
Simulation time 186416244 ps
CPU time 4.33 seconds
Started Aug 21 07:36:36 PM UTC 24
Finished Aug 21 07:36:42 PM UTC 24
Peak memory 257632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1796228264 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.1796228264
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_smoke.4220217156
Short name T471
Test name
Test status
Simulation time 1204334539 ps
CPU time 19.02 seconds
Started Aug 21 07:36:29 PM UTC 24
Finished Aug 21 07:36:49 PM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4220217156 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.4220217156
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all.288828768
Short name T317
Test name
Test status
Simulation time 859741637 ps
CPU time 7.33 seconds
Started Aug 21 07:36:36 PM UTC 24
Finished Aug 21 07:36:45 PM UTC 24
Peak memory 251264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=288828768 -
assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_str
ess_all.288828768
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.1576931869
Short name T89
Test name
Test status
Simulation time 20348563421 ps
CPU time 168.4 seconds
Started Aug 21 07:36:36 PM UTC 24
Finished Aug 21 07:39:28 PM UTC 24
Peak memory 274104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1576931869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.1576931869
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_test_access.3835489609
Short name T316
Test name
Test status
Simulation time 588177295 ps
CPU time 5.74 seconds
Started Aug 21 07:36:36 PM UTC 24
Finished Aug 21 07:36:43 PM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3835489609 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.3835489609
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/11.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_init_fail.1669618274
Short name T900
Test name
Test status
Simulation time 194381748 ps
CPU time 5.05 seconds
Started Aug 21 07:44:05 PM UTC 24
Finished Aug 21 07:44:11 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1669618274 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.1669618274
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/110.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_parallel_lc_esc.4262909415
Short name T904
Test name
Test status
Simulation time 283053694 ps
CPU time 8.04 seconds
Started Aug 21 07:44:05 PM UTC 24
Finished Aug 21 07:44:14 PM UTC 24
Peak memory 251152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4262909415 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.4262909415
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/110.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_init_fail.3465820544
Short name T903
Test name
Test status
Simulation time 364537649 ps
CPU time 5.3 seconds
Started Aug 21 07:44:06 PM UTC 24
Finished Aug 21 07:44:13 PM UTC 24
Peak memory 253200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3465820544 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.3465820544
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/111.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_parallel_lc_esc.736007465
Short name T906
Test name
Test status
Simulation time 285862011 ps
CPU time 6.62 seconds
Started Aug 21 07:44:06 PM UTC 24
Finished Aug 21 07:44:14 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=736007465 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.736007465
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/111.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_parallel_lc_esc.1411324469
Short name T949
Test name
Test status
Simulation time 7652550747 ps
CPU time 21.05 seconds
Started Aug 21 07:44:14 PM UTC 24
Finished Aug 21 07:44:37 PM UTC 24
Peak memory 251500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1411324469 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.1411324469
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/112.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_init_fail.3978270519
Short name T915
Test name
Test status
Simulation time 303332660 ps
CPU time 5.33 seconds
Started Aug 21 07:44:14 PM UTC 24
Finished Aug 21 07:44:21 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3978270519 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.3978270519
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/113.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_parallel_lc_esc.3583743636
Short name T912
Test name
Test status
Simulation time 156163317 ps
CPU time 4.04 seconds
Started Aug 21 07:44:14 PM UTC 24
Finished Aug 21 07:44:20 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3583743636 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.3583743636
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/113.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_parallel_lc_esc.2567428450
Short name T914
Test name
Test status
Simulation time 498886148 ps
CPU time 5.28 seconds
Started Aug 21 07:44:14 PM UTC 24
Finished Aug 21 07:44:21 PM UTC 24
Peak memory 257328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2567428450 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.2567428450
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/114.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_init_fail.3720680962
Short name T913
Test name
Test status
Simulation time 125341308 ps
CPU time 3.96 seconds
Started Aug 21 07:44:14 PM UTC 24
Finished Aug 21 07:44:20 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3720680962 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.3720680962
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/115.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_parallel_lc_esc.3270415770
Short name T916
Test name
Test status
Simulation time 173924225 ps
CPU time 5.22 seconds
Started Aug 21 07:44:14 PM UTC 24
Finished Aug 21 07:44:21 PM UTC 24
Peak memory 251152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3270415770 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.3270415770
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/115.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_init_fail.2351162245
Short name T921
Test name
Test status
Simulation time 451499858 ps
CPU time 5.87 seconds
Started Aug 21 07:44:14 PM UTC 24
Finished Aug 21 07:44:22 PM UTC 24
Peak memory 253172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2351162245 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.2351162245
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/116.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_parallel_lc_esc.968049288
Short name T917
Test name
Test status
Simulation time 183709205 ps
CPU time 5.22 seconds
Started Aug 21 07:44:15 PM UTC 24
Finished Aug 21 07:44:21 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=968049288 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.968049288
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/116.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_init_fail.419730399
Short name T919
Test name
Test status
Simulation time 504202165 ps
CPU time 5.69 seconds
Started Aug 21 07:44:15 PM UTC 24
Finished Aug 21 07:44:22 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=419730399 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.419730399
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/118.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_parallel_lc_esc.1464218747
Short name T931
Test name
Test status
Simulation time 225171031 ps
CPU time 11.39 seconds
Started Aug 21 07:44:15 PM UTC 24
Finished Aug 21 07:44:28 PM UTC 24
Peak memory 251408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1464218747 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.1464218747
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/118.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_init_fail.1108257418
Short name T911
Test name
Test status
Simulation time 224111081 ps
CPU time 3.28 seconds
Started Aug 21 07:44:15 PM UTC 24
Finished Aug 21 07:44:19 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1108257418 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.1108257418
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/119.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_parallel_lc_esc.8110604
Short name T910
Test name
Test status
Simulation time 138820388 ps
CPU time 3.23 seconds
Started Aug 21 07:44:15 PM UTC 24
Finished Aug 21 07:44:19 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=8110604 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.8110604
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/119.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_alert_test.1829003113
Short name T358
Test name
Test status
Simulation time 93965378 ps
CPU time 1.86 seconds
Started Aug 21 07:36:45 PM UTC 24
Finished Aug 21 07:36:48 PM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1829003113 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.1829003113
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_check_fail.1343197079
Short name T44
Test name
Test status
Simulation time 1540653322 ps
CPU time 20.81 seconds
Started Aug 21 07:36:42 PM UTC 24
Finished Aug 21 07:37:04 PM UTC 24
Peak memory 253464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1343197079 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.1343197079
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_errs.2965321159
Short name T379
Test name
Test status
Simulation time 283894636 ps
CPU time 18.6 seconds
Started Aug 21 07:36:42 PM UTC 24
Finished Aug 21 07:37:02 PM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2965321159 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.2965321159
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_init_fail.2753010025
Short name T183
Test name
Test status
Simulation time 500515724 ps
CPU time 5.5 seconds
Started Aug 21 07:36:39 PM UTC 24
Finished Aug 21 07:36:46 PM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2753010025 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.2753010025
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_macro_errs.4140577478
Short name T493
Test name
Test status
Simulation time 4587149294 ps
CPU time 11.31 seconds
Started Aug 21 07:36:44 PM UTC 24
Finished Aug 21 07:36:57 PM UTC 24
Peak memory 257600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4140577478 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.4140577478
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_key_req.2071040441
Short name T279
Test name
Test status
Simulation time 4375669277 ps
CPU time 23.69 seconds
Started Aug 21 07:36:44 PM UTC 24
Finished Aug 21 07:37:09 PM UTC 24
Peak memory 251408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2071040441 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.2071040441
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_esc.1043328728
Short name T281
Test name
Test status
Simulation time 2915513396 ps
CPU time 18.47 seconds
Started Aug 21 07:36:39 PM UTC 24
Finished Aug 21 07:36:59 PM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1043328728 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.1043328728
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_req.71269988
Short name T356
Test name
Test status
Simulation time 482640843 ps
CPU time 7.08 seconds
Started Aug 21 07:36:39 PM UTC 24
Finished Aug 21 07:36:47 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=71269988 -assert nopostpr
oc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.71269988
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_regwen.2686493419
Short name T398
Test name
Test status
Simulation time 352065220 ps
CPU time 10.71 seconds
Started Aug 21 07:36:44 PM UTC 24
Finished Aug 21 07:36:56 PM UTC 24
Peak memory 251300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2686493419 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.2686493419
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_smoke.550624356
Short name T357
Test name
Test status
Simulation time 352060705 ps
CPU time 7.42 seconds
Started Aug 21 07:36:39 PM UTC 24
Finished Aug 21 07:36:47 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=550624356 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.550624356
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all.4134697437
Short name T108
Test name
Test status
Simulation time 5370329638 ps
CPU time 57.82 seconds
Started Aug 21 07:36:45 PM UTC 24
Finished Aug 21 07:37:44 PM UTC 24
Peak memory 257912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4134697437
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_st
ress_all.4134697437
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.1448410054
Short name T292
Test name
Test status
Simulation time 2947091361 ps
CPU time 60.54 seconds
Started Aug 21 07:36:45 PM UTC 24
Finished Aug 21 07:37:47 PM UTC 24
Peak memory 257604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1448410054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.1448410054
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_init_fail.3416967581
Short name T918
Test name
Test status
Simulation time 95814722 ps
CPU time 3.53 seconds
Started Aug 21 07:44:17 PM UTC 24
Finished Aug 21 07:44:22 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3416967581 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.3416967581
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/120.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_parallel_lc_esc.3393717078
Short name T924
Test name
Test status
Simulation time 320275929 ps
CPU time 5.73 seconds
Started Aug 21 07:44:17 PM UTC 24
Finished Aug 21 07:44:24 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3393717078 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.3393717078
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/120.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_init_fail.2287813685
Short name T923
Test name
Test status
Simulation time 183763763 ps
CPU time 4.58 seconds
Started Aug 21 07:44:17 PM UTC 24
Finished Aug 21 07:44:23 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2287813685 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.2287813685
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/121.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_parallel_lc_esc.3664090530
Short name T940
Test name
Test status
Simulation time 1207012575 ps
CPU time 16.87 seconds
Started Aug 21 07:44:17 PM UTC 24
Finished Aug 21 07:44:35 PM UTC 24
Peak memory 251504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3664090530 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.3664090530
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/121.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_init_fail.1287475215
Short name T922
Test name
Test status
Simulation time 422085085 ps
CPU time 4.46 seconds
Started Aug 21 07:44:17 PM UTC 24
Finished Aug 21 07:44:23 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1287475215 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.1287475215
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/122.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_parallel_lc_esc.359422544
Short name T925
Test name
Test status
Simulation time 121666724 ps
CPU time 3.15 seconds
Started Aug 21 07:44:20 PM UTC 24
Finished Aug 21 07:44:24 PM UTC 24
Peak memory 251152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=359422544 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.359422544
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/122.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_init_fail.803581132
Short name T929
Test name
Test status
Simulation time 2047625161 ps
CPU time 4.75 seconds
Started Aug 21 07:44:20 PM UTC 24
Finished Aug 21 07:44:26 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=803581132 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.803581132
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/123.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_parallel_lc_esc.1089096647
Short name T930
Test name
Test status
Simulation time 179735525 ps
CPU time 5.09 seconds
Started Aug 21 07:44:20 PM UTC 24
Finished Aug 21 07:44:26 PM UTC 24
Peak memory 253232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1089096647 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.1089096647
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/123.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_init_fail.4035184891
Short name T928
Test name
Test status
Simulation time 238187322 ps
CPU time 4.39 seconds
Started Aug 21 07:44:20 PM UTC 24
Finished Aug 21 07:44:26 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4035184891 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.4035184891
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/124.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_parallel_lc_esc.3541593526
Short name T927
Test name
Test status
Simulation time 79835322 ps
CPU time 3.38 seconds
Started Aug 21 07:44:20 PM UTC 24
Finished Aug 21 07:44:25 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3541593526 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.3541593526
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/124.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_init_fail.1393800059
Short name T938
Test name
Test status
Simulation time 193563863 ps
CPU time 5.33 seconds
Started Aug 21 07:44:24 PM UTC 24
Finished Aug 21 07:44:30 PM UTC 24
Peak memory 251516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1393800059 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.1393800059
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/125.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_parallel_lc_esc.2541288852
Short name T955
Test name
Test status
Simulation time 1223994840 ps
CPU time 16.44 seconds
Started Aug 21 07:44:24 PM UTC 24
Finished Aug 21 07:44:41 PM UTC 24
Peak memory 253488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2541288852 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.2541288852
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/125.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_init_fail.1323780133
Short name T62
Test name
Test status
Simulation time 548559730 ps
CPU time 5.54 seconds
Started Aug 21 07:44:24 PM UTC 24
Finished Aug 21 07:44:30 PM UTC 24
Peak memory 251324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1323780133 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.1323780133
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/126.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_parallel_lc_esc.576356013
Short name T967
Test name
Test status
Simulation time 667243896 ps
CPU time 19.95 seconds
Started Aug 21 07:44:24 PM UTC 24
Finished Aug 21 07:44:45 PM UTC 24
Peak memory 251180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=576356013 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.576356013
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/126.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_parallel_lc_esc.250279632
Short name T935
Test name
Test status
Simulation time 98404001 ps
CPU time 4.09 seconds
Started Aug 21 07:44:24 PM UTC 24
Finished Aug 21 07:44:29 PM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=250279632 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.250279632
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/127.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_init_fail.4103058418
Short name T70
Test name
Test status
Simulation time 247997521 ps
CPU time 4.47 seconds
Started Aug 21 07:44:24 PM UTC 24
Finished Aug 21 07:44:30 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4103058418 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.4103058418
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/128.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_parallel_lc_esc.560533223
Short name T941
Test name
Test status
Simulation time 782871931 ps
CPU time 5.64 seconds
Started Aug 21 07:44:24 PM UTC 24
Finished Aug 21 07:44:31 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=560533223 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.560533223
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/128.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_init_fail.1113346192
Short name T937
Test name
Test status
Simulation time 139251060 ps
CPU time 4.58 seconds
Started Aug 21 07:44:24 PM UTC 24
Finished Aug 21 07:44:30 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1113346192 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.1113346192
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/129.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_parallel_lc_esc.1154077222
Short name T979
Test name
Test status
Simulation time 1095449704 ps
CPU time 23.29 seconds
Started Aug 21 07:44:24 PM UTC 24
Finished Aug 21 07:44:49 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1154077222 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.1154077222
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/129.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_alert_test.1897712917
Short name T494
Test name
Test status
Simulation time 57644747 ps
CPU time 2.75 seconds
Started Aug 21 07:36:54 PM UTC 24
Finished Aug 21 07:36:58 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1897712917 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.1897712917
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_check_fail.871595071
Short name T439
Test name
Test status
Simulation time 2589871522 ps
CPU time 26.16 seconds
Started Aug 21 07:36:48 PM UTC 24
Finished Aug 21 07:37:16 PM UTC 24
Peak memory 257560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=871595071 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.871595071
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_errs.2941723057
Short name T264
Test name
Test status
Simulation time 3110826851 ps
CPU time 11.08 seconds
Started Aug 21 07:36:48 PM UTC 24
Finished Aug 21 07:37:00 PM UTC 24
Peak memory 251524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2941723057 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.2941723057
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_lock.2910064144
Short name T498
Test name
Test status
Simulation time 695948599 ps
CPU time 15.49 seconds
Started Aug 21 07:36:48 PM UTC 24
Finished Aug 21 07:37:05 PM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2910064144 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.2910064144
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_init_fail.3093501442
Short name T184
Test name
Test status
Simulation time 361557382 ps
CPU time 5.82 seconds
Started Aug 21 07:36:46 PM UTC 24
Finished Aug 21 07:36:53 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3093501442 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.3093501442
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_macro_errs.3753259833
Short name T249
Test name
Test status
Simulation time 1104856827 ps
CPU time 28.29 seconds
Started Aug 21 07:36:48 PM UTC 24
Finished Aug 21 07:37:18 PM UTC 24
Peak memory 257496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3753259833 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.3753259833
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_key_req.99591770
Short name T495
Test name
Test status
Simulation time 252518461 ps
CPU time 10.03 seconds
Started Aug 21 07:36:48 PM UTC 24
Finished Aug 21 07:37:00 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=99591770 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.99591770
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_esc.3185875537
Short name T491
Test name
Test status
Simulation time 558919058 ps
CPU time 5.86 seconds
Started Aug 21 07:36:46 PM UTC 24
Finished Aug 21 07:36:53 PM UTC 24
Peak memory 253164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3185875537 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.3185875537
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_req.1723610203
Short name T446
Test name
Test status
Simulation time 2181385028 ps
CPU time 17.44 seconds
Started Aug 21 07:36:46 PM UTC 24
Finished Aug 21 07:37:05 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1723610203 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc
_req.1723610203
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_regwen.1483129521
Short name T492
Test name
Test status
Simulation time 441404721 ps
CPU time 4.93 seconds
Started Aug 21 07:36:48 PM UTC 24
Finished Aug 21 07:36:54 PM UTC 24
Peak memory 251236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1483129521 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.1483129521
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_smoke.2282875748
Short name T490
Test name
Test status
Simulation time 215569487 ps
CPU time 5.77 seconds
Started Aug 21 07:36:46 PM UTC 24
Finished Aug 21 07:36:53 PM UTC 24
Peak memory 251404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2282875748 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.2282875748
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all.706021939
Short name T436
Test name
Test status
Simulation time 2683042082 ps
CPU time 25.06 seconds
Started Aug 21 07:36:51 PM UTC 24
Finished Aug 21 07:37:18 PM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=706021939 -
assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_str
ess_all.706021939
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all_with_rand_reset.3259175383
Short name T271
Test name
Test status
Simulation time 7060720647 ps
CPU time 72.67 seconds
Started Aug 21 07:36:51 PM UTC 24
Finished Aug 21 07:38:06 PM UTC 24
Peak memory 267868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3259175383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.3259175383
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_test_access.1648154336
Short name T467
Test name
Test status
Simulation time 2232345351 ps
CPU time 33.82 seconds
Started Aug 21 07:36:50 PM UTC 24
Finished Aug 21 07:37:25 PM UTC 24
Peak memory 251636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1648154336 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.1648154336
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/13.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_parallel_lc_esc.1458307566
Short name T933
Test name
Test status
Simulation time 1164433995 ps
CPU time 2.78 seconds
Started Aug 21 07:44:24 PM UTC 24
Finished Aug 21 07:44:28 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1458307566 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.1458307566
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/130.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_init_fail.1949278820
Short name T939
Test name
Test status
Simulation time 195877620 ps
CPU time 4.92 seconds
Started Aug 21 07:44:24 PM UTC 24
Finished Aug 21 07:44:30 PM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1949278820 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.1949278820
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/131.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_parallel_lc_esc.3811783700
Short name T945
Test name
Test status
Simulation time 178724594 ps
CPU time 7.14 seconds
Started Aug 21 07:44:27 PM UTC 24
Finished Aug 21 07:44:36 PM UTC 24
Peak memory 251152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3811783700 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.3811783700
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/131.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_init_fail.4014112010
Short name T891
Test name
Test status
Simulation time 175130034 ps
CPU time 4.84 seconds
Started Aug 21 07:44:28 PM UTC 24
Finished Aug 21 07:44:33 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4014112010 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.4014112010
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/132.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_parallel_lc_esc.2916100668
Short name T886
Test name
Test status
Simulation time 1850717552 ps
CPU time 4.66 seconds
Started Aug 21 07:44:28 PM UTC 24
Finished Aug 21 07:44:33 PM UTC 24
Peak memory 251312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2916100668 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.2916100668
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/132.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_init_fail.1609159147
Short name T944
Test name
Test status
Simulation time 606298481 ps
CPU time 4.55 seconds
Started Aug 21 07:44:28 PM UTC 24
Finished Aug 21 07:44:33 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1609159147 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.1609159147
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/133.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_parallel_lc_esc.3965159617
Short name T908
Test name
Test status
Simulation time 465844354 ps
CPU time 4.78 seconds
Started Aug 21 07:44:28 PM UTC 24
Finished Aug 21 07:44:34 PM UTC 24
Peak memory 251152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3965159617 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.3965159617
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/133.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_init_fail.1389127299
Short name T38
Test name
Test status
Simulation time 176077514 ps
CPU time 3.44 seconds
Started Aug 21 07:44:28 PM UTC 24
Finished Aug 21 07:44:32 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1389127299 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.1389127299
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/134.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_init_fail.2410080000
Short name T943
Test name
Test status
Simulation time 215926512 ps
CPU time 4.3 seconds
Started Aug 21 07:44:28 PM UTC 24
Finished Aug 21 07:44:33 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2410080000 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.2410080000
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/135.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_parallel_lc_esc.1896010257
Short name T942
Test name
Test status
Simulation time 215764714 ps
CPU time 6.28 seconds
Started Aug 21 07:44:28 PM UTC 24
Finished Aug 21 07:44:35 PM UTC 24
Peak memory 253456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1896010257 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.1896010257
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/135.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_init_fail.2634066059
Short name T950
Test name
Test status
Simulation time 231025935 ps
CPU time 4.94 seconds
Started Aug 21 07:44:31 PM UTC 24
Finished Aug 21 07:44:37 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2634066059 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.2634066059
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/136.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_parallel_lc_esc.4222655275
Short name T951
Test name
Test status
Simulation time 239347183 ps
CPU time 5.06 seconds
Started Aug 21 07:44:31 PM UTC 24
Finished Aug 21 07:44:37 PM UTC 24
Peak memory 251180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4222655275 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.4222655275
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/136.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_init_fail.1968534413
Short name T948
Test name
Test status
Simulation time 336723503 ps
CPU time 4.33 seconds
Started Aug 21 07:44:31 PM UTC 24
Finished Aug 21 07:44:37 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1968534413 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.1968534413
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/137.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_parallel_lc_esc.2315674117
Short name T986
Test name
Test status
Simulation time 903977435 ps
CPU time 18.12 seconds
Started Aug 21 07:44:31 PM UTC 24
Finished Aug 21 07:44:51 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2315674117 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.2315674117
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/137.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_init_fail.3545650763
Short name T946
Test name
Test status
Simulation time 160831767 ps
CPU time 4.19 seconds
Started Aug 21 07:44:31 PM UTC 24
Finished Aug 21 07:44:37 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3545650763 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.3545650763
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/138.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_init_fail.3921808237
Short name T947
Test name
Test status
Simulation time 1733186388 ps
CPU time 4.16 seconds
Started Aug 21 07:44:31 PM UTC 24
Finished Aug 21 07:44:37 PM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3921808237 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.3921808237
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/139.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_parallel_lc_esc.2448111331
Short name T957
Test name
Test status
Simulation time 2607897074 ps
CPU time 9.26 seconds
Started Aug 21 07:44:32 PM UTC 24
Finished Aug 21 07:44:42 PM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2448111331 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.2448111331
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/139.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_alert_test.1168134890
Short name T500
Test name
Test status
Simulation time 191562777 ps
CPU time 3.24 seconds
Started Aug 21 07:37:04 PM UTC 24
Finished Aug 21 07:37:08 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1168134890 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.1168134890
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_check_fail.864813538
Short name T499
Test name
Test status
Simulation time 541071150 ps
CPU time 6.73 seconds
Started Aug 21 07:36:58 PM UTC 24
Finished Aug 21 07:37:06 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=864813538 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.864813538
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_errs.795235103
Short name T366
Test name
Test status
Simulation time 21255310851 ps
CPU time 52.56 seconds
Started Aug 21 07:36:58 PM UTC 24
Finished Aug 21 07:37:53 PM UTC 24
Peak memory 259316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=795235103 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.795235103
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_lock.2543664211
Short name T511
Test name
Test status
Simulation time 3133334280 ps
CPU time 31.93 seconds
Started Aug 21 07:36:58 PM UTC 24
Finished Aug 21 07:37:32 PM UTC 24
Peak memory 253848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2543664211 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.2543664211
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_init_fail.2563018563
Short name T220
Test name
Test status
Simulation time 1942122932 ps
CPU time 7.75 seconds
Started Aug 21 07:36:54 PM UTC 24
Finished Aug 21 07:37:03 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2563018563 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.2563018563
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_key_req.1442364013
Short name T438
Test name
Test status
Simulation time 3598502788 ps
CPU time 21.89 seconds
Started Aug 21 07:37:00 PM UTC 24
Finished Aug 21 07:37:23 PM UTC 24
Peak memory 257528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1442364013 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.1442364013
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_esc.1500081309
Short name T497
Test name
Test status
Simulation time 121099746 ps
CPU time 6.53 seconds
Started Aug 21 07:36:55 PM UTC 24
Finished Aug 21 07:37:03 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1500081309 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.1500081309
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_req.1893786652
Short name T466
Test name
Test status
Simulation time 2607021737 ps
CPU time 24.22 seconds
Started Aug 21 07:36:54 PM UTC 24
Finished Aug 21 07:37:20 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1893786652 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc
_req.1893786652
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_regwen.3119801086
Short name T400
Test name
Test status
Simulation time 1074424045 ps
CPU time 11.23 seconds
Started Aug 21 07:37:02 PM UTC 24
Finished Aug 21 07:37:14 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3119801086 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.3119801086
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_smoke.4244521731
Short name T496
Test name
Test status
Simulation time 200836859 ps
CPU time 6.38 seconds
Started Aug 21 07:36:54 PM UTC 24
Finished Aug 21 07:37:02 PM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4244521731 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.4244521731
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all.2305097012
Short name T426
Test name
Test status
Simulation time 30653711110 ps
CPU time 268.93 seconds
Started Aug 21 07:37:03 PM UTC 24
Finished Aug 21 07:41:36 PM UTC 24
Peak memory 290360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2305097012
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_st
ress_all.2305097012
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all_with_rand_reset.24422367
Short name T21
Test name
Test status
Simulation time 15501917951 ps
CPU time 124.57 seconds
Started Aug 21 07:37:02 PM UTC 24
Finished Aug 21 07:39:09 PM UTC 24
Peak memory 267928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24422367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs
/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.24422367
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_test_access.3639612615
Short name T502
Test name
Test status
Simulation time 587112341 ps
CPU time 9.64 seconds
Started Aug 21 07:37:02 PM UTC 24
Finished Aug 21 07:37:13 PM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3639612615 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.3639612615
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/14.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_init_fail.3221586754
Short name T81
Test name
Test status
Simulation time 301004428 ps
CPU time 2.96 seconds
Started Aug 21 07:44:32 PM UTC 24
Finished Aug 21 07:44:36 PM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3221586754 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.3221586754
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/140.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_parallel_lc_esc.3169500791
Short name T952
Test name
Test status
Simulation time 77255522 ps
CPU time 2.24 seconds
Started Aug 21 07:44:36 PM UTC 24
Finished Aug 21 07:44:39 PM UTC 24
Peak memory 253428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3169500791 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.3169500791
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/140.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_init_fail.2289702961
Short name T63
Test name
Test status
Simulation time 589321506 ps
CPU time 5.24 seconds
Started Aug 21 07:44:36 PM UTC 24
Finished Aug 21 07:44:42 PM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2289702961 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.2289702961
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/141.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_parallel_lc_esc.1129625745
Short name T964
Test name
Test status
Simulation time 256157535 ps
CPU time 6.86 seconds
Started Aug 21 07:44:36 PM UTC 24
Finished Aug 21 07:44:44 PM UTC 24
Peak memory 251152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1129625745 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.1129625745
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/141.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_init_fail.2877352512
Short name T963
Test name
Test status
Simulation time 1697795678 ps
CPU time 5.6 seconds
Started Aug 21 07:44:36 PM UTC 24
Finished Aug 21 07:44:43 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2877352512 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.2877352512
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/142.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_parallel_lc_esc.3288155008
Short name T953
Test name
Test status
Simulation time 178526108 ps
CPU time 2.78 seconds
Started Aug 21 07:44:36 PM UTC 24
Finished Aug 21 07:44:40 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3288155008 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.3288155008
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/142.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_init_fail.3225983747
Short name T954
Test name
Test status
Simulation time 2045201970 ps
CPU time 4.1 seconds
Started Aug 21 07:44:36 PM UTC 24
Finished Aug 21 07:44:41 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3225983747 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.3225983747
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/143.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_parallel_lc_esc.896746309
Short name T1013
Test name
Test status
Simulation time 11241658299 ps
CPU time 25.16 seconds
Started Aug 21 07:44:36 PM UTC 24
Finished Aug 21 07:45:03 PM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=896746309 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.896746309
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/143.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_init_fail.4134623766
Short name T965
Test name
Test status
Simulation time 2392762912 ps
CPU time 6.91 seconds
Started Aug 21 07:44:36 PM UTC 24
Finished Aug 21 07:44:44 PM UTC 24
Peak memory 251236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4134623766 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.4134623766
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/144.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_parallel_lc_esc.2711400480
Short name T969
Test name
Test status
Simulation time 628632939 ps
CPU time 7.96 seconds
Started Aug 21 07:44:36 PM UTC 24
Finished Aug 21 07:44:45 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2711400480 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.2711400480
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/144.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_init_fail.2013904894
Short name T958
Test name
Test status
Simulation time 274046967 ps
CPU time 4.55 seconds
Started Aug 21 07:44:36 PM UTC 24
Finished Aug 21 07:44:42 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2013904894 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.2013904894
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/145.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_parallel_lc_esc.1692161173
Short name T984
Test name
Test status
Simulation time 457067109 ps
CPU time 12.33 seconds
Started Aug 21 07:44:36 PM UTC 24
Finished Aug 21 07:44:50 PM UTC 24
Peak memory 257324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1692161173 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.1692161173
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/145.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_parallel_lc_esc.2447489020
Short name T976
Test name
Test status
Simulation time 713192495 ps
CPU time 10.04 seconds
Started Aug 21 07:44:37 PM UTC 24
Finished Aug 21 07:44:48 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2447489020 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.2447489020
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/146.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_init_fail.2343119448
Short name T962
Test name
Test status
Simulation time 101009468 ps
CPU time 4.74 seconds
Started Aug 21 07:44:37 PM UTC 24
Finished Aug 21 07:44:42 PM UTC 24
Peak memory 251232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2343119448 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.2343119448
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/147.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_parallel_lc_esc.784688516
Short name T971
Test name
Test status
Simulation time 119610148 ps
CPU time 4.94 seconds
Started Aug 21 07:44:40 PM UTC 24
Finished Aug 21 07:44:46 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=784688516 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.784688516
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/147.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_init_fail.1133922438
Short name T51
Test name
Test status
Simulation time 478140591 ps
CPU time 3.9 seconds
Started Aug 21 07:44:40 PM UTC 24
Finished Aug 21 07:44:45 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1133922438 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.1133922438
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/148.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_parallel_lc_esc.605747344
Short name T968
Test name
Test status
Simulation time 178627474 ps
CPU time 4.07 seconds
Started Aug 21 07:44:40 PM UTC 24
Finished Aug 21 07:44:45 PM UTC 24
Peak memory 251152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=605747344 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.605747344
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/148.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_init_fail.3383171062
Short name T970
Test name
Test status
Simulation time 284603931 ps
CPU time 4.23 seconds
Started Aug 21 07:44:40 PM UTC 24
Finished Aug 21 07:44:45 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3383171062 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.3383171062
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/149.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_parallel_lc_esc.3861071990
Short name T978
Test name
Test status
Simulation time 175654144 ps
CPU time 7.33 seconds
Started Aug 21 07:44:40 PM UTC 24
Finished Aug 21 07:44:49 PM UTC 24
Peak memory 251152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3861071990 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.3861071990
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/149.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_alert_test.2070054078
Short name T503
Test name
Test status
Simulation time 102191310 ps
CPU time 3.26 seconds
Started Aug 21 07:37:12 PM UTC 24
Finished Aug 21 07:37:16 PM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2070054078 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.2070054078
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/15.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_check_fail.3342249051
Short name T75
Test name
Test status
Simulation time 7704311715 ps
CPU time 20.99 seconds
Started Aug 21 07:37:07 PM UTC 24
Finished Aug 21 07:37:30 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3342249051 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.3342249051
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/15.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_lock.292422787
Short name T437
Test name
Test status
Simulation time 5926683721 ps
CPU time 32.12 seconds
Started Aug 21 07:37:07 PM UTC 24
Finished Aug 21 07:37:41 PM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=292422787 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.292422787
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/15.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_macro_errs.3744526515
Short name T201
Test name
Test status
Simulation time 1560370654 ps
CPU time 20.79 seconds
Started Aug 21 07:37:07 PM UTC 24
Finished Aug 21 07:37:29 PM UTC 24
Peak memory 253632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3744526515 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.3744526515
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/15.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_key_req.3487744985
Short name T513
Test name
Test status
Simulation time 2883663675 ps
CPU time 20.57 seconds
Started Aug 21 07:37:11 PM UTC 24
Finished Aug 21 07:37:33 PM UTC 24
Peak memory 253456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3487744985 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.3487744985
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_esc.3908756631
Short name T375
Test name
Test status
Simulation time 576824080 ps
CPU time 7.09 seconds
Started Aug 21 07:37:07 PM UTC 24
Finished Aug 21 07:37:15 PM UTC 24
Peak memory 251408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3908756631 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.3908756631
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_req.3027797167
Short name T456
Test name
Test status
Simulation time 469065086 ps
CPU time 17.09 seconds
Started Aug 21 07:37:07 PM UTC 24
Finished Aug 21 07:37:25 PM UTC 24
Peak memory 257544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3027797167 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc
_req.3027797167
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_regwen.4252409752
Short name T401
Test name
Test status
Simulation time 226708788 ps
CPU time 8.99 seconds
Started Aug 21 07:37:11 PM UTC 24
Finished Aug 21 07:37:21 PM UTC 24
Peak memory 251552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4252409752 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.4252409752
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/15.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_smoke.463084324
Short name T505
Test name
Test status
Simulation time 277965271 ps
CPU time 12.99 seconds
Started Aug 21 07:37:07 PM UTC 24
Finished Aug 21 07:37:21 PM UTC 24
Peak memory 251232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=463084324 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.463084324
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/15.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all.360624604
Short name T470
Test name
Test status
Simulation time 36784544705 ps
CPU time 358.89 seconds
Started Aug 21 07:37:12 PM UTC 24
Finished Aug 21 07:43:16 PM UTC 24
Peak memory 290264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=360624604 -
assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_str
ess_all.360624604
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_test_access.4153428376
Short name T412
Test name
Test status
Simulation time 3578709704 ps
CPU time 12.81 seconds
Started Aug 21 07:37:11 PM UTC 24
Finished Aug 21 07:37:26 PM UTC 24
Peak memory 251440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4153428376 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.4153428376
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/15.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_init_fail.3189502405
Short name T973
Test name
Test status
Simulation time 252890777 ps
CPU time 5.31 seconds
Started Aug 21 07:44:40 PM UTC 24
Finished Aug 21 07:44:47 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3189502405 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.3189502405
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/150.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_parallel_lc_esc.2495397686
Short name T981
Test name
Test status
Simulation time 146046553 ps
CPU time 7.72 seconds
Started Aug 21 07:44:40 PM UTC 24
Finished Aug 21 07:44:49 PM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2495397686 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.2495397686
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/150.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_init_fail.3359462073
Short name T977
Test name
Test status
Simulation time 2741858565 ps
CPU time 7.08 seconds
Started Aug 21 07:44:40 PM UTC 24
Finished Aug 21 07:44:48 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3359462073 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.3359462073
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/151.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_parallel_lc_esc.3622008528
Short name T966
Test name
Test status
Simulation time 106528915 ps
CPU time 3.2 seconds
Started Aug 21 07:44:40 PM UTC 24
Finished Aug 21 07:44:45 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3622008528 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.3622008528
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/151.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_init_fail.396553019
Short name T972
Test name
Test status
Simulation time 2025320245 ps
CPU time 4.84 seconds
Started Aug 21 07:44:40 PM UTC 24
Finished Aug 21 07:44:46 PM UTC 24
Peak memory 251456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=396553019 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.396553019
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/152.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_parallel_lc_esc.1762239017
Short name T453
Test name
Test status
Simulation time 659260338 ps
CPU time 15.22 seconds
Started Aug 21 07:44:40 PM UTC 24
Finished Aug 21 07:44:57 PM UTC 24
Peak memory 251440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1762239017 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.1762239017
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/152.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_init_fail.2322621738
Short name T982
Test name
Test status
Simulation time 2258011831 ps
CPU time 5.99 seconds
Started Aug 21 07:44:42 PM UTC 24
Finished Aug 21 07:44:49 PM UTC 24
Peak memory 251576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2322621738 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.2322621738
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/153.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_parallel_lc_esc.233618093
Short name T974
Test name
Test status
Simulation time 233610297 ps
CPU time 3.36 seconds
Started Aug 21 07:44:42 PM UTC 24
Finished Aug 21 07:44:47 PM UTC 24
Peak memory 251376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=233618093 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.233618093
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/153.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_init_fail.2379970261
Short name T975
Test name
Test status
Simulation time 142039971 ps
CPU time 3.84 seconds
Started Aug 21 07:44:42 PM UTC 24
Finished Aug 21 07:44:47 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2379970261 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.2379970261
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/154.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_parallel_lc_esc.3061659228
Short name T1024
Test name
Test status
Simulation time 914720722 ps
CPU time 19.3 seconds
Started Aug 21 07:44:48 PM UTC 24
Finished Aug 21 07:45:09 PM UTC 24
Peak memory 251368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3061659228 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.3061659228
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/154.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_init_fail.3810015486
Short name T990
Test name
Test status
Simulation time 113255536 ps
CPU time 3.09 seconds
Started Aug 21 07:44:48 PM UTC 24
Finished Aug 21 07:44:52 PM UTC 24
Peak memory 253340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3810015486 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.3810015486
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/155.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_init_fail.2836554980
Short name T991
Test name
Test status
Simulation time 149219736 ps
CPU time 3.58 seconds
Started Aug 21 07:44:48 PM UTC 24
Finished Aug 21 07:44:53 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2836554980 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.2836554980
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/156.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_parallel_lc_esc.4150540337
Short name T995
Test name
Test status
Simulation time 1197162204 ps
CPU time 4.88 seconds
Started Aug 21 07:44:48 PM UTC 24
Finished Aug 21 07:44:54 PM UTC 24
Peak memory 251344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4150540337 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.4150540337
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/156.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_parallel_lc_esc.1693674713
Short name T993
Test name
Test status
Simulation time 1323691345 ps
CPU time 3.96 seconds
Started Aug 21 07:44:48 PM UTC 24
Finished Aug 21 07:44:53 PM UTC 24
Peak memory 251372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1693674713 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.1693674713
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/157.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_init_fail.3891522360
Short name T73
Test name
Test status
Simulation time 301660134 ps
CPU time 3.13 seconds
Started Aug 21 07:44:48 PM UTC 24
Finished Aug 21 07:44:53 PM UTC 24
Peak memory 253476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3891522360 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.3891522360
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/158.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_parallel_lc_esc.2411996445
Short name T989
Test name
Test status
Simulation time 604320556 ps
CPU time 10.42 seconds
Started Aug 21 07:44:49 PM UTC 24
Finished Aug 21 07:45:00 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2411996445 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.2411996445
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/158.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_init_fail.1268519632
Short name T992
Test name
Test status
Simulation time 129093612 ps
CPU time 3.63 seconds
Started Aug 21 07:44:49 PM UTC 24
Finished Aug 21 07:44:53 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1268519632 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.1268519632
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/159.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_parallel_lc_esc.4064221496
Short name T956
Test name
Test status
Simulation time 2598223640 ps
CPU time 9.96 seconds
Started Aug 21 07:44:49 PM UTC 24
Finished Aug 21 07:45:00 PM UTC 24
Peak memory 251208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4064221496 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.4064221496
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/159.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_alert_test.2171441239
Short name T507
Test name
Test status
Simulation time 80735586 ps
CPU time 2.78 seconds
Started Aug 21 07:37:22 PM UTC 24
Finished Aug 21 07:37:25 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2171441239 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.2171441239
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_check_fail.3019429114
Short name T508
Test name
Test status
Simulation time 205432678 ps
CPU time 7.79 seconds
Started Aug 21 07:37:17 PM UTC 24
Finished Aug 21 07:37:26 PM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3019429114 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.3019429114
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_errs.2075024748
Short name T377
Test name
Test status
Simulation time 959822304 ps
CPU time 27.09 seconds
Started Aug 21 07:37:17 PM UTC 24
Finished Aug 21 07:37:45 PM UTC 24
Peak memory 253444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2075024748 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.2075024748
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_lock.2426006973
Short name T504
Test name
Test status
Simulation time 101748646 ps
CPU time 3.78 seconds
Started Aug 21 07:37:15 PM UTC 24
Finished Aug 21 07:37:20 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2426006973 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.2426006973
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_init_fail.2984692704
Short name T61
Test name
Test status
Simulation time 113732933 ps
CPU time 5.63 seconds
Started Aug 21 07:37:15 PM UTC 24
Finished Aug 21 07:37:22 PM UTC 24
Peak memory 251208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2984692704 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.2984692704
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_macro_errs.1276771991
Short name T454
Test name
Test status
Simulation time 9153395904 ps
CPU time 19.59 seconds
Started Aug 21 07:37:17 PM UTC 24
Finished Aug 21 07:37:38 PM UTC 24
Peak memory 253460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1276771991 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.1276771991
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_key_req.3060575415
Short name T421
Test name
Test status
Simulation time 1067893584 ps
CPU time 22.25 seconds
Started Aug 21 07:37:17 PM UTC 24
Finished Aug 21 07:37:41 PM UTC 24
Peak memory 251312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3060575415 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.3060575415
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_esc.2410706032
Short name T472
Test name
Test status
Simulation time 237810667 ps
CPU time 10.51 seconds
Started Aug 21 07:37:15 PM UTC 24
Finished Aug 21 07:37:27 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2410706032 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.2410706032
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_req.2867133713
Short name T427
Test name
Test status
Simulation time 902707190 ps
CPU time 28.94 seconds
Started Aug 21 07:37:15 PM UTC 24
Finished Aug 21 07:37:46 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2867133713 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc
_req.2867133713
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_regwen.283398045
Short name T510
Test name
Test status
Simulation time 288261984 ps
CPU time 8.6 seconds
Started Aug 21 07:37:19 PM UTC 24
Finished Aug 21 07:37:29 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=283398045 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.283398045
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_smoke.3232162871
Short name T506
Test name
Test status
Simulation time 502250405 ps
CPU time 8.33 seconds
Started Aug 21 07:37:15 PM UTC 24
Finished Aug 21 07:37:25 PM UTC 24
Peak memory 251392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3232162871 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.3232162871
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all.794714250
Short name T842
Test name
Test status
Simulation time 59156669738 ps
CPU time 352.41 seconds
Started Aug 21 07:37:22 PM UTC 24
Finished Aug 21 07:43:19 PM UTC 24
Peak memory 304944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=794714250 -
assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_str
ess_all.794714250
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_test_access.4253116679
Short name T468
Test name
Test status
Simulation time 2058905740 ps
CPU time 34.82 seconds
Started Aug 21 07:37:19 PM UTC 24
Finished Aug 21 07:37:55 PM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4253116679 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.4253116679
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/16.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_init_fail.3284547220
Short name T997
Test name
Test status
Simulation time 652004783 ps
CPU time 4.92 seconds
Started Aug 21 07:44:49 PM UTC 24
Finished Aug 21 07:44:55 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3284547220 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.3284547220
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/160.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_parallel_lc_esc.1956064219
Short name T1041
Test name
Test status
Simulation time 9116436531 ps
CPU time 22.46 seconds
Started Aug 21 07:44:49 PM UTC 24
Finished Aug 21 07:45:12 PM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1956064219 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.1956064219
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/160.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_init_fail.1414615724
Short name T1000
Test name
Test status
Simulation time 555646179 ps
CPU time 5.26 seconds
Started Aug 21 07:44:49 PM UTC 24
Finished Aug 21 07:44:55 PM UTC 24
Peak memory 250880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1414615724 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.1414615724
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/161.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_parallel_lc_esc.4219777534
Short name T1002
Test name
Test status
Simulation time 1320296602 ps
CPU time 6.11 seconds
Started Aug 21 07:44:49 PM UTC 24
Finished Aug 21 07:44:56 PM UTC 24
Peak memory 251092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4219777534 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.4219777534
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/161.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_init_fail.2416141162
Short name T994
Test name
Test status
Simulation time 504662395 ps
CPU time 4.33 seconds
Started Aug 21 07:44:49 PM UTC 24
Finished Aug 21 07:44:54 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2416141162 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.2416141162
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/162.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_parallel_lc_esc.1690115478
Short name T1004
Test name
Test status
Simulation time 320875489 ps
CPU time 7.54 seconds
Started Aug 21 07:44:49 PM UTC 24
Finished Aug 21 07:44:57 PM UTC 24
Peak memory 251180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1690115478 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.1690115478
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/162.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_init_fail.2245117386
Short name T996
Test name
Test status
Simulation time 1765297460 ps
CPU time 4.47 seconds
Started Aug 21 07:44:49 PM UTC 24
Finished Aug 21 07:44:55 PM UTC 24
Peak memory 251180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2245117386 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.2245117386
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/163.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_parallel_lc_esc.2802404312
Short name T1005
Test name
Test status
Simulation time 751096906 ps
CPU time 8.55 seconds
Started Aug 21 07:44:49 PM UTC 24
Finished Aug 21 07:44:59 PM UTC 24
Peak memory 251348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2802404312 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.2802404312
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/163.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_init_fail.2503072922
Short name T998
Test name
Test status
Simulation time 161578223 ps
CPU time 4.56 seconds
Started Aug 21 07:44:49 PM UTC 24
Finished Aug 21 07:44:55 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2503072922 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.2503072922
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/164.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_parallel_lc_esc.3194644635
Short name T1016
Test name
Test status
Simulation time 173328467 ps
CPU time 7.51 seconds
Started Aug 21 07:44:55 PM UTC 24
Finished Aug 21 07:45:04 PM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3194644635 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.3194644635
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/164.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_init_fail.4287821448
Short name T1008
Test name
Test status
Simulation time 190461194 ps
CPU time 3.34 seconds
Started Aug 21 07:44:55 PM UTC 24
Finished Aug 21 07:45:00 PM UTC 24
Peak memory 251516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4287821448 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.4287821448
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/165.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_parallel_lc_esc.1363799088
Short name T1010
Test name
Test status
Simulation time 1833600431 ps
CPU time 5.39 seconds
Started Aug 21 07:44:55 PM UTC 24
Finished Aug 21 07:45:02 PM UTC 24
Peak memory 251152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1363799088 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.1363799088
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/165.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_init_fail.795960638
Short name T1001
Test name
Test status
Simulation time 125763489 ps
CPU time 4.27 seconds
Started Aug 21 07:44:55 PM UTC 24
Finished Aug 21 07:45:01 PM UTC 24
Peak memory 251456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=795960638 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.795960638
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/166.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_parallel_lc_esc.2870498015
Short name T1006
Test name
Test status
Simulation time 1006191654 ps
CPU time 2.68 seconds
Started Aug 21 07:44:55 PM UTC 24
Finished Aug 21 07:44:59 PM UTC 24
Peak memory 251116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2870498015 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.2870498015
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/166.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_init_fail.1901070201
Short name T959
Test name
Test status
Simulation time 448313317 ps
CPU time 4.21 seconds
Started Aug 21 07:44:55 PM UTC 24
Finished Aug 21 07:45:01 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1901070201 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.1901070201
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/167.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_parallel_lc_esc.151602942
Short name T1011
Test name
Test status
Simulation time 214068466 ps
CPU time 5.88 seconds
Started Aug 21 07:44:55 PM UTC 24
Finished Aug 21 07:45:02 PM UTC 24
Peak memory 251500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=151602942 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.151602942
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/167.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_parallel_lc_esc.3548001779
Short name T1039
Test name
Test status
Simulation time 1079828398 ps
CPU time 14.5 seconds
Started Aug 21 07:44:55 PM UTC 24
Finished Aug 21 07:45:11 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3548001779 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.3548001779
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/168.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_parallel_lc_esc.1230333062
Short name T983
Test name
Test status
Simulation time 1356059285 ps
CPU time 3.38 seconds
Started Aug 21 07:44:55 PM UTC 24
Finished Aug 21 07:45:00 PM UTC 24
Peak memory 253460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1230333062 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.1230333062
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/169.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_alert_test.1899793576
Short name T515
Test name
Test status
Simulation time 720361636 ps
CPU time 3.06 seconds
Started Aug 21 07:37:31 PM UTC 24
Finished Aug 21 07:37:35 PM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1899793576 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.1899793576
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_check_fail.719152242
Short name T514
Test name
Test status
Simulation time 140237196 ps
CPU time 3.26 seconds
Started Aug 21 07:37:30 PM UTC 24
Finished Aug 21 07:37:35 PM UTC 24
Peak memory 257468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=719152242 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.719152242
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_errs.2288339203
Short name T363
Test name
Test status
Simulation time 9769288646 ps
CPU time 20.08 seconds
Started Aug 21 07:37:30 PM UTC 24
Finished Aug 21 07:37:52 PM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2288339203 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.2288339203
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_lock.511218804
Short name T529
Test name
Test status
Simulation time 1216203451 ps
CPU time 26.55 seconds
Started Aug 21 07:37:30 PM UTC 24
Finished Aug 21 07:37:58 PM UTC 24
Peak memory 257496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=511218804 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.511218804
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_init_fail.1409416068
Short name T509
Test name
Test status
Simulation time 149540849 ps
CPU time 4.21 seconds
Started Aug 21 07:37:23 PM UTC 24
Finished Aug 21 07:37:28 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1409416068 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.1409416068
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_macro_errs.1180509444
Short name T250
Test name
Test status
Simulation time 227705676 ps
CPU time 4.75 seconds
Started Aug 21 07:37:30 PM UTC 24
Finished Aug 21 07:37:36 PM UTC 24
Peak memory 251608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1180509444 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.1180509444
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_key_req.3481364688
Short name T517
Test name
Test status
Simulation time 1712966091 ps
CPU time 10.8 seconds
Started Aug 21 07:37:30 PM UTC 24
Finished Aug 21 07:37:42 PM UTC 24
Peak memory 251312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3481364688 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.3481364688
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_esc.3074829240
Short name T156
Test name
Test status
Simulation time 751620731 ps
CPU time 6.86 seconds
Started Aug 21 07:37:30 PM UTC 24
Finished Aug 21 07:37:38 PM UTC 24
Peak memory 251276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3074829240 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.3074829240
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_req.3584071799
Short name T364
Test name
Test status
Simulation time 1207741719 ps
CPU time 27.45 seconds
Started Aug 21 07:37:23 PM UTC 24
Finished Aug 21 07:37:52 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3584071799 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc
_req.3584071799
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_regwen.1781564616
Short name T518
Test name
Test status
Simulation time 289409431 ps
CPU time 10.73 seconds
Started Aug 21 07:37:30 PM UTC 24
Finished Aug 21 07:37:42 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1781564616 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.1781564616
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_smoke.2314162090
Short name T512
Test name
Test status
Simulation time 978534251 ps
CPU time 9.11 seconds
Started Aug 21 07:37:22 PM UTC 24
Finished Aug 21 07:37:32 PM UTC 24
Peak memory 251456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2314162090 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.2314162090
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all.3737477647
Short name T722
Test name
Test status
Simulation time 38258629458 ps
CPU time 239.64 seconds
Started Aug 21 07:37:30 PM UTC 24
Finished Aug 21 07:41:34 PM UTC 24
Peak memory 271860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3737477647
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_st
ress_all.3737477647
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all_with_rand_reset.2085856301
Short name T148
Test name
Test status
Simulation time 29856446371 ps
CPU time 126.55 seconds
Started Aug 21 07:37:30 PM UTC 24
Finished Aug 21 07:39:40 PM UTC 24
Peak memory 267960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2085856301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.2085856301
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_test_access.435860791
Short name T516
Test name
Test status
Simulation time 314451742 ps
CPU time 9.99 seconds
Started Aug 21 07:37:30 PM UTC 24
Finished Aug 21 07:37:42 PM UTC 24
Peak memory 251640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=435860791 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.435860791
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/17.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_init_fail.517906412
Short name T961
Test name
Test status
Simulation time 289045164 ps
CPU time 4.41 seconds
Started Aug 21 07:44:55 PM UTC 24
Finished Aug 21 07:45:01 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=517906412 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.517906412
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/170.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_parallel_lc_esc.1173597654
Short name T1018
Test name
Test status
Simulation time 1124508457 ps
CPU time 8.24 seconds
Started Aug 21 07:44:56 PM UTC 24
Finished Aug 21 07:45:05 PM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1173597654 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.1173597654
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/170.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_init_fail.2519819144
Short name T1007
Test name
Test status
Simulation time 102343531 ps
CPU time 2.83 seconds
Started Aug 21 07:44:56 PM UTC 24
Finished Aug 21 07:45:00 PM UTC 24
Peak memory 253476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2519819144 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.2519819144
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/171.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_parallel_lc_esc.2974128529
Short name T985
Test name
Test status
Simulation time 412553714 ps
CPU time 4.42 seconds
Started Aug 21 07:44:56 PM UTC 24
Finished Aug 21 07:45:01 PM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2974128529 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.2974128529
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/171.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_init_fail.766684903
Short name T1012
Test name
Test status
Simulation time 2025281180 ps
CPU time 5.71 seconds
Started Aug 21 07:44:56 PM UTC 24
Finished Aug 21 07:45:02 PM UTC 24
Peak memory 253248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=766684903 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.766684903
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/172.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_parallel_lc_esc.3868302504
Short name T1036
Test name
Test status
Simulation time 1118543235 ps
CPU time 13.8 seconds
Started Aug 21 07:44:56 PM UTC 24
Finished Aug 21 07:45:11 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3868302504 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.3868302504
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/172.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_init_fail.2287525817
Short name T1009
Test name
Test status
Simulation time 205262468 ps
CPU time 4.7 seconds
Started Aug 21 07:44:56 PM UTC 24
Finished Aug 21 07:45:01 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2287525817 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.2287525817
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/173.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_parallel_lc_esc.3027832333
Short name T165
Test name
Test status
Simulation time 1271404024 ps
CPU time 17.2 seconds
Started Aug 21 07:44:56 PM UTC 24
Finished Aug 21 07:45:14 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3027832333 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.3027832333
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/173.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_init_fail.1991810704
Short name T1015
Test name
Test status
Simulation time 1666212394 ps
CPU time 6.8 seconds
Started Aug 21 07:44:56 PM UTC 24
Finished Aug 21 07:45:04 PM UTC 24
Peak memory 253564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1991810704 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.1991810704
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/174.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_parallel_lc_esc.1961163927
Short name T1014
Test name
Test status
Simulation time 4034547449 ps
CPU time 6.63 seconds
Started Aug 21 07:44:56 PM UTC 24
Finished Aug 21 07:45:04 PM UTC 24
Peak memory 253296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1961163927 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.1961163927
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/174.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_init_fail.1667228524
Short name T1022
Test name
Test status
Simulation time 155691301 ps
CPU time 3.69 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:09 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1667228524 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.1667228524
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/175.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_parallel_lc_esc.1592373448
Short name T1030
Test name
Test status
Simulation time 153434261 ps
CPU time 4.61 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:09 PM UTC 24
Peak memory 253232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1592373448 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.1592373448
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/175.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_init_fail.2763174773
Short name T1020
Test name
Test status
Simulation time 158516973 ps
CPU time 3.03 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:08 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2763174773 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.2763174773
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/176.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_parallel_lc_esc.1907723834
Short name T1152
Test name
Test status
Simulation time 19280216504 ps
CPU time 40.5 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:46 PM UTC 24
Peak memory 253288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1907723834 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.1907723834
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/176.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_init_fail.921074061
Short name T1021
Test name
Test status
Simulation time 146272327 ps
CPU time 3.34 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:08 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=921074061 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.921074061
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/177.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_parallel_lc_esc.2042651755
Short name T1044
Test name
Test status
Simulation time 1119234960 ps
CPU time 7.58 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:13 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2042651755 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.2042651755
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/177.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_init_fail.3585368728
Short name T1025
Test name
Test status
Simulation time 509654369 ps
CPU time 3.68 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:09 PM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3585368728 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.3585368728
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/178.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_parallel_lc_esc.251078882
Short name T1032
Test name
Test status
Simulation time 359230903 ps
CPU time 4.87 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:10 PM UTC 24
Peak memory 251096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=251078882 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.251078882
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/178.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_init_fail.2678067067
Short name T1026
Test name
Test status
Simulation time 203163596 ps
CPU time 3.83 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:09 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2678067067 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.2678067067
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/179.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_parallel_lc_esc.2750170166
Short name T1045
Test name
Test status
Simulation time 433338247 ps
CPU time 11.05 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:16 PM UTC 24
Peak memory 251436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2750170166 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.2750170166
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/179.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_alert_test.2837936783
Short name T524
Test name
Test status
Simulation time 674720210 ps
CPU time 3.56 seconds
Started Aug 21 07:37:40 PM UTC 24
Finished Aug 21 07:37:44 PM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2837936783 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.2837936783
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_check_fail.37680508
Short name T519
Test name
Test status
Simulation time 818568735 ps
CPU time 6.68 seconds
Started Aug 21 07:37:35 PM UTC 24
Finished Aug 21 07:37:43 PM UTC 24
Peak memory 257816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=37680508 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.37680508
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_errs.2712184197
Short name T365
Test name
Test status
Simulation time 1021698496 ps
CPU time 16.41 seconds
Started Aug 21 07:37:35 PM UTC 24
Finished Aug 21 07:37:52 PM UTC 24
Peak memory 251608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2712184197 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.2712184197
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_lock.1073195051
Short name T520
Test name
Test status
Simulation time 916053602 ps
CPU time 7.39 seconds
Started Aug 21 07:37:35 PM UTC 24
Finished Aug 21 07:37:43 PM UTC 24
Peak memory 251356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1073195051 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.1073195051
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_init_fail.2958607490
Short name T52
Test name
Test status
Simulation time 148957949 ps
CPU time 4.77 seconds
Started Aug 21 07:37:32 PM UTC 24
Finished Aug 21 07:37:38 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2958607490 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.2958607490
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_macro_errs.3732268665
Short name T193
Test name
Test status
Simulation time 1957714423 ps
CPU time 20.41 seconds
Started Aug 21 07:37:36 PM UTC 24
Finished Aug 21 07:37:58 PM UTC 24
Peak memory 257600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3732268665 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.3732268665
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_key_req.145710385
Short name T526
Test name
Test status
Simulation time 229436266 ps
CPU time 9.15 seconds
Started Aug 21 07:37:36 PM UTC 24
Finished Aug 21 07:37:46 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=145710385 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.145710385
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_esc.2003717905
Short name T376
Test name
Test status
Simulation time 476027319 ps
CPU time 4.92 seconds
Started Aug 21 07:37:32 PM UTC 24
Finished Aug 21 07:37:38 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2003717905 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.2003717905
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_req.1520508472
Short name T367
Test name
Test status
Simulation time 2364023789 ps
CPU time 19.43 seconds
Started Aug 21 07:37:32 PM UTC 24
Finished Aug 21 07:37:53 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1520508472 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc
_req.1520508472
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_regwen.3239223851
Short name T522
Test name
Test status
Simulation time 280415269 ps
CPU time 5.43 seconds
Started Aug 21 07:37:37 PM UTC 24
Finished Aug 21 07:37:44 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3239223851 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.3239223851
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_smoke.1209883928
Short name T523
Test name
Test status
Simulation time 781881306 ps
CPU time 12.04 seconds
Started Aug 21 07:37:31 PM UTC 24
Finished Aug 21 07:37:44 PM UTC 24
Peak memory 251584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1209883928 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.1209883928
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all.1272578861
Short name T894
Test name
Test status
Simulation time 191006212632 ps
CPU time 381.56 seconds
Started Aug 21 07:37:40 PM UTC 24
Finished Aug 21 07:44:07 PM UTC 24
Peak memory 306780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1272578861
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_st
ress_all.1272578861
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_test_access.578003954
Short name T469
Test name
Test status
Simulation time 1615686165 ps
CPU time 33.75 seconds
Started Aug 21 07:37:39 PM UTC 24
Finished Aug 21 07:38:14 PM UTC 24
Peak memory 253396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=578003954 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.578003954
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/18.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_init_fail.290340880
Short name T135
Test name
Test status
Simulation time 427277960 ps
CPU time 3.17 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:08 PM UTC 24
Peak memory 253528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=290340880 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.290340880
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/180.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_parallel_lc_esc.3153090288
Short name T1043
Test name
Test status
Simulation time 250323757 ps
CPU time 7.42 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:13 PM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3153090288 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.3153090288
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/180.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_init_fail.127395379
Short name T29
Test name
Test status
Simulation time 194655949 ps
CPU time 3.49 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:09 PM UTC 24
Peak memory 253336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=127395379 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.127395379
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/181.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_parallel_lc_esc.186818653
Short name T1040
Test name
Test status
Simulation time 154460251 ps
CPU time 6.89 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:12 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=186818653 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.186818653
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/181.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_init_fail.2726032242
Short name T1035
Test name
Test status
Simulation time 153765139 ps
CPU time 5.05 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:10 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2726032242 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.2726032242
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/182.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_parallel_lc_esc.1147167848
Short name T1033
Test name
Test status
Simulation time 564102416 ps
CPU time 4.96 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:10 PM UTC 24
Peak memory 253204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1147167848 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.1147167848
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/182.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_init_fail.380440546
Short name T1034
Test name
Test status
Simulation time 332799164 ps
CPU time 5.04 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:10 PM UTC 24
Peak memory 250840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=380440546 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.380440546
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/183.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_parallel_lc_esc.1074918846
Short name T1046
Test name
Test status
Simulation time 584763465 ps
CPU time 11.7 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:17 PM UTC 24
Peak memory 250792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1074918846 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.1074918846
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/183.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_init_fail.564577064
Short name T1037
Test name
Test status
Simulation time 1781773457 ps
CPU time 5.21 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:11 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=564577064 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.564577064
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/184.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_parallel_lc_esc.1617960127
Short name T1042
Test name
Test status
Simulation time 966840227 ps
CPU time 7.01 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:12 PM UTC 24
Peak memory 257560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1617960127 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.1617960127
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/184.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_init_fail.371846607
Short name T1028
Test name
Test status
Simulation time 365961252 ps
CPU time 3.75 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:09 PM UTC 24
Peak memory 251456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=371846607 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.371846607
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/185.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_parallel_lc_esc.2710867287
Short name T1038
Test name
Test status
Simulation time 1802279400 ps
CPU time 5.54 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:11 PM UTC 24
Peak memory 251020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2710867287 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.2710867287
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/185.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_init_fail.2208058932
Short name T1029
Test name
Test status
Simulation time 272497713 ps
CPU time 3.86 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:09 PM UTC 24
Peak memory 251516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2208058932 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.2208058932
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/186.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_parallel_lc_esc.1377845073
Short name T1065
Test name
Test status
Simulation time 633086097 ps
CPU time 14.01 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:20 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1377845073 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.1377845073
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/186.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_init_fail.1097545309
Short name T1027
Test name
Test status
Simulation time 94149753 ps
CPU time 3.55 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:09 PM UTC 24
Peak memory 253436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1097545309 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.1097545309
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/187.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_parallel_lc_esc.4114110207
Short name T1023
Test name
Test status
Simulation time 221650453 ps
CPU time 3.07 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:09 PM UTC 24
Peak memory 251116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4114110207 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.4114110207
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/187.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_init_fail.460998364
Short name T1031
Test name
Test status
Simulation time 123953895 ps
CPU time 3.84 seconds
Started Aug 21 07:45:04 PM UTC 24
Finished Aug 21 07:45:10 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=460998364 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.460998364
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/188.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.2974558996
Short name T1073
Test name
Test status
Simulation time 481473346 ps
CPU time 8.43 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:23 PM UTC 24
Peak memory 251440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2974558996 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.2974558996
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/188.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_init_fail.1748572531
Short name T1058
Test name
Test status
Simulation time 680480055 ps
CPU time 4.77 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:19 PM UTC 24
Peak memory 251344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1748572531 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.1748572531
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/189.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.3627423664
Short name T1088
Test name
Test status
Simulation time 610090797 ps
CPU time 13.73 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:28 PM UTC 24
Peak memory 250720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3627423664 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.3627423664
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/189.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_alert_test.1862843225
Short name T368
Test name
Test status
Simulation time 137585823 ps
CPU time 3.35 seconds
Started Aug 21 07:37:49 PM UTC 24
Finished Aug 21 07:37:53 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1862843225 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.1862843225
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/19.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_check_fail.1961419621
Short name T530
Test name
Test status
Simulation time 5561176356 ps
CPU time 9.39 seconds
Started Aug 21 07:37:48 PM UTC 24
Finished Aug 21 07:37:59 PM UTC 24
Peak memory 253440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1961419621 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.1961419621
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/19.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_errs.2216213019
Short name T531
Test name
Test status
Simulation time 2413929153 ps
CPU time 20.17 seconds
Started Aug 21 07:37:48 PM UTC 24
Finished Aug 21 07:38:10 PM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2216213019 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.2216213019
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/19.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_lock.1835913369
Short name T548
Test name
Test status
Simulation time 3671446009 ps
CPU time 43.99 seconds
Started Aug 21 07:37:48 PM UTC 24
Finished Aug 21 07:38:34 PM UTC 24
Peak memory 251672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1835913369 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.1835913369
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/19.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_init_fail.1043688291
Short name T221
Test name
Test status
Simulation time 232727379 ps
CPU time 3.98 seconds
Started Aug 21 07:37:42 PM UTC 24
Finished Aug 21 07:37:47 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1043688291 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.1043688291
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/19.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_macro_errs.1989281005
Short name T463
Test name
Test status
Simulation time 425439120 ps
CPU time 10.51 seconds
Started Aug 21 07:37:49 PM UTC 24
Finished Aug 21 07:38:00 PM UTC 24
Peak memory 253632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1989281005 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.1989281005
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/19.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_key_req.4221634510
Short name T443
Test name
Test status
Simulation time 1345553168 ps
CPU time 25.58 seconds
Started Aug 21 07:37:49 PM UTC 24
Finished Aug 21 07:38:15 PM UTC 24
Peak memory 257520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4221634510 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.4221634510
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_esc.3069106739
Short name T161
Test name
Test status
Simulation time 1611113917 ps
CPU time 3.79 seconds
Started Aug 21 07:37:48 PM UTC 24
Finished Aug 21 07:37:53 PM UTC 24
Peak memory 251152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3069106739 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.3069106739
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_req.445430550
Short name T274
Test name
Test status
Simulation time 668700775 ps
CPU time 17.75 seconds
Started Aug 21 07:37:48 PM UTC 24
Finished Aug 21 07:38:07 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=445430550 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_
req.445430550
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_regwen.3585704566
Short name T528
Test name
Test status
Simulation time 291446504 ps
CPU time 7.36 seconds
Started Aug 21 07:37:49 PM UTC 24
Finished Aug 21 07:37:57 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3585704566 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.3585704566
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/19.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_smoke.1800347656
Short name T521
Test name
Test status
Simulation time 310905890 ps
CPU time 5.38 seconds
Started Aug 21 07:37:40 PM UTC 24
Finished Aug 21 07:37:46 PM UTC 24
Peak memory 257532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1800347656 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.1800347656
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/19.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_test_access.2398790085
Short name T414
Test name
Test status
Simulation time 5535585430 ps
CPU time 38.14 seconds
Started Aug 21 07:37:49 PM UTC 24
Finished Aug 21 07:38:28 PM UTC 24
Peak memory 251380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2398790085 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.2398790085
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/19.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_init_fail.38832173
Short name T1055
Test name
Test status
Simulation time 147896056 ps
CPU time 4.24 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:18 PM UTC 24
Peak memory 250932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38832173 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.38832173
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/190.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.2750042960
Short name T1062
Test name
Test status
Simulation time 899975156 ps
CPU time 5.25 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:20 PM UTC 24
Peak memory 251312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2750042960 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.2750042960
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/190.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_init_fail.2260085437
Short name T1051
Test name
Test status
Simulation time 121210623 ps
CPU time 4.1 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:18 PM UTC 24
Peak memory 253540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2260085437 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.2260085437
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/191.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.2456091086
Short name T1066
Test name
Test status
Simulation time 215820931 ps
CPU time 5.61 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:20 PM UTC 24
Peak memory 251504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2456091086 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.2456091086
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/191.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_init_fail.610283073
Short name T1053
Test name
Test status
Simulation time 134065740 ps
CPU time 4.28 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:18 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=610283073 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.610283073
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/192.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_init_fail.1056001171
Short name T1050
Test name
Test status
Simulation time 172989898 ps
CPU time 4.04 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:18 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1056001171 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.1056001171
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/193.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.2371523589
Short name T1085
Test name
Test status
Simulation time 4302137156 ps
CPU time 11.55 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:26 PM UTC 24
Peak memory 253272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2371523589 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.2371523589
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/193.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_init_fail.119688870
Short name T1049
Test name
Test status
Simulation time 450719108 ps
CPU time 3.84 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:18 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=119688870 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.119688870
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/194.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.2766188452
Short name T1084
Test name
Test status
Simulation time 457380540 ps
CPU time 10.07 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:25 PM UTC 24
Peak memory 251180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2766188452 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.2766188452
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/194.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.1317342788
Short name T1064
Test name
Test status
Simulation time 1971935016 ps
CPU time 5.12 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:20 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1317342788 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.1317342788
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/195.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.1531112115
Short name T1089
Test name
Test status
Simulation time 2366450783 ps
CPU time 14.51 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:29 PM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1531112115 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.1531112115
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/195.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.1261553621
Short name T1069
Test name
Test status
Simulation time 2388447129 ps
CPU time 6.47 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:21 PM UTC 24
Peak memory 251516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1261553621 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.1261553621
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/196.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.3341389225
Short name T1077
Test name
Test status
Simulation time 364237200 ps
CPU time 8.42 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:23 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3341389225 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.3341389225
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/196.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.3678187631
Short name T1054
Test name
Test status
Simulation time 136267872 ps
CPU time 3.87 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:18 PM UTC 24
Peak memory 253436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3678187631 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.3678187631
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/197.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.1880678414
Short name T1086
Test name
Test status
Simulation time 524378311 ps
CPU time 13.17 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:28 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1880678414 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.1880678414
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/197.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.1286400509
Short name T1056
Test name
Test status
Simulation time 270840483 ps
CPU time 4.16 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:19 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1286400509 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.1286400509
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/198.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.1332285062
Short name T1071
Test name
Test status
Simulation time 285636827 ps
CPU time 7.11 seconds
Started Aug 21 07:45:13 PM UTC 24
Finished Aug 21 07:45:22 PM UTC 24
Peak memory 251180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1332285062 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.1332285062
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/198.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.2444993357
Short name T187
Test name
Test status
Simulation time 167460794 ps
CPU time 2.52 seconds
Started Aug 21 07:45:14 PM UTC 24
Finished Aug 21 07:45:17 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2444993357 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.2444993357
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/199.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.3592227818
Short name T1070
Test name
Test status
Simulation time 343390197 ps
CPU time 6.94 seconds
Started Aug 21 07:45:14 PM UTC 24
Finished Aug 21 07:45:22 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3592227818 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.3592227818
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/199.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_alert_test.332654467
Short name T124
Test name
Test status
Simulation time 66340956 ps
CPU time 2.46 seconds
Started Aug 21 07:35:13 PM UTC 24
Finished Aug 21 07:35:17 PM UTC 24
Peak memory 251520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=332654467 -ass
ert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.332654467
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_errs.1665918889
Short name T10
Test name
Test status
Simulation time 1834635500 ps
CPU time 30.03 seconds
Started Aug 21 07:35:08 PM UTC 24
Finished Aug 21 07:35:40 PM UTC 24
Peak memory 251324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1665918889 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.1665918889
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_lock.1982388443
Short name T115
Test name
Test status
Simulation time 1222314378 ps
CPU time 17.05 seconds
Started Aug 21 07:35:08 PM UTC 24
Finished Aug 21 07:35:27 PM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1982388443 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.1982388443
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_macro_errs.2292287876
Short name T146
Test name
Test status
Simulation time 1249023787 ps
CPU time 22.9 seconds
Started Aug 21 07:35:09 PM UTC 24
Finished Aug 21 07:35:33 PM UTC 24
Peak memory 255680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2292287876 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.2292287876
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_key_req.2366822071
Short name T118
Test name
Test status
Simulation time 2372721230 ps
CPU time 20.99 seconds
Started Aug 21 07:35:09 PM UTC 24
Finished Aug 21 07:35:31 PM UTC 24
Peak memory 251372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2366822071 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.2366822071
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_req.2408151773
Short name T125
Test name
Test status
Simulation time 284577748 ps
CPU time 9.26 seconds
Started Aug 21 07:35:08 PM UTC 24
Finished Aug 21 07:35:19 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2408151773 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_
req.2408151773
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_regwen.1845373222
Short name T126
Test name
Test status
Simulation time 271396391 ps
CPU time 8.06 seconds
Started Aug 21 07:35:10 PM UTC 24
Finished Aug 21 07:35:19 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1845373222 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.1845373222
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_sec_cm.2669796538
Short name T23
Test name
Test status
Simulation time 10619883240 ps
CPU time 189.73 seconds
Started Aug 21 07:35:13 PM UTC 24
Finished Aug 21 07:38:26 PM UTC 24
Peak memory 296216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2669796538 -ass
ert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.2669796538
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_smoke.4113726868
Short name T127
Test name
Test status
Simulation time 461893600 ps
CPU time 10.1 seconds
Started Aug 21 07:35:07 PM UTC 24
Finished Aug 21 07:35:19 PM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4113726868 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.4113726868
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.700701260
Short name T16
Test name
Test status
Simulation time 11628379532 ps
CPU time 113.02 seconds
Started Aug 21 07:35:11 PM UTC 24
Finished Aug 21 07:37:06 PM UTC 24
Peak memory 267960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=700701260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.700701260
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_test_access.516944511
Short name T19
Test name
Test status
Simulation time 1177288262 ps
CPU time 10.01 seconds
Started Aug 21 07:35:11 PM UTC 24
Finished Aug 21 07:35:22 PM UTC 24
Peak memory 251668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=516944511 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.516944511
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/2.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_alert_test.3357459705
Short name T270
Test name
Test status
Simulation time 231516035 ps
CPU time 4.67 seconds
Started Aug 21 07:37:59 PM UTC 24
Finished Aug 21 07:38:04 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3357459705 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.3357459705
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/20.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_errs.340821632
Short name T541
Test name
Test status
Simulation time 2152959651 ps
CPU time 28.43 seconds
Started Aug 21 07:37:50 PM UTC 24
Finished Aug 21 07:38:20 PM UTC 24
Peak memory 257560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=340821632 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.340821632
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/20.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_lock.229976277
Short name T527
Test name
Test status
Simulation time 239057795 ps
CPU time 3.98 seconds
Started Aug 21 07:37:50 PM UTC 24
Finished Aug 21 07:37:55 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=229976277 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.229976277
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/20.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_init_fail.155342310
Short name T25
Test name
Test status
Simulation time 541101588 ps
CPU time 4.81 seconds
Started Aug 21 07:37:49 PM UTC 24
Finished Aug 21 07:37:55 PM UTC 24
Peak memory 253252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=155342310 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.155342310
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/20.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_macro_errs.942137730
Short name T534
Test name
Test status
Simulation time 2974430328 ps
CPU time 17.86 seconds
Started Aug 21 07:37:53 PM UTC 24
Finished Aug 21 07:38:12 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=942137730 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.942137730
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/20.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_key_req.713570703
Short name T269
Test name
Test status
Simulation time 107927469 ps
CPU time 4.5 seconds
Started Aug 21 07:37:58 PM UTC 24
Finished Aug 21 07:38:04 PM UTC 24
Peak memory 257428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=713570703 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.713570703
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_esc.2258733184
Short name T373
Test name
Test status
Simulation time 302005795 ps
CPU time 6.96 seconds
Started Aug 21 07:37:49 PM UTC 24
Finished Aug 21 07:37:57 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2258733184 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.2258733184
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_req.2757480451
Short name T428
Test name
Test status
Simulation time 788924627 ps
CPU time 30.06 seconds
Started Aug 21 07:37:49 PM UTC 24
Finished Aug 21 07:38:20 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2757480451 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc
_req.2757480451
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_smoke.1242003132
Short name T525
Test name
Test status
Simulation time 263258151 ps
CPU time 8.28 seconds
Started Aug 21 07:37:49 PM UTC 24
Finished Aug 21 07:37:58 PM UTC 24
Peak memory 251648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1242003132 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.1242003132
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/20.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_test_access.3795785683
Short name T324
Test name
Test status
Simulation time 1970646242 ps
CPU time 23.39 seconds
Started Aug 21 07:37:59 PM UTC 24
Finished Aug 21 07:38:23 PM UTC 24
Peak memory 257524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3795785683 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.3795785683
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/20.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.4186374160
Short name T1057
Test name
Test status
Simulation time 141632281 ps
CPU time 4.06 seconds
Started Aug 21 07:45:14 PM UTC 24
Finished Aug 21 07:45:19 PM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4186374160 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.4186374160
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/200.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.3730482201
Short name T1067
Test name
Test status
Simulation time 2225417962 ps
CPU time 5.52 seconds
Started Aug 21 07:45:14 PM UTC 24
Finished Aug 21 07:45:20 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3730482201 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.3730482201
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/201.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.2360598214
Short name T1063
Test name
Test status
Simulation time 162869111 ps
CPU time 4.78 seconds
Started Aug 21 07:45:14 PM UTC 24
Finished Aug 21 07:45:20 PM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2360598214 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.2360598214
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/202.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.1167848694
Short name T1059
Test name
Test status
Simulation time 153277918 ps
CPU time 4.48 seconds
Started Aug 21 07:45:14 PM UTC 24
Finished Aug 21 07:45:19 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1167848694 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.1167848694
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/203.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.3598627809
Short name T1061
Test name
Test status
Simulation time 122418370 ps
CPU time 4.55 seconds
Started Aug 21 07:45:14 PM UTC 24
Finished Aug 21 07:45:19 PM UTC 24
Peak memory 251324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3598627809 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.3598627809
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/204.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.1168367686
Short name T1048
Test name
Test status
Simulation time 81968405 ps
CPU time 3.21 seconds
Started Aug 21 07:45:14 PM UTC 24
Finished Aug 21 07:45:18 PM UTC 24
Peak memory 251516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1168367686 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.1168367686
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/205.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.736433369
Short name T1047
Test name
Test status
Simulation time 257530028 ps
CPU time 3.11 seconds
Started Aug 21 07:45:14 PM UTC 24
Finished Aug 21 07:45:18 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=736433369 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.736433369
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/206.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.1314460039
Short name T1060
Test name
Test status
Simulation time 681494180 ps
CPU time 4.42 seconds
Started Aug 21 07:45:14 PM UTC 24
Finished Aug 21 07:45:19 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1314460039 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.1314460039
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/207.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.205735063
Short name T1079
Test name
Test status
Simulation time 327140071 ps
CPU time 3.81 seconds
Started Aug 21 07:45:18 PM UTC 24
Finished Aug 21 07:45:23 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=205735063 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.205735063
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/208.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.1608007211
Short name T1075
Test name
Test status
Simulation time 564453956 ps
CPU time 3.47 seconds
Started Aug 21 07:45:18 PM UTC 24
Finished Aug 21 07:45:23 PM UTC 24
Peak memory 251128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1608007211 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.1608007211
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/209.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_alert_test.442916567
Short name T533
Test name
Test status
Simulation time 187642953 ps
CPU time 4.46 seconds
Started Aug 21 07:38:05 PM UTC 24
Finished Aug 21 07:38:11 PM UTC 24
Peak memory 251516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=442916567 -ass
ert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.442916567
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/21.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_check_fail.3962233287
Short name T328
Test name
Test status
Simulation time 1921152259 ps
CPU time 23.36 seconds
Started Aug 21 07:38:01 PM UTC 24
Finished Aug 21 07:38:26 PM UTC 24
Peak memory 253400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3962233287 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.3962233287
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/21.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_errs.3134511954
Short name T540
Test name
Test status
Simulation time 875679186 ps
CPU time 18.46 seconds
Started Aug 21 07:37:59 PM UTC 24
Finished Aug 21 07:38:19 PM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3134511954 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.3134511954
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/21.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_lock.242374264
Short name T536
Test name
Test status
Simulation time 778857036 ps
CPU time 13.79 seconds
Started Aug 21 07:37:59 PM UTC 24
Finished Aug 21 07:38:14 PM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=242374264 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.242374264
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/21.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_init_fail.3067888184
Short name T49
Test name
Test status
Simulation time 596295532 ps
CPU time 6.56 seconds
Started Aug 21 07:37:59 PM UTC 24
Finished Aug 21 07:38:07 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3067888184 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.3067888184
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/21.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_macro_errs.3844413815
Short name T251
Test name
Test status
Simulation time 14596169065 ps
CPU time 83.51 seconds
Started Aug 21 07:38:01 PM UTC 24
Finished Aug 21 07:39:27 PM UTC 24
Peak memory 263808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3844413815 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.3844413815
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/21.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_key_req.1430908797
Short name T273
Test name
Test status
Simulation time 126964240 ps
CPU time 4.78 seconds
Started Aug 21 07:38:01 PM UTC 24
Finished Aug 21 07:38:07 PM UTC 24
Peak memory 251508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1430908797 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.1430908797
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_esc.8862056
Short name T268
Test name
Test status
Simulation time 362257440 ps
CPU time 3.93 seconds
Started Aug 21 07:37:59 PM UTC 24
Finished Aug 21 07:38:04 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=8862056 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.8862056
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_req.1306881647
Short name T275
Test name
Test status
Simulation time 379056088 ps
CPU time 12.54 seconds
Started Aug 21 07:37:59 PM UTC 24
Finished Aug 21 07:38:13 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1306881647 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc
_req.1306881647
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_regwen.1591798654
Short name T404
Test name
Test status
Simulation time 498721982 ps
CPU time 13.21 seconds
Started Aug 21 07:38:01 PM UTC 24
Finished Aug 21 07:38:16 PM UTC 24
Peak memory 251064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1591798654 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.1591798654
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/21.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_smoke.2947197894
Short name T532
Test name
Test status
Simulation time 6974124191 ps
CPU time 10.46 seconds
Started Aug 21 07:37:59 PM UTC 24
Finished Aug 21 07:38:10 PM UTC 24
Peak memory 251456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2947197894 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.2947197894
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/21.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all.3052842767
Short name T432
Test name
Test status
Simulation time 12051804685 ps
CPU time 187.81 seconds
Started Aug 21 07:38:04 PM UTC 24
Finished Aug 21 07:41:16 PM UTC 24
Peak memory 257604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3052842767
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_st
ress_all.3052842767
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_test_access.804580064
Short name T321
Test name
Test status
Simulation time 8191870097 ps
CPU time 18.93 seconds
Started Aug 21 07:38:01 PM UTC 24
Finished Aug 21 07:38:22 PM UTC 24
Peak memory 253520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=804580064 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.804580064
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/21.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.1645246607
Short name T936
Test name
Test status
Simulation time 414208472 ps
CPU time 3.78 seconds
Started Aug 21 07:45:18 PM UTC 24
Finished Aug 21 07:45:23 PM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1645246607 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.1645246607
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/210.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.815183750
Short name T1082
Test name
Test status
Simulation time 1626525389 ps
CPU time 3.91 seconds
Started Aug 21 07:45:18 PM UTC 24
Finished Aug 21 07:45:23 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=815183750 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.815183750
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/211.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.2361415939
Short name T1074
Test name
Test status
Simulation time 143636240 ps
CPU time 3.3 seconds
Started Aug 21 07:45:18 PM UTC 24
Finished Aug 21 07:45:23 PM UTC 24
Peak memory 253476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2361415939 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.2361415939
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/212.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.1501494321
Short name T1072
Test name
Test status
Simulation time 86871460 ps
CPU time 2.6 seconds
Started Aug 21 07:45:18 PM UTC 24
Finished Aug 21 07:45:22 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1501494321 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.1501494321
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/213.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.1283184379
Short name T1076
Test name
Test status
Simulation time 352456862 ps
CPU time 3.33 seconds
Started Aug 21 07:45:18 PM UTC 24
Finished Aug 21 07:45:23 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1283184379 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.1283184379
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/214.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.3740025340
Short name T1078
Test name
Test status
Simulation time 310366772 ps
CPU time 3.48 seconds
Started Aug 21 07:45:18 PM UTC 24
Finished Aug 21 07:45:23 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3740025340 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.3740025340
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/215.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.3488523651
Short name T1080
Test name
Test status
Simulation time 509519007 ps
CPU time 3.54 seconds
Started Aug 21 07:45:18 PM UTC 24
Finished Aug 21 07:45:23 PM UTC 24
Peak memory 253500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3488523651 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.3488523651
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/216.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.2197795314
Short name T1083
Test name
Test status
Simulation time 212413288 ps
CPU time 3.94 seconds
Started Aug 21 07:45:19 PM UTC 24
Finished Aug 21 07:45:24 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2197795314 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.2197795314
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/217.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.2871663390
Short name T1081
Test name
Test status
Simulation time 417481282 ps
CPU time 3.59 seconds
Started Aug 21 07:45:19 PM UTC 24
Finished Aug 21 07:45:23 PM UTC 24
Peak memory 251516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2871663390 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.2871663390
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/218.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.971073077
Short name T872
Test name
Test status
Simulation time 381209839 ps
CPU time 3.61 seconds
Started Aug 21 07:45:19 PM UTC 24
Finished Aug 21 07:45:23 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=971073077 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.971073077
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/219.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_alert_test.1573698480
Short name T542
Test name
Test status
Simulation time 146831601 ps
CPU time 3.88 seconds
Started Aug 21 07:38:16 PM UTC 24
Finished Aug 21 07:38:21 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1573698480 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.1573698480
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/22.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_check_fail.3114970400
Short name T538
Test name
Test status
Simulation time 234094084 ps
CPU time 5.63 seconds
Started Aug 21 07:38:09 PM UTC 24
Finished Aug 21 07:38:16 PM UTC 24
Peak memory 251728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3114970400 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.3114970400
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/22.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_errs.396454463
Short name T383
Test name
Test status
Simulation time 3658841353 ps
CPU time 34.17 seconds
Started Aug 21 07:38:09 PM UTC 24
Finished Aug 21 07:38:45 PM UTC 24
Peak memory 257860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=396454463 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.396454463
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/22.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_lock.2356178223
Short name T325
Test name
Test status
Simulation time 563329524 ps
CPU time 16.13 seconds
Started Aug 21 07:38:07 PM UTC 24
Finished Aug 21 07:38:25 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2356178223 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.2356178223
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/22.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_init_fail.1389768168
Short name T535
Test name
Test status
Simulation time 274090335 ps
CPU time 4.64 seconds
Started Aug 21 07:38:06 PM UTC 24
Finished Aug 21 07:38:12 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1389768168 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.1389768168
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/22.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_macro_errs.2008141461
Short name T323
Test name
Test status
Simulation time 354847868 ps
CPU time 10.18 seconds
Started Aug 21 07:38:12 PM UTC 24
Finished Aug 21 07:38:23 PM UTC 24
Peak memory 253372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2008141461 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.2008141461
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/22.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_key_req.3305615423
Short name T327
Test name
Test status
Simulation time 1666514921 ps
CPU time 12.53 seconds
Started Aug 21 07:38:12 PM UTC 24
Finished Aug 21 07:38:25 PM UTC 24
Peak memory 251340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3305615423 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.3305615423
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_esc.758894478
Short name T284
Test name
Test status
Simulation time 415035212 ps
CPU time 7.89 seconds
Started Aug 21 07:38:07 PM UTC 24
Finished Aug 21 07:38:17 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=758894478 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.758894478
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_req.2166365527
Short name T413
Test name
Test status
Simulation time 1956156052 ps
CPU time 12.02 seconds
Started Aug 21 07:38:07 PM UTC 24
Finished Aug 21 07:38:21 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2166365527 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc
_req.2166365527
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_regwen.1833115243
Short name T322
Test name
Test status
Simulation time 273652990 ps
CPU time 9.82 seconds
Started Aug 21 07:38:12 PM UTC 24
Finished Aug 21 07:38:23 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1833115243 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.1833115243
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/22.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_smoke.2255620329
Short name T543
Test name
Test status
Simulation time 853707187 ps
CPU time 14.58 seconds
Started Aug 21 07:38:05 PM UTC 24
Finished Aug 21 07:38:21 PM UTC 24
Peak memory 251456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2255620329 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.2255620329
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/22.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all.4174214047
Short name T382
Test name
Test status
Simulation time 13348934198 ps
CPU time 144.4 seconds
Started Aug 21 07:38:14 PM UTC 24
Finished Aug 21 07:40:41 PM UTC 24
Peak memory 269764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4174214047
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_st
ress_all.4174214047
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_test_access.1301085594
Short name T565
Test name
Test status
Simulation time 12499346466 ps
CPU time 43.38 seconds
Started Aug 21 07:38:13 PM UTC 24
Finished Aug 21 07:38:59 PM UTC 24
Peak memory 253492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1301085594 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.1301085594
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/22.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.2815600489
Short name T1092
Test name
Test status
Simulation time 141645940 ps
CPU time 3.33 seconds
Started Aug 21 07:45:26 PM UTC 24
Finished Aug 21 07:45:31 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2815600489 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.2815600489
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/220.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.656167183
Short name T1095
Test name
Test status
Simulation time 352985870 ps
CPU time 3.46 seconds
Started Aug 21 07:45:26 PM UTC 24
Finished Aug 21 07:45:31 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=656167183 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.656167183
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/221.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.3560680650
Short name T1096
Test name
Test status
Simulation time 84025079 ps
CPU time 3.59 seconds
Started Aug 21 07:45:26 PM UTC 24
Finished Aug 21 07:45:32 PM UTC 24
Peak memory 251516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3560680650 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.3560680650
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/222.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.880978651
Short name T1091
Test name
Test status
Simulation time 121874022 ps
CPU time 2.9 seconds
Started Aug 21 07:45:26 PM UTC 24
Finished Aug 21 07:45:31 PM UTC 24
Peak memory 253504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=880978651 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.880978651
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/223.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.1115072408
Short name T1093
Test name
Test status
Simulation time 148541006 ps
CPU time 3.25 seconds
Started Aug 21 07:45:26 PM UTC 24
Finished Aug 21 07:45:31 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1115072408 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.1115072408
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/224.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.2560502707
Short name T1090
Test name
Test status
Simulation time 314936566 ps
CPU time 2.71 seconds
Started Aug 21 07:45:26 PM UTC 24
Finished Aug 21 07:45:31 PM UTC 24
Peak memory 251116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2560502707 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.2560502707
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/225.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.2955737304
Short name T1102
Test name
Test status
Simulation time 109325908 ps
CPU time 3.84 seconds
Started Aug 21 07:45:26 PM UTC 24
Finished Aug 21 07:45:32 PM UTC 24
Peak memory 253528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2955737304 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.2955737304
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/226.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.3097929280
Short name T1098
Test name
Test status
Simulation time 1864426719 ps
CPU time 3.7 seconds
Started Aug 21 07:45:26 PM UTC 24
Finished Aug 21 07:45:32 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3097929280 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.3097929280
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/228.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.3508893522
Short name T1108
Test name
Test status
Simulation time 274449599 ps
CPU time 4.22 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:32 PM UTC 24
Peak memory 250824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3508893522 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.3508893522
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/229.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_alert_test.1466923148
Short name T544
Test name
Test status
Simulation time 143762076 ps
CPU time 2.89 seconds
Started Aug 21 07:38:23 PM UTC 24
Finished Aug 21 07:38:27 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1466923148 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.1466923148
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/23.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_check_fail.96900377
Short name T57
Test name
Test status
Simulation time 1050098159 ps
CPU time 14.68 seconds
Started Aug 21 07:38:20 PM UTC 24
Finished Aug 21 07:38:36 PM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=96900377 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.96900377
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/23.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_errs.1630918982
Short name T537
Test name
Test status
Simulation time 992961167 ps
CPU time 17.47 seconds
Started Aug 21 07:38:20 PM UTC 24
Finished Aug 21 07:38:39 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1630918982 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.1630918982
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/23.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_lock.151081370
Short name T549
Test name
Test status
Simulation time 4372103234 ps
CPU time 15.88 seconds
Started Aug 21 07:38:18 PM UTC 24
Finished Aug 21 07:38:35 PM UTC 24
Peak memory 253464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=151081370 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.151081370
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/23.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_init_fail.2556647391
Short name T50
Test name
Test status
Simulation time 232315449 ps
CPU time 4.39 seconds
Started Aug 21 07:38:18 PM UTC 24
Finished Aug 21 07:38:23 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2556647391 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.2556647391
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/23.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_macro_errs.2466052509
Short name T169
Test name
Test status
Simulation time 1071556731 ps
CPU time 10.91 seconds
Started Aug 21 07:38:20 PM UTC 24
Finished Aug 21 07:38:32 PM UTC 24
Peak memory 251736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2466052509 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.2466052509
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/23.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_key_req.77484922
Short name T449
Test name
Test status
Simulation time 549806037 ps
CPU time 20.82 seconds
Started Aug 21 07:38:23 PM UTC 24
Finished Aug 21 07:38:45 PM UTC 24
Peak memory 251324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=77484922 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.77484922
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_esc.2907429477
Short name T285
Test name
Test status
Simulation time 1304427793 ps
CPU time 15.07 seconds
Started Aug 21 07:38:18 PM UTC 24
Finished Aug 21 07:38:34 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2907429477 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.2907429477
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_req.2933716302
Short name T555
Test name
Test status
Simulation time 1048588364 ps
CPU time 25.85 seconds
Started Aug 21 07:38:18 PM UTC 24
Finished Aug 21 07:38:45 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2933716302 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc
_req.2933716302
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_regwen.1816163274
Short name T402
Test name
Test status
Simulation time 335336589 ps
CPU time 10.75 seconds
Started Aug 21 07:38:23 PM UTC 24
Finished Aug 21 07:38:35 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1816163274 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.1816163274
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/23.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_smoke.2276157462
Short name T326
Test name
Test status
Simulation time 248306217 ps
CPU time 8.34 seconds
Started Aug 21 07:38:16 PM UTC 24
Finished Aug 21 07:38:25 PM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2276157462 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.2276157462
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/23.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all.2039230202
Short name T153
Test name
Test status
Simulation time 9255155550 ps
CPU time 71.92 seconds
Started Aug 21 07:38:23 PM UTC 24
Finished Aug 21 07:39:37 PM UTC 24
Peak memory 257728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2039230202
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_st
ress_all.2039230202
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_test_access.3482049686
Short name T557
Test name
Test status
Simulation time 2807313666 ps
CPU time 25.52 seconds
Started Aug 21 07:38:23 PM UTC 24
Finished Aug 21 07:38:50 PM UTC 24
Peak memory 253664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3482049686 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.3482049686
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/23.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.2318135878
Short name T1115
Test name
Test status
Simulation time 2456541941 ps
CPU time 4.6 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:33 PM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2318135878 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.2318135878
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/230.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.3073514698
Short name T1105
Test name
Test status
Simulation time 139214131 ps
CPU time 3.97 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:32 PM UTC 24
Peak memory 250992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3073514698 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.3073514698
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/231.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.506007645
Short name T1103
Test name
Test status
Simulation time 120623079 ps
CPU time 3.9 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:32 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=506007645 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.506007645
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/232.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.616156887
Short name T1094
Test name
Test status
Simulation time 134777972 ps
CPU time 3.09 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:31 PM UTC 24
Peak memory 253272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=616156887 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.616156887
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/233.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.3417567508
Short name T1101
Test name
Test status
Simulation time 193418949 ps
CPU time 3.18 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:32 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3417567508 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.3417567508
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/234.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.281419611
Short name T1113
Test name
Test status
Simulation time 632945937 ps
CPU time 4.32 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:33 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=281419611 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.281419611
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/235.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.181601814
Short name T1109
Test name
Test status
Simulation time 103648401 ps
CPU time 3.71 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:32 PM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=181601814 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.181601814
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/237.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.1983114794
Short name T1111
Test name
Test status
Simulation time 220742987 ps
CPU time 3.77 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:33 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1983114794 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.1983114794
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/238.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.1319324411
Short name T1107
Test name
Test status
Simulation time 146908528 ps
CPU time 3.53 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:32 PM UTC 24
Peak memory 251112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1319324411 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.1319324411
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/239.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_alert_test.1083945251
Short name T547
Test name
Test status
Simulation time 218497156 ps
CPU time 1.91 seconds
Started Aug 21 07:38:30 PM UTC 24
Finished Aug 21 07:38:33 PM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1083945251 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.1083945251
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/24.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_check_fail.4027919188
Short name T46
Test name
Test status
Simulation time 2985955570 ps
CPU time 23.1 seconds
Started Aug 21 07:38:28 PM UTC 24
Finished Aug 21 07:38:52 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4027919188 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.4027919188
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/24.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_errs.2434508486
Short name T561
Test name
Test status
Simulation time 5312355750 ps
CPU time 25.56 seconds
Started Aug 21 07:38:27 PM UTC 24
Finished Aug 21 07:38:54 PM UTC 24
Peak memory 251176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2434508486 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.2434508486
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/24.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_lock.1974135981
Short name T442
Test name
Test status
Simulation time 11842600613 ps
CPU time 29.87 seconds
Started Aug 21 07:38:25 PM UTC 24
Finished Aug 21 07:38:57 PM UTC 24
Peak memory 257852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1974135981 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.1974135981
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/24.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_init_fail.2808016057
Short name T199
Test name
Test status
Simulation time 429069192 ps
CPU time 3.29 seconds
Started Aug 21 07:38:25 PM UTC 24
Finished Aug 21 07:38:30 PM UTC 24
Peak memory 250900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2808016057 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.2808016057
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/24.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_macro_errs.554853551
Short name T546
Test name
Test status
Simulation time 102171103 ps
CPU time 3.29 seconds
Started Aug 21 07:38:28 PM UTC 24
Finished Aug 21 07:38:32 PM UTC 24
Peak memory 251676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=554853551 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.554853551
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/24.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_key_req.603519566
Short name T451
Test name
Test status
Simulation time 1402461631 ps
CPU time 28.66 seconds
Started Aug 21 07:38:28 PM UTC 24
Finished Aug 21 07:38:58 PM UTC 24
Peak memory 251312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=603519566 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.603519566
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_esc.1843472316
Short name T158
Test name
Test status
Simulation time 2905096464 ps
CPU time 12.23 seconds
Started Aug 21 07:38:25 PM UTC 24
Finished Aug 21 07:38:39 PM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1843472316 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.1843472316
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_req.2193826367
Short name T539
Test name
Test status
Simulation time 872729597 ps
CPU time 13.67 seconds
Started Aug 21 07:38:25 PM UTC 24
Finished Aug 21 07:38:40 PM UTC 24
Peak memory 250928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2193826367 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc
_req.2193826367
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_regwen.290934622
Short name T550
Test name
Test status
Simulation time 850956697 ps
CPU time 7.82 seconds
Started Aug 21 07:38:28 PM UTC 24
Finished Aug 21 07:38:36 PM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=290934622 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.290934622
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/24.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_smoke.16153057
Short name T545
Test name
Test status
Simulation time 140436481 ps
CPU time 6.34 seconds
Started Aug 21 07:38:23 PM UTC 24
Finished Aug 21 07:38:31 PM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16153057 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch
/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.16153057
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/24.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all.324156066
Short name T681
Test name
Test status
Simulation time 20782267066 ps
CPU time 138.68 seconds
Started Aug 21 07:38:29 PM UTC 24
Finished Aug 21 07:40:51 PM UTC 24
Peak memory 271896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=324156066 -
assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_str
ess_all.324156066
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.915997242
Short name T90
Test name
Test status
Simulation time 2073722067 ps
CPU time 64.56 seconds
Started Aug 21 07:38:29 PM UTC 24
Finished Aug 21 07:39:36 PM UTC 24
Peak memory 257656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=915997242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.915997242
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_test_access.2752354624
Short name T552
Test name
Test status
Simulation time 3047454620 ps
CPU time 8.38 seconds
Started Aug 21 07:38:29 PM UTC 24
Finished Aug 21 07:38:39 PM UTC 24
Peak memory 251704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2752354624 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.2752354624
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/24.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.668281152
Short name T65
Test name
Test status
Simulation time 173633634 ps
CPU time 3.93 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:33 PM UTC 24
Peak memory 253336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=668281152 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.668281152
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/240.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.457604501
Short name T1117
Test name
Test status
Simulation time 2406469884 ps
CPU time 4.56 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:33 PM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=457604501 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.457604501
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/241.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.151136329
Short name T1106
Test name
Test status
Simulation time 1812246276 ps
CPU time 3.55 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:32 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=151136329 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.151136329
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/242.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.2157919921
Short name T1110
Test name
Test status
Simulation time 139233478 ps
CPU time 3.7 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:33 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2157919921 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.2157919921
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/243.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.1001021839
Short name T1112
Test name
Test status
Simulation time 114898877 ps
CPU time 3.84 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:33 PM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1001021839 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.1001021839
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/244.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.17605827
Short name T1100
Test name
Test status
Simulation time 495921263 ps
CPU time 3.18 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:32 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=17605827 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.17605827
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/245.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.3875182213
Short name T1120
Test name
Test status
Simulation time 2275891010 ps
CPU time 4.99 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:34 PM UTC 24
Peak memory 251236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3875182213 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.3875182213
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/246.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.3430142252
Short name T1104
Test name
Test status
Simulation time 87082201 ps
CPU time 3.3 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:32 PM UTC 24
Peak memory 251504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3430142252 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.3430142252
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/247.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.2306819371
Short name T1099
Test name
Test status
Simulation time 137381789 ps
CPU time 3 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:32 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2306819371 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.2306819371
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/248.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.1970766762
Short name T1119
Test name
Test status
Simulation time 294580311 ps
CPU time 4.78 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:34 PM UTC 24
Peak memory 251180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1970766762 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.1970766762
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/249.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_alert_test.2400406295
Short name T553
Test name
Test status
Simulation time 80107278 ps
CPU time 2.56 seconds
Started Aug 21 07:38:40 PM UTC 24
Finished Aug 21 07:38:43 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2400406295 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.2400406295
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/25.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_errs.3093145607
Short name T381
Test name
Test status
Simulation time 768410454 ps
CPU time 18.42 seconds
Started Aug 21 07:38:37 PM UTC 24
Finished Aug 21 07:38:56 PM UTC 24
Peak memory 251268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3093145607 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.3093145607
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/25.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_lock.3376485964
Short name T562
Test name
Test status
Simulation time 1825369747 ps
CPU time 17.98 seconds
Started Aug 21 07:38:36 PM UTC 24
Finished Aug 21 07:38:56 PM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3376485964 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.3376485964
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/25.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_init_fail.1172035702
Short name T64
Test name
Test status
Simulation time 142030957 ps
CPU time 3.81 seconds
Started Aug 21 07:38:36 PM UTC 24
Finished Aug 21 07:38:41 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1172035702 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.1172035702
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/25.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_macro_errs.758113001
Short name T222
Test name
Test status
Simulation time 1629515908 ps
CPU time 13.96 seconds
Started Aug 21 07:38:37 PM UTC 24
Finished Aug 21 07:38:52 PM UTC 24
Peak memory 251456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=758113001 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.758113001
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/25.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_key_req.2907062704
Short name T473
Test name
Test status
Simulation time 464162976 ps
CPU time 14.02 seconds
Started Aug 21 07:38:37 PM UTC 24
Finished Aug 21 07:38:52 PM UTC 24
Peak memory 251340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2907062704 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.2907062704
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_esc.296070076
Short name T238
Test name
Test status
Simulation time 268886718 ps
CPU time 10.27 seconds
Started Aug 21 07:38:36 PM UTC 24
Finished Aug 21 07:38:48 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=296070076 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.296070076
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_req.4166201275
Short name T567
Test name
Test status
Simulation time 571758175 ps
CPU time 22.43 seconds
Started Aug 21 07:38:36 PM UTC 24
Finished Aug 21 07:39:00 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4166201275 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc
_req.4166201275
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_regwen.3889433083
Short name T560
Test name
Test status
Simulation time 1106843929 ps
CPU time 13.62 seconds
Started Aug 21 07:38:38 PM UTC 24
Finished Aug 21 07:38:53 PM UTC 24
Peak memory 251300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3889433083 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.3889433083
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/25.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_smoke.1903337147
Short name T551
Test name
Test status
Simulation time 900887582 ps
CPU time 5.86 seconds
Started Aug 21 07:38:32 PM UTC 24
Finished Aug 21 07:38:39 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1903337147 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.1903337147
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/25.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_test_access.2764441274
Short name T568
Test name
Test status
Simulation time 2492224302 ps
CPU time 21.5 seconds
Started Aug 21 07:38:38 PM UTC 24
Finished Aug 21 07:39:01 PM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2764441274 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.2764441274
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/25.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.3961752444
Short name T1123
Test name
Test status
Simulation time 1849654872 ps
CPU time 6.16 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:35 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3961752444 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.3961752444
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/250.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.1094519871
Short name T1118
Test name
Test status
Simulation time 257133995 ps
CPU time 4.79 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:34 PM UTC 24
Peak memory 251440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1094519871 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.1094519871
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/251.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.4078811580
Short name T1122
Test name
Test status
Simulation time 127578751 ps
CPU time 5.15 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:34 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4078811580 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.4078811580
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/252.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.4024723889
Short name T203
Test name
Test status
Simulation time 97915528 ps
CPU time 3.62 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:33 PM UTC 24
Peak memory 251232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4024723889 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.4024723889
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/253.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.1457605528
Short name T1116
Test name
Test status
Simulation time 159570818 ps
CPU time 4.21 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:33 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1457605528 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.1457605528
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/254.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.2244540432
Short name T1114
Test name
Test status
Simulation time 150728688 ps
CPU time 3.75 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:33 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2244540432 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.2244540432
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/255.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.2843841970
Short name T1121
Test name
Test status
Simulation time 596686429 ps
CPU time 4.92 seconds
Started Aug 21 07:45:27 PM UTC 24
Finished Aug 21 07:45:34 PM UTC 24
Peak memory 251456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2843841970 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.2843841970
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/256.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.3131563285
Short name T1151
Test name
Test status
Simulation time 1833688444 ps
CPU time 5.18 seconds
Started Aug 21 07:45:39 PM UTC 24
Finished Aug 21 07:45:46 PM UTC 24
Peak memory 252580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3131563285 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.3131563285
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/257.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.911943085
Short name T1126
Test name
Test status
Simulation time 116321906 ps
CPU time 3.69 seconds
Started Aug 21 07:45:39 PM UTC 24
Finished Aug 21 07:45:44 PM UTC 24
Peak memory 250912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=911943085 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.911943085
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/258.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.2453542529
Short name T1130
Test name
Test status
Simulation time 193713435 ps
CPU time 4.02 seconds
Started Aug 21 07:45:39 PM UTC 24
Finished Aug 21 07:45:45 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2453542529 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.2453542529
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/259.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_alert_test.3244857650
Short name T564
Test name
Test status
Simulation time 786525228 ps
CPU time 2.48 seconds
Started Aug 21 07:38:55 PM UTC 24
Finished Aug 21 07:38:58 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3244857650 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.3244857650
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/26.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_check_fail.1664389285
Short name T87
Test name
Test status
Simulation time 30672036963 ps
CPU time 47.26 seconds
Started Aug 21 07:38:50 PM UTC 24
Finished Aug 21 07:39:39 PM UTC 24
Peak memory 257560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1664389285 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.1664389285
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/26.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_errs.2007364850
Short name T575
Test name
Test status
Simulation time 9360050688 ps
CPU time 19.34 seconds
Started Aug 21 07:38:50 PM UTC 24
Finished Aug 21 07:39:10 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2007364850 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.2007364850
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/26.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_lock.2595082250
Short name T566
Test name
Test status
Simulation time 952425260 ps
CPU time 8.08 seconds
Started Aug 21 07:38:50 PM UTC 24
Finished Aug 21 07:38:59 PM UTC 24
Peak memory 253724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2595082250 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.2595082250
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/26.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_macro_errs.2928755736
Short name T252
Test name
Test status
Simulation time 1701584987 ps
CPU time 35.6 seconds
Started Aug 21 07:38:50 PM UTC 24
Finished Aug 21 07:39:27 PM UTC 24
Peak memory 267800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2928755736 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.2928755736
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/26.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_key_req.2196178452
Short name T571
Test name
Test status
Simulation time 558697127 ps
CPU time 13.68 seconds
Started Aug 21 07:38:50 PM UTC 24
Finished Aug 21 07:39:05 PM UTC 24
Peak memory 257448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2196178452 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.2196178452
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_esc.926208013
Short name T558
Test name
Test status
Simulation time 227641209 ps
CPU time 6.33 seconds
Started Aug 21 07:38:44 PM UTC 24
Finished Aug 21 07:38:51 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=926208013 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.926208013
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_req.2087712447
Short name T570
Test name
Test status
Simulation time 2271682813 ps
CPU time 19.11 seconds
Started Aug 21 07:38:42 PM UTC 24
Finished Aug 21 07:39:02 PM UTC 24
Peak memory 257432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2087712447 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc
_req.2087712447
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_regwen.388107533
Short name T563
Test name
Test status
Simulation time 206645819 ps
CPU time 6.02 seconds
Started Aug 21 07:38:50 PM UTC 24
Finished Aug 21 07:38:57 PM UTC 24
Peak memory 257440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=388107533 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.388107533
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/26.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_smoke.3516164918
Short name T556
Test name
Test status
Simulation time 266544441 ps
CPU time 6.8 seconds
Started Aug 21 07:38:42 PM UTC 24
Finished Aug 21 07:38:49 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3516164918 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.3516164918
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/26.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all.1758231910
Short name T213
Test name
Test status
Simulation time 21012755543 ps
CPU time 40.1 seconds
Started Aug 21 07:38:53 PM UTC 24
Finished Aug 21 07:39:34 PM UTC 24
Peak memory 255428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1758231910
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_st
ress_all.1758231910
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_test_access.677987013
Short name T573
Test name
Test status
Simulation time 476207270 ps
CPU time 14.34 seconds
Started Aug 21 07:38:53 PM UTC 24
Finished Aug 21 07:39:08 PM UTC 24
Peak memory 251668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=677987013 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.677987013
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/26.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.2278979463
Short name T1125
Test name
Test status
Simulation time 152835429 ps
CPU time 3.63 seconds
Started Aug 21 07:45:39 PM UTC 24
Finished Aug 21 07:45:44 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2278979463 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.2278979463
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/260.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.3851504722
Short name T1129
Test name
Test status
Simulation time 440603732 ps
CPU time 3.95 seconds
Started Aug 21 07:45:39 PM UTC 24
Finished Aug 21 07:45:45 PM UTC 24
Peak memory 251432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3851504722 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.3851504722
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/261.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.4086472816
Short name T1133
Test name
Test status
Simulation time 157886117 ps
CPU time 4.05 seconds
Started Aug 21 07:45:39 PM UTC 24
Finished Aug 21 07:45:45 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4086472816 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.4086472816
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/262.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.904811880
Short name T1163
Test name
Test status
Simulation time 2505870893 ps
CPU time 6.29 seconds
Started Aug 21 07:45:39 PM UTC 24
Finished Aug 21 07:45:47 PM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=904811880 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.904811880
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/263.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.3747039399
Short name T1157
Test name
Test status
Simulation time 2007439394 ps
CPU time 5.42 seconds
Started Aug 21 07:45:39 PM UTC 24
Finished Aug 21 07:45:46 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3747039399 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.3747039399
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/264.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.4134145023
Short name T1149
Test name
Test status
Simulation time 232492330 ps
CPU time 5.01 seconds
Started Aug 21 07:45:39 PM UTC 24
Finished Aug 21 07:45:46 PM UTC 24
Peak memory 251212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4134145023 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.4134145023
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/265.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.3204158582
Short name T1134
Test name
Test status
Simulation time 299820750 ps
CPU time 3.79 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:45 PM UTC 24
Peak memory 251340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3204158582 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.3204158582
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/266.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.1691786772
Short name T1136
Test name
Test status
Simulation time 124206241 ps
CPU time 4.07 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:45 PM UTC 24
Peak memory 251012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1691786772 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.1691786772
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/267.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.3791618338
Short name T1158
Test name
Test status
Simulation time 189455733 ps
CPU time 5.28 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:46 PM UTC 24
Peak memory 253012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3791618338 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.3791618338
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/268.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.2176121648
Short name T1142
Test name
Test status
Simulation time 92187884 ps
CPU time 4.27 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:45 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2176121648 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.2176121648
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/269.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_alert_test.227272745
Short name T572
Test name
Test status
Simulation time 101915583 ps
CPU time 2.76 seconds
Started Aug 21 07:39:04 PM UTC 24
Finished Aug 21 07:39:08 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=227272745 -ass
ert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.227272745
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/27.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_check_fail.4068747137
Short name T131
Test name
Test status
Simulation time 3428997476 ps
CPU time 11.35 seconds
Started Aug 21 07:38:59 PM UTC 24
Finished Aug 21 07:39:12 PM UTC 24
Peak memory 251208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4068747137 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.4068747137
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/27.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_errs.3461577115
Short name T590
Test name
Test status
Simulation time 894077699 ps
CPU time 29.33 seconds
Started Aug 21 07:38:59 PM UTC 24
Finished Aug 21 07:39:30 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3461577115 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.3461577115
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/27.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_lock.2028937628
Short name T596
Test name
Test status
Simulation time 2991061007 ps
CPU time 38.97 seconds
Started Aug 21 07:38:59 PM UTC 24
Finished Aug 21 07:39:40 PM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2028937628 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.2028937628
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/27.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_init_fail.2251953193
Short name T194
Test name
Test status
Simulation time 467399649 ps
CPU time 5.24 seconds
Started Aug 21 07:38:55 PM UTC 24
Finished Aug 21 07:39:01 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2251953193 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.2251953193
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/27.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_macro_errs.2468042774
Short name T574
Test name
Test status
Simulation time 1034266039 ps
CPU time 9.68 seconds
Started Aug 21 07:38:59 PM UTC 24
Finished Aug 21 07:39:10 PM UTC 24
Peak memory 251300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2468042774 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.2468042774
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/27.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_key_req.372051256
Short name T594
Test name
Test status
Simulation time 843007924 ps
CPU time 31.69 seconds
Started Aug 21 07:38:59 PM UTC 24
Finished Aug 21 07:39:32 PM UTC 24
Peak memory 253332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=372051256 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.372051256
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_esc.159462126
Short name T586
Test name
Test status
Simulation time 1048725264 ps
CPU time 23.61 seconds
Started Aug 21 07:38:59 PM UTC 24
Finished Aug 21 07:39:24 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=159462126 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.159462126
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_req.1525674271
Short name T585
Test name
Test status
Simulation time 2409753979 ps
CPU time 27.34 seconds
Started Aug 21 07:38:55 PM UTC 24
Finished Aug 21 07:39:24 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1525674271 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc
_req.1525674271
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_regwen.4193134270
Short name T577
Test name
Test status
Simulation time 1204268835 ps
CPU time 12.52 seconds
Started Aug 21 07:38:59 PM UTC 24
Finished Aug 21 07:39:13 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4193134270 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.4193134270
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/27.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_smoke.774101935
Short name T569
Test name
Test status
Simulation time 239446458 ps
CPU time 6.15 seconds
Started Aug 21 07:38:55 PM UTC 24
Finished Aug 21 07:39:02 PM UTC 24
Peak memory 251680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=774101935 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.774101935
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/27.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all.3493616220
Short name T750
Test name
Test status
Simulation time 17982930685 ps
CPU time 169.23 seconds
Started Aug 21 07:39:04 PM UTC 24
Finished Aug 21 07:41:56 PM UTC 24
Peak memory 284384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3493616220
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_st
ress_all.3493616220
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.2745263338
Short name T91
Test name
Test status
Simulation time 4720903568 ps
CPU time 105.14 seconds
Started Aug 21 07:38:59 PM UTC 24
Finished Aug 21 07:40:47 PM UTC 24
Peak memory 267836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2745263338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.2745263338
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_test_access.1302052668
Short name T605
Test name
Test status
Simulation time 23076736659 ps
CPU time 48.31 seconds
Started Aug 21 07:38:59 PM UTC 24
Finished Aug 21 07:39:49 PM UTC 24
Peak memory 253424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1302052668 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.1302052668
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/27.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.2285595622
Short name T1140
Test name
Test status
Simulation time 152871846 ps
CPU time 4.24 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:45 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2285595622 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.2285595622
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/270.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.699841224
Short name T1124
Test name
Test status
Simulation time 1350398446 ps
CPU time 2.93 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:44 PM UTC 24
Peak memory 252804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=699841224 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.699841224
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/271.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.1135941522
Short name T1143
Test name
Test status
Simulation time 315760898 ps
CPU time 4.18 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:45 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1135941522 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.1135941522
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/272.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.1428665440
Short name T1144
Test name
Test status
Simulation time 2529097552 ps
CPU time 4.36 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:45 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1428665440 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.1428665440
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/273.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.2988566635
Short name T204
Test name
Test status
Simulation time 213637235 ps
CPU time 3.26 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:44 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2988566635 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.2988566635
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/274.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.3682786560
Short name T1128
Test name
Test status
Simulation time 330715073 ps
CPU time 3.47 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:45 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3682786560 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.3682786560
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/275.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.1035360959
Short name T1156
Test name
Test status
Simulation time 192566264 ps
CPU time 4.93 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:46 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1035360959 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.1035360959
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/276.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.1566018561
Short name T1145
Test name
Test status
Simulation time 1607151495 ps
CPU time 4.33 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:46 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1566018561 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.1566018561
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/277.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.1600659269
Short name T1132
Test name
Test status
Simulation time 245041388 ps
CPU time 3.56 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:45 PM UTC 24
Peak memory 251108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1600659269 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.1600659269
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/278.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.4127037546
Short name T1127
Test name
Test status
Simulation time 566296536 ps
CPU time 3.36 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:45 PM UTC 24
Peak memory 253476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4127037546 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.4127037546
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/279.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_alert_test.1841308188
Short name T584
Test name
Test status
Simulation time 217076538 ps
CPU time 3.68 seconds
Started Aug 21 07:39:18 PM UTC 24
Finished Aug 21 07:39:23 PM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1841308188 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.1841308188
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/28.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_check_fail.51548950
Short name T578
Test name
Test status
Simulation time 924105633 ps
CPU time 7.35 seconds
Started Aug 21 07:39:07 PM UTC 24
Finished Aug 21 07:39:15 PM UTC 24
Peak memory 257560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=51548950 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.51548950
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/28.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_errs.625810609
Short name T595
Test name
Test status
Simulation time 870919536 ps
CPU time 26.66 seconds
Started Aug 21 07:39:04 PM UTC 24
Finished Aug 21 07:39:32 PM UTC 24
Peak memory 255448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=625810609 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.625810609
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/28.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_lock.498585480
Short name T582
Test name
Test status
Simulation time 5160789571 ps
CPU time 15.78 seconds
Started Aug 21 07:39:04 PM UTC 24
Finished Aug 21 07:39:21 PM UTC 24
Peak memory 253240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=498585480 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.498585480
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/28.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_init_fail.2774467677
Short name T576
Test name
Test status
Simulation time 2199048287 ps
CPU time 5.98 seconds
Started Aug 21 07:39:04 PM UTC 24
Finished Aug 21 07:39:11 PM UTC 24
Peak memory 251516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2774467677 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.2774467677
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/28.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_macro_errs.3444238302
Short name T223
Test name
Test status
Simulation time 1286923412 ps
CPU time 22.92 seconds
Started Aug 21 07:39:07 PM UTC 24
Finished Aug 21 07:39:31 PM UTC 24
Peak memory 253504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3444238302 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.3444238302
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/28.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_key_req.72595015
Short name T588
Test name
Test status
Simulation time 961177854 ps
CPU time 13.68 seconds
Started Aug 21 07:39:10 PM UTC 24
Finished Aug 21 07:39:25 PM UTC 24
Peak memory 257412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=72595015 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.72595015
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_esc.211222893
Short name T290
Test name
Test status
Simulation time 565702058 ps
CPU time 4.81 seconds
Started Aug 21 07:39:04 PM UTC 24
Finished Aug 21 07:39:10 PM UTC 24
Peak memory 251436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=211222893 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.211222893
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_req.4020356352
Short name T581
Test name
Test status
Simulation time 779131776 ps
CPU time 15.21 seconds
Started Aug 21 07:39:04 PM UTC 24
Finished Aug 21 07:39:21 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4020356352 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc
_req.4020356352
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_regwen.2200436307
Short name T583
Test name
Test status
Simulation time 3031089837 ps
CPU time 10.84 seconds
Started Aug 21 07:39:10 PM UTC 24
Finished Aug 21 07:39:22 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2200436307 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.2200436307
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/28.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_smoke.327744653
Short name T579
Test name
Test status
Simulation time 566376605 ps
CPU time 10.95 seconds
Started Aug 21 07:39:04 PM UTC 24
Finished Aug 21 07:39:16 PM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=327744653 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.327744653
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/28.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all.4047328678
Short name T445
Test name
Test status
Simulation time 15057070767 ps
CPU time 98.7 seconds
Started Aug 21 07:39:18 PM UTC 24
Finished Aug 21 07:40:59 PM UTC 24
Peak memory 255712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4047328678
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_st
ress_all.4047328678
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_test_access.3334702906
Short name T580
Test name
Test status
Simulation time 2376012836 ps
CPU time 5.71 seconds
Started Aug 21 07:39:10 PM UTC 24
Finished Aug 21 07:39:17 PM UTC 24
Peak memory 253408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3334702906 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.3334702906
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/28.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.194924675
Short name T1160
Test name
Test status
Simulation time 635553561 ps
CPU time 5.37 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:47 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=194924675 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.194924675
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/280.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.2069862143
Short name T1139
Test name
Test status
Simulation time 242632628 ps
CPU time 3.8 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:45 PM UTC 24
Peak memory 251516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2069862143 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.2069862143
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/281.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.1816468202
Short name T1155
Test name
Test status
Simulation time 476161133 ps
CPU time 4.66 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:46 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1816468202 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.1816468202
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/282.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.2574550204
Short name T1138
Test name
Test status
Simulation time 137113211 ps
CPU time 3.72 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:45 PM UTC 24
Peak memory 251580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2574550204 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.2574550204
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/283.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.3233310595
Short name T1159
Test name
Test status
Simulation time 129232837 ps
CPU time 5.09 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:46 PM UTC 24
Peak memory 251448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3233310595 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.3233310595
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/284.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.2305180459
Short name T1153
Test name
Test status
Simulation time 444587300 ps
CPU time 4.53 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:46 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2305180459 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.2305180459
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/285.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.51450743
Short name T1131
Test name
Test status
Simulation time 556773810 ps
CPU time 3.28 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:45 PM UTC 24
Peak memory 251520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=51450743 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.51450743
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/286.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.3623629116
Short name T1148
Test name
Test status
Simulation time 413956707 ps
CPU time 4.28 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:46 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3623629116 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.3623629116
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/287.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.1687937078
Short name T1141
Test name
Test status
Simulation time 210319240 ps
CPU time 3.75 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:45 PM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1687937078 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.1687937078
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/288.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.4280057368
Short name T1161
Test name
Test status
Simulation time 2287334652 ps
CPU time 5.34 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:47 PM UTC 24
Peak memory 251236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4280057368 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.4280057368
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/289.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_alert_test.3771096320
Short name T592
Test name
Test status
Simulation time 695758487 ps
CPU time 2.92 seconds
Started Aug 21 07:39:27 PM UTC 24
Finished Aug 21 07:39:31 PM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3771096320 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.3771096320
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/29.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_check_fail.1645074457
Short name T589
Test name
Test status
Simulation time 269022797 ps
CPU time 4.64 seconds
Started Aug 21 07:39:21 PM UTC 24
Finished Aug 21 07:39:26 PM UTC 24
Peak memory 253400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1645074457 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.1645074457
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/29.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_errs.3166060237
Short name T599
Test name
Test status
Simulation time 1420082703 ps
CPU time 18.3 seconds
Started Aug 21 07:39:21 PM UTC 24
Finished Aug 21 07:39:40 PM UTC 24
Peak memory 251264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3166060237 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.3166060237
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/29.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_lock.3916242707
Short name T622
Test name
Test status
Simulation time 6533389542 ps
CPU time 40.89 seconds
Started Aug 21 07:39:18 PM UTC 24
Finished Aug 21 07:40:01 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3916242707 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.3916242707
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/29.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_init_fail.730980701
Short name T587
Test name
Test status
Simulation time 139436678 ps
CPU time 4.94 seconds
Started Aug 21 07:39:18 PM UTC 24
Finished Aug 21 07:39:24 PM UTC 24
Peak memory 253252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=730980701 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.730980701
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/29.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_macro_errs.2428145169
Short name T637
Test name
Test status
Simulation time 11558050773 ps
CPU time 53.38 seconds
Started Aug 21 07:39:21 PM UTC 24
Finished Aug 21 07:40:16 PM UTC 24
Peak memory 253784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2428145169 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.2428145169
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/29.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_key_req.2752729522
Short name T214
Test name
Test status
Simulation time 1156241808 ps
CPU time 11.52 seconds
Started Aug 21 07:39:23 PM UTC 24
Finished Aug 21 07:39:35 PM UTC 24
Peak memory 257716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2752729522 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.2752729522
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_esc.213701659
Short name T138
Test name
Test status
Simulation time 2788284757 ps
CPU time 6.81 seconds
Started Aug 21 07:39:18 PM UTC 24
Finished Aug 21 07:39:26 PM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=213701659 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.213701659
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_req.1208148975
Short name T429
Test name
Test status
Simulation time 618977353 ps
CPU time 11.02 seconds
Started Aug 21 07:39:18 PM UTC 24
Finished Aug 21 07:39:30 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1208148975 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc
_req.1208148975
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_regwen.1184930781
Short name T217
Test name
Test status
Simulation time 3507576386 ps
CPU time 12.62 seconds
Started Aug 21 07:39:23 PM UTC 24
Finished Aug 21 07:39:36 PM UTC 24
Peak memory 251360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1184930781 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.1184930781
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/29.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_smoke.2567599001
Short name T593
Test name
Test status
Simulation time 662278721 ps
CPU time 11.98 seconds
Started Aug 21 07:39:18 PM UTC 24
Finished Aug 21 07:39:31 PM UTC 24
Peak memory 257596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2567599001 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.2567599001
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/29.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all.2272744163
Short name T591
Test name
Test status
Simulation time 132959697 ps
CPU time 2.74 seconds
Started Aug 21 07:39:27 PM UTC 24
Finished Aug 21 07:39:30 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2272744163
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_st
ress_all.2272744163
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_test_access.1639261718
Short name T601
Test name
Test status
Simulation time 617215616 ps
CPU time 19.41 seconds
Started Aug 21 07:39:23 PM UTC 24
Finished Aug 21 07:39:43 PM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1639261718 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.1639261718
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/29.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.360185425
Short name T1150
Test name
Test status
Simulation time 250448121 ps
CPU time 4.13 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:46 PM UTC 24
Peak memory 251116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=360185425 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.360185425
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/290.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.345994322
Short name T1165
Test name
Test status
Simulation time 1964437407 ps
CPU time 5.71 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:47 PM UTC 24
Peak memory 251392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=345994322 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.345994322
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/291.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.3937771685
Short name T1135
Test name
Test status
Simulation time 210975567 ps
CPU time 3.3 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:45 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3937771685 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.3937771685
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/292.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.3343961996
Short name T1154
Test name
Test status
Simulation time 536538718 ps
CPU time 4.33 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:46 PM UTC 24
Peak memory 251260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3343961996 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.3343961996
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/293.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.3854988847
Short name T1146
Test name
Test status
Simulation time 131616867 ps
CPU time 3.94 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:46 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3854988847 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.3854988847
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/294.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.3271512860
Short name T1137
Test name
Test status
Simulation time 258047697 ps
CPU time 3.38 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:45 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3271512860 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.3271512860
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/295.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.4030459777
Short name T1164
Test name
Test status
Simulation time 644872145 ps
CPU time 5.43 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:47 PM UTC 24
Peak memory 251172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4030459777 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.4030459777
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/296.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.3488648108
Short name T1166
Test name
Test status
Simulation time 2175397846 ps
CPU time 5.94 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:48 PM UTC 24
Peak memory 251396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3488648108 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.3488648108
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/297.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.3601002923
Short name T1147
Test name
Test status
Simulation time 1528333588 ps
CPU time 4.02 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:46 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3601002923 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.3601002923
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/298.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.1217856794
Short name T1162
Test name
Test status
Simulation time 2175370747 ps
CPU time 5.15 seconds
Started Aug 21 07:45:40 PM UTC 24
Finished Aug 21 07:45:47 PM UTC 24
Peak memory 251236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1217856794 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.1217856794
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/299.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_alert_test.2075521689
Short name T113
Test name
Test status
Simulation time 101661266 ps
CPU time 2.61 seconds
Started Aug 21 07:35:22 PM UTC 24
Finished Aug 21 07:35:26 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2075521689 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.2075521689
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_background_chks.361279095
Short name T95
Test name
Test status
Simulation time 1013666818 ps
CPU time 8.56 seconds
Started Aug 21 07:35:15 PM UTC 24
Finished Aug 21 07:35:25 PM UTC 24
Peak memory 257116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=361279095 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.361279095
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_background_chks/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_check_fail.608668368
Short name T106
Test name
Test status
Simulation time 1069080233 ps
CPU time 9.51 seconds
Started Aug 21 07:35:17 PM UTC 24
Finished Aug 21 07:35:28 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=608668368 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.608668368
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_errs.2762358163
Short name T9
Test name
Test status
Simulation time 713853826 ps
CPU time 20.58 seconds
Started Aug 21 07:35:15 PM UTC 24
Finished Aug 21 07:35:37 PM UTC 24
Peak memory 251104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2762358163 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.2762358163
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_lock.3072332533
Short name T122
Test name
Test status
Simulation time 1889081642 ps
CPU time 25.87 seconds
Started Aug 21 07:35:15 PM UTC 24
Finished Aug 21 07:35:43 PM UTC 24
Peak memory 251324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3072332533 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.3072332533
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_key_req.4076607678
Short name T121
Test name
Test status
Simulation time 759798757 ps
CPU time 25.11 seconds
Started Aug 21 07:35:18 PM UTC 24
Finished Aug 21 07:35:45 PM UTC 24
Peak memory 251304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4076607678 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.4076607678
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_esc.2676166100
Short name T97
Test name
Test status
Simulation time 319482957 ps
CPU time 9.34 seconds
Started Aug 21 07:35:15 PM UTC 24
Finished Aug 21 07:35:26 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2676166100 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.2676166100
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_req.3468528098
Short name T119
Test name
Test status
Simulation time 1549520575 ps
CPU time 22.21 seconds
Started Aug 21 07:35:15 PM UTC 24
Finished Aug 21 07:35:39 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3468528098 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_
req.3468528098
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_sec_cm.1842535765
Short name T267
Test name
Test status
Simulation time 173514398999 ps
CPU time 274.37 seconds
Started Aug 21 07:35:21 PM UTC 24
Finished Aug 21 07:39:59 PM UTC 24
Peak memory 300152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1842535765 -ass
ert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.1842535765
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/3.otp_ctrl_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_alert_test.1716145470
Short name T554
Test name
Test status
Simulation time 56365061 ps
CPU time 2.73 seconds
Started Aug 21 07:39:32 PM UTC 24
Finished Aug 21 07:39:37 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1716145470 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.1716145470
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/30.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_check_fail.511278329
Short name T626
Test name
Test status
Simulation time 11214109961 ps
CPU time 29.27 seconds
Started Aug 21 07:39:30 PM UTC 24
Finished Aug 21 07:40:03 PM UTC 24
Peak memory 253532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=511278329 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.511278329
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/30.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_errs.845006218
Short name T611
Test name
Test status
Simulation time 9350685203 ps
CPU time 21.4 seconds
Started Aug 21 07:39:30 PM UTC 24
Finished Aug 21 07:39:55 PM UTC 24
Peak memory 251584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=845006218 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.845006218
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/30.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_lock.2429063598
Short name T448
Test name
Test status
Simulation time 8826020544 ps
CPU time 17.99 seconds
Started Aug 21 07:39:30 PM UTC 24
Finished Aug 21 07:39:51 PM UTC 24
Peak memory 251484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2429063598 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.2429063598
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/30.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_macro_errs.1199041175
Short name T598
Test name
Test status
Simulation time 214219113 ps
CPU time 6.72 seconds
Started Aug 21 07:39:30 PM UTC 24
Finished Aug 21 07:39:40 PM UTC 24
Peak memory 251356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1199041175 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.1199041175
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/30.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_key_req.2941616469
Short name T597
Test name
Test status
Simulation time 285962027 ps
CPU time 6.64 seconds
Started Aug 21 07:39:30 PM UTC 24
Finished Aug 21 07:39:40 PM UTC 24
Peak memory 251312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2941616469 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.2941616469
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_esc.166368262
Short name T219
Test name
Test status
Simulation time 769854108 ps
CPU time 11.3 seconds
Started Aug 21 07:39:27 PM UTC 24
Finished Aug 21 07:39:39 PM UTC 24
Peak memory 257328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=166368262 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.166368262
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_req.4054030232
Short name T218
Test name
Test status
Simulation time 684261168 ps
CPU time 8.82 seconds
Started Aug 21 07:39:27 PM UTC 24
Finished Aug 21 07:39:37 PM UTC 24
Peak memory 257364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4054030232 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc
_req.4054030232
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_regwen.1599453622
Short name T600
Test name
Test status
Simulation time 898457009 ps
CPU time 7.12 seconds
Started Aug 21 07:39:30 PM UTC 24
Finished Aug 21 07:39:41 PM UTC 24
Peak memory 251552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1599453622 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.1599453622
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/30.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_smoke.1629857589
Short name T215
Test name
Test status
Simulation time 463466230 ps
CPU time 7.94 seconds
Started Aug 21 07:39:27 PM UTC 24
Finished Aug 21 07:39:36 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1629857589 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.1629857589
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/30.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all.1837497588
Short name T371
Test name
Test status
Simulation time 19127154557 ps
CPU time 108.85 seconds
Started Aug 21 07:39:32 PM UTC 24
Finished Aug 21 07:41:24 PM UTC 24
Peak memory 274040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1837497588
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_st
ress_all.1837497588
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_test_access.2615016931
Short name T615
Test name
Test status
Simulation time 1651169739 ps
CPU time 23.83 seconds
Started Aug 21 07:39:30 PM UTC 24
Finished Aug 21 07:39:58 PM UTC 24
Peak memory 253368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2615016931 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.2615016931
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/30.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_alert_test.1528964216
Short name T607
Test name
Test status
Simulation time 848890211 ps
CPU time 2.76 seconds
Started Aug 21 07:39:45 PM UTC 24
Finished Aug 21 07:39:49 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1528964216 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.1528964216
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/31.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_check_fail.2879778928
Short name T433
Test name
Test status
Simulation time 1015356393 ps
CPU time 7.25 seconds
Started Aug 21 07:39:37 PM UTC 24
Finished Aug 21 07:39:46 PM UTC 24
Peak memory 251324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2879778928 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.2879778928
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/31.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_errs.924173858
Short name T629
Test name
Test status
Simulation time 1011921827 ps
CPU time 30.26 seconds
Started Aug 21 07:39:37 PM UTC 24
Finished Aug 21 07:40:09 PM UTC 24
Peak memory 251264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=924173858 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.924173858
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/31.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_lock.3271120990
Short name T606
Test name
Test status
Simulation time 371118033 ps
CPU time 10.95 seconds
Started Aug 21 07:39:37 PM UTC 24
Finished Aug 21 07:39:49 PM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3271120990 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.3271120990
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/31.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_init_fail.1760679069
Short name T53
Test name
Test status
Simulation time 147228097 ps
CPU time 4.68 seconds
Started Aug 21 07:39:32 PM UTC 24
Finished Aug 21 07:39:39 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1760679069 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.1760679069
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/31.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_macro_errs.4038351653
Short name T170
Test name
Test status
Simulation time 1767170690 ps
CPU time 21.17 seconds
Started Aug 21 07:39:37 PM UTC 24
Finished Aug 21 07:40:00 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4038351653 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.4038351653
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/31.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_key_req.239691408
Short name T602
Test name
Test status
Simulation time 287143263 ps
CPU time 5.82 seconds
Started Aug 21 07:39:37 PM UTC 24
Finished Aug 21 07:39:44 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=239691408 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.239691408
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_esc.2290936993
Short name T603
Test name
Test status
Simulation time 3605124498 ps
CPU time 7.23 seconds
Started Aug 21 07:39:37 PM UTC 24
Finished Aug 21 07:39:46 PM UTC 24
Peak memory 251500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2290936993 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.2290936993
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_req.3325199174
Short name T604
Test name
Test status
Simulation time 1511698739 ps
CPU time 12.12 seconds
Started Aug 21 07:39:34 PM UTC 24
Finished Aug 21 07:39:47 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3325199174 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc
_req.3325199174
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_regwen.3501422934
Short name T613
Test name
Test status
Simulation time 420923535 ps
CPU time 8.94 seconds
Started Aug 21 07:39:45 PM UTC 24
Finished Aug 21 07:39:56 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3501422934 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.3501422934
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/31.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_smoke.1122083402
Short name T559
Test name
Test status
Simulation time 361969553 ps
CPU time 6.31 seconds
Started Aug 21 07:39:32 PM UTC 24
Finished Aug 21 07:39:41 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1122083402 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.1122083402
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/31.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.3440620096
Short name T434
Test name
Test status
Simulation time 12911270287 ps
CPU time 91.15 seconds
Started Aug 21 07:39:45 PM UTC 24
Finished Aug 21 07:41:19 PM UTC 24
Peak memory 268036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3440620096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.3440620096
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_test_access.1609799537
Short name T636
Test name
Test status
Simulation time 2157114216 ps
CPU time 28.15 seconds
Started Aug 21 07:39:45 PM UTC 24
Finished Aug 21 07:40:15 PM UTC 24
Peak memory 257528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1609799537 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.1609799537
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/31.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_alert_test.35497045
Short name T609
Test name
Test status
Simulation time 71709038 ps
CPU time 2.7 seconds
Started Aug 21 07:39:48 PM UTC 24
Finished Aug 21 07:39:52 PM UTC 24
Peak memory 251196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=35497045 -asse
rt nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.35497045
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/32.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_check_fail.2655807135
Short name T32
Test name
Test status
Simulation time 1167617268 ps
CPU time 18.16 seconds
Started Aug 21 07:39:46 PM UTC 24
Finished Aug 21 07:40:05 PM UTC 24
Peak memory 251324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2655807135 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.2655807135
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/32.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_errs.171766598
Short name T625
Test name
Test status
Simulation time 1061096428 ps
CPU time 15.47 seconds
Started Aug 21 07:39:46 PM UTC 24
Finished Aug 21 07:40:03 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=171766598 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.171766598
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/32.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_lock.2510425757
Short name T430
Test name
Test status
Simulation time 6263877155 ps
CPU time 16.21 seconds
Started Aug 21 07:39:46 PM UTC 24
Finished Aug 21 07:40:03 PM UTC 24
Peak memory 251676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2510425757 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.2510425757
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/32.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_init_fail.3112956298
Short name T224
Test name
Test status
Simulation time 96733664 ps
CPU time 3.22 seconds
Started Aug 21 07:39:46 PM UTC 24
Finished Aug 21 07:39:50 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3112956298 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.3112956298
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/32.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_macro_errs.2007195871
Short name T644
Test name
Test status
Simulation time 1253063588 ps
CPU time 31.61 seconds
Started Aug 21 07:39:46 PM UTC 24
Finished Aug 21 07:40:19 PM UTC 24
Peak memory 257372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2007195871 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.2007195871
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/32.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_key_req.3821595782
Short name T612
Test name
Test status
Simulation time 444318283 ps
CPU time 8.08 seconds
Started Aug 21 07:39:46 PM UTC 24
Finished Aug 21 07:39:55 PM UTC 24
Peak memory 257488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3821595782 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.3821595782
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_esc.2986371186
Short name T297
Test name
Test status
Simulation time 776240873 ps
CPU time 8.58 seconds
Started Aug 21 07:39:46 PM UTC 24
Finished Aug 21 07:39:56 PM UTC 24
Peak memory 250912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2986371186 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.2986371186
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_req.1495715162
Short name T616
Test name
Test status
Simulation time 1344302037 ps
CPU time 11.33 seconds
Started Aug 21 07:39:46 PM UTC 24
Finished Aug 21 07:39:58 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1495715162 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc
_req.1495715162
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_regwen.462555410
Short name T608
Test name
Test status
Simulation time 1998958319 ps
CPU time 4.29 seconds
Started Aug 21 07:39:46 PM UTC 24
Finished Aug 21 07:39:51 PM UTC 24
Peak memory 257440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=462555410 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.462555410
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/32.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_smoke.3151816885
Short name T620
Test name
Test status
Simulation time 4144533314 ps
CPU time 12.77 seconds
Started Aug 21 07:39:46 PM UTC 24
Finished Aug 21 07:40:00 PM UTC 24
Peak memory 251428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3151816885 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.3151816885
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/32.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all.2445893202
Short name T102
Test name
Test status
Simulation time 12364021299 ps
CPU time 117.25 seconds
Started Aug 21 07:39:48 PM UTC 24
Finished Aug 21 07:41:48 PM UTC 24
Peak memory 267868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2445893202
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_st
ress_all.2445893202
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.3190758466
Short name T352
Test name
Test status
Simulation time 2200010676 ps
CPU time 36.01 seconds
Started Aug 21 07:39:46 PM UTC 24
Finished Aug 21 07:40:24 PM UTC 24
Peak memory 268028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3190758466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.3190758466
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_test_access.4068563847
Short name T459
Test name
Test status
Simulation time 1856981416 ps
CPU time 37.36 seconds
Started Aug 21 07:39:46 PM UTC 24
Finished Aug 21 07:40:25 PM UTC 24
Peak memory 251384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4068563847 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.4068563847
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/32.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_alert_test.3757026215
Short name T614
Test name
Test status
Simulation time 93280905 ps
CPU time 2.56 seconds
Started Aug 21 07:39:54 PM UTC 24
Finished Aug 21 07:39:58 PM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3757026215 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.3757026215
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/33.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_check_fail.3631728879
Short name T631
Test name
Test status
Simulation time 1346593635 ps
CPU time 17.21 seconds
Started Aug 21 07:39:52 PM UTC 24
Finished Aug 21 07:40:10 PM UTC 24
Peak memory 257816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3631728879 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.3631728879
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/33.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_errs.3740446461
Short name T623
Test name
Test status
Simulation time 277611819 ps
CPU time 8.46 seconds
Started Aug 21 07:39:52 PM UTC 24
Finished Aug 21 07:40:01 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3740446461 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.3740446461
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/33.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_lock.760799516
Short name T447
Test name
Test status
Simulation time 2909283944 ps
CPU time 35.54 seconds
Started Aug 21 07:39:48 PM UTC 24
Finished Aug 21 07:40:25 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=760799516 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.760799516
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/33.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_init_fail.404413363
Short name T610
Test name
Test status
Simulation time 121571972 ps
CPU time 3.7 seconds
Started Aug 21 07:39:48 PM UTC 24
Finished Aug 21 07:39:53 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=404413363 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.404413363
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/33.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_macro_errs.2676718425
Short name T617
Test name
Test status
Simulation time 278700333 ps
CPU time 5.69 seconds
Started Aug 21 07:39:52 PM UTC 24
Finished Aug 21 07:39:58 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2676718425 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.2676718425
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/33.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_key_req.3767933033
Short name T652
Test name
Test status
Simulation time 4439924706 ps
CPU time 36.42 seconds
Started Aug 21 07:39:52 PM UTC 24
Finished Aug 21 07:40:29 PM UTC 24
Peak memory 251408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3767933033 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.3767933033
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_esc.2201033733
Short name T618
Test name
Test status
Simulation time 3122232410 ps
CPU time 9.59 seconds
Started Aug 21 07:39:48 PM UTC 24
Finished Aug 21 07:39:59 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2201033733 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.2201033733
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_req.2642186794
Short name T638
Test name
Test status
Simulation time 10670850788 ps
CPU time 26.69 seconds
Started Aug 21 07:39:48 PM UTC 24
Finished Aug 21 07:40:16 PM UTC 24
Peak memory 257428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2642186794 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc
_req.2642186794
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_regwen.3226693421
Short name T619
Test name
Test status
Simulation time 140355315 ps
CPU time 4.76 seconds
Started Aug 21 07:39:53 PM UTC 24
Finished Aug 21 07:39:59 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3226693421 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.3226693421
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/33.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_smoke.2172341168
Short name T621
Test name
Test status
Simulation time 1102695360 ps
CPU time 11.02 seconds
Started Aug 21 07:39:48 PM UTC 24
Finished Aug 21 07:40:00 PM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2172341168 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.2172341168
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/33.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all.2515563164
Short name T143
Test name
Test status
Simulation time 8697067981 ps
CPU time 103.29 seconds
Started Aug 21 07:39:54 PM UTC 24
Finished Aug 21 07:41:39 PM UTC 24
Peak memory 257476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2515563164
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_st
ress_all.2515563164
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.2068188655
Short name T422
Test name
Test status
Simulation time 3171680189 ps
CPU time 84.43 seconds
Started Aug 21 07:39:54 PM UTC 24
Finished Aug 21 07:41:20 PM UTC 24
Peak memory 257716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2068188655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.2068188655
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_test_access.3163420463
Short name T632
Test name
Test status
Simulation time 12091068983 ps
CPU time 16.8 seconds
Started Aug 21 07:39:53 PM UTC 24
Finished Aug 21 07:40:12 PM UTC 24
Peak memory 251616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3163420463 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.3163420463
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/33.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_alert_test.1373890449
Short name T630
Test name
Test status
Simulation time 71164968 ps
CPU time 2.8 seconds
Started Aug 21 07:40:05 PM UTC 24
Finished Aug 21 07:40:09 PM UTC 24
Peak memory 251508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1373890449 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.1373890449
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/34.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_check_fail.851960552
Short name T660
Test name
Test status
Simulation time 12267459067 ps
CPU time 30.71 seconds
Started Aug 21 07:40:01 PM UTC 24
Finished Aug 21 07:40:33 PM UTC 24
Peak memory 257796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=851960552 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.851960552
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/34.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_errs.3854497298
Short name T648
Test name
Test status
Simulation time 1473414075 ps
CPU time 20.89 seconds
Started Aug 21 07:40:00 PM UTC 24
Finished Aug 21 07:40:23 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3854497298 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.3854497298
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/34.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_lock.1150158170
Short name T634
Test name
Test status
Simulation time 394528900 ps
CPU time 10.91 seconds
Started Aug 21 07:40:00 PM UTC 24
Finished Aug 21 07:40:13 PM UTC 24
Peak memory 253460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1150158170 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.1150158170
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/34.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_macro_errs.1009701813
Short name T661
Test name
Test status
Simulation time 4098194662 ps
CPU time 29.07 seconds
Started Aug 21 07:40:05 PM UTC 24
Finished Aug 21 07:40:35 PM UTC 24
Peak memory 257560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1009701813 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.1009701813
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/34.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_key_req.1733877926
Short name T656
Test name
Test status
Simulation time 2044745576 ps
CPU time 25.05 seconds
Started Aug 21 07:40:05 PM UTC 24
Finished Aug 21 07:40:31 PM UTC 24
Peak memory 251568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1733877926 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.1733877926
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_esc.448218810
Short name T627
Test name
Test status
Simulation time 121242617 ps
CPU time 7.35 seconds
Started Aug 21 07:39:57 PM UTC 24
Finished Aug 21 07:40:05 PM UTC 24
Peak memory 253208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=448218810 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.448218810
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_req.135715558
Short name T276
Test name
Test status
Simulation time 2272480960 ps
CPU time 17.6 seconds
Started Aug 21 07:39:57 PM UTC 24
Finished Aug 21 07:40:16 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=135715558 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_
req.135715558
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_regwen.2580837072
Short name T633
Test name
Test status
Simulation time 282538064 ps
CPU time 6.49 seconds
Started Aug 21 07:40:05 PM UTC 24
Finished Aug 21 07:40:13 PM UTC 24
Peak memory 251264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2580837072 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.2580837072
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/34.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_smoke.3585370793
Short name T628
Test name
Test status
Simulation time 894758095 ps
CPU time 10.19 seconds
Started Aug 21 07:39:57 PM UTC 24
Finished Aug 21 07:40:08 PM UTC 24
Peak memory 251456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3585370793 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.3585370793
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/34.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all.1359994382
Short name T852
Test name
Test status
Simulation time 48130533320 ps
CPU time 202.69 seconds
Started Aug 21 07:40:05 PM UTC 24
Finished Aug 21 07:43:31 PM UTC 24
Peak memory 284276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1359994382
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_st
ress_all.1359994382
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_test_access.122145372
Short name T643
Test name
Test status
Simulation time 1082620577 ps
CPU time 12.33 seconds
Started Aug 21 07:40:05 PM UTC 24
Finished Aug 21 07:40:19 PM UTC 24
Peak memory 257448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=122145372 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.122145372
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/34.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_alert_test.2339626995
Short name T640
Test name
Test status
Simulation time 56869764 ps
CPU time 2.56 seconds
Started Aug 21 07:40:13 PM UTC 24
Finished Aug 21 07:40:16 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2339626995 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.2339626995
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/35.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_check_fail.2857814171
Short name T455
Test name
Test status
Simulation time 2343109819 ps
CPU time 13.63 seconds
Started Aug 21 07:40:08 PM UTC 24
Finished Aug 21 07:40:22 PM UTC 24
Peak memory 257556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2857814171 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.2857814171
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/35.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_errs.3759625243
Short name T624
Test name
Test status
Simulation time 416836444 ps
CPU time 21.26 seconds
Started Aug 21 07:40:08 PM UTC 24
Finished Aug 21 07:40:30 PM UTC 24
Peak memory 251336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3759625243 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.3759625243
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/35.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_lock.2456629801
Short name T642
Test name
Test status
Simulation time 769778431 ps
CPU time 11.22 seconds
Started Aug 21 07:40:05 PM UTC 24
Finished Aug 21 07:40:18 PM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2456629801 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.2456629801
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/35.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_init_fail.3852441662
Short name T225
Test name
Test status
Simulation time 577062840 ps
CPU time 5.24 seconds
Started Aug 21 07:40:05 PM UTC 24
Finished Aug 21 07:40:12 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3852441662 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.3852441662
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/35.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_macro_errs.3608894213
Short name T645
Test name
Test status
Simulation time 574964192 ps
CPU time 11.09 seconds
Started Aug 21 07:40:08 PM UTC 24
Finished Aug 21 07:40:20 PM UTC 24
Peak memory 257596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3608894213 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.3608894213
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/35.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_key_req.1897879818
Short name T646
Test name
Test status
Simulation time 577841913 ps
CPU time 11.23 seconds
Started Aug 21 07:40:08 PM UTC 24
Finished Aug 21 07:40:20 PM UTC 24
Peak memory 253620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1897879818 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.1897879818
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_esc.2020588158
Short name T460
Test name
Test status
Simulation time 593499346 ps
CPU time 7.12 seconds
Started Aug 21 07:40:05 PM UTC 24
Finished Aug 21 07:40:14 PM UTC 24
Peak memory 257324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2020588158 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.2020588158
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_req.2326154322
Short name T655
Test name
Test status
Simulation time 11758972454 ps
CPU time 24.05 seconds
Started Aug 21 07:40:05 PM UTC 24
Finished Aug 21 07:40:31 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2326154322 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc
_req.2326154322
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_regwen.1226673206
Short name T405
Test name
Test status
Simulation time 1018739173 ps
CPU time 11.94 seconds
Started Aug 21 07:40:09 PM UTC 24
Finished Aug 21 07:40:22 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1226673206 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.1226673206
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/35.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_smoke.2676906051
Short name T639
Test name
Test status
Simulation time 1462945069 ps
CPU time 9.94 seconds
Started Aug 21 07:40:05 PM UTC 24
Finished Aug 21 07:40:16 PM UTC 24
Peak memory 251648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2676906051 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.2676906051
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/35.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all.3242452848
Short name T237
Test name
Test status
Simulation time 35605160810 ps
CPU time 125.46 seconds
Started Aug 21 07:40:11 PM UTC 24
Finished Aug 21 07:42:19 PM UTC 24
Peak memory 257732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3242452848
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_st
ress_all.3242452848
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_test_access.3458548704
Short name T658
Test name
Test status
Simulation time 917173518 ps
CPU time 19.92 seconds
Started Aug 21 07:40:11 PM UTC 24
Finished Aug 21 07:40:32 PM UTC 24
Peak memory 251380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3458548704 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.3458548704
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/35.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_alert_test.4010302455
Short name T650
Test name
Test status
Simulation time 67893903 ps
CPU time 2.41 seconds
Started Aug 21 07:40:20 PM UTC 24
Finished Aug 21 07:40:23 PM UTC 24
Peak memory 251264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4010302455 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.4010302455
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/36.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_check_fail.1588508036
Short name T33
Test name
Test status
Simulation time 1943193296 ps
CPU time 17.23 seconds
Started Aug 21 07:40:17 PM UTC 24
Finished Aug 21 07:40:36 PM UTC 24
Peak memory 253396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1588508036 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.1588508036
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/36.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_errs.3067946488
Short name T666
Test name
Test status
Simulation time 1644344070 ps
CPU time 22.06 seconds
Started Aug 21 07:40:17 PM UTC 24
Finished Aug 21 07:40:40 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3067946488 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.3067946488
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/36.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_lock.2486880200
Short name T671
Test name
Test status
Simulation time 3347213180 ps
CPU time 22.84 seconds
Started Aug 21 07:40:17 PM UTC 24
Finished Aug 21 07:40:41 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2486880200 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.2486880200
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/36.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_init_fail.1167274468
Short name T41
Test name
Test status
Simulation time 161719505 ps
CPU time 4.13 seconds
Started Aug 21 07:40:14 PM UTC 24
Finished Aug 21 07:40:19 PM UTC 24
Peak memory 250808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1167274468 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.1167274468
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/36.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_macro_errs.292280285
Short name T651
Test name
Test status
Simulation time 201633863 ps
CPU time 4.91 seconds
Started Aug 21 07:40:17 PM UTC 24
Finished Aug 21 07:40:23 PM UTC 24
Peak memory 251264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=292280285 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.292280285
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/36.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_key_req.3597529557
Short name T683
Test name
Test status
Simulation time 4538017046 ps
CPU time 34.31 seconds
Started Aug 21 07:40:17 PM UTC 24
Finished Aug 21 07:40:53 PM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3597529557 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.3597529557
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_esc.1170558221
Short name T653
Test name
Test status
Simulation time 5423609332 ps
CPU time 14.45 seconds
Started Aug 21 07:40:14 PM UTC 24
Finished Aug 21 07:40:30 PM UTC 24
Peak memory 252956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1170558221 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.1170558221
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_req.3403224396
Short name T672
Test name
Test status
Simulation time 707098223 ps
CPU time 25.73 seconds
Started Aug 21 07:40:14 PM UTC 24
Finished Aug 21 07:40:41 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3403224396 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc
_req.3403224396
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_regwen.818290126
Short name T649
Test name
Test status
Simulation time 149472640 ps
CPU time 4.61 seconds
Started Aug 21 07:40:17 PM UTC 24
Finished Aug 21 07:40:23 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=818290126 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.818290126
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/36.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_smoke.3008828286
Short name T647
Test name
Test status
Simulation time 202922799 ps
CPU time 6.27 seconds
Started Aug 21 07:40:13 PM UTC 24
Finished Aug 21 07:40:20 PM UTC 24
Peak memory 251588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3008828286 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.3008828286
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/36.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all.3172917236
Short name T701
Test name
Test status
Simulation time 4370315839 ps
CPU time 50.97 seconds
Started Aug 21 07:40:20 PM UTC 24
Finished Aug 21 07:41:12 PM UTC 24
Peak memory 257476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3172917236
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_st
ress_all.3172917236
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.2690223116
Short name T423
Test name
Test status
Simulation time 1743490358 ps
CPU time 63.02 seconds
Started Aug 21 07:40:20 PM UTC 24
Finished Aug 21 07:41:24 PM UTC 24
Peak memory 257540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2690223116 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.2690223116
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_test_access.3544637851
Short name T441
Test name
Test status
Simulation time 12855336154 ps
CPU time 45.82 seconds
Started Aug 21 07:40:20 PM UTC 24
Finished Aug 21 07:41:07 PM UTC 24
Peak memory 251440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3544637851 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.3544637851
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/36.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_alert_test.2298899347
Short name T659
Test name
Test status
Simulation time 169017877 ps
CPU time 2.24 seconds
Started Aug 21 07:40:29 PM UTC 24
Finished Aug 21 07:40:32 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2298899347 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.2298899347
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/37.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_check_fail.2651982054
Short name T662
Test name
Test status
Simulation time 5968366934 ps
CPU time 7.83 seconds
Started Aug 21 07:40:27 PM UTC 24
Finished Aug 21 07:40:36 PM UTC 24
Peak memory 251392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2651982054 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.2651982054
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/37.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_errs.32547575
Short name T670
Test name
Test status
Simulation time 704878749 ps
CPU time 12.79 seconds
Started Aug 21 07:40:27 PM UTC 24
Finished Aug 21 07:40:41 PM UTC 24
Peak memory 253540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=32547575 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scra
tch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.32547575
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/37.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_lock.3064107468
Short name T419
Test name
Test status
Simulation time 4735754027 ps
CPU time 19.3 seconds
Started Aug 21 07:40:22 PM UTC 24
Finished Aug 21 07:40:43 PM UTC 24
Peak memory 253440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3064107468 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.3064107468
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/37.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_init_fail.2487333934
Short name T641
Test name
Test status
Simulation time 168291070 ps
CPU time 3.95 seconds
Started Aug 21 07:40:22 PM UTC 24
Finished Aug 21 07:40:27 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2487333934 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.2487333934
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/37.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_macro_errs.3354124536
Short name T691
Test name
Test status
Simulation time 2055487246 ps
CPU time 34.53 seconds
Started Aug 21 07:40:27 PM UTC 24
Finished Aug 21 07:41:03 PM UTC 24
Peak memory 255424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3354124536 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.3354124536
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/37.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_key_req.917138759
Short name T669
Test name
Test status
Simulation time 390605215 ps
CPU time 12.59 seconds
Started Aug 21 07:40:27 PM UTC 24
Finished Aug 21 07:40:41 PM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=917138759 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.917138759
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_esc.4141193217
Short name T654
Test name
Test status
Simulation time 2666366839 ps
CPU time 7.1 seconds
Started Aug 21 07:40:22 PM UTC 24
Finished Aug 21 07:40:30 PM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4141193217 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.4141193217
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_req.3907983729
Short name T674
Test name
Test status
Simulation time 8989472680 ps
CPU time 21.77 seconds
Started Aug 21 07:40:22 PM UTC 24
Finished Aug 21 07:40:45 PM UTC 24
Peak memory 257428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3907983729 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc
_req.3907983729
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_regwen.3457656141
Short name T664
Test name
Test status
Simulation time 363543750 ps
CPU time 11.41 seconds
Started Aug 21 07:40:27 PM UTC 24
Finished Aug 21 07:40:39 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3457656141 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.3457656141
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/37.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_smoke.1340981819
Short name T657
Test name
Test status
Simulation time 251967859 ps
CPU time 8.46 seconds
Started Aug 21 07:40:22 PM UTC 24
Finished Aug 21 07:40:32 PM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1340981819 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.1340981819
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/37.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.2017589213
Short name T236
Test name
Test status
Simulation time 5555754045 ps
CPU time 75.76 seconds
Started Aug 21 07:40:27 PM UTC 24
Finished Aug 21 07:41:45 PM UTC 24
Peak memory 255516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2017589213
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_st
ress_all.2017589213
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_test_access.4004981423
Short name T450
Test name
Test status
Simulation time 15556614851 ps
CPU time 41.51 seconds
Started Aug 21 07:40:27 PM UTC 24
Finished Aug 21 07:41:10 PM UTC 24
Peak memory 253680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4004981423 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.4004981423
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/37.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_alert_test.3416341730
Short name T665
Test name
Test status
Simulation time 183948021 ps
CPU time 2.74 seconds
Started Aug 21 07:40:36 PM UTC 24
Finished Aug 21 07:40:40 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3416341730 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.3416341730
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/38.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_check_fail.1022513270
Short name T84
Test name
Test status
Simulation time 1842927977 ps
CPU time 15.19 seconds
Started Aug 21 07:40:31 PM UTC 24
Finished Aug 21 07:40:48 PM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1022513270 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.1022513270
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/38.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_errs.3170638907
Short name T703
Test name
Test status
Simulation time 11344418217 ps
CPU time 41.03 seconds
Started Aug 21 07:40:31 PM UTC 24
Finished Aug 21 07:41:14 PM UTC 24
Peak memory 251588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3170638907 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.3170638907
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/38.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_lock.3429725191
Short name T675
Test name
Test status
Simulation time 557659631 ps
CPU time 13.85 seconds
Started Aug 21 07:40:31 PM UTC 24
Finished Aug 21 07:40:46 PM UTC 24
Peak memory 251476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3429725191 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.3429725191
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/38.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_init_fail.301516306
Short name T28
Test name
Test status
Simulation time 194116904 ps
CPU time 5.35 seconds
Started Aug 21 07:40:29 PM UTC 24
Finished Aug 21 07:40:36 PM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=301516306 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.301516306
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/38.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_macro_errs.3508279925
Short name T673
Test name
Test status
Simulation time 513649389 ps
CPU time 8.55 seconds
Started Aug 21 07:40:34 PM UTC 24
Finished Aug 21 07:40:43 PM UTC 24
Peak memory 253372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3508279925 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.3508279925
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/38.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_key_req.2392542614
Short name T678
Test name
Test status
Simulation time 1852435724 ps
CPU time 14.68 seconds
Started Aug 21 07:40:34 PM UTC 24
Finished Aug 21 07:40:50 PM UTC 24
Peak memory 253400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2392542614 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.2392542614
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_esc.3834533615
Short name T685
Test name
Test status
Simulation time 841743656 ps
CPU time 20.61 seconds
Started Aug 21 07:40:31 PM UTC 24
Finished Aug 21 07:40:53 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3834533615 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.3834533615
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_req.1182530564
Short name T689
Test name
Test status
Simulation time 872674804 ps
CPU time 27.06 seconds
Started Aug 21 07:40:31 PM UTC 24
Finished Aug 21 07:41:00 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1182530564 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc
_req.1182530564
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_regwen.2664505807
Short name T667
Test name
Test status
Simulation time 235077382 ps
CPU time 5.44 seconds
Started Aug 21 07:40:34 PM UTC 24
Finished Aug 21 07:40:40 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2664505807 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.2664505807
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/38.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_smoke.3644956363
Short name T663
Test name
Test status
Simulation time 566172961 ps
CPU time 6.52 seconds
Started Aug 21 07:40:29 PM UTC 24
Finished Aug 21 07:40:37 PM UTC 24
Peak memory 251456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3644956363 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.3644956363
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/38.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all.1372879548
Short name T464
Test name
Test status
Simulation time 47232274407 ps
CPU time 43.95 seconds
Started Aug 21 07:40:36 PM UTC 24
Finished Aug 21 07:41:22 PM UTC 24
Peak memory 253372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1372879548
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_st
ress_all.1372879548
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_test_access.175391993
Short name T668
Test name
Test status
Simulation time 441582550 ps
CPU time 5.41 seconds
Started Aug 21 07:40:34 PM UTC 24
Finished Aug 21 07:40:41 PM UTC 24
Peak memory 257404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=175391993 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.175391993
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/38.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_alert_test.293253301
Short name T679
Test name
Test status
Simulation time 106533599 ps
CPU time 2.56 seconds
Started Aug 21 07:40:46 PM UTC 24
Finished Aug 21 07:40:50 PM UTC 24
Peak memory 251264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=293253301 -ass
ert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.293253301
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/39.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_check_fail.768431246
Short name T85
Test name
Test status
Simulation time 6936433085 ps
CPU time 18.68 seconds
Started Aug 21 07:40:46 PM UTC 24
Finished Aug 21 07:41:06 PM UTC 24
Peak memory 251468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=768431246 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.768431246
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/39.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_errs.217491588
Short name T688
Test name
Test status
Simulation time 372167781 ps
CPU time 17.4 seconds
Started Aug 21 07:40:40 PM UTC 24
Finished Aug 21 07:40:59 PM UTC 24
Peak memory 251356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=217491588 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.217491588
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/39.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_lock.1649235976
Short name T694
Test name
Test status
Simulation time 1397216303 ps
CPU time 27.49 seconds
Started Aug 21 07:40:38 PM UTC 24
Finished Aug 21 07:41:07 PM UTC 24
Peak memory 251608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1649235976 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.1649235976
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/39.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_init_fail.2674376817
Short name T195
Test name
Test status
Simulation time 334281070 ps
CPU time 6.24 seconds
Started Aug 21 07:40:37 PM UTC 24
Finished Aug 21 07:40:44 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2674376817 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.2674376817
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/39.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_macro_errs.1959666917
Short name T705
Test name
Test status
Simulation time 1484068395 ps
CPU time 27.45 seconds
Started Aug 21 07:40:46 PM UTC 24
Finished Aug 21 07:41:15 PM UTC 24
Peak memory 253632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1959666917 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.1959666917
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/39.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_key_req.178281487
Short name T700
Test name
Test status
Simulation time 1916042643 ps
CPU time 24.27 seconds
Started Aug 21 07:40:46 PM UTC 24
Finished Aug 21 07:41:12 PM UTC 24
Peak memory 251312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=178281487 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.178281487
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_esc.1208695743
Short name T680
Test name
Test status
Simulation time 489385281 ps
CPU time 12.74 seconds
Started Aug 21 07:40:37 PM UTC 24
Finished Aug 21 07:40:50 PM UTC 24
Peak memory 251180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1208695743 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.1208695743
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_req.1057777672
Short name T682
Test name
Test status
Simulation time 2245621671 ps
CPU time 14.68 seconds
Started Aug 21 07:40:37 PM UTC 24
Finished Aug 21 07:40:52 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1057777672 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc
_req.1057777672
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_regwen.4131289452
Short name T684
Test name
Test status
Simulation time 277074445 ps
CPU time 5.76 seconds
Started Aug 21 07:40:46 PM UTC 24
Finished Aug 21 07:40:53 PM UTC 24
Peak memory 251616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4131289452 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.4131289452
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/39.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_smoke.1585379431
Short name T676
Test name
Test status
Simulation time 299887994 ps
CPU time 9.63 seconds
Started Aug 21 07:40:36 PM UTC 24
Finished Aug 21 07:40:47 PM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1585379431 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.1585379431
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/39.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all_with_rand_reset.3448845980
Short name T104
Test name
Test status
Simulation time 11330290256 ps
CPU time 154.97 seconds
Started Aug 21 07:40:46 PM UTC 24
Finished Aug 21 07:43:24 PM UTC 24
Peak memory 267956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3448845980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.3448845980
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_test_access.4095802993
Short name T746
Test name
Test status
Simulation time 4615119702 ps
CPU time 62.79 seconds
Started Aug 21 07:40:46 PM UTC 24
Finished Aug 21 07:41:51 PM UTC 24
Peak memory 253684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4095802993 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.4095802993
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/39.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_alert_test.681620735
Short name T311
Test name
Test status
Simulation time 292877929 ps
CPU time 3.28 seconds
Started Aug 21 07:35:33 PM UTC 24
Finished Aug 21 07:35:37 PM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=681620735 -ass
ert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.681620735
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_background_chks.2122733737
Short name T259
Test name
Test status
Simulation time 1552702179 ps
CPU time 31.4 seconds
Started Aug 21 07:35:27 PM UTC 24
Finished Aug 21 07:35:59 PM UTC 24
Peak memory 253364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2122733737 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.2122733737
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_background_chks/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_check_fail.1661627035
Short name T56
Test name
Test status
Simulation time 1649372917 ps
CPU time 25.83 seconds
Started Aug 21 07:35:27 PM UTC 24
Finished Aug 21 07:35:54 PM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1661627035 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.1661627035
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_errs.606993910
Short name T173
Test name
Test status
Simulation time 920499201 ps
CPU time 22.41 seconds
Started Aug 21 07:35:27 PM UTC 24
Finished Aug 21 07:35:50 PM UTC 24
Peak memory 251240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=606993910 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.606993910
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_lock.1525880253
Short name T416
Test name
Test status
Simulation time 10303179864 ps
CPU time 23.58 seconds
Started Aug 21 07:35:27 PM UTC 24
Finished Aug 21 07:35:52 PM UTC 24
Peak memory 253296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1525880253 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.1525880253
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_init_fail.1970132914
Short name T133
Test name
Test status
Simulation time 152947116 ps
CPU time 4.35 seconds
Started Aug 21 07:35:24 PM UTC 24
Finished Aug 21 07:35:30 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1970132914 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.1970132914
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_macro_errs.2097135377
Short name T174
Test name
Test status
Simulation time 4242878219 ps
CPU time 21.64 seconds
Started Aug 21 07:35:29 PM UTC 24
Finished Aug 21 07:35:52 PM UTC 24
Peak memory 257920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2097135377 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.2097135377
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_key_req.952850462
Short name T171
Test name
Test status
Simulation time 3162232265 ps
CPU time 10.11 seconds
Started Aug 21 07:35:29 PM UTC 24
Finished Aug 21 07:35:41 PM UTC 24
Peak memory 253428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=952850462 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.952850462
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_esc.3804724432
Short name T155
Test name
Test status
Simulation time 1454139387 ps
CPU time 11.45 seconds
Started Aug 21 07:35:27 PM UTC 24
Finished Aug 21 07:35:39 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3804724432 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.3804724432
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_req.2431984994
Short name T234
Test name
Test status
Simulation time 603648879 ps
CPU time 5.13 seconds
Started Aug 21 07:35:27 PM UTC 24
Finished Aug 21 07:35:33 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2431984994 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_
req.2431984994
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_regwen.3514734859
Short name T476
Test name
Test status
Simulation time 146320150 ps
CPU time 5.87 seconds
Started Aug 21 07:35:29 PM UTC 24
Finished Aug 21 07:35:37 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3514734859 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.3514734859
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_sec_cm.3401657630
Short name T24
Test name
Test status
Simulation time 21075187367 ps
CPU time 203.17 seconds
Started Aug 21 07:35:33 PM UTC 24
Finished Aug 21 07:38:59 PM UTC 24
Peak memory 290064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enable
d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3401657630 -ass
ert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.3401657630
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_sec_cm/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_smoke.1775417489
Short name T178
Test name
Test status
Simulation time 1559182668 ps
CPU time 5.23 seconds
Started Aug 21 07:35:23 PM UTC 24
Finished Aug 21 07:35:30 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1775417489 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.1775417489
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/4.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_alert_test.2646702673
Short name T687
Test name
Test status
Simulation time 63596148 ps
CPU time 2.35 seconds
Started Aug 21 07:40:54 PM UTC 24
Finished Aug 21 07:40:58 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2646702673 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.2646702673
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/40.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_check_fail.1033921890
Short name T431
Test name
Test status
Simulation time 3237435770 ps
CPU time 6.22 seconds
Started Aug 21 07:40:50 PM UTC 24
Finished Aug 21 07:40:57 PM UTC 24
Peak memory 257620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1033921890 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.1033921890
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/40.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_errs.3408198850
Short name T693
Test name
Test status
Simulation time 13729172410 ps
CPU time 31.44 seconds
Started Aug 21 07:40:50 PM UTC 24
Finished Aug 21 07:41:22 PM UTC 24
Peak memory 253376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3408198850 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.3408198850
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/40.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_lock.4218037581
Short name T706
Test name
Test status
Simulation time 4447077252 ps
CPU time 25.95 seconds
Started Aug 21 07:40:50 PM UTC 24
Finished Aug 21 07:41:17 PM UTC 24
Peak memory 253720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4218037581 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.4218037581
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/40.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_init_fail.2777110434
Short name T200
Test name
Test status
Simulation time 300721227 ps
CPU time 3.28 seconds
Started Aug 21 07:40:47 PM UTC 24
Finished Aug 21 07:40:51 PM UTC 24
Peak memory 251520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2777110434 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.2777110434
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/40.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_macro_errs.1633557666
Short name T702
Test name
Test status
Simulation time 1828493528 ps
CPU time 22.92 seconds
Started Aug 21 07:40:50 PM UTC 24
Finished Aug 21 07:41:14 PM UTC 24
Peak memory 255704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1633557666 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.1633557666
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/40.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_key_req.3807418966
Short name T710
Test name
Test status
Simulation time 754516267 ps
CPU time 27.57 seconds
Started Aug 21 07:40:50 PM UTC 24
Finished Aug 21 07:41:19 PM UTC 24
Peak memory 253360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3807418966 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.3807418966
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_esc.3761357898
Short name T235
Test name
Test status
Simulation time 605524477 ps
CPU time 21.52 seconds
Started Aug 21 07:40:47 PM UTC 24
Finished Aug 21 07:41:09 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3761357898 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.3761357898
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_req.2296730245
Short name T704
Test name
Test status
Simulation time 1547615325 ps
CPU time 26.75 seconds
Started Aug 21 07:40:47 PM UTC 24
Finished Aug 21 07:41:15 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2296730245 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc
_req.2296730245
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_regwen.3860121547
Short name T695
Test name
Test status
Simulation time 307285888 ps
CPU time 14.09 seconds
Started Aug 21 07:40:52 PM UTC 24
Finished Aug 21 07:41:07 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3860121547 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.3860121547
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/40.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_smoke.779123074
Short name T686
Test name
Test status
Simulation time 995013115 ps
CPU time 7.56 seconds
Started Aug 21 07:40:46 PM UTC 24
Finished Aug 21 07:40:55 PM UTC 24
Peak memory 251440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=779123074 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.779123074
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/40.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all.723560490
Short name T791
Test name
Test status
Simulation time 13681402259 ps
CPU time 92.92 seconds
Started Aug 21 07:40:52 PM UTC 24
Finished Aug 21 07:42:27 PM UTC 24
Peak memory 255424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=723560490 -
assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_str
ess_all.723560490
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.256994951
Short name T1003
Test name
Test status
Simulation time 63681635494 ps
CPU time 244.32 seconds
Started Aug 21 07:40:52 PM UTC 24
Finished Aug 21 07:45:00 PM UTC 24
Peak memory 284276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=256994951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.256994951
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_test_access.2918982140
Short name T733
Test name
Test status
Simulation time 4315863274 ps
CPU time 48.36 seconds
Started Aug 21 07:40:52 PM UTC 24
Finished Aug 21 07:41:42 PM UTC 24
Peak memory 253432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2918982140 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.2918982140
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/40.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_alert_test.1670200811
Short name T698
Test name
Test status
Simulation time 153195985 ps
CPU time 2.68 seconds
Started Aug 21 07:41:06 PM UTC 24
Finished Aug 21 07:41:10 PM UTC 24
Peak memory 251228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1670200811 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.1670200811
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/41.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_check_fail.1382135654
Short name T58
Test name
Test status
Simulation time 1186936561 ps
CPU time 26.79 seconds
Started Aug 21 07:41:00 PM UTC 24
Finished Aug 21 07:41:28 PM UTC 24
Peak memory 257752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1382135654 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.1382135654
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/41.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_errs.1054192549
Short name T719
Test name
Test status
Simulation time 1095557270 ps
CPU time 31.11 seconds
Started Aug 21 07:40:58 PM UTC 24
Finished Aug 21 07:41:30 PM UTC 24
Peak memory 253444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1054192549 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.1054192549
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/41.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_lock.2693817640
Short name T709
Test name
Test status
Simulation time 901336085 ps
CPU time 21.26 seconds
Started Aug 21 07:40:56 PM UTC 24
Finished Aug 21 07:41:18 PM UTC 24
Peak memory 251668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2693817640 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.2693817640
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/41.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_init_fail.3423930054
Short name T690
Test name
Test status
Simulation time 458774577 ps
CPU time 5.14 seconds
Started Aug 21 07:40:55 PM UTC 24
Finished Aug 21 07:41:01 PM UTC 24
Peak memory 253272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3423930054 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.3423930054
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/41.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_macro_errs.1688854073
Short name T769
Test name
Test status
Simulation time 4356948212 ps
CPU time 67.18 seconds
Started Aug 21 07:41:00 PM UTC 24
Finished Aug 21 07:42:09 PM UTC 24
Peak memory 267904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1688854073 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.1688854073
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/41.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_key_req.2907842334
Short name T715
Test name
Test status
Simulation time 9992960759 ps
CPU time 24.1 seconds
Started Aug 21 07:41:01 PM UTC 24
Finished Aug 21 07:41:26 PM UTC 24
Peak memory 253420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2907842334 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.2907842334
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_esc.1640305910
Short name T440
Test name
Test status
Simulation time 2035280682 ps
CPU time 8.66 seconds
Started Aug 21 07:40:55 PM UTC 24
Finished Aug 21 07:41:04 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1640305910 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.1640305910
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_req.869212623
Short name T697
Test name
Test status
Simulation time 1492489972 ps
CPU time 13.33 seconds
Started Aug 21 07:40:55 PM UTC 24
Finished Aug 21 07:41:09 PM UTC 24
Peak memory 257688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=869212623 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_
req.869212623
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_regwen.766346956
Short name T696
Test name
Test status
Simulation time 157714759 ps
CPU time 4.09 seconds
Started Aug 21 07:41:02 PM UTC 24
Finished Aug 21 07:41:07 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=766346956 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.766346956
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/41.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_smoke.3661714532
Short name T692
Test name
Test status
Simulation time 459471432 ps
CPU time 7.64 seconds
Started Aug 21 07:40:55 PM UTC 24
Finished Aug 21 07:41:03 PM UTC 24
Peak memory 251648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3661714532 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.3661714532
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/41.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all.3270092040
Short name T713
Test name
Test status
Simulation time 1638944741 ps
CPU time 19.44 seconds
Started Aug 21 07:41:05 PM UTC 24
Finished Aug 21 07:41:25 PM UTC 24
Peak memory 251268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3270092040
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_st
ress_all.3270092040
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.1821785788
Short name T149
Test name
Test status
Simulation time 4452360548 ps
CPU time 117.11 seconds
Started Aug 21 07:41:04 PM UTC 24
Finished Aug 21 07:43:04 PM UTC 24
Peak memory 270004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1821785788 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.1821785788
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_test_access.3021798305
Short name T699
Test name
Test status
Simulation time 503980755 ps
CPU time 6.91 seconds
Started Aug 21 07:41:02 PM UTC 24
Finished Aug 21 07:41:10 PM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3021798305 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.3021798305
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/41.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_alert_test.3688509432
Short name T712
Test name
Test status
Simulation time 79056259 ps
CPU time 2.35 seconds
Started Aug 21 07:41:18 PM UTC 24
Finished Aug 21 07:41:22 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3688509432 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.3688509432
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/42.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_check_fail.2400044904
Short name T727
Test name
Test status
Simulation time 2903847436 ps
CPU time 25.81 seconds
Started Aug 21 07:41:11 PM UTC 24
Finished Aug 21 07:41:38 PM UTC 24
Peak memory 255768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2400044904 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.2400044904
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/42.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_errs.4054776610
Short name T729
Test name
Test status
Simulation time 3630747647 ps
CPU time 26.64 seconds
Started Aug 21 07:41:11 PM UTC 24
Finished Aug 21 07:41:39 PM UTC 24
Peak memory 255448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4054776610 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.4054776610
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/42.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_lock.1920239524
Short name T739
Test name
Test status
Simulation time 7259098328 ps
CPU time 36.52 seconds
Started Aug 21 07:41:11 PM UTC 24
Finished Aug 21 07:41:49 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1920239524 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.1920239524
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/42.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_init_fail.1885238499
Short name T708
Test name
Test status
Simulation time 316437762 ps
CPU time 6.3 seconds
Started Aug 21 07:41:11 PM UTC 24
Finished Aug 21 07:41:18 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1885238499 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.1885238499
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/42.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_macro_errs.948556894
Short name T718
Test name
Test status
Simulation time 12392586441 ps
CPU time 14.54 seconds
Started Aug 21 07:41:13 PM UTC 24
Finished Aug 21 07:41:29 PM UTC 24
Peak memory 253860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=948556894 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.948556894
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/42.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_key_req.3811961100
Short name T461
Test name
Test status
Simulation time 8672805531 ps
CPU time 22.74 seconds
Started Aug 21 07:41:13 PM UTC 24
Finished Aug 21 07:41:37 PM UTC 24
Peak memory 253428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3811961100 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.3811961100
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_esc.3108624765
Short name T711
Test name
Test status
Simulation time 1002788101 ps
CPU time 8.77 seconds
Started Aug 21 07:41:11 PM UTC 24
Finished Aug 21 07:41:21 PM UTC 24
Peak memory 257300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3108624765 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.3108624765
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_req.3362840368
Short name T457
Test name
Test status
Simulation time 1398339547 ps
CPU time 25.62 seconds
Started Aug 21 07:41:11 PM UTC 24
Finished Aug 21 07:41:38 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3362840368 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc
_req.3362840368
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_regwen.2913493486
Short name T707
Test name
Test status
Simulation time 255665279 ps
CPU time 3.11 seconds
Started Aug 21 07:41:14 PM UTC 24
Finished Aug 21 07:41:18 PM UTC 24
Peak memory 257436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2913493486 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.2913493486
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/42.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_smoke.228893532
Short name T677
Test name
Test status
Simulation time 609366737 ps
CPU time 13.71 seconds
Started Aug 21 07:41:07 PM UTC 24
Finished Aug 21 07:41:22 PM UTC 24
Peak memory 251332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=228893532 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.228893532
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/42.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all.2426319756
Short name T458
Test name
Test status
Simulation time 4020707233 ps
CPU time 78.3 seconds
Started Aug 21 07:41:18 PM UTC 24
Finished Aug 21 07:42:39 PM UTC 24
Peak memory 269816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2426319756
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_st
ress_all.2426319756
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_test_access.2819633084
Short name T334
Test name
Test status
Simulation time 457692135 ps
CPU time 8.1 seconds
Started Aug 21 07:41:14 PM UTC 24
Finished Aug 21 07:41:23 PM UTC 24
Peak memory 251376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2819633084 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.2819633084
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/42.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_alert_test.1526747935
Short name T721
Test name
Test status
Simulation time 57045496 ps
CPU time 2.33 seconds
Started Aug 21 07:41:30 PM UTC 24
Finished Aug 21 07:41:33 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1526747935 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.1526747935
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/43.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_check_fail.1352161783
Short name T736
Test name
Test status
Simulation time 5310549229 ps
CPU time 14.41 seconds
Started Aug 21 07:41:30 PM UTC 24
Finished Aug 21 07:41:45 PM UTC 24
Peak memory 253460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1352161783 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.1352161783
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/43.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_errs.1396894194
Short name T794
Test name
Test status
Simulation time 18412771310 ps
CPU time 57.18 seconds
Started Aug 21 07:41:30 PM UTC 24
Finished Aug 21 07:42:28 PM UTC 24
Peak memory 259544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1396894194 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.1396894194
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/43.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_lock.3577044694
Short name T760
Test name
Test status
Simulation time 16473965217 ps
CPU time 31.07 seconds
Started Aug 21 07:41:30 PM UTC 24
Finished Aug 21 07:42:02 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3577044694 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.3577044694
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/43.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_init_fail.987678537
Short name T716
Test name
Test status
Simulation time 187276992 ps
CPU time 6.31 seconds
Started Aug 21 07:41:19 PM UTC 24
Finished Aug 21 07:41:26 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=987678537 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.987678537
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/43.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_macro_errs.306710037
Short name T740
Test name
Test status
Simulation time 862069685 ps
CPU time 18.73 seconds
Started Aug 21 07:41:30 PM UTC 24
Finished Aug 21 07:41:50 PM UTC 24
Peak memory 253404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=306710037 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.306710037
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/43.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_key_req.128206588
Short name T725
Test name
Test status
Simulation time 434904388 ps
CPU time 5.9 seconds
Started Aug 21 07:41:30 PM UTC 24
Finished Aug 21 07:41:37 PM UTC 24
Peak memory 251560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=128206588 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.128206588
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_esc.2024608135
Short name T717
Test name
Test status
Simulation time 210595704 ps
CPU time 7.71 seconds
Started Aug 21 07:41:19 PM UTC 24
Finished Aug 21 07:41:28 PM UTC 24
Peak memory 251408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2024608135 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.2024608135
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_req.4085594704
Short name T462
Test name
Test status
Simulation time 2961840640 ps
CPU time 17.92 seconds
Started Aug 21 07:41:19 PM UTC 24
Finished Aug 21 07:41:38 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4085594704 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc
_req.4085594704
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_regwen.2075215099
Short name T724
Test name
Test status
Simulation time 498865008 ps
CPU time 5.77 seconds
Started Aug 21 07:41:30 PM UTC 24
Finished Aug 21 07:41:37 PM UTC 24
Peak memory 251232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2075215099 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.2075215099
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/43.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_smoke.3519603955
Short name T720
Test name
Test status
Simulation time 1286686244 ps
CPU time 13.18 seconds
Started Aug 21 07:41:18 PM UTC 24
Finished Aug 21 07:41:33 PM UTC 24
Peak memory 251376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3519603955 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.3519603955
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/43.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all.4272932303
Short name T770
Test name
Test status
Simulation time 19938433829 ps
CPU time 39.31 seconds
Started Aug 21 07:41:30 PM UTC 24
Finished Aug 21 07:42:11 PM UTC 24
Peak memory 253792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4272932303
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_st
ress_all.4272932303
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_test_access.954396197
Short name T744
Test name
Test status
Simulation time 685307091 ps
CPU time 19.02 seconds
Started Aug 21 07:41:30 PM UTC 24
Finished Aug 21 07:41:50 PM UTC 24
Peak memory 251668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=954396197 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.954396197
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/43.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_alert_test.3254079693
Short name T737
Test name
Test status
Simulation time 728749498 ps
CPU time 2.7 seconds
Started Aug 21 07:41:42 PM UTC 24
Finished Aug 21 07:41:45 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3254079693 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.3254079693
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/44.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_check_fail.3484480288
Short name T752
Test name
Test status
Simulation time 5303384385 ps
CPU time 25.17 seconds
Started Aug 21 07:41:30 PM UTC 24
Finished Aug 21 07:41:57 PM UTC 24
Peak memory 253464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3484480288 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.3484480288
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/44.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_errs.2974663655
Short name T742
Test name
Test status
Simulation time 4455023091 ps
CPU time 18.58 seconds
Started Aug 21 07:41:30 PM UTC 24
Finished Aug 21 07:41:50 PM UTC 24
Peak memory 251332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2974663655 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.2974663655
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/44.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_lock.2926370103
Short name T753
Test name
Test status
Simulation time 5598600771 ps
CPU time 27.28 seconds
Started Aug 21 07:41:30 PM UTC 24
Finished Aug 21 07:41:59 PM UTC 24
Peak memory 251520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2926370103 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.2926370103
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/44.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_init_fail.4140233398
Short name T723
Test name
Test status
Simulation time 1775620567 ps
CPU time 4.05 seconds
Started Aug 21 07:41:30 PM UTC 24
Finished Aug 21 07:41:35 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4140233398 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.4140233398
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/44.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_macro_errs.2439724647
Short name T735
Test name
Test status
Simulation time 942722146 ps
CPU time 12.1 seconds
Started Aug 21 07:41:30 PM UTC 24
Finished Aug 21 07:41:44 PM UTC 24
Peak memory 257600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2439724647 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.2439724647
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/44.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_key_req.2725787390
Short name T732
Test name
Test status
Simulation time 880432940 ps
CPU time 9.6 seconds
Started Aug 21 07:41:30 PM UTC 24
Finished Aug 21 07:41:41 PM UTC 24
Peak memory 251312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2725787390 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.2725787390
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_esc.88416306
Short name T728
Test name
Test status
Simulation time 842686826 ps
CPU time 6.89 seconds
Started Aug 21 07:41:30 PM UTC 24
Finished Aug 21 07:41:38 PM UTC 24
Peak memory 251440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=88416306 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit
an/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.88416306
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_req.2031164343
Short name T741
Test name
Test status
Simulation time 610408758 ps
CPU time 18.53 seconds
Started Aug 21 07:41:30 PM UTC 24
Finished Aug 21 07:41:50 PM UTC 24
Peak memory 253268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2031164343 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc
_req.2031164343
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_regwen.1095661956
Short name T731
Test name
Test status
Simulation time 486931541 ps
CPU time 6.86 seconds
Started Aug 21 07:41:32 PM UTC 24
Finished Aug 21 07:41:40 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1095661956 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.1095661956
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/44.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_smoke.1166366305
Short name T726
Test name
Test status
Simulation time 155298563 ps
CPU time 6.08 seconds
Started Aug 21 07:41:30 PM UTC 24
Finished Aug 21 07:41:37 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1166366305 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.1166366305
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/44.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all.2890115322
Short name T807
Test name
Test status
Simulation time 17054832385 ps
CPU time 63.5 seconds
Started Aug 21 07:41:33 PM UTC 24
Finished Aug 21 07:42:39 PM UTC 24
Peak memory 255428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2890115322
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_st
ress_all.2890115322
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_test_access.3206480798
Short name T734
Test name
Test status
Simulation time 612730248 ps
CPU time 9.72 seconds
Started Aug 21 07:41:32 PM UTC 24
Finished Aug 21 07:41:43 PM UTC 24
Peak memory 257440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3206480798 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.3206480798
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/44.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_alert_test.3079862810
Short name T743
Test name
Test status
Simulation time 64418802 ps
CPU time 2.71 seconds
Started Aug 21 07:41:46 PM UTC 24
Finished Aug 21 07:41:50 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3079862810 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.3079862810
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/45.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_check_fail.2550569836
Short name T66
Test name
Test status
Simulation time 899174761 ps
CPU time 17.31 seconds
Started Aug 21 07:41:42 PM UTC 24
Finished Aug 21 07:42:00 PM UTC 24
Peak memory 253656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2550569836 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.2550569836
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/45.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_errs.4120773688
Short name T761
Test name
Test status
Simulation time 898580529 ps
CPU time 20.02 seconds
Started Aug 21 07:41:42 PM UTC 24
Finished Aug 21 07:42:03 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4120773688 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.4120773688
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/45.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_lock.2435506803
Short name T758
Test name
Test status
Simulation time 11721856135 ps
CPU time 17.6 seconds
Started Aug 21 07:41:42 PM UTC 24
Finished Aug 21 07:42:01 PM UTC 24
Peak memory 253456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2435506803 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.2435506803
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/45.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_init_fail.2952050999
Short name T738
Test name
Test status
Simulation time 246626395 ps
CPU time 4.29 seconds
Started Aug 21 07:41:42 PM UTC 24
Finished Aug 21 07:41:47 PM UTC 24
Peak memory 253248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2952050999 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.2952050999
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/45.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_macro_errs.3739496759
Short name T763
Test name
Test status
Simulation time 1046679190 ps
CPU time 21.09 seconds
Started Aug 21 07:41:42 PM UTC 24
Finished Aug 21 07:42:04 PM UTC 24
Peak memory 257816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3739496759 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.3739496759
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/45.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_key_req.1471375413
Short name T764
Test name
Test status
Simulation time 1012885418 ps
CPU time 22.05 seconds
Started Aug 21 07:41:42 PM UTC 24
Finished Aug 21 07:42:05 PM UTC 24
Peak memory 251340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1471375413 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.1471375413
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_esc.3252413332
Short name T162
Test name
Test status
Simulation time 245277167 ps
CPU time 8.52 seconds
Started Aug 21 07:41:42 PM UTC 24
Finished Aug 21 07:41:51 PM UTC 24
Peak memory 251440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3252413332 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.3252413332
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_req.3707557263
Short name T766
Test name
Test status
Simulation time 9497627492 ps
CPU time 23.74 seconds
Started Aug 21 07:41:42 PM UTC 24
Finished Aug 21 07:42:07 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3707557263 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc
_req.3707557263
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_regwen.509760486
Short name T745
Test name
Test status
Simulation time 1089083890 ps
CPU time 7.44 seconds
Started Aug 21 07:41:42 PM UTC 24
Finished Aug 21 07:41:50 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=509760486 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.509760486
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/45.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_smoke.3051400855
Short name T747
Test name
Test status
Simulation time 527705024 ps
CPU time 9.74 seconds
Started Aug 21 07:41:42 PM UTC 24
Finished Aug 21 07:41:53 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3051400855 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.3051400855
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/45.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all.868764444
Short name T867
Test name
Test status
Simulation time 40597345886 ps
CPU time 112.96 seconds
Started Aug 21 07:41:46 PM UTC 24
Finished Aug 21 07:43:41 PM UTC 24
Peak memory 257468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=868764444 -
assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_str
ess_all.868764444
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.2282807559
Short name T806
Test name
Test status
Simulation time 29930973226 ps
CPU time 49.95 seconds
Started Aug 21 07:41:46 PM UTC 24
Finished Aug 21 07:42:38 PM UTC 24
Peak memory 257720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2282807559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.2282807559
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_test_access.1199895067
Short name T749
Test name
Test status
Simulation time 1141510713 ps
CPU time 12.85 seconds
Started Aug 21 07:41:42 PM UTC 24
Finished Aug 21 07:41:56 PM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1199895067 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.1199895067
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/45.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_alert_test.3369010542
Short name T759
Test name
Test status
Simulation time 372459498 ps
CPU time 6.77 seconds
Started Aug 21 07:41:53 PM UTC 24
Finished Aug 21 07:42:01 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3369010542 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.3369010542
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/46.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_errs.909240882
Short name T786
Test name
Test status
Simulation time 5008925589 ps
CPU time 36.42 seconds
Started Aug 21 07:41:47 PM UTC 24
Finished Aug 21 07:42:24 PM UTC 24
Peak memory 257488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=909240882 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.909240882
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/46.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_lock.1270199703
Short name T754
Test name
Test status
Simulation time 2016530561 ps
CPU time 11.44 seconds
Started Aug 21 07:41:47 PM UTC 24
Finished Aug 21 07:41:59 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1270199703 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.1270199703
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/46.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_init_fail.1395939188
Short name T748
Test name
Test status
Simulation time 1691187160 ps
CPU time 5.47 seconds
Started Aug 21 07:41:46 PM UTC 24
Finished Aug 21 07:41:53 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1395939188 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.1395939188
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/46.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_macro_errs.4051964468
Short name T795
Test name
Test status
Simulation time 1566024872 ps
CPU time 34.35 seconds
Started Aug 21 07:41:53 PM UTC 24
Finished Aug 21 07:42:28 PM UTC 24
Peak memory 257816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4051964468 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.4051964468
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/46.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_key_req.1308876902
Short name T784
Test name
Test status
Simulation time 2156506042 ps
CPU time 26.62 seconds
Started Aug 21 07:41:53 PM UTC 24
Finished Aug 21 07:42:21 PM UTC 24
Peak memory 251400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1308876902 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.1308876902
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_req.488649371
Short name T452
Test name
Test status
Simulation time 11165895768 ps
CPU time 23.69 seconds
Started Aug 21 07:41:46 PM UTC 24
Finished Aug 21 07:42:11 PM UTC 24
Peak memory 257428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=488649371 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_
req.488649371
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_regwen.784518256
Short name T757
Test name
Test status
Simulation time 533119896 ps
CPU time 6.49 seconds
Started Aug 21 07:41:53 PM UTC 24
Finished Aug 21 07:42:00 PM UTC 24
Peak memory 250988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=784518256 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.784518256
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/46.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_smoke.1422643911
Short name T751
Test name
Test status
Simulation time 314299503 ps
CPU time 9.03 seconds
Started Aug 21 07:41:46 PM UTC 24
Finished Aug 21 07:41:56 PM UTC 24
Peak memory 251456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1422643911 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.1422643911
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/46.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all.1660136169
Short name T877
Test name
Test status
Simulation time 10401310396 ps
CPU time 114.79 seconds
Started Aug 21 07:41:53 PM UTC 24
Finished Aug 21 07:43:50 PM UTC 24
Peak memory 257500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1660136169
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_st
ress_all.1660136169
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_test_access.1991756832
Short name T768
Test name
Test status
Simulation time 2518998982 ps
CPU time 15.33 seconds
Started Aug 21 07:41:53 PM UTC 24
Finished Aug 21 07:42:09 PM UTC 24
Peak memory 253392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1991756832 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.1991756832
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/46.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_alert_test.3926261290
Short name T765
Test name
Test status
Simulation time 132667534 ps
CPU time 2.33 seconds
Started Aug 21 07:42:02 PM UTC 24
Finished Aug 21 07:42:05 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3926261290 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.3926261290
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/47.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_errs.562780870
Short name T776
Test name
Test status
Simulation time 629670811 ps
CPU time 16.34 seconds
Started Aug 21 07:41:57 PM UTC 24
Finished Aug 21 07:42:14 PM UTC 24
Peak memory 251456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=562780870 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.562780870
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/47.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_lock.3465261647
Short name T820
Test name
Test status
Simulation time 4991398927 ps
CPU time 47.56 seconds
Started Aug 21 07:41:57 PM UTC 24
Finished Aug 21 07:42:46 PM UTC 24
Peak memory 253444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3465261647 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.3465261647
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/47.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_init_fail.998165100
Short name T755
Test name
Test status
Simulation time 363023139 ps
CPU time 5.44 seconds
Started Aug 21 07:41:53 PM UTC 24
Finished Aug 21 07:42:00 PM UTC 24
Peak memory 251256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=998165100 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.998165100
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/47.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_macro_errs.1706515237
Short name T730
Test name
Test status
Simulation time 1094275083 ps
CPU time 17.29 seconds
Started Aug 21 07:41:57 PM UTC 24
Finished Aug 21 07:42:15 PM UTC 24
Peak memory 253376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1706515237 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.1706515237
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/47.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_key_req.3734779234
Short name T809
Test name
Test status
Simulation time 6404881677 ps
CPU time 35.95 seconds
Started Aug 21 07:42:02 PM UTC 24
Finished Aug 21 07:42:39 PM UTC 24
Peak memory 253280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3734779234 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.3734779234
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_esc.2538490238
Short name T774
Test name
Test status
Simulation time 767221417 ps
CPU time 17.89 seconds
Started Aug 21 07:41:53 PM UTC 24
Finished Aug 21 07:42:12 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2538490238 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.2538490238
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_req.2713455135
Short name T773
Test name
Test status
Simulation time 1140633576 ps
CPU time 16.47 seconds
Started Aug 21 07:41:53 PM UTC 24
Finished Aug 21 07:42:11 PM UTC 24
Peak memory 257368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2713455135 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc
_req.2713455135
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_regwen.456730480
Short name T771
Test name
Test status
Simulation time 397596020 ps
CPU time 7.63 seconds
Started Aug 21 07:42:02 PM UTC 24
Finished Aug 21 07:42:11 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=456730480 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/
opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.456730480
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/47.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_smoke.1703204780
Short name T756
Test name
Test status
Simulation time 169556712 ps
CPU time 5.84 seconds
Started Aug 21 07:41:53 PM UTC 24
Finished Aug 21 07:42:00 PM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1703204780 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.1703204780
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/47.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all.1594197658
Short name T1172
Test name
Test status
Simulation time 55830147678 ps
CPU time 303.3 seconds
Started Aug 21 07:42:02 PM UTC 24
Finished Aug 21 07:47:10 PM UTC 24
Peak memory 273948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1594197658
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_st
ress_all.1594197658
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_test_access.2392438263
Short name T779
Test name
Test status
Simulation time 523202301 ps
CPU time 12.47 seconds
Started Aug 21 07:42:02 PM UTC 24
Finished Aug 21 07:42:16 PM UTC 24
Peak memory 257460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2392438263 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.2392438263
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/47.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_alert_test.382132996
Short name T777
Test name
Test status
Simulation time 71735197 ps
CPU time 1.84 seconds
Started Aug 21 07:42:11 PM UTC 24
Finished Aug 21 07:42:14 PM UTC 24
Peak memory 249740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=382132996 -ass
ert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.382132996
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/48.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_check_fail.1331446616
Short name T796
Test name
Test status
Simulation time 996866535 ps
CPU time 22.96 seconds
Started Aug 21 07:42:04 PM UTC 24
Finished Aug 21 07:42:29 PM UTC 24
Peak memory 253400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1331446616 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.1331446616
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/48.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_errs.885826698
Short name T775
Test name
Test status
Simulation time 312515579 ps
CPU time 9.01 seconds
Started Aug 21 07:42:02 PM UTC 24
Finished Aug 21 07:42:12 PM UTC 24
Peak memory 251512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=885826698 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.885826698
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/48.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_lock.3866693934
Short name T780
Test name
Test status
Simulation time 6168982995 ps
CPU time 13.7 seconds
Started Aug 21 07:42:02 PM UTC 24
Finished Aug 21 07:42:17 PM UTC 24
Peak memory 253440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3866693934 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.3866693934
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/48.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_init_fail.1261706656
Short name T767
Test name
Test status
Simulation time 151313097 ps
CPU time 4.01 seconds
Started Aug 21 07:42:02 PM UTC 24
Finished Aug 21 07:42:07 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1261706656 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.1261706656
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/48.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_macro_errs.2899387302
Short name T819
Test name
Test status
Simulation time 17069007722 ps
CPU time 39.37 seconds
Started Aug 21 07:42:04 PM UTC 24
Finished Aug 21 07:42:45 PM UTC 24
Peak memory 257684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2899387302 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.2899387302
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/48.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_key_req.1132628294
Short name T778
Test name
Test status
Simulation time 325787504 ps
CPU time 8 seconds
Started Aug 21 07:42:06 PM UTC 24
Finished Aug 21 07:42:15 PM UTC 24
Peak memory 251340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1132628294 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.1132628294
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_esc.2529375047
Short name T417
Test name
Test status
Simulation time 219339412 ps
CPU time 5.62 seconds
Started Aug 21 07:42:02 PM UTC 24
Finished Aug 21 07:42:09 PM UTC 24
Peak memory 251212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2529375047 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.2529375047
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_req.1872644048
Short name T801
Test name
Test status
Simulation time 3066318844 ps
CPU time 26.83 seconds
Started Aug 21 07:42:02 PM UTC 24
Finished Aug 21 07:42:30 PM UTC 24
Peak memory 257428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1872644048 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc
_req.1872644048
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_smoke.2040737655
Short name T772
Test name
Test status
Simulation time 375056558 ps
CPU time 7.42 seconds
Started Aug 21 07:42:02 PM UTC 24
Finished Aug 21 07:42:11 PM UTC 24
Peak memory 251456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2040737655 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.2040737655
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/48.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.942826809
Short name T353
Test name
Test status
Simulation time 6554238279 ps
CPU time 57.37 seconds
Started Aug 21 07:42:08 PM UTC 24
Finished Aug 21 07:43:07 PM UTC 24
Peak memory 257692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=942826809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.942826809
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_test_access.1158011850
Short name T783
Test name
Test status
Simulation time 417753578 ps
CPU time 11.62 seconds
Started Aug 21 07:42:06 PM UTC 24
Finished Aug 21 07:42:19 PM UTC 24
Peak memory 251320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1158011850 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.1158011850
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/48.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_alert_test.2883351647
Short name T785
Test name
Test status
Simulation time 68212367 ps
CPU time 2.11 seconds
Started Aug 21 07:42:19 PM UTC 24
Finished Aug 21 07:42:22 PM UTC 24
Peak memory 251420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2883351647 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.2883351647
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/49.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_errs.2349595132
Short name T799
Test name
Test status
Simulation time 440009202 ps
CPU time 13.28 seconds
Started Aug 21 07:42:16 PM UTC 24
Finished Aug 21 07:42:30 PM UTC 24
Peak memory 251388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2349595132 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.2349595132
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/49.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_lock.3488905042
Short name T803
Test name
Test status
Simulation time 7145103856 ps
CPU time 17.63 seconds
Started Aug 21 07:42:16 PM UTC 24
Finished Aug 21 07:42:34 PM UTC 24
Peak memory 253440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3488905042 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.3488905042
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/49.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_init_fail.3866246129
Short name T781
Test name
Test status
Simulation time 2312816370 ps
CPU time 5.09 seconds
Started Aug 21 07:42:11 PM UTC 24
Finished Aug 21 07:42:17 PM UTC 24
Peak memory 253336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3866246129 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.3866246129
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/49.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_macro_errs.3648670340
Short name T811
Test name
Test status
Simulation time 1469273380 ps
CPU time 22.6 seconds
Started Aug 21 07:42:16 PM UTC 24
Finished Aug 21 07:42:40 PM UTC 24
Peak memory 253436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3648670340 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.3648670340
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/49.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_key_req.1024019388
Short name T823
Test name
Test status
Simulation time 1281046988 ps
CPU time 33.01 seconds
Started Aug 21 07:42:16 PM UTC 24
Finished Aug 21 07:42:50 PM UTC 24
Peak memory 257488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1024019388 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.1024019388
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_esc.4187944284
Short name T137
Test name
Test status
Simulation time 4186756278 ps
CPU time 17.05 seconds
Started Aug 21 07:42:11 PM UTC 24
Finished Aug 21 07:42:30 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4187944284 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.4187944284
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_req.2301731272
Short name T787
Test name
Test status
Simulation time 789421213 ps
CPU time 12.44 seconds
Started Aug 21 07:42:11 PM UTC 24
Finished Aug 21 07:42:25 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2301731272 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc
_req.2301731272
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_regwen.3051514519
Short name T790
Test name
Test status
Simulation time 4616139416 ps
CPU time 9.29 seconds
Started Aug 21 07:42:16 PM UTC 24
Finished Aug 21 07:42:26 PM UTC 24
Peak memory 253408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3051514519 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.3051514519
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/49.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_smoke.3860964336
Short name T782
Test name
Test status
Simulation time 322400847 ps
CPU time 5.21 seconds
Started Aug 21 07:42:11 PM UTC 24
Finished Aug 21 07:42:18 PM UTC 24
Peak memory 251652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3860964336 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.3860964336
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/49.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all.3425537643
Short name T798
Test name
Test status
Simulation time 968979264 ps
CPU time 9.06 seconds
Started Aug 21 07:42:19 PM UTC 24
Finished Aug 21 07:42:29 PM UTC 24
Peak memory 251488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3425537643
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_st
ress_all.3425537643
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.1746203859
Short name T999
Test name
Test status
Simulation time 9931535460 ps
CPU time 156.57 seconds
Started Aug 21 07:42:16 PM UTC 24
Finished Aug 21 07:44:55 PM UTC 24
Peak memory 274360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1746203859 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.1746203859
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_test_access.2797318153
Short name T800
Test name
Test status
Simulation time 1465237803 ps
CPU time 13.33 seconds
Started Aug 21 07:42:16 PM UTC 24
Finished Aug 21 07:42:30 PM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2797318153 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.2797318153
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/49.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_alert_test.1078263769
Short name T477
Test name
Test status
Simulation time 96903172 ps
CPU time 2.62 seconds
Started Aug 21 07:35:39 PM UTC 24
Finished Aug 21 07:35:43 PM UTC 24
Peak memory 251164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1078263769 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.1078263769
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_background_chks.3817951783
Short name T233
Test name
Test status
Simulation time 1097473939 ps
CPU time 27.63 seconds
Started Aug 21 07:35:33 PM UTC 24
Finished Aug 21 07:36:02 PM UTC 24
Peak memory 257460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3817951783 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.3817951783
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_background_chks/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_check_fail.3463900390
Short name T77
Test name
Test status
Simulation time 6343235843 ps
CPU time 40.67 seconds
Started Aug 21 07:35:33 PM UTC 24
Finished Aug 21 07:36:16 PM UTC 24
Peak memory 257424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3463900390 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.3463900390
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_errs.3260434154
Short name T483
Test name
Test status
Simulation time 4601743961 ps
CPU time 39.49 seconds
Started Aug 21 07:35:33 PM UTC 24
Finished Aug 21 07:36:14 PM UTC 24
Peak memory 257596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3260434154 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.3260434154
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_lock.4074291178
Short name T239
Test name
Test status
Simulation time 11998922464 ps
CPU time 28.65 seconds
Started Aug 21 07:35:33 PM UTC 24
Finished Aug 21 07:36:03 PM UTC 24
Peak memory 253496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4074291178 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.4074291178
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_init_fail.1039079358
Short name T189
Test name
Test status
Simulation time 327169519 ps
CPU time 4.49 seconds
Started Aug 21 07:35:33 PM UTC 24
Finished Aug 21 07:35:39 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1039079358 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.1039079358
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_macro_errs.1466790746
Short name T190
Test name
Test status
Simulation time 937218807 ps
CPU time 27.44 seconds
Started Aug 21 07:35:35 PM UTC 24
Finished Aug 21 07:36:04 PM UTC 24
Peak memory 255680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1466790746 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.1466790746
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_key_req.2998753182
Short name T142
Test name
Test status
Simulation time 911786372 ps
CPU time 10.95 seconds
Started Aug 21 07:35:35 PM UTC 24
Finished Aug 21 07:35:47 PM UTC 24
Peak memory 251400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2998753182 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.2998753182
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_esc.4157333308
Short name T280
Test name
Test status
Simulation time 395331521 ps
CPU time 5.71 seconds
Started Aug 21 07:35:33 PM UTC 24
Finished Aug 21 07:35:40 PM UTC 24
Peak memory 253204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4157333308 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.4157333308
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_regwen.2312412722
Short name T478
Test name
Test status
Simulation time 2501148456 ps
CPU time 7.53 seconds
Started Aug 21 07:35:36 PM UTC 24
Finished Aug 21 07:35:45 PM UTC 24
Peak memory 251356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2312412722 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.2312412722
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_smoke.2574016448
Short name T296
Test name
Test status
Simulation time 2002678066 ps
CPU time 5.6 seconds
Started Aug 21 07:35:33 PM UTC 24
Finished Aug 21 07:35:40 PM UTC 24
Peak memory 251456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2574016448 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.2574016448
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_test_access.2529479977
Short name T260
Test name
Test status
Simulation time 988690302 ps
CPU time 24.94 seconds
Started Aug 21 07:35:37 PM UTC 24
Finished Aug 21 07:36:04 PM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2529479977 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.2529479977
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/5.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_init_fail.727566543
Short name T789
Test name
Test status
Simulation time 324400870 ps
CPU time 6.34 seconds
Started Aug 21 07:42:19 PM UTC 24
Finished Aug 21 07:42:26 PM UTC 24
Peak memory 251548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=727566543 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.727566543
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/50.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_parallel_lc_esc.328222528
Short name T103
Test name
Test status
Simulation time 166579736 ps
CPU time 6.68 seconds
Started Aug 21 07:42:19 PM UTC 24
Finished Aug 21 07:42:27 PM UTC 24
Peak memory 253204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=328222528 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.328222528
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/50.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.510013960
Short name T420
Test name
Test status
Simulation time 2067229638 ps
CPU time 74.28 seconds
Started Aug 21 07:42:19 PM UTC 24
Finished Aug 21 07:43:35 PM UTC 24
Peak memory 257504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=510013960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.510013960
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_init_fail.1054434010
Short name T788
Test name
Test status
Simulation time 339019164 ps
CPU time 5.47 seconds
Started Aug 21 07:42:19 PM UTC 24
Finished Aug 21 07:42:26 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1054434010 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.1054434010
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/51.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_parallel_lc_esc.3098699337
Short name T804
Test name
Test status
Simulation time 617749509 ps
CPU time 14.53 seconds
Started Aug 21 07:42:19 PM UTC 24
Finished Aug 21 07:42:35 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3098699337 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.3098699337
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/51.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_parallel_lc_esc.1034339535
Short name T797
Test name
Test status
Simulation time 402492559 ps
CPU time 4.8 seconds
Started Aug 21 07:42:23 PM UTC 24
Finished Aug 21 07:42:29 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1034339535 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.1034339535
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/52.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_init_fail.3518635417
Short name T793
Test name
Test status
Simulation time 542999108 ps
CPU time 4.05 seconds
Started Aug 21 07:42:23 PM UTC 24
Finished Aug 21 07:42:28 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3518635417 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.3518635417
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/53.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_parallel_lc_esc.4165424657
Short name T802
Test name
Test status
Simulation time 262632028 ps
CPU time 7.42 seconds
Started Aug 21 07:42:23 PM UTC 24
Finished Aug 21 07:42:32 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4165424657 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.4165424657
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/53.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_init_fail.1317836413
Short name T68
Test name
Test status
Simulation time 299118578 ps
CPU time 3.53 seconds
Started Aug 21 07:42:29 PM UTC 24
Finished Aug 21 07:42:35 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1317836413 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.1317836413
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/54.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_parallel_lc_esc.3088012746
Short name T810
Test name
Test status
Simulation time 337200161 ps
CPU time 8.25 seconds
Started Aug 21 07:42:29 PM UTC 24
Finished Aug 21 07:42:39 PM UTC 24
Peak memory 253228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3088012746 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.3088012746
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/54.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.1059119250
Short name T359
Test name
Test status
Simulation time 12971437108 ps
CPU time 78.28 seconds
Started Aug 21 07:42:30 PM UTC 24
Finished Aug 21 07:43:50 PM UTC 24
Peak memory 257860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1059119250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.1059119250
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/54.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_init_fail.297968942
Short name T71
Test name
Test status
Simulation time 411778619 ps
CPU time 4.62 seconds
Started Aug 21 07:42:35 PM UTC 24
Finished Aug 21 07:42:41 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=297968942 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.297968942
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/55.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_parallel_lc_esc.2900035891
Short name T816
Test name
Test status
Simulation time 163916557 ps
CPU time 7.14 seconds
Started Aug 21 07:42:35 PM UTC 24
Finished Aug 21 07:42:43 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2900035891 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.2900035891
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/55.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_init_fail.3708558770
Short name T36
Test name
Test status
Simulation time 148564063 ps
CPU time 4.17 seconds
Started Aug 21 07:42:35 PM UTC 24
Finished Aug 21 07:42:40 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3708558770 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.3708558770
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/56.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_parallel_lc_esc.1876336731
Short name T805
Test name
Test status
Simulation time 3100858603 ps
CPU time 22.18 seconds
Started Aug 21 07:42:35 PM UTC 24
Finished Aug 21 07:42:59 PM UTC 24
Peak memory 251440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1876336731 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.1876336731
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/56.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_init_fail.1237310497
Short name T814
Test name
Test status
Simulation time 184142079 ps
CPU time 6.05 seconds
Started Aug 21 07:42:35 PM UTC 24
Finished Aug 21 07:42:42 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1237310497 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.1237310497
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/57.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.3158369985
Short name T884
Test name
Test status
Simulation time 4225155493 ps
CPU time 84.54 seconds
Started Aug 21 07:42:35 PM UTC 24
Finished Aug 21 07:44:02 PM UTC 24
Peak memory 267872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3158369985 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.3158369985
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/57.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_init_fail.358482797
Short name T78
Test name
Test status
Simulation time 579375839 ps
CPU time 5.18 seconds
Started Aug 21 07:42:35 PM UTC 24
Finished Aug 21 07:42:42 PM UTC 24
Peak memory 253340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=358482797 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.358482797
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/58.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_parallel_lc_esc.4021861196
Short name T159
Test name
Test status
Simulation time 3664335181 ps
CPU time 7.42 seconds
Started Aug 21 07:42:35 PM UTC 24
Finished Aug 21 07:42:44 PM UTC 24
Peak memory 251280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4021861196 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.4021861196
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/58.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_init_fail.375229596
Short name T813
Test name
Test status
Simulation time 125832855 ps
CPU time 5.09 seconds
Started Aug 21 07:42:35 PM UTC 24
Finished Aug 21 07:42:42 PM UTC 24
Peak memory 251460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=375229596 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.375229596
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/59.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_parallel_lc_esc.3234124732
Short name T815
Test name
Test status
Simulation time 241604255 ps
CPU time 6.44 seconds
Started Aug 21 07:42:35 PM UTC 24
Finished Aug 21 07:42:43 PM UTC 24
Peak memory 253208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3234124732 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.3234124732
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/59.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.3960856842
Short name T839
Test name
Test status
Simulation time 2899061959 ps
CPU time 39.17 seconds
Started Aug 21 07:42:35 PM UTC 24
Finished Aug 21 07:43:16 PM UTC 24
Peak memory 257720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3960856842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.3960856842
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/59.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_alert_test.270205726
Short name T310
Test name
Test status
Simulation time 106233070 ps
CPU time 2.05 seconds
Started Aug 21 07:35:49 PM UTC 24
Finished Aug 21 07:35:52 PM UTC 24
Peak memory 251168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=270205726 -ass
ert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.270205726
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_check_fail.358779288
Short name T240
Test name
Test status
Simulation time 558116990 ps
CPU time 8.78 seconds
Started Aug 21 07:35:45 PM UTC 24
Finished Aug 21 07:35:55 PM UTC 24
Peak memory 251672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=358779288 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.358779288
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_errs.3374193950
Short name T175
Test name
Test status
Simulation time 655738188 ps
CPU time 13.14 seconds
Started Aug 21 07:35:45 PM UTC 24
Finished Aug 21 07:35:59 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3374193950 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.3374193950
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_lock.2052066853
Short name T372
Test name
Test status
Simulation time 6365044045 ps
CPU time 78.81 seconds
Started Aug 21 07:35:42 PM UTC 24
Finished Aug 21 07:37:03 PM UTC 24
Peak memory 251672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2052066853 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.2052066853
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_init_fail.3753616927
Short name T98
Test name
Test status
Simulation time 282534497 ps
CPU time 4.22 seconds
Started Aug 21 07:35:42 PM UTC 24
Finished Aug 21 07:35:47 PM UTC 24
Peak memory 251204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3753616927 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.3753616927
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_macro_errs.3362896361
Short name T485
Test name
Test status
Simulation time 2704067625 ps
CPU time 32.19 seconds
Started Aug 21 07:35:45 PM UTC 24
Finished Aug 21 07:36:18 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3362896361 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.3362896361
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_key_req.2119450555
Short name T229
Test name
Test status
Simulation time 368006926 ps
CPU time 22.25 seconds
Started Aug 21 07:35:45 PM UTC 24
Finished Aug 21 07:36:08 PM UTC 24
Peak memory 253620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2119450555 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.2119450555
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_esc.1104284904
Short name T408
Test name
Test status
Simulation time 1562843088 ps
CPU time 29.07 seconds
Started Aug 21 07:35:42 PM UTC 24
Finished Aug 21 07:36:13 PM UTC 24
Peak memory 251252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1104284904 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.1104284904
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_regwen.1013542392
Short name T480
Test name
Test status
Simulation time 670339452 ps
CPU time 8.52 seconds
Started Aug 21 07:35:47 PM UTC 24
Finished Aug 21 07:35:57 PM UTC 24
Peak memory 251552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1013542392 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.1013542392
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_smoke.2369523752
Short name T479
Test name
Test status
Simulation time 2899629504 ps
CPU time 7.24 seconds
Started Aug 21 07:35:42 PM UTC 24
Finished Aug 21 07:35:50 PM UTC 24
Peak memory 251392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2369523752 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.2369523752
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_test_access.3824437555
Short name T230
Test name
Test status
Simulation time 2358596524 ps
CPU time 20.28 seconds
Started Aug 21 07:35:47 PM UTC 24
Finished Aug 21 07:36:09 PM UTC 24
Peak memory 251636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3824437555 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.3824437555
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/6.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_init_fail.2786807115
Short name T812
Test name
Test status
Simulation time 136204065 ps
CPU time 4.7 seconds
Started Aug 21 07:42:35 PM UTC 24
Finished Aug 21 07:42:41 PM UTC 24
Peak memory 253272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2786807115 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.2786807115
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/60.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_parallel_lc_esc.1361536017
Short name T288
Test name
Test status
Simulation time 787198898 ps
CPU time 10.34 seconds
Started Aug 21 07:42:36 PM UTC 24
Finished Aug 21 07:42:47 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1361536017 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.1361536017
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/60.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.1797241155
Short name T848
Test name
Test status
Simulation time 5627204175 ps
CPU time 49.47 seconds
Started Aug 21 07:42:36 PM UTC 24
Finished Aug 21 07:43:27 PM UTC 24
Peak memory 257976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1797241155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.1797241155
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/60.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_init_fail.1480406339
Short name T817
Test name
Test status
Simulation time 166106821 ps
CPU time 4.32 seconds
Started Aug 21 07:42:38 PM UTC 24
Finished Aug 21 07:42:43 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1480406339 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.1480406339
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/61.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_parallel_lc_esc.3056815204
Short name T818
Test name
Test status
Simulation time 649229900 ps
CPU time 5.23 seconds
Started Aug 21 07:42:38 PM UTC 24
Finished Aug 21 07:42:44 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3056815204 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.3056815204
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/61.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.3128834022
Short name T354
Test name
Test status
Simulation time 1971795763 ps
CPU time 48.92 seconds
Started Aug 21 07:42:38 PM UTC 24
Finished Aug 21 07:43:29 PM UTC 24
Peak memory 257796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3128834022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.3128834022
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_init_fail.2644469804
Short name T824
Test name
Test status
Simulation time 348241603 ps
CPU time 5.8 seconds
Started Aug 21 07:42:43 PM UTC 24
Finished Aug 21 07:42:50 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2644469804 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.2644469804
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/62.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_parallel_lc_esc.3693609785
Short name T245
Test name
Test status
Simulation time 1317610717 ps
CPU time 10.2 seconds
Started Aug 21 07:42:43 PM UTC 24
Finished Aug 21 07:42:55 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3693609785 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.3693609785
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/62.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.1043963143
Short name T864
Test name
Test status
Simulation time 6262234921 ps
CPU time 55.11 seconds
Started Aug 21 07:42:43 PM UTC 24
Finished Aug 21 07:43:40 PM UTC 24
Peak memory 257608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1043963143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.1043963143
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/62.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_init_fail.3342748378
Short name T821
Test name
Test status
Simulation time 261623063 ps
CPU time 3.67 seconds
Started Aug 21 07:42:43 PM UTC 24
Finished Aug 21 07:42:48 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3342748378 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.3342748378
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/63.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_parallel_lc_esc.883865788
Short name T241
Test name
Test status
Simulation time 309832212 ps
CPU time 6.07 seconds
Started Aug 21 07:42:43 PM UTC 24
Finished Aug 21 07:42:51 PM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=883865788 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.883865788
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/63.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.1812161629
Short name T980
Test name
Test status
Simulation time 14515854774 ps
CPU time 122.68 seconds
Started Aug 21 07:42:43 PM UTC 24
Finished Aug 21 07:44:49 PM UTC 24
Peak memory 267960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1812161629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.1812161629
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_init_fail.238142697
Short name T242
Test name
Test status
Simulation time 1502257060 ps
CPU time 5.83 seconds
Started Aug 21 07:42:44 PM UTC 24
Finished Aug 21 07:42:51 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=238142697 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.238142697
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/64.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_parallel_lc_esc.2659104978
Short name T825
Test name
Test status
Simulation time 423071350 ps
CPU time 13.23 seconds
Started Aug 21 07:42:44 PM UTC 24
Finished Aug 21 07:42:58 PM UTC 24
Peak memory 251188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2659104978 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.2659104978
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/64.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_init_fail.1145124713
Short name T822
Test name
Test status
Simulation time 2587384790 ps
CPU time 4.19 seconds
Started Aug 21 07:42:44 PM UTC 24
Finished Aug 21 07:42:49 PM UTC 24
Peak memory 251140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1145124713 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.1145124713
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/65.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_parallel_lc_esc.560963959
Short name T465
Test name
Test status
Simulation time 596169118 ps
CPU time 5.23 seconds
Started Aug 21 07:42:44 PM UTC 24
Finished Aug 21 07:42:50 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=560963959 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.560963959
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/65.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.1647424075
Short name T362
Test name
Test status
Simulation time 2403313160 ps
CPU time 66.43 seconds
Started Aug 21 07:42:44 PM UTC 24
Finished Aug 21 07:43:52 PM UTC 24
Peak memory 257656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1647424075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.1647424075
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_init_fail.2576788416
Short name T179
Test name
Test status
Simulation time 178899299 ps
CPU time 5.41 seconds
Started Aug 21 07:42:44 PM UTC 24
Finished Aug 21 07:42:51 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2576788416 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.2576788416
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/66.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_parallel_lc_esc.726981743
Short name T160
Test name
Test status
Simulation time 217046198 ps
CPU time 4.16 seconds
Started Aug 21 07:42:44 PM UTC 24
Finished Aug 21 07:42:50 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=726981743 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.726981743
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/66.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.2815377566
Short name T960
Test name
Test status
Simulation time 57098496357 ps
CPU time 114.25 seconds
Started Aug 21 07:42:46 PM UTC 24
Finished Aug 21 07:44:42 PM UTC 24
Peak memory 268188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2815377566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.2815377566
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_parallel_lc_esc.1971604251
Short name T244
Test name
Test status
Simulation time 172497313 ps
CPU time 5.13 seconds
Started Aug 21 07:42:46 PM UTC 24
Finished Aug 21 07:42:52 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1971604251 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.1971604251
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/67.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_init_fail.2629138728
Short name T243
Test name
Test status
Simulation time 283278573 ps
CPU time 4.16 seconds
Started Aug 21 07:42:46 PM UTC 24
Finished Aug 21 07:42:51 PM UTC 24
Peak memory 251452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2629138728 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.2629138728
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/68.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_parallel_lc_esc.1293727918
Short name T837
Test name
Test status
Simulation time 1356242799 ps
CPU time 27.96 seconds
Started Aug 21 07:42:46 PM UTC 24
Finished Aug 21 07:43:16 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1293727918 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.1293727918
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/68.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.1844654537
Short name T435
Test name
Test status
Simulation time 9600597169 ps
CPU time 101.53 seconds
Started Aug 21 07:42:48 PM UTC 24
Finished Aug 21 07:44:32 PM UTC 24
Peak memory 257600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1844654537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.1844654537
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_init_fail.867172190
Short name T246
Test name
Test status
Simulation time 144301924 ps
CPU time 5.42 seconds
Started Aug 21 07:42:48 PM UTC 24
Finished Aug 21 07:42:55 PM UTC 24
Peak memory 253552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=867172190 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.867172190
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/69.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_parallel_lc_esc.4065281648
Short name T808
Test name
Test status
Simulation time 641061205 ps
CPU time 9.07 seconds
Started Aug 21 07:42:49 PM UTC 24
Finished Aug 21 07:42:59 PM UTC 24
Peak memory 253200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4065281648 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.4065281648
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/69.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_alert_test.1528325220
Short name T226
Test name
Test status
Simulation time 110468942 ps
CPU time 2.96 seconds
Started Aug 21 07:36:00 PM UTC 24
Finished Aug 21 07:36:04 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1528325220 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.1528325220
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_background_chks.1843216984
Short name T410
Test name
Test status
Simulation time 965688160 ps
CPU time 27.03 seconds
Started Aug 21 07:35:52 PM UTC 24
Finished Aug 21 07:36:20 PM UTC 24
Peak memory 257432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1843216984 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.1843216984
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_background_chks/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_check_fail.3031427568
Short name T76
Test name
Test status
Simulation time 376911586 ps
CPU time 10.18 seconds
Started Aug 21 07:35:54 PM UTC 24
Finished Aug 21 07:36:06 PM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3031427568 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.3031427568
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_errs.2426669999
Short name T262
Test name
Test status
Simulation time 1350669057 ps
CPU time 19.75 seconds
Started Aug 21 07:35:54 PM UTC 24
Finished Aug 21 07:36:15 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2426669999 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.2426669999
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_lock.2226442924
Short name T228
Test name
Test status
Simulation time 2532410357 ps
CPU time 11.4 seconds
Started Aug 21 07:35:54 PM UTC 24
Finished Aug 21 07:36:07 PM UTC 24
Peak memory 251444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2226442924 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.2226442924
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_init_fail.89660314
Short name T181
Test name
Test status
Simulation time 169010185 ps
CPU time 4.15 seconds
Started Aug 21 07:35:49 PM UTC 24
Finished Aug 21 07:35:54 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=89660314 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.89660314
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_macro_errs.1262929318
Short name T186
Test name
Test status
Simulation time 5580849156 ps
CPU time 37.21 seconds
Started Aug 21 07:35:56 PM UTC 24
Finished Aug 21 07:36:34 PM UTC 24
Peak memory 255612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1262929318 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/
scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.1262929318
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_esc.3251622494
Short name T286
Test name
Test status
Simulation time 182425807 ps
CPU time 7.14 seconds
Started Aug 21 07:35:54 PM UTC 24
Finished Aug 21 07:36:02 PM UTC 24
Peak memory 251412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3251622494 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.3251622494
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_req.1372869037
Short name T411
Test name
Test status
Simulation time 873531822 ps
CPU time 9.06 seconds
Started Aug 21 07:35:52 PM UTC 24
Finished Aug 21 07:36:02 PM UTC 24
Peak memory 257364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1372869037 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_
req.1372869037
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_regwen.1760797394
Short name T227
Test name
Test status
Simulation time 338355766 ps
CPU time 8.2 seconds
Started Aug 21 07:35:56 PM UTC 24
Finished Aug 21 07:36:05 PM UTC 24
Peak memory 251552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1760797394 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.1760797394
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_smoke.1071502904
Short name T475
Test name
Test status
Simulation time 219636824 ps
CPU time 7.26 seconds
Started Aug 21 07:35:49 PM UTC 24
Finished Aug 21 07:35:57 PM UTC 24
Peak memory 251328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1071502904 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.1071502904
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all.1805574598
Short name T370
Test name
Test status
Simulation time 125425312319 ps
CPU time 235.65 seconds
Started Aug 21 07:35:59 PM UTC 24
Finished Aug 21 07:39:58 PM UTC 24
Peak memory 269792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1805574598
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_str
ess_all.1805574598
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.1714358928
Short name T15
Test name
Test status
Simulation time 9409011310 ps
CPU time 44.27 seconds
Started Aug 21 07:35:58 PM UTC 24
Finished Aug 21 07:36:44 PM UTC 24
Peak memory 267840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1714358928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.1714358928
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_test_access.1131943192
Short name T207
Test name
Test status
Simulation time 4151785184 ps
CPU time 37.25 seconds
Started Aug 21 07:35:57 PM UTC 24
Finished Aug 21 07:36:36 PM UTC 24
Peak memory 251376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1131943192 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.1131943192
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/7.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_init_fail.3834167988
Short name T247
Test name
Test status
Simulation time 264593532 ps
CPU time 5.86 seconds
Started Aug 21 07:42:50 PM UTC 24
Finished Aug 21 07:42:57 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3834167988 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.3834167988
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/70.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_parallel_lc_esc.1502214081
Short name T840
Test name
Test status
Simulation time 13887138072 ps
CPU time 26.54 seconds
Started Aug 21 07:42:50 PM UTC 24
Finished Aug 21 07:43:18 PM UTC 24
Peak memory 251340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1502214081 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.1502214081
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/70.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_init_fail.4261719439
Short name T54
Test name
Test status
Simulation time 493338978 ps
CPU time 4.01 seconds
Started Aug 21 07:42:52 PM UTC 24
Finished Aug 21 07:42:57 PM UTC 24
Peak memory 251180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4261719439 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.4261719439
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/71.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_parallel_lc_esc.806102880
Short name T826
Test name
Test status
Simulation time 169583179 ps
CPU time 5.66 seconds
Started Aug 21 07:42:52 PM UTC 24
Finished Aug 21 07:42:59 PM UTC 24
Peak memory 253140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=806102880 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.806102880
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/71.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_init_fail.451420290
Short name T248
Test name
Test status
Simulation time 127230611 ps
CPU time 3.78 seconds
Started Aug 21 07:42:53 PM UTC 24
Finished Aug 21 07:42:57 PM UTC 24
Peak memory 253504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=451420290 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.451420290
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/72.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_parallel_lc_esc.27467971
Short name T834
Test name
Test status
Simulation time 665615536 ps
CPU time 18.96 seconds
Started Aug 21 07:42:53 PM UTC 24
Finished Aug 21 07:43:13 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=27467971 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit
an/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.27467971
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/72.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_init_fail.4168757995
Short name T42
Test name
Test status
Simulation time 580120482 ps
CPU time 5.03 seconds
Started Aug 21 07:42:53 PM UTC 24
Finished Aug 21 07:42:59 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4168757995 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.4168757995
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/73.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_parallel_lc_esc.6212901
Short name T762
Test name
Test status
Simulation time 117827624 ps
CPU time 4.98 seconds
Started Aug 21 07:42:54 PM UTC 24
Finished Aug 21 07:43:00 PM UTC 24
Peak memory 257560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=6212901 -assert nopostproc +UVM_TESTNAME
=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentita
n/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.6212901
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/73.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.3986633015
Short name T1170
Test name
Test status
Simulation time 71812540815 ps
CPU time 223.01 seconds
Started Aug 21 07:42:55 PM UTC 24
Finished Aug 21 07:46:42 PM UTC 24
Peak memory 274012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3986633015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.3986633015
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_init_fail.3059994313
Short name T828
Test name
Test status
Simulation time 396642557 ps
CPU time 6.75 seconds
Started Aug 21 07:42:57 PM UTC 24
Finished Aug 21 07:43:04 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3059994313 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.3059994313
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/74.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_parallel_lc_esc.109472074
Short name T836
Test name
Test status
Simulation time 964476660 ps
CPU time 15.72 seconds
Started Aug 21 07:42:57 PM UTC 24
Finished Aug 21 07:43:14 PM UTC 24
Peak memory 251152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=109472074 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.109472074
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/74.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_init_fail.2341501681
Short name T827
Test name
Test status
Simulation time 311355122 ps
CPU time 4.81 seconds
Started Aug 21 07:42:58 PM UTC 24
Finished Aug 21 07:43:04 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2341501681 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.2341501681
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/75.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_parallel_lc_esc.348073116
Short name T830
Test name
Test status
Simulation time 503596673 ps
CPU time 7.26 seconds
Started Aug 21 07:42:58 PM UTC 24
Finished Aug 21 07:43:07 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=348073116 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.348073116
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/75.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.410490405
Short name T926
Test name
Test status
Simulation time 3025280632 ps
CPU time 81.31 seconds
Started Aug 21 07:43:01 PM UTC 24
Finished Aug 21 07:44:25 PM UTC 24
Peak memory 257824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=410490405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.410490405
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/75.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_init_fail.3702981635
Short name T79
Test name
Test status
Simulation time 586362000 ps
CPU time 4.21 seconds
Started Aug 21 07:43:02 PM UTC 24
Finished Aug 21 07:43:07 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3702981635 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.3702981635
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/76.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_parallel_lc_esc.866618800
Short name T831
Test name
Test status
Simulation time 133822856 ps
CPU time 4.38 seconds
Started Aug 21 07:43:02 PM UTC 24
Finished Aug 21 07:43:07 PM UTC 24
Peak memory 251092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=866618800 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.866618800
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/76.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_init_fail.3441089194
Short name T833
Test name
Test status
Simulation time 2143741060 ps
CPU time 5.38 seconds
Started Aug 21 07:43:02 PM UTC 24
Finished Aug 21 07:43:08 PM UTC 24
Peak memory 251520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3441089194 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.3441089194
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/77.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_parallel_lc_esc.3719638866
Short name T838
Test name
Test status
Simulation time 243309095 ps
CPU time 12.91 seconds
Started Aug 21 07:43:02 PM UTC 24
Finished Aug 21 07:43:16 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3719638866 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.3719638866
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/77.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_stress_all_with_rand_reset.3019031121
Short name T361
Test name
Test status
Simulation time 26358429817 ps
CPU time 159.46 seconds
Started Aug 21 07:43:06 PM UTC 24
Finished Aug 21 07:45:48 PM UTC 24
Peak memory 284260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3019031121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.3019031121
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/77.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_parallel_lc_esc.4239664037
Short name T835
Test name
Test status
Simulation time 244169333 ps
CPU time 6.11 seconds
Started Aug 21 07:43:06 PM UTC 24
Finished Aug 21 07:43:14 PM UTC 24
Peak memory 251180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4239664037 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.4239664037
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/78.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_init_fail.3966143525
Short name T83
Test name
Test status
Simulation time 395633555 ps
CPU time 3.62 seconds
Started Aug 21 07:43:15 PM UTC 24
Finished Aug 21 07:43:20 PM UTC 24
Peak memory 251284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3966143525 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.3966143525
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/79.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_parallel_lc_esc.20174556
Short name T444
Test name
Test status
Simulation time 6044639752 ps
CPU time 15.7 seconds
Started Aug 21 07:43:15 PM UTC 24
Finished Aug 21 07:43:32 PM UTC 24
Peak memory 251244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=20174556 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentit
an/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.20174556
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/79.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_alert_test.2560492080
Short name T482
Test name
Test status
Simulation time 113966623 ps
CPU time 2.87 seconds
Started Aug 21 07:36:09 PM UTC 24
Finished Aug 21 07:36:12 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2560492080 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.2560492080
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_background_chks.2136683531
Short name T209
Test name
Test status
Simulation time 14803206069 ps
CPU time 33.33 seconds
Started Aug 21 07:36:03 PM UTC 24
Finished Aug 21 07:36:38 PM UTC 24
Peak memory 251380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2136683531 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.2136683531
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_background_chks/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_check_fail.254685740
Short name T34
Test name
Test status
Simulation time 2258256197 ps
CPU time 19.03 seconds
Started Aug 21 07:36:07 PM UTC 24
Finished Aug 21 07:36:27 PM UTC 24
Peak memory 253464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=254685740 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.254685740
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_check_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_errs.3252731704
Short name T265
Test name
Test status
Simulation time 1110650718 ps
CPU time 15.86 seconds
Started Aug 21 07:36:07 PM UTC 24
Finished Aug 21 07:36:24 PM UTC 24
Peak memory 251616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3252731704 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.3252731704
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_lock.2850787204
Short name T487
Test name
Test status
Simulation time 597028117 ps
CPU time 16.36 seconds
Started Aug 21 07:36:04 PM UTC 24
Finished Aug 21 07:36:21 PM UTC 24
Peak memory 251416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2850787204 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.2850787204
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_init_fail.1233534681
Short name T60
Test name
Test status
Simulation time 2728835408 ps
CPU time 6.6 seconds
Started Aug 21 07:36:02 PM UTC 24
Finished Aug 21 07:36:09 PM UTC 24
Peak memory 251268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1233534681 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.1233534681
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_macro_errs.22477162
Short name T196
Test name
Test status
Simulation time 2981767032 ps
CPU time 25.72 seconds
Started Aug 21 07:36:07 PM UTC 24
Finished Aug 21 07:36:34 PM UTC 24
Peak memory 257824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=22477162 -assert nopostproc +UVM_TESTNAM
E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.22477162
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_key_req.2660421515
Short name T256
Test name
Test status
Simulation time 404745017 ps
CPU time 20.31 seconds
Started Aug 21 07:36:07 PM UTC 24
Finished Aug 21 07:36:29 PM UTC 24
Peak memory 257456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2660421515 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/open
titan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.2660421515
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_key_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_esc.3438781335
Short name T351
Test name
Test status
Simulation time 1433669146 ps
CPU time 13.02 seconds
Started Aug 21 07:36:04 PM UTC 24
Finished Aug 21 07:36:18 PM UTC 24
Peak memory 251504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3438781335 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.3438781335
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_req.3259314990
Short name T206
Test name
Test status
Simulation time 6635125690 ps
CPU time 29.67 seconds
Started Aug 21 07:36:03 PM UTC 24
Finished Aug 21 07:36:35 PM UTC 24
Peak memory 251292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3259314990 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_
req.3259314990
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_regwen.1214885621
Short name T399
Test name
Test status
Simulation time 322867247 ps
CPU time 6 seconds
Started Aug 21 07:36:07 PM UTC 24
Finished Aug 21 07:36:14 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1214885621 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.1214885621
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_smoke.1173940853
Short name T231
Test name
Test status
Simulation time 398367570 ps
CPU time 7.53 seconds
Started Aug 21 07:36:00 PM UTC 24
Finished Aug 21 07:36:09 PM UTC 24
Peak memory 251456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1173940853 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scrat
ch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.1173940853
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_test_access.3779781500
Short name T266
Test name
Test status
Simulation time 675976192 ps
CPU time 16.16 seconds
Started Aug 21 07:36:07 PM UTC 24
Finished Aug 21 07:36:25 PM UTC 24
Peak memory 253364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3779781500 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.3779781500
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/8.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_init_fail.3601433197
Short name T845
Test name
Test status
Simulation time 1844259848 ps
CPU time 6.77 seconds
Started Aug 21 07:43:15 PM UTC 24
Finished Aug 21 07:43:23 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3601433197 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.3601433197
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/80.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_parallel_lc_esc.3941929668
Short name T850
Test name
Test status
Simulation time 366244562 ps
CPU time 12.48 seconds
Started Aug 21 07:43:15 PM UTC 24
Finished Aug 21 07:43:29 PM UTC 24
Peak memory 251180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3941929668 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.3941929668
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/80.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_init_fail.1001699824
Short name T844
Test name
Test status
Simulation time 212217792 ps
CPU time 5.55 seconds
Started Aug 21 07:43:15 PM UTC 24
Finished Aug 21 07:43:22 PM UTC 24
Peak memory 251200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1001699824 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.1001699824
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/81.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_parallel_lc_esc.3525277411
Short name T846
Test name
Test status
Simulation time 560082524 ps
CPU time 6.92 seconds
Started Aug 21 07:43:16 PM UTC 24
Finished Aug 21 07:43:24 PM UTC 24
Peak memory 251176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3525277411 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.3525277411
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/81.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_init_fail.3113669743
Short name T843
Test name
Test status
Simulation time 391476467 ps
CPU time 4.67 seconds
Started Aug 21 07:43:16 PM UTC 24
Finished Aug 21 07:43:21 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3113669743 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.3113669743
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/82.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_parallel_lc_esc.3261605539
Short name T851
Test name
Test status
Simulation time 3559885082 ps
CPU time 12.23 seconds
Started Aug 21 07:43:16 PM UTC 24
Finished Aug 21 07:43:29 PM UTC 24
Peak memory 251056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3261605539 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.3261605539
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/82.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_stress_all_with_rand_reset.618390299
Short name T1017
Test name
Test status
Simulation time 2951046734 ps
CPU time 106.64 seconds
Started Aug 21 07:43:16 PM UTC 24
Finished Aug 21 07:45:04 PM UTC 24
Peak memory 274076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=618390299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.618390299
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/82.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_init_fail.510962675
Short name T857
Test name
Test status
Simulation time 133021061 ps
CPU time 3.97 seconds
Started Aug 21 07:43:30 PM UTC 24
Finished Aug 21 07:43:36 PM UTC 24
Peak memory 253528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=510962675 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.510962675
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/83.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_parallel_lc_esc.3484542897
Short name T858
Test name
Test status
Simulation time 314209534 ps
CPU time 4.56 seconds
Started Aug 21 07:43:31 PM UTC 24
Finished Aug 21 07:43:36 PM UTC 24
Peak memory 253228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3484542897 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.3484542897
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/83.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_init_fail.2800736486
Short name T859
Test name
Test status
Simulation time 519924575 ps
CPU time 4.6 seconds
Started Aug 21 07:43:31 PM UTC 24
Finished Aug 21 07:43:36 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2800736486 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.2800736486
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/84.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_parallel_lc_esc.1231886529
Short name T854
Test name
Test status
Simulation time 95718881 ps
CPU time 2.08 seconds
Started Aug 21 07:43:31 PM UTC 24
Finished Aug 21 07:43:34 PM UTC 24
Peak memory 251116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1231886529 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.1231886529
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/84.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_stress_all_with_rand_reset.3286650950
Short name T1052
Test name
Test status
Simulation time 4523732890 ps
CPU time 105.58 seconds
Started Aug 21 07:43:31 PM UTC 24
Finished Aug 21 07:45:18 PM UTC 24
Peak memory 257604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3286650950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.3286650950
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/84.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_init_fail.4091639413
Short name T855
Test name
Test status
Simulation time 115122282 ps
CPU time 2.99 seconds
Started Aug 21 07:43:31 PM UTC 24
Finished Aug 21 07:43:35 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4091639413 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.4091639413
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/85.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_parallel_lc_esc.2623820440
Short name T863
Test name
Test status
Simulation time 324420487 ps
CPU time 8.08 seconds
Started Aug 21 07:43:31 PM UTC 24
Finished Aug 21 07:43:40 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2623820440 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.2623820440
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/85.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_init_fail.1692847025
Short name T856
Test name
Test status
Simulation time 246558414 ps
CPU time 3.3 seconds
Started Aug 21 07:43:31 PM UTC 24
Finished Aug 21 07:43:35 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1692847025 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.1692847025
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/86.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_parallel_lc_esc.3906829031
Short name T866
Test name
Test status
Simulation time 1093909003 ps
CPU time 9.13 seconds
Started Aug 21 07:43:31 PM UTC 24
Finished Aug 21 07:43:41 PM UTC 24
Peak memory 253232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3906829031 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.3906829031
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/86.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.424725315
Short name T1169
Test name
Test status
Simulation time 15436794083 ps
CPU time 175 seconds
Started Aug 21 07:43:31 PM UTC 24
Finished Aug 21 07:46:29 PM UTC 24
Peak memory 274036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=424725315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.424725315
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/86.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_init_fail.631049420
Short name T860
Test name
Test status
Simulation time 122725859 ps
CPU time 4.62 seconds
Started Aug 21 07:43:31 PM UTC 24
Finished Aug 21 07:43:37 PM UTC 24
Peak memory 253248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=631049420 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.631049420
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/87.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_parallel_lc_esc.4064706809
Short name T849
Test name
Test status
Simulation time 13663194036 ps
CPU time 22.28 seconds
Started Aug 21 07:43:31 PM UTC 24
Finished Aug 21 07:43:55 PM UTC 24
Peak memory 253296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4064706809 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.4064706809
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/87.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_stress_all_with_rand_reset.2773870860
Short name T1087
Test name
Test status
Simulation time 3639075861 ps
CPU time 114.34 seconds
Started Aug 21 07:43:31 PM UTC 24
Finished Aug 21 07:45:28 PM UTC 24
Peak memory 274356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2773870860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.2773870860
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/87.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_init_fail.2354310277
Short name T861
Test name
Test status
Simulation time 2220510655 ps
CPU time 7.68 seconds
Started Aug 21 07:43:31 PM UTC 24
Finished Aug 21 07:43:40 PM UTC 24
Peak memory 251540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2354310277 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.2354310277
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/88.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_parallel_lc_esc.1079577287
Short name T871
Test name
Test status
Simulation time 3178813196 ps
CPU time 11.11 seconds
Started Aug 21 07:43:31 PM UTC 24
Finished Aug 21 07:43:43 PM UTC 24
Peak memory 251220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1079577287 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.1079577287
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/88.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_stress_all_with_rand_reset.1544681822
Short name T425
Test name
Test status
Simulation time 35036892376 ps
CPU time 106.24 seconds
Started Aug 21 07:43:36 PM UTC 24
Finished Aug 21 07:45:24 PM UTC 24
Peak memory 257824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1544681822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.1544681822
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/88.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_init_fail.4182826590
Short name T869
Test name
Test status
Simulation time 281236933 ps
CPU time 5.21 seconds
Started Aug 21 07:43:36 PM UTC 24
Finished Aug 21 07:43:42 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4182826590 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.4182826590
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/89.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_parallel_lc_esc.3600638958
Short name T874
Test name
Test status
Simulation time 1577020505 ps
CPU time 8.87 seconds
Started Aug 21 07:43:36 PM UTC 24
Finished Aug 21 07:43:46 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3600638958 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.3600638958
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/89.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_stress_all_with_rand_reset.2757851869
Short name T1168
Test name
Test status
Simulation time 12866753970 ps
CPU time 152.9 seconds
Started Aug 21 07:43:36 PM UTC 24
Finished Aug 21 07:46:12 PM UTC 24
Peak memory 268220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2757851869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.2757851869
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/89.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_alert_test.2901745711
Short name T312
Test name
Test status
Simulation time 722065297 ps
CPU time 3.48 seconds
Started Aug 21 07:36:19 PM UTC 24
Finished Aug 21 07:36:23 PM UTC 24
Peak memory 251160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabl
ed=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2901745711 -as
sert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.2901745711
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_alert_test/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_background_chks.1308107614
Short name T212
Test name
Test status
Simulation time 3028696949 ps
CPU time 27.69 seconds
Started Aug 21 07:36:12 PM UTC 24
Finished Aug 21 07:36:40 PM UTC 24
Peak memory 251352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1308107614 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.1308107614
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_background_chks/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_errs.1886504825
Short name T380
Test name
Test status
Simulation time 719714160 ps
CPU time 18.44 seconds
Started Aug 21 07:36:13 PM UTC 24
Finished Aug 21 07:36:33 PM UTC 24
Peak memory 251192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1886504825 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/sc
ratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.1886504825
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_dai_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_lock.636405995
Short name T486
Test name
Test status
Simulation time 523449027 ps
CPU time 6.63 seconds
Started Aug 21 07:36:12 PM UTC 24
Finished Aug 21 07:36:19 PM UTC 24
Peak memory 251316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=636405995 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scr
atch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.636405995
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_dai_lock/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_macro_errs.193191929
Short name T197
Test name
Test status
Simulation time 3452694620 ps
CPU time 49.69 seconds
Started Aug 21 07:36:17 PM UTC 24
Finished Aug 21 07:37:08 PM UTC 24
Peak memory 267880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=193191929 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.193191929
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_macro_errs/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_esc.1956436359
Short name T167
Test name
Test status
Simulation time 5201220896 ps
CPU time 12.45 seconds
Started Aug 21 07:36:12 PM UTC 24
Finished Aug 21 07:36:25 PM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1956436359 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.1956436359
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_req.913930145
Short name T484
Test name
Test status
Simulation time 283512635 ps
CPU time 4.96 seconds
Started Aug 21 07:36:12 PM UTC 24
Finished Aug 21 07:36:17 PM UTC 24
Peak memory 251364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=913930145 -assert nopostp
roc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.913930145
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_req/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_regwen.1353537367
Short name T257
Test name
Test status
Simulation time 518511506 ps
CPU time 11.09 seconds
Started Aug 21 07:36:17 PM UTC 24
Finished Aug 21 07:36:29 PM UTC 24
Peak memory 251296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1353537367 -assert nopost
proc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc
/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.1353537367
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_regwen/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_smoke.728383369
Short name T258
Test name
Test status
Simulation time 3373773867 ps
CPU time 18.48 seconds
Started Aug 21 07:36:11 PM UTC 24
Finished Aug 21 07:36:31 PM UTC 24
Peak memory 251596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=728383369 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratc
h/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.728383369
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_smoke/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all.2285701622
Short name T369
Test name
Test status
Simulation time 27942042317 ps
CPU time 201 seconds
Started Aug 21 07:36:19 PM UTC 24
Finished Aug 21 07:39:43 PM UTC 24
Peak memory 274360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2285701622
-assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_str
ess_all.2285701622
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_test_access.1296703327
Short name T255
Test name
Test status
Simulation time 242232861 ps
CPU time 8.95 seconds
Started Aug 21 07:36:17 PM UTC 24
Finished Aug 21 07:36:27 PM UTC 24
Peak memory 253272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1296703327 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan
/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.1296703327
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/9.otp_ctrl_test_access/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_init_fail.3558063320
Short name T865
Test name
Test status
Simulation time 297147349 ps
CPU time 3.67 seconds
Started Aug 21 07:43:36 PM UTC 24
Finished Aug 21 07:43:41 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3558063320 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.3558063320
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/90.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_parallel_lc_esc.3936798941
Short name T862
Test name
Test status
Simulation time 1952378230 ps
CPU time 19.42 seconds
Started Aug 21 07:43:36 PM UTC 24
Finished Aug 21 07:43:57 PM UTC 24
Peak memory 251472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3936798941 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.3936798941
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/90.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_init_fail.4204953842
Short name T870
Test name
Test status
Simulation time 1786558796 ps
CPU time 5.03 seconds
Started Aug 21 07:43:36 PM UTC 24
Finished Aug 21 07:43:42 PM UTC 24
Peak memory 251480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4204953842 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.4204953842
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/91.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_parallel_lc_esc.3166689029
Short name T880
Test name
Test status
Simulation time 820617181 ps
CPU time 20.26 seconds
Started Aug 21 07:43:36 PM UTC 24
Finished Aug 21 07:43:58 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3166689029 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.3166689029
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/91.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_init_fail.1811070742
Short name T873
Test name
Test status
Simulation time 109268769 ps
CPU time 4.37 seconds
Started Aug 21 07:43:40 PM UTC 24
Finished Aug 21 07:43:46 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1811070742 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.1811070742
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/92.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_parallel_lc_esc.3316309718
Short name T853
Test name
Test status
Simulation time 418283263 ps
CPU time 15.36 seconds
Started Aug 21 07:43:40 PM UTC 24
Finished Aug 21 07:43:57 PM UTC 24
Peak memory 251184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3316309718 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.3316309718
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/92.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_parallel_lc_esc.1181675843
Short name T879
Test name
Test status
Simulation time 360524738 ps
CPU time 9.48 seconds
Started Aug 21 07:43:40 PM UTC 24
Finished Aug 21 07:43:51 PM UTC 24
Peak memory 251472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1181675843 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.1181675843
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/93.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_stress_all_with_rand_reset.1190397715
Short name T1019
Test name
Test status
Simulation time 6757062937 ps
CPU time 81.65 seconds
Started Aug 21 07:43:43 PM UTC 24
Finished Aug 21 07:45:07 PM UTC 24
Peak memory 270008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1190397715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.1190397715
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/93.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_init_fail.3545698087
Short name T878
Test name
Test status
Simulation time 2386804238 ps
CPU time 5.77 seconds
Started Aug 21 07:43:43 PM UTC 24
Finished Aug 21 07:43:50 PM UTC 24
Peak memory 251264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3545698087 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.3545698087
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/94.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_parallel_lc_esc.3281919018
Short name T875
Test name
Test status
Simulation time 548095218 ps
CPU time 4.26 seconds
Started Aug 21 07:43:43 PM UTC 24
Finished Aug 21 07:43:49 PM UTC 24
Peak memory 251216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3281919018 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.3281919018
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/94.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.4010972580
Short name T988
Test name
Test status
Simulation time 3775513069 ps
CPU time 66.4 seconds
Started Aug 21 07:43:43 PM UTC 24
Finished Aug 21 07:44:51 PM UTC 24
Peak memory 257976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4010972580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.4010972580
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_init_fail.4021987953
Short name T876
Test name
Test status
Simulation time 166182903 ps
CPU time 5.3 seconds
Started Aug 21 07:43:43 PM UTC 24
Finished Aug 21 07:43:50 PM UTC 24
Peak memory 251544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4021987953 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.4021987953
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/95.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_parallel_lc_esc.202343201
Short name T882
Test name
Test status
Simulation time 550157123 ps
CPU time 14.04 seconds
Started Aug 21 07:43:43 PM UTC 24
Finished Aug 21 07:43:59 PM UTC 24
Peak memory 251180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=202343201 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.202343201
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/95.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.3499408423
Short name T360
Test name
Test status
Simulation time 20013477220 ps
CPU time 78.12 seconds
Started Aug 21 07:43:43 PM UTC 24
Finished Aug 21 07:45:03 PM UTC 24
Peak memory 268212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3499408423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.3499408423
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/95.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_init_fail.1898011147
Short name T841
Test name
Test status
Simulation time 1839165846 ps
CPU time 9.28 seconds
Started Aug 21 07:43:43 PM UTC 24
Finished Aug 21 07:43:54 PM UTC 24
Peak memory 251288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1898011147 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.1898011147
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/96.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_parallel_lc_esc.2229767546
Short name T881
Test name
Test status
Simulation time 1158801284 ps
CPU time 5.25 seconds
Started Aug 21 07:43:46 PM UTC 24
Finished Aug 21 07:43:52 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2229767546 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.2229767546
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/96.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.4047518862
Short name T1167
Test name
Test status
Simulation time 4704458271 ps
CPU time 120.56 seconds
Started Aug 21 07:43:46 PM UTC 24
Finished Aug 21 07:45:49 PM UTC 24
Peak memory 257724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=100
00000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
es/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4047518862 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.4047518862
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/96.otp_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_init_fail.1478914988
Short name T832
Test name
Test status
Simulation time 2043371194 ps
CPU time 8.09 seconds
Started Aug 21 07:43:46 PM UTC 24
Finished Aug 21 07:43:55 PM UTC 24
Peak memory 251224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1478914988 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.1478914988
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/97.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_parallel_lc_esc.2927616915
Short name T901
Test name
Test status
Simulation time 4008916169 ps
CPU time 23.47 seconds
Started Aug 21 07:43:46 PM UTC 24
Finished Aug 21 07:44:11 PM UTC 24
Peak memory 251248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2927616915 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.2927616915
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/97.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_init_fail.3574680074
Short name T847
Test name
Test status
Simulation time 260435614 ps
CPU time 5.38 seconds
Started Aug 21 07:43:48 PM UTC 24
Finished Aug 21 07:43:54 PM UTC 24
Peak memory 251212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3574680074 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.3574680074
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/98.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_parallel_lc_esc.2142368331
Short name T883
Test name
Test status
Simulation time 334357409 ps
CPU time 10.19 seconds
Started Aug 21 07:43:50 PM UTC 24
Finished Aug 21 07:44:02 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2142368331 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opent
itan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.2142368331
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/98.otp_ctrl_parallel_lc_esc/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_init_fail.3655424766
Short name T868
Test name
Test status
Simulation time 310782284 ps
CPU time 3.32 seconds
Started Aug 21 07:43:56 PM UTC 24
Finished Aug 21 07:44:01 PM UTC 24
Peak memory 251176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3655424766 -assert nopostproc +UVM_TESTN
AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/opentitan/s
cratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.3655424766
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/99.otp_ctrl_init_fail/latest

Test location /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_parallel_lc_esc.336076048
Short name T895
Test name
Test status
Simulation time 207981867 ps
CPU time 11.56 seconds
Started Aug 21 07:43:56 PM UTC 24
Finished Aug 21 07:44:09 PM UTC 24
Peak memory 251156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM
_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/lowrisc/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=336076048 -assert nopostproc +UVM_TESTNA
ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/lowrisc/openti
tan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.336076048
Directory /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/otp_ctrl-sim-vcs/99.otp_ctrl_parallel_lc_esc/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%