| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 94.85 | 93.86 | 96.18 | 95.75 | 91.65 | 96.91 | 96.34 | 93.28 |
| T1256 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1319325543 | Aug 23 05:11:19 PM UTC 24 | Aug 23 05:11:24 PM UTC 24 | 277799474 ps | ||
| T1257 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.163868299 | Aug 23 05:11:21 PM UTC 24 | Aug 23 05:11:24 PM UTC 24 | 85830397 ps | ||
| T1258 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.2715546940 | Aug 23 05:11:21 PM UTC 24 | Aug 23 05:11:24 PM UTC 24 | 103765576 ps | ||
| T1259 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.2220438943 | Aug 23 05:11:23 PM UTC 24 | Aug 23 05:11:26 PM UTC 24 | 83741928 ps | ||
| T371 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3202101260 | Aug 23 05:11:15 PM UTC 24 | Aug 23 05:11:26 PM UTC 24 | 2457358054 ps | ||
| T1260 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.3728051773 | Aug 23 05:11:22 PM UTC 24 | Aug 23 05:11:26 PM UTC 24 | 76504308 ps | ||
| T1261 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3759761571 | Aug 23 05:11:23 PM UTC 24 | Aug 23 05:11:26 PM UTC 24 | 591344539 ps | ||
| T1262 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.832531534 | Aug 23 05:11:23 PM UTC 24 | Aug 23 05:11:27 PM UTC 24 | 815462828 ps | ||
| T1263 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.2777134629 | Aug 23 05:11:24 PM UTC 24 | Aug 23 05:11:27 PM UTC 24 | 39983523 ps | ||
| T1264 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.393897573 | Aug 23 05:11:24 PM UTC 24 | Aug 23 05:11:27 PM UTC 24 | 582687502 ps | ||
| T1265 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.3727629960 | Aug 23 05:11:26 PM UTC 24 | Aug 23 05:11:28 PM UTC 24 | 45176827 ps | ||
| T1266 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.663809428 | Aug 23 05:11:25 PM UTC 24 | Aug 23 05:11:28 PM UTC 24 | 104742639 ps | ||
| T1267 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1979661743 | Aug 23 05:11:24 PM UTC 24 | Aug 23 05:11:28 PM UTC 24 | 264685838 ps | ||
| T372 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2846698231 | Aug 23 05:11:19 PM UTC 24 | Aug 23 05:11:29 PM UTC 24 | 2349005622 ps | ||
| T1268 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.1098982728 | Aug 23 05:11:27 PM UTC 24 | Aug 23 05:11:29 PM UTC 24 | 38915718 ps | ||
| T1269 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.3262643220 | Aug 23 05:11:27 PM UTC 24 | Aug 23 05:11:29 PM UTC 24 | 134901018 ps | ||
| T1270 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2623737653 | Aug 23 05:11:24 PM UTC 24 | Aug 23 05:11:29 PM UTC 24 | 127146623 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.4156884218 | Aug 23 05:11:27 PM UTC 24 | Aug 23 05:11:29 PM UTC 24 | 149850985 ps | ||
| T1272 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.628902316 | Aug 23 05:11:27 PM UTC 24 | Aug 23 05:11:29 PM UTC 24 | 135162283 ps | ||
| T1273 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1707962966 | Aug 23 05:11:25 PM UTC 24 | Aug 23 05:11:30 PM UTC 24 | 1558352465 ps | ||
| T1274 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2986989018 | Aug 23 05:11:10 PM UTC 24 | Aug 23 05:11:30 PM UTC 24 | 4783356049 ps | ||
| T1275 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.4120454924 | Aug 23 05:11:11 PM UTC 24 | Aug 23 05:11:30 PM UTC 24 | 2402286272 ps | ||
| T1276 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.3831243513 | Aug 23 05:11:28 PM UTC 24 | Aug 23 05:11:30 PM UTC 24 | 38066274 ps | ||
| T1277 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.1028340391 | Aug 23 05:11:28 PM UTC 24 | Aug 23 05:11:30 PM UTC 24 | 91485284 ps | ||
| T1278 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.3256551699 | Aug 23 05:11:28 PM UTC 24 | Aug 23 05:11:30 PM UTC 24 | 144115601 ps | ||
| T1279 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.3199281182 | Aug 23 05:11:29 PM UTC 24 | Aug 23 05:11:31 PM UTC 24 | 70588985 ps | ||
| T1280 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.1715970451 | Aug 23 05:11:29 PM UTC 24 | Aug 23 05:11:31 PM UTC 24 | 79291045 ps | ||
| T1281 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.1298367140 | Aug 23 05:11:29 PM UTC 24 | Aug 23 05:11:31 PM UTC 24 | 43067816 ps | ||
| T373 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.783978684 | Aug 23 05:11:22 PM UTC 24 | Aug 23 05:11:32 PM UTC 24 | 1244012208 ps | ||
| T1282 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.1469954984 | Aug 23 05:11:30 PM UTC 24 | Aug 23 05:11:32 PM UTC 24 | 131253396 ps | ||
| T1283 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.1023449311 | Aug 23 05:11:30 PM UTC 24 | Aug 23 05:11:32 PM UTC 24 | 40807010 ps | ||
| T1284 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.1843360397 | Aug 23 05:11:30 PM UTC 24 | Aug 23 05:11:32 PM UTC 24 | 76027661 ps | ||
| T1285 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.697348815 | Aug 23 05:11:30 PM UTC 24 | Aug 23 05:11:32 PM UTC 24 | 140596561 ps | ||
| T1286 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.268254209 | Aug 23 05:11:30 PM UTC 24 | Aug 23 05:11:32 PM UTC 24 | 93168158 ps | ||
| T1287 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.3629595741 | Aug 23 05:11:30 PM UTC 24 | Aug 23 05:11:33 PM UTC 24 | 62127742 ps | ||
| T1288 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.60616126 | Aug 23 05:11:30 PM UTC 24 | Aug 23 05:11:33 PM UTC 24 | 588605095 ps | ||
| T1289 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.767177703 | Aug 23 05:11:31 PM UTC 24 | Aug 23 05:11:34 PM UTC 24 | 47043319 ps | ||
| T1290 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.239140919 | Aug 23 05:11:31 PM UTC 24 | Aug 23 05:11:34 PM UTC 24 | 141108791 ps | ||
| T1291 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.3008501397 | Aug 23 05:11:31 PM UTC 24 | Aug 23 05:11:34 PM UTC 24 | 584264068 ps | ||
| T1292 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.3673120943 | Aug 23 05:11:31 PM UTC 24 | Aug 23 05:11:34 PM UTC 24 | 117656785 ps | ||
| T1293 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.3323149935 | Aug 23 05:11:31 PM UTC 24 | Aug 23 05:11:34 PM UTC 24 | 145317555 ps | ||
| T1294 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.4157422142 | Aug 23 05:11:32 PM UTC 24 | Aug 23 05:11:35 PM UTC 24 | 74040686 ps | ||
| T1295 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.1355969251 | Aug 23 05:11:32 PM UTC 24 | Aug 23 05:11:35 PM UTC 24 | 130408818 ps | ||
| T1296 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.2293119066 | Aug 23 05:11:32 PM UTC 24 | Aug 23 05:11:35 PM UTC 24 | 43702998 ps | ||
| T1297 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.3580081271 | Aug 23 05:11:32 PM UTC 24 | Aug 23 05:11:35 PM UTC 24 | 39204820 ps | ||
| T370 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.732253954 | Aug 23 05:10:58 PM UTC 24 | Aug 23 05:11:35 PM UTC 24 | 20020354287 ps | ||
| T1298 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.715008250 | Aug 23 05:11:34 PM UTC 24 | Aug 23 05:11:36 PM UTC 24 | 39445473 ps | ||
| T1299 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.3595994151 | Aug 23 05:11:34 PM UTC 24 | Aug 23 05:11:36 PM UTC 24 | 37639223 ps | ||
| T1300 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.1983917276 | Aug 23 05:11:34 PM UTC 24 | Aug 23 05:11:36 PM UTC 24 | 60824755 ps | ||
| T364 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2614168868 | Aug 23 05:11:18 PM UTC 24 | Aug 23 05:11:43 PM UTC 24 | 18782637286 ps | ||
| T1301 | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.3393558854 | Aug 23 05:11:24 PM UTC 24 | Aug 23 05:11:43 PM UTC 24 | 4868076972 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_req.879356137 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 468693283 ps |
| CPU time | 11.11 seconds |
| Started | Aug 23 05:30:42 PM UTC 24 |
| Finished | Aug 23 05:30:54 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879356137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.879356137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_check_fail.3355143257 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 7161524053 ps |
| CPU time | 19.27 seconds |
| Started | Aug 23 05:30:44 PM UTC 24 |
| Finished | Aug 23 05:31:04 PM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355143257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.3355143257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.1328577466 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 9682864896 ps |
| CPU time | 61.11 seconds |
| Started | Aug 23 05:31:35 PM UTC 24 |
| Finished | Aug 23 05:32:37 PM UTC 24 |
| Peak memory | 274236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1328577466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 4.otp_ctrl_stress_all_with_rand_reset.1328577466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all.1131803449 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 40749333553 ps |
| CPU time | 102.26 seconds |
| Started | Aug 23 05:30:47 PM UTC 24 |
| Finished | Aug 23 05:32:32 PM UTC 24 |
| Peak memory | 267820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131803449 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.1131803449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_test_access.631393124 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 2224102914 ps |
| CPU time | 11.78 seconds |
| Started | Aug 23 05:30:58 PM UTC 24 |
| Finished | Aug 23 05:31:10 PM UTC 24 |
| Peak memory | 253464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631393124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.631393124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all.3018070551 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 41809293752 ps |
| CPU time | 83.9 seconds |
| Started | Aug 23 05:30:58 PM UTC 24 |
| Finished | Aug 23 05:32:24 PM UTC 24 |
| Peak memory | 267704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018070551 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.3018070551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_init_fail.2160670875 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 265024260 ps |
| CPU time | 3.39 seconds |
| Started | Aug 23 05:34:43 PM UTC 24 |
| Finished | Aug 23 05:34:47 PM UTC 24 |
| Peak memory | 250896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160670875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.2160670875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/18.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all.2469378117 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 17272848044 ps |
| CPU time | 80.91 seconds |
| Started | Aug 23 05:31:24 PM UTC 24 |
| Finished | Aug 23 05:32:46 PM UTC 24 |
| Peak memory | 272084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469378117 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.2469378117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_esc.4141299675 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 487624247 ps |
| CPU time | 4.59 seconds |
| Started | Aug 23 05:30:42 PM UTC 24 |
| Finished | Aug 23 05:30:47 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141299675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.4141299675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_sec_cm.3853756099 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 16236450551 ps |
| CPU time | 171.17 seconds |
| Started | Aug 23 05:30:58 PM UTC 24 |
| Finished | Aug 23 05:33:51 PM UTC 24 |
| Peak memory | 296304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853756099 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.3853756099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_lock.2043354058 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1332030061 ps |
| CPU time | 19.2 seconds |
| Started | Aug 23 05:30:53 PM UTC 24 |
| Finished | Aug 23 05:31:13 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043354058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.2043354058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_macro_errs.152560489 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 5331377350 ps |
| CPU time | 23.53 seconds |
| Started | Aug 23 05:31:05 PM UTC 24 |
| Finished | Aug 23 05:31:30 PM UTC 24 |
| Peak memory | 257632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152560489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.152560489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_check_fail.1941223081 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1026072260 ps |
| CPU time | 16.96 seconds |
| Started | Aug 23 05:31:04 PM UTC 24 |
| Finished | Aug 23 05:31:22 PM UTC 24 |
| Peak memory | 257720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941223081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.1941223081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all.2582574595 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 79088514039 ps |
| CPU time | 124.01 seconds |
| Started | Aug 23 05:35:16 PM UTC 24 |
| Finished | Aug 23 05:37:22 PM UTC 24 |
| Peak memory | 269788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582574595 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.2582574595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all.898414355 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 36244221219 ps |
| CPU time | 223.03 seconds |
| Started | Aug 23 05:31:13 PM UTC 24 |
| Finished | Aug 23 05:34:59 PM UTC 24 |
| Peak memory | 261392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898414355 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.898414355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.853686305 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 1310062609 ps |
| CPU time | 16.48 seconds |
| Started | Aug 23 05:10:17 PM UTC 24 |
| Finished | Aug 23 05:10:34 PM UTC 24 |
| Peak memory | 256800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853686305 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_intg_err.853686305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.2292265383 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1717644297 ps |
| CPU time | 79.14 seconds |
| Started | Aug 23 05:32:23 PM UTC 24 |
| Finished | Aug 23 05:33:44 PM UTC 24 |
| Peak memory | 257496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2292265383 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.otp_ctrl_stress_all_with_rand_reset.2292265383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_init_fail.4132122819 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1580900040 ps |
| CPU time | 4.9 seconds |
| Started | Aug 23 05:34:06 PM UTC 24 |
| Finished | Aug 23 05:34:12 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132122819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.4132122819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_req.135414117 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 450685001 ps |
| CPU time | 3.3 seconds |
| Started | Aug 23 05:30:51 PM UTC 24 |
| Finished | Aug 23 05:30:55 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135414117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.135414117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all_with_rand_reset.223165243 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 9545141127 ps |
| CPU time | 109.24 seconds |
| Started | Aug 23 05:39:34 PM UTC 24 |
| Finished | Aug 23 05:41:25 PM UTC 24 |
| Peak memory | 267440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=223165243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.223165243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all.24563182 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 61842375571 ps |
| CPU time | 161.03 seconds |
| Started | Aug 23 05:33:50 PM UTC 24 |
| Finished | Aug 23 05:36:34 PM UTC 24 |
| Peak memory | 273908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24563182 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.24563182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_macro_errs.3121536520 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 1965783399 ps |
| CPU time | 23.33 seconds |
| Started | Aug 23 05:35:51 PM UTC 24 |
| Finished | Aug 23 05:36:16 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121536520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.3121536520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/23.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_init_fail.1959421399 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 626384286 ps |
| CPU time | 3.6 seconds |
| Started | Aug 23 05:32:10 PM UTC 24 |
| Finished | Aug 23 05:32:15 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959421399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.1959421399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all.589843272 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 66972702584 ps |
| CPU time | 86.98 seconds |
| Started | Aug 23 05:32:58 PM UTC 24 |
| Finished | Aug 23 05:34:27 PM UTC 24 |
| Peak memory | 257460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589843272 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.589843272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all_with_rand_reset.2353978497 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 8668974983 ps |
| CPU time | 81.89 seconds |
| Started | Aug 23 05:33:11 PM UTC 24 |
| Finished | Aug 23 05:34:35 PM UTC 24 |
| Peak memory | 268156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2353978497 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 10.otp_ctrl_stress_all_with_rand_reset.2353978497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_init_fail.3147994723 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 2479808386 ps |
| CPU time | 4.7 seconds |
| Started | Aug 23 05:43:28 PM UTC 24 |
| Finished | Aug 23 05:43:34 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147994723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.3147994723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/95.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_key_req.218717189 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 9014045304 ps |
| CPU time | 19.13 seconds |
| Started | Aug 23 05:31:33 PM UTC 24 |
| Finished | Aug 23 05:31:54 PM UTC 24 |
| Peak memory | 253396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218717189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.218717189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_alert_test.1260149772 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 150165670 ps |
| CPU time | 1.66 seconds |
| Started | Aug 23 05:30:47 PM UTC 24 |
| Finished | Aug 23 05:30:50 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260149772 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.1260149772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.943405785 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 3259174944 ps |
| CPU time | 9.17 seconds |
| Started | Aug 23 05:10:36 PM UTC 24 |
| Finished | Aug 23 05:10:46 PM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943405785 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_aliasing.943405785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_init_fail.614548353 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 594919712 ps |
| CPU time | 3.51 seconds |
| Started | Aug 23 05:31:38 PM UTC 24 |
| Finished | Aug 23 05:31:43 PM UTC 24 |
| Peak memory | 251456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614548353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.614548353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_check_fail.3917831275 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 2024174005 ps |
| CPU time | 18.37 seconds |
| Started | Aug 23 05:33:04 PM UTC 24 |
| Finished | Aug 23 05:33:24 PM UTC 24 |
| Peak memory | 253360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917831275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.3917831275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_check_fail.2393368436 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 13211312765 ps |
| CPU time | 13.45 seconds |
| Started | Aug 23 05:31:44 PM UTC 24 |
| Finished | Aug 23 05:31:59 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393368436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.2393368436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_macro_errs.2616929486 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 15651662269 ps |
| CPU time | 27.25 seconds |
| Started | Aug 23 05:34:58 PM UTC 24 |
| Finished | Aug 23 05:35:26 PM UTC 24 |
| Peak memory | 257492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616929486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.2616929486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_init_fail.3062781734 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 285595842 ps |
| CPU time | 4.35 seconds |
| Started | Aug 23 05:33:27 PM UTC 24 |
| Finished | Aug 23 05:33:32 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062781734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.3062781734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_init_fail.2614422747 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 484224963 ps |
| CPU time | 3.73 seconds |
| Started | Aug 23 05:33:13 PM UTC 24 |
| Finished | Aug 23 05:33:18 PM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614422747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.2614422747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_init_fail.463432295 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 411871818 ps |
| CPU time | 3.11 seconds |
| Started | Aug 23 05:38:26 PM UTC 24 |
| Finished | Aug 23 05:38:30 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463432295 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.463432295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/37.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_init_fail.4017387574 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 2578591558 ps |
| CPU time | 3.3 seconds |
| Started | Aug 23 05:43:58 PM UTC 24 |
| Finished | Aug 23 05:44:02 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017387574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.4017387574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/114.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.2196369504 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 140048595 ps |
| CPU time | 3.33 seconds |
| Started | Aug 23 05:45:13 PM UTC 24 |
| Finished | Aug 23 05:45:17 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196369504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.2196369504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/198.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_init_fail.1556671721 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 218303135 ps |
| CPU time | 2.85 seconds |
| Started | Aug 23 05:44:28 PM UTC 24 |
| Finished | Aug 23 05:44:32 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556671721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.1556671721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/147.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_lock.2526407480 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 2415059801 ps |
| CPU time | 17.33 seconds |
| Started | Aug 23 05:31:04 PM UTC 24 |
| Finished | Aug 23 05:31:22 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526407480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.2526407480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all_with_rand_reset.820822250 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 14457131425 ps |
| CPU time | 113.53 seconds |
| Started | Aug 23 05:37:54 PM UTC 24 |
| Finished | Aug 23 05:39:50 PM UTC 24 |
| Peak memory | 274100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=820822250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.820822250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_init_fail.3969005108 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 1690582853 ps |
| CPU time | 3.3 seconds |
| Started | Aug 23 05:30:42 PM UTC 24 |
| Finished | Aug 23 05:30:46 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969005108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.3969005108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_regwen.3122311247 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 317568462 ps |
| CPU time | 9.18 seconds |
| Started | Aug 23 05:32:51 PM UTC 24 |
| Finished | Aug 23 05:33:01 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122311247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.3122311247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_init_fail.1194919531 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 86218221 ps |
| CPU time | 2.5 seconds |
| Started | Aug 23 05:38:52 PM UTC 24 |
| Finished | Aug 23 05:38:56 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194919531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.1194919531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/39.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_esc.1927981623 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 2288000977 ps |
| CPU time | 6.43 seconds |
| Started | Aug 23 05:40:13 PM UTC 24 |
| Finished | Aug 23 05:40:21 PM UTC 24 |
| Peak memory | 250920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927981623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.1927981623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_parallel_lc_esc.549045082 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 7753837135 ps |
| CPU time | 15.12 seconds |
| Started | Aug 23 05:44:42 PM UTC 24 |
| Finished | Aug 23 05:44:58 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549045082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.549045082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/161.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all.1982478451 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 51866641170 ps |
| CPU time | 210 seconds |
| Started | Aug 23 05:35:55 PM UTC 24 |
| Finished | Aug 23 05:39:27 PM UTC 24 |
| Peak memory | 286336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982478451 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all.1982478451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_init_fail.873571020 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1727858269 ps |
| CPU time | 3.7 seconds |
| Started | Aug 23 05:36:50 PM UTC 24 |
| Finished | Aug 23 05:36:55 PM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873571020 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.873571020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/28.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all.3236614996 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 34197377292 ps |
| CPU time | 310.36 seconds |
| Started | Aug 23 05:32:39 PM UTC 24 |
| Finished | Aug 23 05:37:54 PM UTC 24 |
| Peak memory | 288176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236614996 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.3236614996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_regwen.89861808 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 244908768 ps |
| CPU time | 7.31 seconds |
| Started | Aug 23 05:34:25 PM UTC 24 |
| Finished | Aug 23 05:34:33 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89861808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ot p_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.89861808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.4202315035 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 3087852963 ps |
| CPU time | 4.94 seconds |
| Started | Aug 23 05:45:29 PM UTC 24 |
| Finished | Aug 23 05:45:35 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202315035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.4202315035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/245.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.3779762323 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 19684469195 ps |
| CPU time | 165.35 seconds |
| Started | Aug 23 05:39:45 PM UTC 24 |
| Finished | Aug 23 05:42:33 PM UTC 24 |
| Peak memory | 267952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3779762323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 43.otp_ctrl_stress_all_with_rand_reset.3779762323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all.1572607674 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 9290997596 ps |
| CPU time | 108.16 seconds |
| Started | Aug 23 05:31:52 PM UTC 24 |
| Finished | Aug 23 05:33:42 PM UTC 24 |
| Peak memory | 255416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572607674 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.1572607674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_check_fail.2930581360 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1087477829 ps |
| CPU time | 15.78 seconds |
| Started | Aug 23 05:37:46 PM UTC 24 |
| Finished | Aug 23 05:38:03 PM UTC 24 |
| Peak memory | 253360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930581360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.2930581360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/33.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_parallel_lc_esc.3145574282 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 698822283 ps |
| CPU time | 4.97 seconds |
| Started | Aug 23 05:44:38 PM UTC 24 |
| Finished | Aug 23 05:44:44 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145574282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.3145574282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/152.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.732253954 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 20020354287 ps |
| CPU time | 36.22 seconds |
| Started | Aug 23 05:10:58 PM UTC 24 |
| Finished | Aug 23 05:11:35 PM UTC 24 |
| Peak memory | 252936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732253954 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_intg_err.732253954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_lock.1346628142 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 3663600440 ps |
| CPU time | 17.57 seconds |
| Started | Aug 23 05:30:43 PM UTC 24 |
| Finished | Aug 23 05:31:01 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346628142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.1346628142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_esc.1731668563 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 184003172 ps |
| CPU time | 6.42 seconds |
| Started | Aug 23 05:34:46 PM UTC 24 |
| Finished | Aug 23 05:34:53 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731668563 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.1731668563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_check_fail.829633547 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2841662565 ps |
| CPU time | 13.08 seconds |
| Started | Aug 23 05:34:46 PM UTC 24 |
| Finished | Aug 23 05:35:00 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829633547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.829633547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/18.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_parallel_lc_esc.2995044896 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 2567900255 ps |
| CPU time | 6.79 seconds |
| Started | Aug 23 05:43:35 PM UTC 24 |
| Finished | Aug 23 05:43:43 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995044896 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.2995044896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/97.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all.3414970635 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 18553609181 ps |
| CPU time | 227.48 seconds |
| Started | Aug 23 05:32:25 PM UTC 24 |
| Finished | Aug 23 05:36:15 PM UTC 24 |
| Peak memory | 271752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414970635 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.3414970635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_parallel_lc_esc.313285721 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 865646391 ps |
| CPU time | 8.45 seconds |
| Started | Aug 23 05:43:50 PM UTC 24 |
| Finished | Aug 23 05:44:00 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313285721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.313285721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/107.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_parallel_lc_esc.1630179807 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 1217015658 ps |
| CPU time | 8.31 seconds |
| Started | Aug 23 05:44:39 PM UTC 24 |
| Finished | Aug 23 05:44:48 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630179807 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.1630179807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/158.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_parallel_lc_esc.994624623 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 3044782799 ps |
| CPU time | 11.15 seconds |
| Started | Aug 23 05:44:49 PM UTC 24 |
| Finished | Aug 23 05:45:02 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994624623 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.994624623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/170.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_background_chks.792596391 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1292677346 ps |
| CPU time | 13.84 seconds |
| Started | Aug 23 05:32:28 PM UTC 24 |
| Finished | Aug 23 05:32:43 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792596391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.792596391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_req.1384126628 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 2361269743 ps |
| CPU time | 17.07 seconds |
| Started | Aug 23 05:31:40 PM UTC 24 |
| Finished | Aug 23 05:31:59 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384126628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.1384126628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.3024477446 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 9049922409 ps |
| CPU time | 53.35 seconds |
| Started | Aug 23 05:33:21 PM UTC 24 |
| Finished | Aug 23 05:34:16 PM UTC 24 |
| Peak memory | 274096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3024477446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.otp_ctrl_stress_all_with_rand_reset.3024477446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_parallel_lc_esc.2674716700 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 293196032 ps |
| CPU time | 5.55 seconds |
| Started | Aug 23 05:41:19 PM UTC 24 |
| Finished | Aug 23 05:41:26 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674716700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.2674716700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/57.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.4138594059 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 175269267 ps |
| CPU time | 1.88 seconds |
| Started | Aug 23 05:10:26 PM UTC 24 |
| Finished | Aug 23 05:10:29 PM UTC 24 |
| Peak memory | 251888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138594059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_same_csr_outstanding.4138594059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_regwen.4201779598 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 5298805863 ps |
| CPU time | 10.33 seconds |
| Started | Aug 23 05:32:21 PM UTC 24 |
| Finished | Aug 23 05:32:32 PM UTC 24 |
| Peak memory | 253652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201779598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.4201779598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.485431701 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 122376789 ps |
| CPU time | 3.73 seconds |
| Started | Aug 23 05:45:19 PM UTC 24 |
| Finished | Aug 23 05:45:24 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485431701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.485431701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/201.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_init_fail.2391353728 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 128680132 ps |
| CPU time | 3 seconds |
| Started | Aug 23 05:42:47 PM UTC 24 |
| Finished | Aug 23 05:42:51 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391353728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.2391353728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/81.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all_with_rand_reset.1475141089 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4682564940 ps |
| CPU time | 103.85 seconds |
| Started | Aug 23 05:31:24 PM UTC 24 |
| Finished | Aug 23 05:33:09 PM UTC 24 |
| Peak memory | 268208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1475141089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 3.otp_ctrl_stress_all_with_rand_reset.1475141089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_check_fail.1501590751 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1241501950 ps |
| CPU time | 20.83 seconds |
| Started | Aug 23 05:34:23 PM UTC 24 |
| Finished | Aug 23 05:34:45 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501590751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.1501590751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_init_fail.531904716 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 146181279 ps |
| CPU time | 3.51 seconds |
| Started | Aug 23 05:32:40 PM UTC 24 |
| Finished | Aug 23 05:32:44 PM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531904716 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.531904716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_regwen.2284194001 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 4976582762 ps |
| CPU time | 14.27 seconds |
| Started | Aug 23 05:32:37 PM UTC 24 |
| Finished | Aug 23 05:32:53 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284194001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.2284194001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_check_fail.3427328818 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 744089834 ps |
| CPU time | 23.08 seconds |
| Started | Aug 23 05:35:08 PM UTC 24 |
| Finished | Aug 23 05:35:33 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427328818 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.3427328818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/20.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_check_fail.2505460466 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 1557801880 ps |
| CPU time | 10.6 seconds |
| Started | Aug 23 05:38:11 PM UTC 24 |
| Finished | Aug 23 05:38:23 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505460466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.2505460466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/35.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all.2076106424 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 46537026056 ps |
| CPU time | 195.51 seconds |
| Started | Aug 23 05:33:11 PM UTC 24 |
| Finished | Aug 23 05:36:29 PM UTC 24 |
| Peak memory | 284148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076106424 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.2076106424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_init_fail.2040653615 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 621441195 ps |
| CPU time | 3.34 seconds |
| Started | Aug 23 05:33:39 PM UTC 24 |
| Finished | Aug 23 05:33:44 PM UTC 24 |
| Peak memory | 251396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040653615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.2040653615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_macro_errs.2329556055 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 769616103 ps |
| CPU time | 8.62 seconds |
| Started | Aug 23 05:33:16 PM UTC 24 |
| Finished | Aug 23 05:33:26 PM UTC 24 |
| Peak memory | 253400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329556055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.2329556055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_wake_up.2256824060 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 776369195 ps |
| CPU time | 1.48 seconds |
| Started | Aug 23 05:30:40 PM UTC 24 |
| Finished | Aug 23 05:30:43 PM UTC 24 |
| Peak memory | 247800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256824060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes t +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.2256824060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_smoke.2286448809 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 5164772109 ps |
| CPU time | 10.73 seconds |
| Started | Aug 23 05:30:47 PM UTC 24 |
| Finished | Aug 23 05:30:59 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286448809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.2286448809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.722565429 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 1251034412 ps |
| CPU time | 16.2 seconds |
| Started | Aug 23 05:11:07 PM UTC 24 |
| Finished | Aug 23 05:11:24 PM UTC 24 |
| Peak memory | 252784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722565429 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_intg_err.722565429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all.2117967345 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 31499568648 ps |
| CPU time | 50.25 seconds |
| Started | Aug 23 05:34:14 PM UTC 24 |
| Finished | Aug 23 05:35:06 PM UTC 24 |
| Peak memory | 288316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117967345 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.2117967345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_regwen.3475361939 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 291637521 ps |
| CPU time | 9.57 seconds |
| Started | Aug 23 05:35:02 PM UTC 24 |
| Finished | Aug 23 05:35:13 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475361939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.3475361939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.10168040 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 47256493 ps |
| CPU time | 1.49 seconds |
| Started | Aug 23 05:11:12 PM UTC 24 |
| Finished | Aug 23 05:11:15 PM UTC 24 |
| Peak memory | 251876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10168040 -assert nopostproc +UVM_TESTNAME=otp_c trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.10168040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_key_req.14747176 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 615953526 ps |
| CPU time | 10.81 seconds |
| Started | Aug 23 05:32:01 PM UTC 24 |
| Finished | Aug 23 05:32:13 PM UTC 24 |
| Peak memory | 253356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14747176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.14747176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_background_chks.2298796633 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 14211441169 ps |
| CPU time | 31.86 seconds |
| Started | Aug 23 05:30:42 PM UTC 24 |
| Finished | Aug 23 05:31:15 PM UTC 24 |
| Peak memory | 253492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298796633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.2298796633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_init_fail.605926632 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 1575484395 ps |
| CPU time | 4 seconds |
| Started | Aug 23 05:44:07 PM UTC 24 |
| Finished | Aug 23 05:44:12 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605926632 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.605926632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/124.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.968224250 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 133697874 ps |
| CPU time | 4.06 seconds |
| Started | Aug 23 05:45:28 PM UTC 24 |
| Finished | Aug 23 05:45:33 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968224250 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.968224250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/218.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_init_fail.3051196973 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 188841746 ps |
| CPU time | 3.4 seconds |
| Started | Aug 23 05:43:38 PM UTC 24 |
| Finished | Aug 23 05:43:42 PM UTC 24 |
| Peak memory | 251492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051196973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.3051196973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/99.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.3293159584 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2475693727 ps |
| CPU time | 9.01 seconds |
| Started | Aug 23 05:11:06 PM UTC 24 |
| Finished | Aug 23 05:11:16 PM UTC 24 |
| Peak memory | 257104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293159584 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_intg_err.3293159584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_init_fail.3036042054 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 266608901 ps |
| CPU time | 3.8 seconds |
| Started | Aug 23 05:44:39 PM UTC 24 |
| Finished | Aug 23 05:44:44 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036042054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.3036042054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/158.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.2257851347 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 296702475 ps |
| CPU time | 2.88 seconds |
| Started | Aug 23 05:45:28 PM UTC 24 |
| Finished | Aug 23 05:45:32 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257851347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.2257851347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/217.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_smoke.2649675168 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 1761564640 ps |
| CPU time | 9.44 seconds |
| Started | Aug 23 05:31:15 PM UTC 24 |
| Finished | Aug 23 05:31:25 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649675168 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.2649675168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_init_fail.3593347481 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 292969639 ps |
| CPU time | 2.97 seconds |
| Started | Aug 23 05:45:02 PM UTC 24 |
| Finished | Aug 23 05:45:06 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593347481 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.3593347481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/181.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.1928383251 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 160947615 ps |
| CPU time | 3.15 seconds |
| Started | Aug 23 05:45:19 PM UTC 24 |
| Finished | Aug 23 05:45:24 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928383251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.1928383251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/212.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.2037757584 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 336710194 ps |
| CPU time | 3.95 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:46 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037757584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.2037757584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/259.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_init_fail.330357621 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 249230082 ps |
| CPU time | 3.44 seconds |
| Started | Aug 23 05:38:08 PM UTC 24 |
| Finished | Aug 23 05:38:12 PM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330357621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.330357621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/35.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.1695723325 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 405183659 ps |
| CPU time | 3.19 seconds |
| Started | Aug 23 05:10:25 PM UTC 24 |
| Finished | Aug 23 05:10:29 PM UTC 24 |
| Peak memory | 252764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695723325 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_aliasing.1695723325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2243281850 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 916589217 ps |
| CPU time | 7.94 seconds |
| Started | Aug 23 05:10:25 PM UTC 24 |
| Finished | Aug 23 05:10:34 PM UTC 24 |
| Peak memory | 252636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243281850 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_bash.2243281850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.85294738 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 75138858 ps |
| CPU time | 1.56 seconds |
| Started | Aug 23 05:10:22 PM UTC 24 |
| Finished | Aug 23 05:10:25 PM UTC 24 |
| Peak memory | 251928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85294738 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_reset.85294738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.2377044056 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 142261740 ps |
| CPU time | 1.86 seconds |
| Started | Aug 23 05:10:27 PM UTC 24 |
| Finished | Aug 23 05:10:30 PM UTC 24 |
| Peak memory | 255892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2377044056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_cs r_mem_rw_with_rand_reset.2377044056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.2456051026 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 643292527 ps |
| CPU time | 1.8 seconds |
| Started | Aug 23 05:10:22 PM UTC 24 |
| Finished | Aug 23 05:10:25 PM UTC 24 |
| Peak memory | 254100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456051026 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.2456051026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.1829086867 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 43985210 ps |
| CPU time | 1.18 seconds |
| Started | Aug 23 05:10:19 PM UTC 24 |
| Finished | Aug 23 05:10:21 PM UTC 24 |
| Peak memory | 241908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829086867 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.1829086867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.1205294858 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 36478109 ps |
| CPU time | 1.18 seconds |
| Started | Aug 23 05:10:22 PM UTC 24 |
| Finished | Aug 23 05:10:24 PM UTC 24 |
| Peak memory | 240272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205294858 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_partial_access.1205294858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.1714716139 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 36620941 ps |
| CPU time | 1.18 seconds |
| Started | Aug 23 05:10:19 PM UTC 24 |
| Finished | Aug 23 05:10:21 PM UTC 24 |
| Peak memory | 240332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714716139 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.1714716139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.4149477720 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 221538470 ps |
| CPU time | 3.47 seconds |
| Started | Aug 23 05:10:17 PM UTC 24 |
| Finished | Aug 23 05:10:21 PM UTC 24 |
| Peak memory | 259132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149477720 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.4149477720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.1470643291 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 117165745 ps |
| CPU time | 3.2 seconds |
| Started | Aug 23 05:10:35 PM UTC 24 |
| Finished | Aug 23 05:10:39 PM UTC 24 |
| Peak memory | 252688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470643291 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_bash.1470643291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.3269857176 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 186066959 ps |
| CPU time | 2.23 seconds |
| Started | Aug 23 05:10:35 PM UTC 24 |
| Finished | Aug 23 05:10:38 PM UTC 24 |
| Peak memory | 254820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269857176 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_reset.3269857176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.1554771149 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 140728267 ps |
| CPU time | 1.86 seconds |
| Started | Aug 23 05:10:37 PM UTC 24 |
| Finished | Aug 23 05:10:40 PM UTC 24 |
| Peak memory | 256064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1554771149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_cs r_mem_rw_with_rand_reset.1554771149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.662172273 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 571048727 ps |
| CPU time | 1.52 seconds |
| Started | Aug 23 05:10:35 PM UTC 24 |
| Finished | Aug 23 05:10:37 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662172273 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.662172273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.1178711011 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 70379166 ps |
| CPU time | 1.22 seconds |
| Started | Aug 23 05:10:32 PM UTC 24 |
| Finished | Aug 23 05:10:34 PM UTC 24 |
| Peak memory | 241192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178711011 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.1178711011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.3940345456 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 49988576 ps |
| CPU time | 1.21 seconds |
| Started | Aug 23 05:10:33 PM UTC 24 |
| Finished | Aug 23 05:10:35 PM UTC 24 |
| Peak memory | 241684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940345456 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_partial_access.3940345456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2302237941 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 67271756 ps |
| CPU time | 1.15 seconds |
| Started | Aug 23 05:10:32 PM UTC 24 |
| Finished | Aug 23 05:10:34 PM UTC 24 |
| Peak memory | 240328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302237941 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.2302237941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.206706023 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 114031134 ps |
| CPU time | 2.83 seconds |
| Started | Aug 23 05:10:36 PM UTC 24 |
| Finished | Aug 23 05:10:40 PM UTC 24 |
| Peak memory | 252748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206706023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_same_csr_outstanding.206706023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1436554252 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 489116149 ps |
| CPU time | 4.83 seconds |
| Started | Aug 23 05:10:30 PM UTC 24 |
| Finished | Aug 23 05:10:36 PM UTC 24 |
| Peak memory | 259096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436554252 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.1436554252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1457250975 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 9774801704 ps |
| CPU time | 13.46 seconds |
| Started | Aug 23 05:10:30 PM UTC 24 |
| Finished | Aug 23 05:10:45 PM UTC 24 |
| Peak memory | 257000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457250975 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_intg_err.1457250975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3908068835 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 297099178 ps |
| CPU time | 2.68 seconds |
| Started | Aug 23 05:11:06 PM UTC 24 |
| Finished | Aug 23 05:11:10 PM UTC 24 |
| Peak memory | 258880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3908068835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_c sr_mem_rw_with_rand_reset.3908068835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.1813103325 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 45146570 ps |
| CPU time | 1.36 seconds |
| Started | Aug 23 05:11:06 PM UTC 24 |
| Finished | Aug 23 05:11:09 PM UTC 24 |
| Peak memory | 251800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813103325 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.1813103325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.923088742 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 77565124 ps |
| CPU time | 1.22 seconds |
| Started | Aug 23 05:11:06 PM UTC 24 |
| Finished | Aug 23 05:11:09 PM UTC 24 |
| Peak memory | 241700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923088742 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.923088742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.3622499945 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 133855148 ps |
| CPU time | 1.97 seconds |
| Started | Aug 23 05:11:06 PM UTC 24 |
| Finished | Aug 23 05:11:09 PM UTC 24 |
| Peak memory | 251876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622499945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_same_csr_outstanding.3622499945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.851698745 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 677962562 ps |
| CPU time | 5.67 seconds |
| Started | Aug 23 05:11:06 PM UTC 24 |
| Finished | Aug 23 05:11:13 PM UTC 24 |
| Peak memory | 258984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851698745 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.851698745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3974601655 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 1090909425 ps |
| CPU time | 2.39 seconds |
| Started | Aug 23 05:11:10 PM UTC 24 |
| Finished | Aug 23 05:11:13 PM UTC 24 |
| Peak memory | 256824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3974601655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_c sr_mem_rw_with_rand_reset.3974601655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1512994404 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 49228175 ps |
| CPU time | 1.42 seconds |
| Started | Aug 23 05:11:08 PM UTC 24 |
| Finished | Aug 23 05:11:10 PM UTC 24 |
| Peak memory | 251976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512994404 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.1512994404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.3938264284 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 132218957 ps |
| CPU time | 1.32 seconds |
| Started | Aug 23 05:11:07 PM UTC 24 |
| Finished | Aug 23 05:11:09 PM UTC 24 |
| Peak memory | 241192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938264284 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.3938264284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.2555633062 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 173390668 ps |
| CPU time | 1.7 seconds |
| Started | Aug 23 05:11:08 PM UTC 24 |
| Finished | Aug 23 05:11:10 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555633062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_same_csr_outstanding.2555633062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.1524846188 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 297612157 ps |
| CPU time | 3.03 seconds |
| Started | Aug 23 05:11:06 PM UTC 24 |
| Finished | Aug 23 05:11:11 PM UTC 24 |
| Peak memory | 259028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524846188 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.1524846188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.1381710348 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 110378667 ps |
| CPU time | 2.5 seconds |
| Started | Aug 23 05:11:11 PM UTC 24 |
| Finished | Aug 23 05:11:14 PM UTC 24 |
| Peak memory | 258880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1381710348 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_c sr_mem_rw_with_rand_reset.1381710348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1203995884 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 41657433 ps |
| CPU time | 1.51 seconds |
| Started | Aug 23 05:11:10 PM UTC 24 |
| Finished | Aug 23 05:11:12 PM UTC 24 |
| Peak memory | 253960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203995884 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.1203995884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.2593009528 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 41140633 ps |
| CPU time | 1.27 seconds |
| Started | Aug 23 05:11:10 PM UTC 24 |
| Finished | Aug 23 05:11:12 PM UTC 24 |
| Peak memory | 241700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593009528 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.2593009528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.332635961 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 102453582 ps |
| CPU time | 1.6 seconds |
| Started | Aug 23 05:11:10 PM UTC 24 |
| Finished | Aug 23 05:11:13 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332635961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_same_csr_outstanding.332635961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.3502849583 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 2481071661 ps |
| CPU time | 6.54 seconds |
| Started | Aug 23 05:11:10 PM UTC 24 |
| Finished | Aug 23 05:11:17 PM UTC 24 |
| Peak memory | 259096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502849583 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.3502849583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.2986989018 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 4783356049 ps |
| CPU time | 18.74 seconds |
| Started | Aug 23 05:11:10 PM UTC 24 |
| Finished | Aug 23 05:11:30 PM UTC 24 |
| Peak memory | 257132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986989018 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_intg_err.2986989018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1929239171 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 71548690 ps |
| CPU time | 1.8 seconds |
| Started | Aug 23 05:11:13 PM UTC 24 |
| Finished | Aug 23 05:11:16 PM UTC 24 |
| Peak memory | 255980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1929239171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_c sr_mem_rw_with_rand_reset.1929239171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.1486133647 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 40798896 ps |
| CPU time | 1.22 seconds |
| Started | Aug 23 05:11:11 PM UTC 24 |
| Finished | Aug 23 05:11:13 PM UTC 24 |
| Peak memory | 240064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486133647 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.1486133647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.4045522790 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 135420675 ps |
| CPU time | 2.5 seconds |
| Started | Aug 23 05:11:12 PM UTC 24 |
| Finished | Aug 23 05:11:16 PM UTC 24 |
| Peak memory | 252676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045522790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_same_csr_outstanding.4045522790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1858699849 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 131818176 ps |
| CPU time | 2.68 seconds |
| Started | Aug 23 05:11:11 PM UTC 24 |
| Finished | Aug 23 05:11:15 PM UTC 24 |
| Peak memory | 258464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858699849 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.1858699849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.4120454924 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 2402286272 ps |
| CPU time | 17.64 seconds |
| Started | Aug 23 05:11:11 PM UTC 24 |
| Finished | Aug 23 05:11:30 PM UTC 24 |
| Peak memory | 252824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120454924 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_intg_err.4120454924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.1246860535 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 117002779 ps |
| CPU time | 1.82 seconds |
| Started | Aug 23 05:11:14 PM UTC 24 |
| Finished | Aug 23 05:11:17 PM UTC 24 |
| Peak memory | 258052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1246860535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_c sr_mem_rw_with_rand_reset.1246860535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.3585277824 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 82734677 ps |
| CPU time | 1.45 seconds |
| Started | Aug 23 05:11:14 PM UTC 24 |
| Finished | Aug 23 05:11:17 PM UTC 24 |
| Peak memory | 251908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585277824 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.3585277824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.3774615017 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 38970662 ps |
| CPU time | 1.25 seconds |
| Started | Aug 23 05:11:14 PM UTC 24 |
| Finished | Aug 23 05:11:17 PM UTC 24 |
| Peak memory | 241464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774615017 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.3774615017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.2649909712 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 73365983 ps |
| CPU time | 1.95 seconds |
| Started | Aug 23 05:11:14 PM UTC 24 |
| Finished | Aug 23 05:11:17 PM UTC 24 |
| Peak memory | 251876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649909712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_same_csr_outstanding.2649909712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.2247399100 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 2655180734 ps |
| CPU time | 5.62 seconds |
| Started | Aug 23 05:11:13 PM UTC 24 |
| Finished | Aug 23 05:11:20 PM UTC 24 |
| Peak memory | 259096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247399100 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.2247399100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3814804350 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1209962007 ps |
| CPU time | 8.95 seconds |
| Started | Aug 23 05:11:13 PM UTC 24 |
| Finished | Aug 23 05:11:23 PM UTC 24 |
| Peak memory | 256876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814804350 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_intg_err.3814804350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.2148047456 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 1650658128 ps |
| CPU time | 4.09 seconds |
| Started | Aug 23 05:11:17 PM UTC 24 |
| Finished | Aug 23 05:11:22 PM UTC 24 |
| Peak memory | 258940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2148047456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_c sr_mem_rw_with_rand_reset.2148047456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.1970269374 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 81367370 ps |
| CPU time | 1.33 seconds |
| Started | Aug 23 05:11:16 PM UTC 24 |
| Finished | Aug 23 05:11:18 PM UTC 24 |
| Peak memory | 251860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970269374 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.1970269374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.1897190609 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 44128422 ps |
| CPU time | 1.28 seconds |
| Started | Aug 23 05:11:15 PM UTC 24 |
| Finished | Aug 23 05:11:18 PM UTC 24 |
| Peak memory | 241700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897190609 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.1897190609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.2490757210 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 976535141 ps |
| CPU time | 1.78 seconds |
| Started | Aug 23 05:11:17 PM UTC 24 |
| Finished | Aug 23 05:11:19 PM UTC 24 |
| Peak memory | 251952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490757210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_same_csr_outstanding.2490757210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.2604274958 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 3440439397 ps |
| CPU time | 7.84 seconds |
| Started | Aug 23 05:11:14 PM UTC 24 |
| Finished | Aug 23 05:11:23 PM UTC 24 |
| Peak memory | 259104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604274958 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.2604274958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3202101260 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2457358054 ps |
| CPU time | 9.19 seconds |
| Started | Aug 23 05:11:15 PM UTC 24 |
| Finished | Aug 23 05:11:26 PM UTC 24 |
| Peak memory | 252968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202101260 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_intg_err.3202101260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.1080945843 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 105294653 ps |
| CPU time | 2.6 seconds |
| Started | Aug 23 05:11:19 PM UTC 24 |
| Finished | Aug 23 05:11:23 PM UTC 24 |
| Peak memory | 259092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1080945843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_c sr_mem_rw_with_rand_reset.1080945843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.288834278 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 93996183 ps |
| CPU time | 1.3 seconds |
| Started | Aug 23 05:11:18 PM UTC 24 |
| Finished | Aug 23 05:11:20 PM UTC 24 |
| Peak memory | 251876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288834278 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.288834278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.3869255564 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 77724511 ps |
| CPU time | 1.28 seconds |
| Started | Aug 23 05:11:18 PM UTC 24 |
| Finished | Aug 23 05:11:20 PM UTC 24 |
| Peak memory | 241464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869255564 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.3869255564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.2867781867 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 970848247 ps |
| CPU time | 2.36 seconds |
| Started | Aug 23 05:11:18 PM UTC 24 |
| Finished | Aug 23 05:11:21 PM UTC 24 |
| Peak memory | 252836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867781867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_same_csr_outstanding.2867781867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.2128694600 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 174174785 ps |
| CPU time | 5.17 seconds |
| Started | Aug 23 05:11:18 PM UTC 24 |
| Finished | Aug 23 05:11:24 PM UTC 24 |
| Peak memory | 258916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128694600 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.2128694600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2614168868 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 18782637286 ps |
| CPU time | 23.66 seconds |
| Started | Aug 23 05:11:18 PM UTC 24 |
| Finished | Aug 23 05:11:43 PM UTC 24 |
| Peak memory | 252832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614168868 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_intg_err.2614168868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.2715546940 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 103765576 ps |
| CPU time | 2.18 seconds |
| Started | Aug 23 05:11:21 PM UTC 24 |
| Finished | Aug 23 05:11:24 PM UTC 24 |
| Peak memory | 256896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2715546940 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_c sr_mem_rw_with_rand_reset.2715546940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.36901726 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 43343729 ps |
| CPU time | 1.37 seconds |
| Started | Aug 23 05:11:21 PM UTC 24 |
| Finished | Aug 23 05:11:23 PM UTC 24 |
| Peak memory | 253752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36901726 -assert nopostproc +UVM_TESTNAME=otp_c trl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.36901726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/17.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.360926867 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 79600948 ps |
| CPU time | 1.24 seconds |
| Started | Aug 23 05:11:20 PM UTC 24 |
| Finished | Aug 23 05:11:22 PM UTC 24 |
| Peak memory | 241144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360926867 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.360926867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/17.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.163868299 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 85830397 ps |
| CPU time | 2.4 seconds |
| Started | Aug 23 05:11:21 PM UTC 24 |
| Finished | Aug 23 05:11:24 PM UTC 24 |
| Peak memory | 254472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163868299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_same_csr_outstanding.163868299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/17.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1319325543 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 277799474 ps |
| CPU time | 4.18 seconds |
| Started | Aug 23 05:11:19 PM UTC 24 |
| Finished | Aug 23 05:11:24 PM UTC 24 |
| Peak memory | 258964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319325543 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1319325543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/17.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.2846698231 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 2349005622 ps |
| CPU time | 8.8 seconds |
| Started | Aug 23 05:11:19 PM UTC 24 |
| Finished | Aug 23 05:11:29 PM UTC 24 |
| Peak memory | 252952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846698231 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_intg_err.2846698231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/17.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1979661743 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 264685838 ps |
| CPU time | 2.91 seconds |
| Started | Aug 23 05:11:24 PM UTC 24 |
| Finished | Aug 23 05:11:28 PM UTC 24 |
| Peak memory | 258528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1979661743 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_c sr_mem_rw_with_rand_reset.1979661743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.3759761571 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 591344539 ps |
| CPU time | 1.56 seconds |
| Started | Aug 23 05:11:23 PM UTC 24 |
| Finished | Aug 23 05:11:26 PM UTC 24 |
| Peak memory | 258020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759761571 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.3759761571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/18.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.2220438943 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 83741928 ps |
| CPU time | 1.34 seconds |
| Started | Aug 23 05:11:23 PM UTC 24 |
| Finished | Aug 23 05:11:26 PM UTC 24 |
| Peak memory | 241700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220438943 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.2220438943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/18.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.832531534 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 815462828 ps |
| CPU time | 2.38 seconds |
| Started | Aug 23 05:11:23 PM UTC 24 |
| Finished | Aug 23 05:11:27 PM UTC 24 |
| Peak memory | 254808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832531534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_same_csr_outstanding.832531534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/18.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.3728051773 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 76504308 ps |
| CPU time | 2.62 seconds |
| Started | Aug 23 05:11:22 PM UTC 24 |
| Finished | Aug 23 05:11:26 PM UTC 24 |
| Peak memory | 259040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728051773 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.3728051773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/18.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.783978684 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 1244012208 ps |
| CPU time | 8.45 seconds |
| Started | Aug 23 05:11:22 PM UTC 24 |
| Finished | Aug 23 05:11:32 PM UTC 24 |
| Peak memory | 256908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783978684 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_intg_err.783978684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/18.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_mem_rw_with_rand_reset.1707962966 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 1558352465 ps |
| CPU time | 3.07 seconds |
| Started | Aug 23 05:11:25 PM UTC 24 |
| Finished | Aug 23 05:11:30 PM UTC 24 |
| Peak memory | 258936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1707962966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_c sr_mem_rw_with_rand_reset.1707962966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.393897573 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 582687502 ps |
| CPU time | 2 seconds |
| Started | Aug 23 05:11:24 PM UTC 24 |
| Finished | Aug 23 05:11:27 PM UTC 24 |
| Peak memory | 252840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393897573 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.393897573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.2777134629 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 39983523 ps |
| CPU time | 1.24 seconds |
| Started | Aug 23 05:11:24 PM UTC 24 |
| Finished | Aug 23 05:11:27 PM UTC 24 |
| Peak memory | 241752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777134629 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.2777134629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.663809428 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 104742639 ps |
| CPU time | 1.75 seconds |
| Started | Aug 23 05:11:25 PM UTC 24 |
| Finished | Aug 23 05:11:28 PM UTC 24 |
| Peak memory | 251904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663809428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_same_csr_outstanding.663809428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2623737653 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 127146623 ps |
| CPU time | 3.49 seconds |
| Started | Aug 23 05:11:24 PM UTC 24 |
| Finished | Aug 23 05:11:29 PM UTC 24 |
| Peak memory | 259132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623737653 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.2623737653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.3393558854 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 4868076972 ps |
| CPU time | 17.55 seconds |
| Started | Aug 23 05:11:24 PM UTC 24 |
| Finished | Aug 23 05:11:43 PM UTC 24 |
| Peak memory | 256908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393558854 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_intg_err.3393558854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.1916742200 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 1551480943 ps |
| CPU time | 4.27 seconds |
| Started | Aug 23 05:10:45 PM UTC 24 |
| Finished | Aug 23 05:10:50 PM UTC 24 |
| Peak memory | 252692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916742200 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_aliasing.1916742200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.1950748902 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 1272873159 ps |
| CPU time | 4.61 seconds |
| Started | Aug 23 05:10:45 PM UTC 24 |
| Finished | Aug 23 05:10:50 PM UTC 24 |
| Peak memory | 252844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950748902 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_bash.1950748902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.3284924422 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 140762200 ps |
| CPU time | 1.63 seconds |
| Started | Aug 23 05:10:40 PM UTC 24 |
| Finished | Aug 23 05:10:43 PM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284924422 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_reset.3284924422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.715645378 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 1105085206 ps |
| CPU time | 2.51 seconds |
| Started | Aug 23 05:10:45 PM UTC 24 |
| Finished | Aug 23 05:10:49 PM UTC 24 |
| Peak memory | 256900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=715645378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr _mem_rw_with_rand_reset.715645378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.2505402502 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 671094480 ps |
| CPU time | 1.64 seconds |
| Started | Aug 23 05:10:45 PM UTC 24 |
| Finished | Aug 23 05:10:48 PM UTC 24 |
| Peak memory | 251864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505402502 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.2505402502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.3987508775 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 43950066 ps |
| CPU time | 1.25 seconds |
| Started | Aug 23 05:10:40 PM UTC 24 |
| Finished | Aug 23 05:10:42 PM UTC 24 |
| Peak memory | 241200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987508775 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.3987508775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.2451258083 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 38448170 ps |
| CPU time | 1.24 seconds |
| Started | Aug 23 05:10:40 PM UTC 24 |
| Finished | Aug 23 05:10:42 PM UTC 24 |
| Peak memory | 241684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451258083 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_partial_access.2451258083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.3209600186 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 135103302 ps |
| CPU time | 1.29 seconds |
| Started | Aug 23 05:10:40 PM UTC 24 |
| Finished | Aug 23 05:10:42 PM UTC 24 |
| Peak memory | 240328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209600186 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.3209600186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.1867060482 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 50071114 ps |
| CPU time | 1.72 seconds |
| Started | Aug 23 05:10:45 PM UTC 24 |
| Finished | Aug 23 05:10:48 PM UTC 24 |
| Peak memory | 253884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867060482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_same_csr_outstanding.1867060482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.2029751270 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 651755583 ps |
| CPU time | 5.96 seconds |
| Started | Aug 23 05:10:38 PM UTC 24 |
| Finished | Aug 23 05:10:45 PM UTC 24 |
| Peak memory | 253024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029751270 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.2029751270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.3497439441 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1005814355 ps |
| CPU time | 10.37 seconds |
| Started | Aug 23 05:10:39 PM UTC 24 |
| Finished | Aug 23 05:10:50 PM UTC 24 |
| Peak memory | 252768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497439441 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_intg_err.3497439441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.3727629960 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 45176827 ps |
| CPU time | 1.25 seconds |
| Started | Aug 23 05:11:26 PM UTC 24 |
| Finished | Aug 23 05:11:28 PM UTC 24 |
| Peak memory | 241132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727629960 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.3727629960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/20.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.1098982728 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 38915718 ps |
| CPU time | 1.21 seconds |
| Started | Aug 23 05:11:27 PM UTC 24 |
| Finished | Aug 23 05:11:29 PM UTC 24 |
| Peak memory | 241192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098982728 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.1098982728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/21.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.628902316 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 135162283 ps |
| CPU time | 1.28 seconds |
| Started | Aug 23 05:11:27 PM UTC 24 |
| Finished | Aug 23 05:11:29 PM UTC 24 |
| Peak memory | 241192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628902316 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.628902316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/22.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.3262643220 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 134901018 ps |
| CPU time | 1.15 seconds |
| Started | Aug 23 05:11:27 PM UTC 24 |
| Finished | Aug 23 05:11:29 PM UTC 24 |
| Peak memory | 241132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262643220 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.3262643220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/23.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.4156884218 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 149850985 ps |
| CPU time | 1.25 seconds |
| Started | Aug 23 05:11:27 PM UTC 24 |
| Finished | Aug 23 05:11:29 PM UTC 24 |
| Peak memory | 241700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156884218 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.4156884218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/24.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.3256551699 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 144115601 ps |
| CPU time | 1.25 seconds |
| Started | Aug 23 05:11:28 PM UTC 24 |
| Finished | Aug 23 05:11:30 PM UTC 24 |
| Peak memory | 241096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256551699 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.3256551699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/25.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.1028340391 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 91485284 ps |
| CPU time | 1.23 seconds |
| Started | Aug 23 05:11:28 PM UTC 24 |
| Finished | Aug 23 05:11:30 PM UTC 24 |
| Peak memory | 241632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028340391 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.1028340391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/26.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.3831243513 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 38066274 ps |
| CPU time | 1.2 seconds |
| Started | Aug 23 05:11:28 PM UTC 24 |
| Finished | Aug 23 05:11:30 PM UTC 24 |
| Peak memory | 241192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831243513 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.3831243513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/27.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.3199281182 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 70588985 ps |
| CPU time | 1.17 seconds |
| Started | Aug 23 05:11:29 PM UTC 24 |
| Finished | Aug 23 05:11:31 PM UTC 24 |
| Peak memory | 241700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199281182 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.3199281182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/28.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.1298367140 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 43067816 ps |
| CPU time | 1.27 seconds |
| Started | Aug 23 05:11:29 PM UTC 24 |
| Finished | Aug 23 05:11:31 PM UTC 24 |
| Peak memory | 241260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298367140 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.1298367140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/29.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.1808890711 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 221304768 ps |
| CPU time | 3.23 seconds |
| Started | Aug 23 05:10:49 PM UTC 24 |
| Finished | Aug 23 05:10:54 PM UTC 24 |
| Peak memory | 252636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808890711 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_aliasing.1808890711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.3817468594 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 855888585 ps |
| CPU time | 7.73 seconds |
| Started | Aug 23 05:10:49 PM UTC 24 |
| Finished | Aug 23 05:10:58 PM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817468594 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_bash.3817468594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.2647474214 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 109112202 ps |
| CPU time | 2.09 seconds |
| Started | Aug 23 05:10:48 PM UTC 24 |
| Finished | Aug 23 05:10:51 PM UTC 24 |
| Peak memory | 254816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647474214 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_reset.2647474214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.823677207 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 103684849 ps |
| CPU time | 2.05 seconds |
| Started | Aug 23 05:10:51 PM UTC 24 |
| Finished | Aug 23 05:10:54 PM UTC 24 |
| Peak memory | 258940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=823677207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr _mem_rw_with_rand_reset.823677207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.3313869471 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 86930061 ps |
| CPU time | 1.52 seconds |
| Started | Aug 23 05:10:49 PM UTC 24 |
| Finished | Aug 23 05:10:52 PM UTC 24 |
| Peak memory | 253472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313869471 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.3313869471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.33517375 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 141855369 ps |
| CPU time | 1.19 seconds |
| Started | Aug 23 05:10:46 PM UTC 24 |
| Finished | Aug 23 05:10:48 PM UTC 24 |
| Peak memory | 241700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33517375 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.33517375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.1774406345 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 40745919 ps |
| CPU time | 1.18 seconds |
| Started | Aug 23 05:10:48 PM UTC 24 |
| Finished | Aug 23 05:10:50 PM UTC 24 |
| Peak memory | 240272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774406345 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_partial_access.1774406345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.3920287153 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 139147734 ps |
| CPU time | 1.25 seconds |
| Started | Aug 23 05:10:47 PM UTC 24 |
| Finished | Aug 23 05:10:49 PM UTC 24 |
| Peak memory | 240332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920287153 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.3920287153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2630218928 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 75160558 ps |
| CPU time | 1.58 seconds |
| Started | Aug 23 05:10:51 PM UTC 24 |
| Finished | Aug 23 05:10:53 PM UTC 24 |
| Peak memory | 251856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630218928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_same_csr_outstanding.2630218928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.3206145614 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 188551172 ps |
| CPU time | 5.35 seconds |
| Started | Aug 23 05:10:45 PM UTC 24 |
| Finished | Aug 23 05:10:52 PM UTC 24 |
| Peak memory | 258964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206145614 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.3206145614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.1843649403 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 5773887937 ps |
| CPU time | 18.48 seconds |
| Started | Aug 23 05:10:46 PM UTC 24 |
| Finished | Aug 23 05:11:06 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843649403 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_intg_err.1843649403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.1715970451 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 79291045 ps |
| CPU time | 1.31 seconds |
| Started | Aug 23 05:11:29 PM UTC 24 |
| Finished | Aug 23 05:11:31 PM UTC 24 |
| Peak memory | 241140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715970451 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.1715970451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/30.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.60616126 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 588605095 ps |
| CPU time | 1.99 seconds |
| Started | Aug 23 05:11:30 PM UTC 24 |
| Finished | Aug 23 05:11:33 PM UTC 24 |
| Peak memory | 241132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60616126 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.60616126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/31.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.1023449311 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 40807010 ps |
| CPU time | 1.26 seconds |
| Started | Aug 23 05:11:30 PM UTC 24 |
| Finished | Aug 23 05:11:32 PM UTC 24 |
| Peak memory | 241648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023449311 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.1023449311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/32.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.1469954984 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 131253396 ps |
| CPU time | 1.26 seconds |
| Started | Aug 23 05:11:30 PM UTC 24 |
| Finished | Aug 23 05:11:32 PM UTC 24 |
| Peak memory | 241192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469954984 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.1469954984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/33.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.268254209 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 93168158 ps |
| CPU time | 1.33 seconds |
| Started | Aug 23 05:11:30 PM UTC 24 |
| Finished | Aug 23 05:11:32 PM UTC 24 |
| Peak memory | 241084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268254209 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.268254209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/34.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.3629595741 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 62127742 ps |
| CPU time | 1.36 seconds |
| Started | Aug 23 05:11:30 PM UTC 24 |
| Finished | Aug 23 05:11:33 PM UTC 24 |
| Peak memory | 241292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629595741 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.3629595741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/35.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.1843360397 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 76027661 ps |
| CPU time | 1.23 seconds |
| Started | Aug 23 05:11:30 PM UTC 24 |
| Finished | Aug 23 05:11:32 PM UTC 24 |
| Peak memory | 241140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843360397 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.1843360397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/36.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.697348815 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 140596561 ps |
| CPU time | 1.21 seconds |
| Started | Aug 23 05:11:30 PM UTC 24 |
| Finished | Aug 23 05:11:32 PM UTC 24 |
| Peak memory | 241192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697348815 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.697348815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/37.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.767177703 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 47043319 ps |
| CPU time | 1.28 seconds |
| Started | Aug 23 05:11:31 PM UTC 24 |
| Finished | Aug 23 05:11:34 PM UTC 24 |
| Peak memory | 241752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767177703 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.767177703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/38.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.239140919 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 141108791 ps |
| CPU time | 1.33 seconds |
| Started | Aug 23 05:11:31 PM UTC 24 |
| Finished | Aug 23 05:11:34 PM UTC 24 |
| Peak memory | 241752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=239140919 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.239140919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/39.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.312959533 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 213902424 ps |
| CPU time | 2.81 seconds |
| Started | Aug 23 05:10:53 PM UTC 24 |
| Finished | Aug 23 05:10:57 PM UTC 24 |
| Peak memory | 254728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312959533 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_aliasing.312959533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.1411359938 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 567757574 ps |
| CPU time | 4.89 seconds |
| Started | Aug 23 05:10:53 PM UTC 24 |
| Finished | Aug 23 05:10:59 PM UTC 24 |
| Peak memory | 252900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411359938 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_bash.1411359938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.3925939473 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 149000378 ps |
| CPU time | 1.73 seconds |
| Started | Aug 23 05:10:52 PM UTC 24 |
| Finished | Aug 23 05:10:55 PM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925939473 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_reset.3925939473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.219422566 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 207021697 ps |
| CPU time | 2.57 seconds |
| Started | Aug 23 05:10:54 PM UTC 24 |
| Finished | Aug 23 05:10:58 PM UTC 24 |
| Peak memory | 258824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=219422566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr _mem_rw_with_rand_reset.219422566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.940876993 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 90524313 ps |
| CPU time | 1.49 seconds |
| Started | Aug 23 05:10:52 PM UTC 24 |
| Finished | Aug 23 05:10:55 PM UTC 24 |
| Peak memory | 251876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940876993 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.940876993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.3386090988 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 76812740 ps |
| CPU time | 1.27 seconds |
| Started | Aug 23 05:10:52 PM UTC 24 |
| Finished | Aug 23 05:10:54 PM UTC 24 |
| Peak memory | 241172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386090988 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.3386090988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.3748704008 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 549903174 ps |
| CPU time | 1.45 seconds |
| Started | Aug 23 05:10:52 PM UTC 24 |
| Finished | Aug 23 05:10:54 PM UTC 24 |
| Peak memory | 240272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748704008 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_partial_access.3748704008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.159729012 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 72498405 ps |
| CPU time | 1.19 seconds |
| Started | Aug 23 05:10:52 PM UTC 24 |
| Finished | Aug 23 05:10:54 PM UTC 24 |
| Peak memory | 241676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159729012 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.159729012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.1938823159 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 68522773 ps |
| CPU time | 2.01 seconds |
| Started | Aug 23 05:10:54 PM UTC 24 |
| Finished | Aug 23 05:10:57 PM UTC 24 |
| Peak memory | 252836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938823159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_same_csr_outstanding.1938823159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.1576414362 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 168959836 ps |
| CPU time | 2.91 seconds |
| Started | Aug 23 05:10:52 PM UTC 24 |
| Finished | Aug 23 05:10:56 PM UTC 24 |
| Peak memory | 259044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576414362 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.1576414362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.3035592844 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 596498728 ps |
| CPU time | 8.64 seconds |
| Started | Aug 23 05:10:52 PM UTC 24 |
| Finished | Aug 23 05:11:02 PM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035592844 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_intg_err.3035592844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.3323149935 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 145317555 ps |
| CPU time | 1.38 seconds |
| Started | Aug 23 05:11:31 PM UTC 24 |
| Finished | Aug 23 05:11:34 PM UTC 24 |
| Peak memory | 241192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323149935 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.3323149935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/40.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.3008501397 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 584264068 ps |
| CPU time | 1.33 seconds |
| Started | Aug 23 05:11:31 PM UTC 24 |
| Finished | Aug 23 05:11:34 PM UTC 24 |
| Peak memory | 241200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008501397 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.3008501397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/41.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.3673120943 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 117656785 ps |
| CPU time | 1.21 seconds |
| Started | Aug 23 05:11:31 PM UTC 24 |
| Finished | Aug 23 05:11:34 PM UTC 24 |
| Peak memory | 241344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673120943 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.3673120943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/42.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.1355969251 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 130408818 ps |
| CPU time | 1.29 seconds |
| Started | Aug 23 05:11:32 PM UTC 24 |
| Finished | Aug 23 05:11:35 PM UTC 24 |
| Peak memory | 240032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355969251 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.1355969251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/43.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.2293119066 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 43702998 ps |
| CPU time | 1.26 seconds |
| Started | Aug 23 05:11:32 PM UTC 24 |
| Finished | Aug 23 05:11:35 PM UTC 24 |
| Peak memory | 241700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293119066 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.2293119066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/44.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.4157422142 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 74040686 ps |
| CPU time | 1.25 seconds |
| Started | Aug 23 05:11:32 PM UTC 24 |
| Finished | Aug 23 05:11:35 PM UTC 24 |
| Peak memory | 241760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157422142 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.4157422142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/45.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.3580081271 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 39204820 ps |
| CPU time | 1.23 seconds |
| Started | Aug 23 05:11:32 PM UTC 24 |
| Finished | Aug 23 05:11:35 PM UTC 24 |
| Peak memory | 241192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580081271 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.3580081271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/46.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.715008250 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 39445473 ps |
| CPU time | 1.21 seconds |
| Started | Aug 23 05:11:34 PM UTC 24 |
| Finished | Aug 23 05:11:36 PM UTC 24 |
| Peak memory | 241344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715008250 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.715008250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/47.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.3595994151 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 37639223 ps |
| CPU time | 1.23 seconds |
| Started | Aug 23 05:11:34 PM UTC 24 |
| Finished | Aug 23 05:11:36 PM UTC 24 |
| Peak memory | 241200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595994151 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.3595994151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/48.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.1983917276 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 60824755 ps |
| CPU time | 1.25 seconds |
| Started | Aug 23 05:11:34 PM UTC 24 |
| Finished | Aug 23 05:11:36 PM UTC 24 |
| Peak memory | 241140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983917276 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.1983917276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/49.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.1374189093 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 1694407370 ps |
| CPU time | 3.45 seconds |
| Started | Aug 23 05:10:56 PM UTC 24 |
| Finished | Aug 23 05:11:00 PM UTC 24 |
| Peak memory | 258972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1374189093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_cs r_mem_rw_with_rand_reset.1374189093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.3188278603 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 42773880 ps |
| CPU time | 1.43 seconds |
| Started | Aug 23 05:10:55 PM UTC 24 |
| Finished | Aug 23 05:10:58 PM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188278603 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.3188278603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.3518916205 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 572407615 ps |
| CPU time | 1.85 seconds |
| Started | Aug 23 05:10:55 PM UTC 24 |
| Finished | Aug 23 05:10:58 PM UTC 24 |
| Peak memory | 241468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518916205 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.3518916205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.1238613789 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 107446025 ps |
| CPU time | 2.19 seconds |
| Started | Aug 23 05:10:55 PM UTC 24 |
| Finished | Aug 23 05:10:59 PM UTC 24 |
| Peak memory | 252764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238613789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_same_csr_outstanding.1238613789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.2170193171 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 81858212 ps |
| CPU time | 4.65 seconds |
| Started | Aug 23 05:10:54 PM UTC 24 |
| Finished | Aug 23 05:11:00 PM UTC 24 |
| Peak memory | 258948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170193171 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.2170193171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2141044047 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 2541069245 ps |
| CPU time | 16.8 seconds |
| Started | Aug 23 05:10:55 PM UTC 24 |
| Finished | Aug 23 05:11:13 PM UTC 24 |
| Peak memory | 256860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141044047 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_intg_err.2141044047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2453044456 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 122901231 ps |
| CPU time | 1.93 seconds |
| Started | Aug 23 05:10:59 PM UTC 24 |
| Finished | Aug 23 05:11:02 PM UTC 24 |
| Peak memory | 258032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2453044456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_cs r_mem_rw_with_rand_reset.2453044456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.1655743767 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 638197862 ps |
| CPU time | 1.94 seconds |
| Started | Aug 23 05:10:59 PM UTC 24 |
| Finished | Aug 23 05:11:02 PM UTC 24 |
| Peak memory | 254084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655743767 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.1655743767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.951804905 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 557543373 ps |
| CPU time | 1.25 seconds |
| Started | Aug 23 05:10:58 PM UTC 24 |
| Finished | Aug 23 05:11:00 PM UTC 24 |
| Peak memory | 241752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951804905 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.951804905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.3429439680 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 1027266308 ps |
| CPU time | 2.14 seconds |
| Started | Aug 23 05:10:59 PM UTC 24 |
| Finished | Aug 23 05:11:02 PM UTC 24 |
| Peak memory | 252908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429439680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_same_csr_outstanding.3429439680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.2606859069 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 308168966 ps |
| CPU time | 2.89 seconds |
| Started | Aug 23 05:10:57 PM UTC 24 |
| Finished | Aug 23 05:11:00 PM UTC 24 |
| Peak memory | 258972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606859069 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.2606859069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.914762478 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 83449316 ps |
| CPU time | 2.11 seconds |
| Started | Aug 23 05:11:01 PM UTC 24 |
| Finished | Aug 23 05:11:04 PM UTC 24 |
| Peak memory | 258212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=914762478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr _mem_rw_with_rand_reset.914762478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.795718375 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 40703511 ps |
| CPU time | 1.3 seconds |
| Started | Aug 23 05:11:00 PM UTC 24 |
| Finished | Aug 23 05:11:02 PM UTC 24 |
| Peak memory | 252024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795718375 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.795718375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.1233733645 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 40472961 ps |
| CPU time | 1.26 seconds |
| Started | Aug 23 05:11:00 PM UTC 24 |
| Finished | Aug 23 05:11:02 PM UTC 24 |
| Peak memory | 241752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233733645 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.1233733645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1558101484 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 1129609299 ps |
| CPU time | 2.19 seconds |
| Started | Aug 23 05:11:01 PM UTC 24 |
| Finished | Aug 23 05:11:04 PM UTC 24 |
| Peak memory | 252068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558101484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_same_csr_outstanding.1558101484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.3898036775 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 531490800 ps |
| CPU time | 4.86 seconds |
| Started | Aug 23 05:10:59 PM UTC 24 |
| Finished | Aug 23 05:11:05 PM UTC 24 |
| Peak memory | 259084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898036775 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.3898036775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.2097456268 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 871978197 ps |
| CPU time | 9.06 seconds |
| Started | Aug 23 05:10:59 PM UTC 24 |
| Finished | Aug 23 05:11:09 PM UTC 24 |
| Peak memory | 256728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097456268 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_intg_err.2097456268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.1832438706 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 84447157 ps |
| CPU time | 1.89 seconds |
| Started | Aug 23 05:11:02 PM UTC 24 |
| Finished | Aug 23 05:11:05 PM UTC 24 |
| Peak memory | 255684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1832438706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_cs r_mem_rw_with_rand_reset.1832438706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.3280173145 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 686529875 ps |
| CPU time | 1.68 seconds |
| Started | Aug 23 05:11:02 PM UTC 24 |
| Finished | Aug 23 05:11:05 PM UTC 24 |
| Peak memory | 251848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280173145 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.3280173145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.3124457150 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 139637611 ps |
| CPU time | 1.25 seconds |
| Started | Aug 23 05:11:01 PM UTC 24 |
| Finished | Aug 23 05:11:04 PM UTC 24 |
| Peak memory | 241132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124457150 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.3124457150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.7571777 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 72382478 ps |
| CPU time | 2 seconds |
| Started | Aug 23 05:11:02 PM UTC 24 |
| Finished | Aug 23 05:11:05 PM UTC 24 |
| Peak memory | 251620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7571777 -assert nopostproc +U VM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_same_csr_outstanding.7571777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.33489342 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 246807680 ps |
| CPU time | 3.69 seconds |
| Started | Aug 23 05:11:01 PM UTC 24 |
| Finished | Aug 23 05:11:06 PM UTC 24 |
| Peak memory | 259084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33489342 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.33489342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.3561290735 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 1492797818 ps |
| CPU time | 9.37 seconds |
| Started | Aug 23 05:11:01 PM UTC 24 |
| Finished | Aug 23 05:11:12 PM UTC 24 |
| Peak memory | 256804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561290735 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_intg_err.3561290735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.2362027805 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 169859042 ps |
| CPU time | 1.84 seconds |
| Started | Aug 23 05:11:06 PM UTC 24 |
| Finished | Aug 23 05:11:09 PM UTC 24 |
| Peak memory | 258108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2362027805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_cs r_mem_rw_with_rand_reset.2362027805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.1362155649 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 37447359 ps |
| CPU time | 1.32 seconds |
| Started | Aug 23 05:11:04 PM UTC 24 |
| Finished | Aug 23 05:11:06 PM UTC 24 |
| Peak memory | 252104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362155649 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.1362155649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.855160601 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 39729633 ps |
| CPU time | 1.22 seconds |
| Started | Aug 23 05:11:04 PM UTC 24 |
| Finished | Aug 23 05:11:06 PM UTC 24 |
| Peak memory | 241464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855160601 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.855160601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.230229131 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 86625950 ps |
| CPU time | 1.9 seconds |
| Started | Aug 23 05:11:06 PM UTC 24 |
| Finished | Aug 23 05:11:09 PM UTC 24 |
| Peak memory | 251584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230229131 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_same_csr_outstanding.230229131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.3126149145 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 873627664 ps |
| CPU time | 3.04 seconds |
| Started | Aug 23 05:11:02 PM UTC 24 |
| Finished | Aug 23 05:11:06 PM UTC 24 |
| Peak memory | 258964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126149145 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.3126149145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.3626081507 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 5093647031 ps |
| CPU time | 18.16 seconds |
| Started | Aug 23 05:11:04 PM UTC 24 |
| Finished | Aug 23 05:11:23 PM UTC 24 |
| Peak memory | 257052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626081507 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_intg_err.3626081507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_errs.3190773904 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 758630135 ps |
| CPU time | 17.06 seconds |
| Started | Aug 23 05:30:44 PM UTC 24 |
| Finished | Aug 23 05:31:02 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190773904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.3190773904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_low_freq_read.89876447 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 5947223777 ps |
| CPU time | 10.42 seconds |
| Started | Aug 23 05:30:41 PM UTC 24 |
| Finished | Aug 23 05:30:52 PM UTC 24 |
| Peak memory | 251264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89876447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.89876447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_macro_errs.445115319 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 263820998 ps |
| CPU time | 3.85 seconds |
| Started | Aug 23 05:30:44 PM UTC 24 |
| Finished | Aug 23 05:30:49 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445115319 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.445115319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_key_req.1458644272 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 6318509463 ps |
| CPU time | 14.22 seconds |
| Started | Aug 23 05:30:45 PM UTC 24 |
| Finished | Aug 23 05:31:00 PM UTC 24 |
| Peak memory | 253436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458644272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.1458644272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_partition_walk.2627283746 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 606031694 ps |
| CPU time | 14.8 seconds |
| Started | Aug 23 05:30:40 PM UTC 24 |
| Finished | Aug 23 05:30:56 PM UTC 24 |
| Peak memory | 248536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627283746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.2627283746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_regwen.1873360970 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 210340995 ps |
| CPU time | 5.41 seconds |
| Started | Aug 23 05:30:45 PM UTC 24 |
| Finished | Aug 23 05:30:52 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873360970 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.1873360970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_sec_cm.2202292502 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10454579042 ps |
| CPU time | 159.99 seconds |
| Started | Aug 23 05:30:47 PM UTC 24 |
| Finished | Aug 23 05:33:30 PM UTC 24 |
| Peak memory | 298124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202292502 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.2202292502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_smoke.2475424448 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 2584363508 ps |
| CPU time | 4.9 seconds |
| Started | Aug 23 05:30:40 PM UTC 24 |
| Finished | Aug 23 05:30:46 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475424448 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.2475424448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.617310002 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 10622101813 ps |
| CPU time | 107.86 seconds |
| Started | Aug 23 05:30:46 PM UTC 24 |
| Finished | Aug 23 05:32:36 PM UTC 24 |
| Peak memory | 257652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=617310002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.617310002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_test_access.1120300939 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 787271730 ps |
| CPU time | 9.95 seconds |
| Started | Aug 23 05:30:45 PM UTC 24 |
| Finished | Aug 23 05:30:56 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120300939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.1120300939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_alert_test.2307155367 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 134836181 ps |
| CPU time | 1.53 seconds |
| Started | Aug 23 05:31:00 PM UTC 24 |
| Finished | Aug 23 05:31:02 PM UTC 24 |
| Peak memory | 251120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307155367 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.2307155367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_background_chks.2280478397 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 445722299 ps |
| CPU time | 11.44 seconds |
| Started | Aug 23 05:30:50 PM UTC 24 |
| Finished | Aug 23 05:31:02 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280478397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.2280478397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_check_fail.2011023580 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 603667614 ps |
| CPU time | 7.9 seconds |
| Started | Aug 23 05:30:53 PM UTC 24 |
| Finished | Aug 23 05:31:02 PM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011023580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.2011023580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_errs.1664524904 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 415552422 ps |
| CPU time | 19.43 seconds |
| Started | Aug 23 05:30:53 PM UTC 24 |
| Finished | Aug 23 05:31:14 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664524904 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.1664524904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_init_fail.153252039 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 2410453678 ps |
| CPU time | 5.37 seconds |
| Started | Aug 23 05:30:49 PM UTC 24 |
| Finished | Aug 23 05:30:55 PM UTC 24 |
| Peak memory | 251264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153252039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.153252039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_macro_errs.973384455 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 521876784 ps |
| CPU time | 10.46 seconds |
| Started | Aug 23 05:30:55 PM UTC 24 |
| Finished | Aug 23 05:31:07 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973384455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.973384455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_key_req.3391065878 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 9212344588 ps |
| CPU time | 13.78 seconds |
| Started | Aug 23 05:30:56 PM UTC 24 |
| Finished | Aug 23 05:31:11 PM UTC 24 |
| Peak memory | 253500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391065878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.3391065878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_esc.2547493527 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 300149510 ps |
| CPU time | 3.2 seconds |
| Started | Aug 23 05:30:53 PM UTC 24 |
| Finished | Aug 23 05:30:57 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547493527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.2547493527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_regwen.3533763870 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 141079816 ps |
| CPU time | 3.19 seconds |
| Started | Aug 23 05:30:56 PM UTC 24 |
| Finished | Aug 23 05:31:01 PM UTC 24 |
| Peak memory | 257360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533763870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.3533763870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/1.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_alert_test.1803060547 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 130184497 ps |
| CPU time | 1.56 seconds |
| Started | Aug 23 05:33:11 PM UTC 24 |
| Finished | Aug 23 05:33:14 PM UTC 24 |
| Peak memory | 251120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803060547 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.1803060547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_errs.1274968290 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 1135064199 ps |
| CPU time | 8.41 seconds |
| Started | Aug 23 05:33:03 PM UTC 24 |
| Finished | Aug 23 05:33:13 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274968290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.1274968290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_lock.1282360298 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 5614554087 ps |
| CPU time | 26.19 seconds |
| Started | Aug 23 05:33:03 PM UTC 24 |
| Finished | Aug 23 05:33:30 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282360298 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.1282360298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_init_fail.408946354 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 521911992 ps |
| CPU time | 2.98 seconds |
| Started | Aug 23 05:32:59 PM UTC 24 |
| Finished | Aug 23 05:33:03 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408946354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.408946354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_macro_errs.2751850249 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 917865570 ps |
| CPU time | 8.34 seconds |
| Started | Aug 23 05:33:04 PM UTC 24 |
| Finished | Aug 23 05:33:14 PM UTC 24 |
| Peak memory | 253464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751850249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.2751850249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_key_req.2820115155 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 254454846 ps |
| CPU time | 4.93 seconds |
| Started | Aug 23 05:33:07 PM UTC 24 |
| Finished | Aug 23 05:33:13 PM UTC 24 |
| Peak memory | 253340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820115155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.2820115155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_esc.456167156 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 473098722 ps |
| CPU time | 10.58 seconds |
| Started | Aug 23 05:33:03 PM UTC 24 |
| Finished | Aug 23 05:33:15 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456167156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.456167156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_req.3137640105 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 12401237810 ps |
| CPU time | 33.3 seconds |
| Started | Aug 23 05:33:01 PM UTC 24 |
| Finished | Aug 23 05:33:36 PM UTC 24 |
| Peak memory | 257432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137640105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.3137640105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_regwen.2941291578 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 4249973440 ps |
| CPU time | 6.29 seconds |
| Started | Aug 23 05:33:08 PM UTC 24 |
| Finished | Aug 23 05:33:15 PM UTC 24 |
| Peak memory | 251664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941291578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.2941291578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_smoke.4037799553 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 897595627 ps |
| CPU time | 9.37 seconds |
| Started | Aug 23 05:32:59 PM UTC 24 |
| Finished | Aug 23 05:33:10 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037799553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.4037799553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_test_access.3191323958 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 9214369441 ps |
| CPU time | 20.42 seconds |
| Started | Aug 23 05:33:09 PM UTC 24 |
| Finished | Aug 23 05:33:31 PM UTC 24 |
| Peak memory | 253488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191323958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.3191323958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/10.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_init_fail.224801648 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 139105924 ps |
| CPU time | 3.22 seconds |
| Started | Aug 23 05:43:42 PM UTC 24 |
| Finished | Aug 23 05:43:47 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224801648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.224801648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/100.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_parallel_lc_esc.2466192074 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 3722529650 ps |
| CPU time | 12.51 seconds |
| Started | Aug 23 05:43:42 PM UTC 24 |
| Finished | Aug 23 05:43:56 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466192074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.2466192074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/100.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_init_fail.2837669075 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 192594504 ps |
| CPU time | 3.08 seconds |
| Started | Aug 23 05:43:42 PM UTC 24 |
| Finished | Aug 23 05:43:46 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837669075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.2837669075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/101.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_parallel_lc_esc.1029414171 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 890651818 ps |
| CPU time | 19.63 seconds |
| Started | Aug 23 05:43:42 PM UTC 24 |
| Finished | Aug 23 05:44:03 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029414171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.1029414171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/101.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_init_fail.1670217574 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 2295232469 ps |
| CPU time | 3.9 seconds |
| Started | Aug 23 05:43:42 PM UTC 24 |
| Finished | Aug 23 05:43:47 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670217574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.1670217574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/102.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_parallel_lc_esc.3969274571 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 1786209624 ps |
| CPU time | 24.86 seconds |
| Started | Aug 23 05:43:42 PM UTC 24 |
| Finished | Aug 23 05:44:09 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969274571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.3969274571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/102.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_init_fail.2768869646 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 493700938 ps |
| CPU time | 3.47 seconds |
| Started | Aug 23 05:43:42 PM UTC 24 |
| Finished | Aug 23 05:43:47 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768869646 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.2768869646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/103.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_parallel_lc_esc.1806961007 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 631765779 ps |
| CPU time | 3.77 seconds |
| Started | Aug 23 05:43:45 PM UTC 24 |
| Finished | Aug 23 05:43:50 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806961007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.1806961007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/103.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_init_fail.907729926 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 593557885 ps |
| CPU time | 3.02 seconds |
| Started | Aug 23 05:43:45 PM UTC 24 |
| Finished | Aug 23 05:43:49 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907729926 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.907729926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/104.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_parallel_lc_esc.1646769661 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 986248990 ps |
| CPU time | 4.54 seconds |
| Started | Aug 23 05:43:45 PM UTC 24 |
| Finished | Aug 23 05:43:50 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646769661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.1646769661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/104.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_init_fail.3348357253 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 161410662 ps |
| CPU time | 3.33 seconds |
| Started | Aug 23 05:43:45 PM UTC 24 |
| Finished | Aug 23 05:43:49 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348357253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.3348357253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/105.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_parallel_lc_esc.1929377150 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 372757293 ps |
| CPU time | 2.95 seconds |
| Started | Aug 23 05:43:45 PM UTC 24 |
| Finished | Aug 23 05:43:49 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929377150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.1929377150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/105.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_init_fail.4291215701 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 132457623 ps |
| CPU time | 2.95 seconds |
| Started | Aug 23 05:43:47 PM UTC 24 |
| Finished | Aug 23 05:43:51 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291215701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.4291215701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/106.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_parallel_lc_esc.2571185555 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 414074135 ps |
| CPU time | 8.78 seconds |
| Started | Aug 23 05:43:50 PM UTC 24 |
| Finished | Aug 23 05:44:00 PM UTC 24 |
| Peak memory | 250940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571185555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.2571185555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/106.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_init_fail.3973447711 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 100150038 ps |
| CPU time | 3.54 seconds |
| Started | Aug 23 05:43:50 PM UTC 24 |
| Finished | Aug 23 05:43:55 PM UTC 24 |
| Peak memory | 251144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973447711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.3973447711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/107.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_init_fail.3523064670 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 382834134 ps |
| CPU time | 2.74 seconds |
| Started | Aug 23 05:43:50 PM UTC 24 |
| Finished | Aug 23 05:43:54 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523064670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.3523064670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/108.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_parallel_lc_esc.2225505422 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 235883135 ps |
| CPU time | 4.41 seconds |
| Started | Aug 23 05:43:50 PM UTC 24 |
| Finished | Aug 23 05:43:56 PM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225505422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.2225505422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/108.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_init_fail.509066995 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 210474476 ps |
| CPU time | 3.71 seconds |
| Started | Aug 23 05:43:51 PM UTC 24 |
| Finished | Aug 23 05:43:55 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509066995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.509066995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/109.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_parallel_lc_esc.1961096273 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 242529747 ps |
| CPU time | 3.83 seconds |
| Started | Aug 23 05:43:51 PM UTC 24 |
| Finished | Aug 23 05:43:56 PM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961096273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.1961096273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/109.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_alert_test.603141065 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 106840133 ps |
| CPU time | 1.64 seconds |
| Started | Aug 23 05:33:25 PM UTC 24 |
| Finished | Aug 23 05:33:27 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603141065 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.603141065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_check_fail.2784970772 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 1501328065 ps |
| CPU time | 6.63 seconds |
| Started | Aug 23 05:33:16 PM UTC 24 |
| Finished | Aug 23 05:33:24 PM UTC 24 |
| Peak memory | 253616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784970772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.2784970772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_errs.2493566943 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 8693531285 ps |
| CPU time | 21.14 seconds |
| Started | Aug 23 05:33:16 PM UTC 24 |
| Finished | Aug 23 05:33:38 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493566943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.2493566943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_lock.2465573954 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 24016667793 ps |
| CPU time | 34.92 seconds |
| Started | Aug 23 05:33:15 PM UTC 24 |
| Finished | Aug 23 05:33:51 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465573954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.2465573954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_key_req.3212859891 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 313407172 ps |
| CPU time | 8.53 seconds |
| Started | Aug 23 05:33:19 PM UTC 24 |
| Finished | Aug 23 05:33:29 PM UTC 24 |
| Peak memory | 253600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212859891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.3212859891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_esc.103933533 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 591335576 ps |
| CPU time | 4.68 seconds |
| Started | Aug 23 05:33:15 PM UTC 24 |
| Finished | Aug 23 05:33:20 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103933533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.103933533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_req.1196852493 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 462224562 ps |
| CPU time | 11.08 seconds |
| Started | Aug 23 05:33:13 PM UTC 24 |
| Finished | Aug 23 05:33:26 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196852493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.1196852493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_regwen.1798641899 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 182630518 ps |
| CPU time | 2.9 seconds |
| Started | Aug 23 05:33:20 PM UTC 24 |
| Finished | Aug 23 05:33:24 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798641899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.1798641899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_smoke.2336903797 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 396150398 ps |
| CPU time | 8.07 seconds |
| Started | Aug 23 05:33:11 PM UTC 24 |
| Finished | Aug 23 05:33:20 PM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336903797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.2336903797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all.1858146222 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 22081370481 ps |
| CPU time | 237.03 seconds |
| Started | Aug 23 05:33:25 PM UTC 24 |
| Finished | Aug 23 05:37:25 PM UTC 24 |
| Peak memory | 257472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858146222 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.1858146222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_test_access.4046265321 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 5158799958 ps |
| CPU time | 7.76 seconds |
| Started | Aug 23 05:33:21 PM UTC 24 |
| Finished | Aug 23 05:33:30 PM UTC 24 |
| Peak memory | 257648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046265321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.4046265321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/11.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_init_fail.1063352466 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 249650021 ps |
| CPU time | 3.06 seconds |
| Started | Aug 23 05:43:51 PM UTC 24 |
| Finished | Aug 23 05:43:55 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063352466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.1063352466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/110.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_parallel_lc_esc.723878132 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 3452310854 ps |
| CPU time | 11.4 seconds |
| Started | Aug 23 05:43:51 PM UTC 24 |
| Finished | Aug 23 05:44:03 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723878132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.723878132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/110.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_init_fail.2739286855 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 537819740 ps |
| CPU time | 3.68 seconds |
| Started | Aug 23 05:43:52 PM UTC 24 |
| Finished | Aug 23 05:43:57 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739286855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.2739286855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/111.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_parallel_lc_esc.2251685616 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 207102015 ps |
| CPU time | 8.46 seconds |
| Started | Aug 23 05:43:52 PM UTC 24 |
| Finished | Aug 23 05:44:02 PM UTC 24 |
| Peak memory | 251396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251685616 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.2251685616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/111.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_init_fail.2202569891 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 309032450 ps |
| CPU time | 2.47 seconds |
| Started | Aug 23 05:43:52 PM UTC 24 |
| Finished | Aug 23 05:43:56 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202569891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.2202569891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/112.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_parallel_lc_esc.2209969176 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 264292588 ps |
| CPU time | 5.86 seconds |
| Started | Aug 23 05:43:54 PM UTC 24 |
| Finished | Aug 23 05:44:00 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209969176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.2209969176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/112.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_init_fail.2731780049 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 136533128 ps |
| CPU time | 4.26 seconds |
| Started | Aug 23 05:43:55 PM UTC 24 |
| Finished | Aug 23 05:44:00 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731780049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.2731780049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/113.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_parallel_lc_esc.3414994004 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 277233667 ps |
| CPU time | 6.45 seconds |
| Started | Aug 23 05:43:58 PM UTC 24 |
| Finished | Aug 23 05:44:06 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414994004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.3414994004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/113.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_parallel_lc_esc.237631937 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 2543550948 ps |
| CPU time | 24.23 seconds |
| Started | Aug 23 05:43:58 PM UTC 24 |
| Finished | Aug 23 05:44:24 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237631937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.237631937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/114.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_init_fail.409567908 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 142621871 ps |
| CPU time | 3.05 seconds |
| Started | Aug 23 05:43:58 PM UTC 24 |
| Finished | Aug 23 05:44:02 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409567908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.409567908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/115.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_parallel_lc_esc.2651208479 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 841512226 ps |
| CPU time | 6.92 seconds |
| Started | Aug 23 05:43:58 PM UTC 24 |
| Finished | Aug 23 05:44:06 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651208479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.2651208479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/115.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_init_fail.1386716088 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 228122833 ps |
| CPU time | 2.93 seconds |
| Started | Aug 23 05:43:58 PM UTC 24 |
| Finished | Aug 23 05:44:02 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386716088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.1386716088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/116.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_parallel_lc_esc.3670270104 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 731383614 ps |
| CPU time | 5.56 seconds |
| Started | Aug 23 05:43:58 PM UTC 24 |
| Finished | Aug 23 05:44:05 PM UTC 24 |
| Peak memory | 251456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670270104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.3670270104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/116.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_init_fail.1835850268 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 1659771028 ps |
| CPU time | 3.22 seconds |
| Started | Aug 23 05:43:58 PM UTC 24 |
| Finished | Aug 23 05:44:03 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835850268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.1835850268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/117.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_parallel_lc_esc.2137331521 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 320248661 ps |
| CPU time | 6.91 seconds |
| Started | Aug 23 05:43:58 PM UTC 24 |
| Finished | Aug 23 05:44:07 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137331521 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.2137331521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/117.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_init_fail.2115189208 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 138414311 ps |
| CPU time | 3.28 seconds |
| Started | Aug 23 05:44:00 PM UTC 24 |
| Finished | Aug 23 05:44:04 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115189208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.2115189208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/118.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_parallel_lc_esc.3908090171 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 527306402 ps |
| CPU time | 5.61 seconds |
| Started | Aug 23 05:44:02 PM UTC 24 |
| Finished | Aug 23 05:44:09 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908090171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.3908090171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/118.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_init_fail.3159789050 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 185428298 ps |
| CPU time | 3.13 seconds |
| Started | Aug 23 05:44:02 PM UTC 24 |
| Finished | Aug 23 05:44:06 PM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159789050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.3159789050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/119.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_parallel_lc_esc.1835941434 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 10783773271 ps |
| CPU time | 17.05 seconds |
| Started | Aug 23 05:44:02 PM UTC 24 |
| Finished | Aug 23 05:44:20 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835941434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.1835941434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/119.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_alert_test.2915027960 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 145013075 ps |
| CPU time | 1.79 seconds |
| Started | Aug 23 05:33:37 PM UTC 24 |
| Finished | Aug 23 05:33:40 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915027960 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.2915027960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_check_fail.538167748 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 3593031661 ps |
| CPU time | 20.24 seconds |
| Started | Aug 23 05:33:31 PM UTC 24 |
| Finished | Aug 23 05:33:53 PM UTC 24 |
| Peak memory | 253436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538167748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.538167748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_errs.3900333418 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1240496363 ps |
| CPU time | 13.59 seconds |
| Started | Aug 23 05:33:31 PM UTC 24 |
| Finished | Aug 23 05:33:46 PM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900333418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.3900333418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_lock.3201046282 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 863301482 ps |
| CPU time | 22.41 seconds |
| Started | Aug 23 05:33:29 PM UTC 24 |
| Finished | Aug 23 05:33:53 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201046282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.3201046282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_macro_errs.3661411955 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 423446081 ps |
| CPU time | 5.92 seconds |
| Started | Aug 23 05:33:31 PM UTC 24 |
| Finished | Aug 23 05:33:38 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3661411955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.3661411955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_key_req.3070577615 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 2034030297 ps |
| CPU time | 12.39 seconds |
| Started | Aug 23 05:33:32 PM UTC 24 |
| Finished | Aug 23 05:33:46 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070577615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.3070577615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_esc.1928016596 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 173026586 ps |
| CPU time | 4.68 seconds |
| Started | Aug 23 05:33:28 PM UTC 24 |
| Finished | Aug 23 05:33:34 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928016596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.1928016596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_req.1519420078 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 818517134 ps |
| CPU time | 10.96 seconds |
| Started | Aug 23 05:33:27 PM UTC 24 |
| Finished | Aug 23 05:33:39 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519420078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.1519420078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_regwen.1077840671 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 472080201 ps |
| CPU time | 5 seconds |
| Started | Aug 23 05:33:32 PM UTC 24 |
| Finished | Aug 23 05:33:38 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077840671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.1077840671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_smoke.3515431858 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 1393370949 ps |
| CPU time | 6.41 seconds |
| Started | Aug 23 05:33:25 PM UTC 24 |
| Finished | Aug 23 05:33:32 PM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515431858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.3515431858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all.2697672659 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 12553394106 ps |
| CPU time | 139.83 seconds |
| Started | Aug 23 05:33:34 PM UTC 24 |
| Finished | Aug 23 05:35:57 PM UTC 24 |
| Peak memory | 267736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697672659 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.2697672659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_test_access.2606484820 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2798049605 ps |
| CPU time | 14.66 seconds |
| Started | Aug 23 05:33:33 PM UTC 24 |
| Finished | Aug 23 05:33:49 PM UTC 24 |
| Peak memory | 253680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606484820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.2606484820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/12.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_init_fail.2787917313 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 272772335 ps |
| CPU time | 2.85 seconds |
| Started | Aug 23 05:44:02 PM UTC 24 |
| Finished | Aug 23 05:44:06 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787917313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.2787917313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/120.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_parallel_lc_esc.2732889603 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 3230563733 ps |
| CPU time | 19.45 seconds |
| Started | Aug 23 05:44:04 PM UTC 24 |
| Finished | Aug 23 05:44:25 PM UTC 24 |
| Peak memory | 251096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732889603 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.2732889603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/120.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_init_fail.1099498266 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 624156667 ps |
| CPU time | 3.42 seconds |
| Started | Aug 23 05:44:04 PM UTC 24 |
| Finished | Aug 23 05:44:09 PM UTC 24 |
| Peak memory | 251060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099498266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.1099498266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/121.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_parallel_lc_esc.731343869 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 280938288 ps |
| CPU time | 5.28 seconds |
| Started | Aug 23 05:44:04 PM UTC 24 |
| Finished | Aug 23 05:44:10 PM UTC 24 |
| Peak memory | 251116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731343869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.731343869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/121.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_init_fail.153195982 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 1621329777 ps |
| CPU time | 3.45 seconds |
| Started | Aug 23 05:44:04 PM UTC 24 |
| Finished | Aug 23 05:44:09 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153195982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.153195982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/122.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_parallel_lc_esc.353344232 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 391732356 ps |
| CPU time | 3.92 seconds |
| Started | Aug 23 05:44:04 PM UTC 24 |
| Finished | Aug 23 05:44:09 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353344232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.353344232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/122.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_init_fail.3578296316 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 2229930398 ps |
| CPU time | 3.65 seconds |
| Started | Aug 23 05:44:07 PM UTC 24 |
| Finished | Aug 23 05:44:12 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578296316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.3578296316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/123.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_parallel_lc_esc.3814785182 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 692778805 ps |
| CPU time | 5.03 seconds |
| Started | Aug 23 05:44:07 PM UTC 24 |
| Finished | Aug 23 05:44:13 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814785182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.3814785182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/123.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_parallel_lc_esc.3999181723 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 1859298649 ps |
| CPU time | 21.78 seconds |
| Started | Aug 23 05:44:07 PM UTC 24 |
| Finished | Aug 23 05:44:30 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999181723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.3999181723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/124.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_init_fail.2294137678 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 149668032 ps |
| CPU time | 3.26 seconds |
| Started | Aug 23 05:44:07 PM UTC 24 |
| Finished | Aug 23 05:44:11 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294137678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.2294137678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/125.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_parallel_lc_esc.3762276679 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 653596168 ps |
| CPU time | 4.5 seconds |
| Started | Aug 23 05:44:07 PM UTC 24 |
| Finished | Aug 23 05:44:13 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762276679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.3762276679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/125.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_init_fail.1653612197 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 208446000 ps |
| CPU time | 2.84 seconds |
| Started | Aug 23 05:44:07 PM UTC 24 |
| Finished | Aug 23 05:44:11 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653612197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.1653612197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/126.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_parallel_lc_esc.1388476199 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 333013141 ps |
| CPU time | 5.66 seconds |
| Started | Aug 23 05:44:09 PM UTC 24 |
| Finished | Aug 23 05:44:16 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388476199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.1388476199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/126.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_init_fail.209095673 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 2137598784 ps |
| CPU time | 4.05 seconds |
| Started | Aug 23 05:44:09 PM UTC 24 |
| Finished | Aug 23 05:44:14 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209095673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.209095673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/127.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_parallel_lc_esc.166864191 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 4757133527 ps |
| CPU time | 17.21 seconds |
| Started | Aug 23 05:44:12 PM UTC 24 |
| Finished | Aug 23 05:44:30 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166864191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.166864191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/127.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_init_fail.2706209634 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 132041513 ps |
| CPU time | 2.83 seconds |
| Started | Aug 23 05:44:12 PM UTC 24 |
| Finished | Aug 23 05:44:16 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706209634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.2706209634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/128.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_parallel_lc_esc.1019443483 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 72224364 ps |
| CPU time | 2.08 seconds |
| Started | Aug 23 05:44:12 PM UTC 24 |
| Finished | Aug 23 05:44:15 PM UTC 24 |
| Peak memory | 251096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019443483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.1019443483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/128.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_init_fail.1919969499 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 302597891 ps |
| CPU time | 3.56 seconds |
| Started | Aug 23 05:44:12 PM UTC 24 |
| Finished | Aug 23 05:44:17 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919969499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.1919969499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/129.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_parallel_lc_esc.1602945288 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 533715080 ps |
| CPU time | 6.63 seconds |
| Started | Aug 23 05:44:12 PM UTC 24 |
| Finished | Aug 23 05:44:20 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602945288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.1602945288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/129.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_alert_test.1222762622 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 89699312 ps |
| CPU time | 1.9 seconds |
| Started | Aug 23 05:33:52 PM UTC 24 |
| Finished | Aug 23 05:33:55 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222762622 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.1222762622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_check_fail.4261930811 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3182399958 ps |
| CPU time | 19.91 seconds |
| Started | Aug 23 05:33:44 PM UTC 24 |
| Finished | Aug 23 05:34:05 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261930811 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.4261930811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_errs.3519052237 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 624305398 ps |
| CPU time | 13.74 seconds |
| Started | Aug 23 05:33:44 PM UTC 24 |
| Finished | Aug 23 05:33:59 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519052237 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.3519052237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_lock.1109186817 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1739924035 ps |
| CPU time | 18.94 seconds |
| Started | Aug 23 05:33:40 PM UTC 24 |
| Finished | Aug 23 05:34:01 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109186817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.1109186817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_macro_errs.1395318273 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 747883374 ps |
| CPU time | 13.42 seconds |
| Started | Aug 23 05:33:46 PM UTC 24 |
| Finished | Aug 23 05:34:01 PM UTC 24 |
| Peak memory | 254488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395318273 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.1395318273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_key_req.2296340376 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 244644835 ps |
| CPU time | 5.21 seconds |
| Started | Aug 23 05:33:46 PM UTC 24 |
| Finished | Aug 23 05:33:53 PM UTC 24 |
| Peak memory | 251580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296340376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.2296340376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_esc.308786464 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 2309971667 ps |
| CPU time | 13.72 seconds |
| Started | Aug 23 05:33:40 PM UTC 24 |
| Finished | Aug 23 05:33:55 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308786464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.308786464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_req.2516546039 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 1295176704 ps |
| CPU time | 20.14 seconds |
| Started | Aug 23 05:33:39 PM UTC 24 |
| Finished | Aug 23 05:34:01 PM UTC 24 |
| Peak memory | 257372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516546039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.2516546039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_regwen.193221980 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 273483506 ps |
| CPU time | 3.4 seconds |
| Started | Aug 23 05:33:47 PM UTC 24 |
| Finished | Aug 23 05:33:52 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193221980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.193221980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_smoke.1679011342 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 513094255 ps |
| CPU time | 4.89 seconds |
| Started | Aug 23 05:33:39 PM UTC 24 |
| Finished | Aug 23 05:33:45 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679011342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.1679011342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_test_access.3625389930 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 2106038047 ps |
| CPU time | 19.39 seconds |
| Started | Aug 23 05:33:47 PM UTC 24 |
| Finished | Aug 23 05:34:08 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625389930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.3625389930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/13.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_init_fail.188463826 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 364830617 ps |
| CPU time | 3.58 seconds |
| Started | Aug 23 05:44:12 PM UTC 24 |
| Finished | Aug 23 05:44:17 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188463826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.188463826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/130.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_parallel_lc_esc.2176030635 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 183099691 ps |
| CPU time | 4.07 seconds |
| Started | Aug 23 05:44:12 PM UTC 24 |
| Finished | Aug 23 05:44:17 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176030635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.2176030635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/130.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_init_fail.1544305382 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 737889871 ps |
| CPU time | 4.11 seconds |
| Started | Aug 23 05:44:12 PM UTC 24 |
| Finished | Aug 23 05:44:17 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544305382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.1544305382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/131.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_parallel_lc_esc.1634960339 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 752825685 ps |
| CPU time | 10.17 seconds |
| Started | Aug 23 05:44:14 PM UTC 24 |
| Finished | Aug 23 05:44:26 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634960339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.1634960339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/131.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_init_fail.166586024 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 123314842 ps |
| CPU time | 4.04 seconds |
| Started | Aug 23 05:44:14 PM UTC 24 |
| Finished | Aug 23 05:44:19 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166586024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.166586024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/132.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_parallel_lc_esc.1394115474 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 1296291335 ps |
| CPU time | 6.27 seconds |
| Started | Aug 23 05:44:14 PM UTC 24 |
| Finished | Aug 23 05:44:22 PM UTC 24 |
| Peak memory | 250880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394115474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.1394115474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/132.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_init_fail.2775639073 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 150216957 ps |
| CPU time | 3.41 seconds |
| Started | Aug 23 05:44:14 PM UTC 24 |
| Finished | Aug 23 05:44:19 PM UTC 24 |
| Peak memory | 251052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775639073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.2775639073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/133.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_parallel_lc_esc.347461444 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 145472112 ps |
| CPU time | 5.33 seconds |
| Started | Aug 23 05:44:15 PM UTC 24 |
| Finished | Aug 23 05:44:22 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347461444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.347461444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/133.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_init_fail.3776319976 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 434853841 ps |
| CPU time | 2.87 seconds |
| Started | Aug 23 05:44:16 PM UTC 24 |
| Finished | Aug 23 05:44:19 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776319976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.3776319976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/134.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_parallel_lc_esc.811941026 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 418625299 ps |
| CPU time | 3.31 seconds |
| Started | Aug 23 05:44:16 PM UTC 24 |
| Finished | Aug 23 05:44:20 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811941026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.811941026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/134.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_init_fail.1806291569 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 148375408 ps |
| CPU time | 2.96 seconds |
| Started | Aug 23 05:44:17 PM UTC 24 |
| Finished | Aug 23 05:44:21 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806291569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.1806291569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/135.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_parallel_lc_esc.2849652917 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 1861905072 ps |
| CPU time | 5.26 seconds |
| Started | Aug 23 05:44:17 PM UTC 24 |
| Finished | Aug 23 05:44:24 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849652917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.2849652917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/135.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_init_fail.2521978079 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 343013117 ps |
| CPU time | 3.98 seconds |
| Started | Aug 23 05:44:17 PM UTC 24 |
| Finished | Aug 23 05:44:23 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521978079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.2521978079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/136.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_parallel_lc_esc.2673290833 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 596144020 ps |
| CPU time | 6.25 seconds |
| Started | Aug 23 05:44:17 PM UTC 24 |
| Finished | Aug 23 05:44:25 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673290833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.2673290833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/136.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_init_fail.1328755774 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 206039224 ps |
| CPU time | 2.99 seconds |
| Started | Aug 23 05:44:19 PM UTC 24 |
| Finished | Aug 23 05:44:23 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328755774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.1328755774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/137.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_parallel_lc_esc.1669893542 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 527694087 ps |
| CPU time | 11.07 seconds |
| Started | Aug 23 05:44:19 PM UTC 24 |
| Finished | Aug 23 05:44:31 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669893542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.1669893542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/137.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_init_fail.402370510 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 163929002 ps |
| CPU time | 3.43 seconds |
| Started | Aug 23 05:44:21 PM UTC 24 |
| Finished | Aug 23 05:44:25 PM UTC 24 |
| Peak memory | 251092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402370510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.402370510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/138.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_parallel_lc_esc.2810445225 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 133250626 ps |
| CPU time | 3.22 seconds |
| Started | Aug 23 05:44:21 PM UTC 24 |
| Finished | Aug 23 05:44:25 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810445225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.2810445225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/138.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_init_fail.380084414 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 165888019 ps |
| CPU time | 2.8 seconds |
| Started | Aug 23 05:44:21 PM UTC 24 |
| Finished | Aug 23 05:44:25 PM UTC 24 |
| Peak memory | 251064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380084414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.380084414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/139.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_parallel_lc_esc.547244863 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 525959341 ps |
| CPU time | 7.65 seconds |
| Started | Aug 23 05:44:21 PM UTC 24 |
| Finished | Aug 23 05:44:30 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547244863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.547244863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/139.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_alert_test.2551844987 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 749365238 ps |
| CPU time | 2.1 seconds |
| Started | Aug 23 05:34:03 PM UTC 24 |
| Finished | Aug 23 05:34:06 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551844987 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.2551844987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_check_fail.535196459 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 8384133243 ps |
| CPU time | 14.34 seconds |
| Started | Aug 23 05:33:56 PM UTC 24 |
| Finished | Aug 23 05:34:12 PM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535196459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.535196459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_errs.3900262147 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 755424629 ps |
| CPU time | 16.33 seconds |
| Started | Aug 23 05:33:54 PM UTC 24 |
| Finished | Aug 23 05:34:12 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900262147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.3900262147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_lock.1582784324 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 32386803757 ps |
| CPU time | 65.49 seconds |
| Started | Aug 23 05:33:54 PM UTC 24 |
| Finished | Aug 23 05:35:01 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582784324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.1582784324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_init_fail.1847025211 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 561460303 ps |
| CPU time | 3.73 seconds |
| Started | Aug 23 05:33:54 PM UTC 24 |
| Finished | Aug 23 05:33:59 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847025211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.1847025211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_macro_errs.297191289 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 3854787585 ps |
| CPU time | 6.84 seconds |
| Started | Aug 23 05:33:56 PM UTC 24 |
| Finished | Aug 23 05:34:05 PM UTC 24 |
| Peak memory | 253536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297191289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.297191289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_key_req.3390503465 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 915758135 ps |
| CPU time | 16.04 seconds |
| Started | Aug 23 05:34:00 PM UTC 24 |
| Finished | Aug 23 05:34:17 PM UTC 24 |
| Peak memory | 253348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390503465 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.3390503465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_esc.2606328767 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 363370095 ps |
| CPU time | 3.52 seconds |
| Started | Aug 23 05:33:54 PM UTC 24 |
| Finished | Aug 23 05:33:59 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606328767 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.2606328767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_req.740024313 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 558304764 ps |
| CPU time | 13.63 seconds |
| Started | Aug 23 05:33:54 PM UTC 24 |
| Finished | Aug 23 05:34:09 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740024313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.740024313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_regwen.734113130 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 4864469725 ps |
| CPU time | 11.27 seconds |
| Started | Aug 23 05:34:00 PM UTC 24 |
| Finished | Aug 23 05:34:12 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734113130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.734113130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_smoke.2181591048 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 515334530 ps |
| CPU time | 6.75 seconds |
| Started | Aug 23 05:33:52 PM UTC 24 |
| Finished | Aug 23 05:34:00 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181591048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.2181591048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all.2829944309 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 5748828163 ps |
| CPU time | 37.51 seconds |
| Started | Aug 23 05:34:03 PM UTC 24 |
| Finished | Aug 23 05:34:42 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829944309 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.2829944309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_test_access.838555582 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 5833764427 ps |
| CPU time | 11.26 seconds |
| Started | Aug 23 05:34:00 PM UTC 24 |
| Finished | Aug 23 05:34:12 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838555582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.838555582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/14.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_init_fail.2046534147 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 565995234 ps |
| CPU time | 4.61 seconds |
| Started | Aug 23 05:44:24 PM UTC 24 |
| Finished | Aug 23 05:44:30 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046534147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.2046534147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/140.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_parallel_lc_esc.1119904663 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 541874856 ps |
| CPU time | 13.19 seconds |
| Started | Aug 23 05:44:24 PM UTC 24 |
| Finished | Aug 23 05:44:38 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119904663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.1119904663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/140.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_init_fail.2636085438 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 409072443 ps |
| CPU time | 3.17 seconds |
| Started | Aug 23 05:44:24 PM UTC 24 |
| Finished | Aug 23 05:44:28 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636085438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.2636085438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/141.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_parallel_lc_esc.1248831311 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 429264069 ps |
| CPU time | 11.86 seconds |
| Started | Aug 23 05:44:24 PM UTC 24 |
| Finished | Aug 23 05:44:37 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248831311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.1248831311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/141.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_init_fail.3480285507 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 308643775 ps |
| CPU time | 3.87 seconds |
| Started | Aug 23 05:44:24 PM UTC 24 |
| Finished | Aug 23 05:44:29 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480285507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.3480285507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/142.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_parallel_lc_esc.2330204700 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 271440850 ps |
| CPU time | 5.39 seconds |
| Started | Aug 23 05:44:24 PM UTC 24 |
| Finished | Aug 23 05:44:31 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330204700 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.2330204700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/142.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_init_fail.2009754622 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 194886661 ps |
| CPU time | 3.4 seconds |
| Started | Aug 23 05:44:24 PM UTC 24 |
| Finished | Aug 23 05:44:29 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009754622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.2009754622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/143.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_parallel_lc_esc.914795439 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 720031286 ps |
| CPU time | 5.29 seconds |
| Started | Aug 23 05:44:24 PM UTC 24 |
| Finished | Aug 23 05:44:31 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914795439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.914795439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/143.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_init_fail.802752241 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 1832033187 ps |
| CPU time | 5.41 seconds |
| Started | Aug 23 05:44:28 PM UTC 24 |
| Finished | Aug 23 05:44:34 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802752241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.802752241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/144.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_parallel_lc_esc.3993438037 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 747778918 ps |
| CPU time | 7.35 seconds |
| Started | Aug 23 05:44:28 PM UTC 24 |
| Finished | Aug 23 05:44:36 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993438037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.3993438037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/144.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_init_fail.3633812893 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 371754934 ps |
| CPU time | 3.4 seconds |
| Started | Aug 23 05:44:28 PM UTC 24 |
| Finished | Aug 23 05:44:32 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633812893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.3633812893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/145.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_parallel_lc_esc.784900353 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 577067602 ps |
| CPU time | 4.06 seconds |
| Started | Aug 23 05:44:28 PM UTC 24 |
| Finished | Aug 23 05:44:33 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784900353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.784900353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/145.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_init_fail.4106267947 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 420401549 ps |
| CPU time | 3.83 seconds |
| Started | Aug 23 05:44:28 PM UTC 24 |
| Finished | Aug 23 05:44:33 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106267947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.4106267947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/146.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_parallel_lc_esc.552683913 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 693490568 ps |
| CPU time | 14.53 seconds |
| Started | Aug 23 05:44:28 PM UTC 24 |
| Finished | Aug 23 05:44:44 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552683913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.552683913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/146.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_parallel_lc_esc.4058146685 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 869397202 ps |
| CPU time | 9.72 seconds |
| Started | Aug 23 05:44:28 PM UTC 24 |
| Finished | Aug 23 05:44:39 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058146685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.4058146685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/147.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_init_fail.2857640877 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 188172967 ps |
| CPU time | 3.76 seconds |
| Started | Aug 23 05:44:28 PM UTC 24 |
| Finished | Aug 23 05:44:33 PM UTC 24 |
| Peak memory | 251584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857640877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.2857640877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/148.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_parallel_lc_esc.1341585394 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 134153651 ps |
| CPU time | 3.51 seconds |
| Started | Aug 23 05:44:33 PM UTC 24 |
| Finished | Aug 23 05:44:37 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341585394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.1341585394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/148.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_init_fail.764704983 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 357390556 ps |
| CPU time | 3.26 seconds |
| Started | Aug 23 05:44:33 PM UTC 24 |
| Finished | Aug 23 05:44:37 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764704983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.764704983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/149.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_parallel_lc_esc.545219916 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 528959931 ps |
| CPU time | 4.33 seconds |
| Started | Aug 23 05:44:33 PM UTC 24 |
| Finished | Aug 23 05:44:38 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545219916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.545219916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/149.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_alert_test.2291047404 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 150841396 ps |
| CPU time | 1.65 seconds |
| Started | Aug 23 05:34:14 PM UTC 24 |
| Finished | Aug 23 05:34:17 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291047404 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.2291047404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_check_fail.1128291529 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 2357284915 ps |
| CPU time | 29.54 seconds |
| Started | Aug 23 05:34:10 PM UTC 24 |
| Finished | Aug 23 05:34:41 PM UTC 24 |
| Peak memory | 257520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128291529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.1128291529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_errs.2230124077 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 16437831691 ps |
| CPU time | 29.89 seconds |
| Started | Aug 23 05:34:10 PM UTC 24 |
| Finished | Aug 23 05:34:41 PM UTC 24 |
| Peak memory | 257396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230124077 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.2230124077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_lock.2067201670 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 830528836 ps |
| CPU time | 14.98 seconds |
| Started | Aug 23 05:34:07 PM UTC 24 |
| Finished | Aug 23 05:34:23 PM UTC 24 |
| Peak memory | 253340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067201670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.2067201670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_macro_errs.3041624541 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 1017704511 ps |
| CPU time | 12.5 seconds |
| Started | Aug 23 05:34:11 PM UTC 24 |
| Finished | Aug 23 05:34:25 PM UTC 24 |
| Peak memory | 253420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041624541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.3041624541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_key_req.3019013973 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 2659435717 ps |
| CPU time | 12.66 seconds |
| Started | Aug 23 05:34:12 PM UTC 24 |
| Finished | Aug 23 05:34:26 PM UTC 24 |
| Peak memory | 257568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019013973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.3019013973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_esc.3312667322 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 166031231 ps |
| CPU time | 3.55 seconds |
| Started | Aug 23 05:34:06 PM UTC 24 |
| Finished | Aug 23 05:34:11 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312667322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.3312667322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_req.381487639 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1009455482 ps |
| CPU time | 16.2 seconds |
| Started | Aug 23 05:34:06 PM UTC 24 |
| Finished | Aug 23 05:34:24 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381487639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.381487639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_regwen.2047541382 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 1157835155 ps |
| CPU time | 8.45 seconds |
| Started | Aug 23 05:34:14 PM UTC 24 |
| Finished | Aug 23 05:34:23 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047541382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.2047541382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_smoke.480334011 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 1089508278 ps |
| CPU time | 6.05 seconds |
| Started | Aug 23 05:34:03 PM UTC 24 |
| Finished | Aug 23 05:34:10 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480334011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.480334011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.2994824876 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 1119740029 ps |
| CPU time | 29.35 seconds |
| Started | Aug 23 05:34:14 PM UTC 24 |
| Finished | Aug 23 05:34:44 PM UTC 24 |
| Peak memory | 257616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2994824876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.otp_ctrl_stress_all_with_rand_reset.2994824876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_test_access.1678204792 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 6309563770 ps |
| CPU time | 33.12 seconds |
| Started | Aug 23 05:34:14 PM UTC 24 |
| Finished | Aug 23 05:34:48 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678204792 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.1678204792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/15.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_init_fail.162463664 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 146859850 ps |
| CPU time | 3.4 seconds |
| Started | Aug 23 05:44:33 PM UTC 24 |
| Finished | Aug 23 05:44:37 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162463664 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.162463664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/150.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_parallel_lc_esc.372547049 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 138167529 ps |
| CPU time | 3.24 seconds |
| Started | Aug 23 05:44:33 PM UTC 24 |
| Finished | Aug 23 05:44:37 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372547049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.372547049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/150.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_init_fail.3113593416 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 450579873 ps |
| CPU time | 3.35 seconds |
| Started | Aug 23 05:44:38 PM UTC 24 |
| Finished | Aug 23 05:44:43 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113593416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.3113593416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/151.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_parallel_lc_esc.1515145321 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 269057548 ps |
| CPU time | 5.16 seconds |
| Started | Aug 23 05:44:38 PM UTC 24 |
| Finished | Aug 23 05:44:44 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515145321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.1515145321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/151.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_init_fail.3593654314 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 370809375 ps |
| CPU time | 3.04 seconds |
| Started | Aug 23 05:44:38 PM UTC 24 |
| Finished | Aug 23 05:44:42 PM UTC 24 |
| Peak memory | 251060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593654314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.3593654314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/152.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_init_fail.3347624680 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 1531493043 ps |
| CPU time | 2.93 seconds |
| Started | Aug 23 05:44:38 PM UTC 24 |
| Finished | Aug 23 05:44:42 PM UTC 24 |
| Peak memory | 253264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347624680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.3347624680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/153.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_parallel_lc_esc.2321759889 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 684778167 ps |
| CPU time | 7.25 seconds |
| Started | Aug 23 05:44:38 PM UTC 24 |
| Finished | Aug 23 05:44:47 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2321759889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.2321759889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/153.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_init_fail.1921509613 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 301957389 ps |
| CPU time | 3.29 seconds |
| Started | Aug 23 05:44:38 PM UTC 24 |
| Finished | Aug 23 05:44:43 PM UTC 24 |
| Peak memory | 250748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921509613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.1921509613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/154.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_parallel_lc_esc.3832808692 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 3056271076 ps |
| CPU time | 9.04 seconds |
| Started | Aug 23 05:44:38 PM UTC 24 |
| Finished | Aug 23 05:44:49 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832808692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.3832808692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/154.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_init_fail.2890492660 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 173907613 ps |
| CPU time | 3.79 seconds |
| Started | Aug 23 05:44:38 PM UTC 24 |
| Finished | Aug 23 05:44:43 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890492660 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.2890492660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/155.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_parallel_lc_esc.1613096942 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 4005557587 ps |
| CPU time | 22.75 seconds |
| Started | Aug 23 05:44:38 PM UTC 24 |
| Finished | Aug 23 05:45:03 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613096942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.1613096942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/155.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_init_fail.4070690015 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 330388083 ps |
| CPU time | 3.62 seconds |
| Started | Aug 23 05:44:38 PM UTC 24 |
| Finished | Aug 23 05:44:43 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070690015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.4070690015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/156.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_parallel_lc_esc.2613526321 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 96712136 ps |
| CPU time | 2.35 seconds |
| Started | Aug 23 05:44:38 PM UTC 24 |
| Finished | Aug 23 05:44:42 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613526321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.2613526321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/156.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_init_fail.3538452662 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 227199571 ps |
| CPU time | 3.57 seconds |
| Started | Aug 23 05:44:38 PM UTC 24 |
| Finished | Aug 23 05:44:43 PM UTC 24 |
| Peak memory | 250456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538452662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.3538452662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/157.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_parallel_lc_esc.2256887601 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 13781146066 ps |
| CPU time | 22.22 seconds |
| Started | Aug 23 05:44:39 PM UTC 24 |
| Finished | Aug 23 05:45:02 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256887601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.2256887601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/157.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_init_fail.1158160043 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 658332733 ps |
| CPU time | 3.75 seconds |
| Started | Aug 23 05:44:41 PM UTC 24 |
| Finished | Aug 23 05:44:46 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158160043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.1158160043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/159.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_parallel_lc_esc.589248526 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 849749563 ps |
| CPU time | 4.6 seconds |
| Started | Aug 23 05:44:41 PM UTC 24 |
| Finished | Aug 23 05:44:47 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589248526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.589248526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/159.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_alert_test.920963250 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 80079345 ps |
| CPU time | 1.67 seconds |
| Started | Aug 23 05:34:27 PM UTC 24 |
| Finished | Aug 23 05:34:30 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920963250 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.920963250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_errs.1667633480 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 656569618 ps |
| CPU time | 15.25 seconds |
| Started | Aug 23 05:34:19 PM UTC 24 |
| Finished | Aug 23 05:34:35 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667633480 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.1667633480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_lock.3326331347 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 596550812 ps |
| CPU time | 4.67 seconds |
| Started | Aug 23 05:34:19 PM UTC 24 |
| Finished | Aug 23 05:34:24 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326331347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.3326331347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_init_fail.20523981 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 323863623 ps |
| CPU time | 3.93 seconds |
| Started | Aug 23 05:34:17 PM UTC 24 |
| Finished | Aug 23 05:34:22 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20523981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.20523981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_macro_errs.3344293342 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 2402181686 ps |
| CPU time | 5.97 seconds |
| Started | Aug 23 05:34:23 PM UTC 24 |
| Finished | Aug 23 05:34:30 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344293342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.3344293342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_key_req.1156284297 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 891935558 ps |
| CPU time | 12.44 seconds |
| Started | Aug 23 05:34:24 PM UTC 24 |
| Finished | Aug 23 05:34:38 PM UTC 24 |
| Peak memory | 253344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156284297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.1156284297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_esc.236296052 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 3009278815 ps |
| CPU time | 25.57 seconds |
| Started | Aug 23 05:34:17 PM UTC 24 |
| Finished | Aug 23 05:34:44 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236296052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.236296052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_req.1755368522 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1609904267 ps |
| CPU time | 11.77 seconds |
| Started | Aug 23 05:34:17 PM UTC 24 |
| Finished | Aug 23 05:34:30 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755368522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.1755368522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_smoke.3432378486 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2030424190 ps |
| CPU time | 4.97 seconds |
| Started | Aug 23 05:34:16 PM UTC 24 |
| Finished | Aug 23 05:34:22 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432378486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.3432378486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all.3237801022 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 12860368303 ps |
| CPU time | 165.46 seconds |
| Started | Aug 23 05:34:26 PM UTC 24 |
| Finished | Aug 23 05:37:14 PM UTC 24 |
| Peak memory | 257464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237801022 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.3237801022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.2029036087 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 5188298890 ps |
| CPU time | 128.28 seconds |
| Started | Aug 23 05:34:26 PM UTC 24 |
| Finished | Aug 23 05:36:36 PM UTC 24 |
| Peak memory | 268180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2029036087 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.otp_ctrl_stress_all_with_rand_reset.2029036087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_test_access.1746569212 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 691379983 ps |
| CPU time | 5.22 seconds |
| Started | Aug 23 05:34:25 PM UTC 24 |
| Finished | Aug 23 05:34:31 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746569212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.1746569212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/16.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_init_fail.93795865 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 97905881 ps |
| CPU time | 2.8 seconds |
| Started | Aug 23 05:44:42 PM UTC 24 |
| Finished | Aug 23 05:44:45 PM UTC 24 |
| Peak memory | 251520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93795865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.93795865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/160.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_parallel_lc_esc.2581866059 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 496859494 ps |
| CPU time | 11.8 seconds |
| Started | Aug 23 05:44:42 PM UTC 24 |
| Finished | Aug 23 05:44:55 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581866059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.2581866059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/160.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_init_fail.2075265350 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 468136569 ps |
| CPU time | 2.97 seconds |
| Started | Aug 23 05:44:42 PM UTC 24 |
| Finished | Aug 23 05:44:46 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075265350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.2075265350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/161.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_init_fail.42652847 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 2116645600 ps |
| CPU time | 5.42 seconds |
| Started | Aug 23 05:44:49 PM UTC 24 |
| Finished | Aug 23 05:44:56 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42652847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.42652847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/162.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_parallel_lc_esc.1348656239 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 285559746 ps |
| CPU time | 4.23 seconds |
| Started | Aug 23 05:44:49 PM UTC 24 |
| Finished | Aug 23 05:44:55 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348656239 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.1348656239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/162.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_init_fail.147325684 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 603742903 ps |
| CPU time | 4.02 seconds |
| Started | Aug 23 05:44:49 PM UTC 24 |
| Finished | Aug 23 05:44:54 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147325684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.147325684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/163.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_parallel_lc_esc.3911644322 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 265263836 ps |
| CPU time | 5.6 seconds |
| Started | Aug 23 05:44:49 PM UTC 24 |
| Finished | Aug 23 05:44:56 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911644322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.3911644322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/163.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_init_fail.844802561 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 478583719 ps |
| CPU time | 3.26 seconds |
| Started | Aug 23 05:44:49 PM UTC 24 |
| Finished | Aug 23 05:44:54 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844802561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.844802561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/164.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_parallel_lc_esc.3679854454 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 196830411 ps |
| CPU time | 4.61 seconds |
| Started | Aug 23 05:44:49 PM UTC 24 |
| Finished | Aug 23 05:44:55 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679854454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.3679854454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/164.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_init_fail.730040675 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 241494557 ps |
| CPU time | 2.76 seconds |
| Started | Aug 23 05:44:49 PM UTC 24 |
| Finished | Aug 23 05:44:53 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730040675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.730040675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/165.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_parallel_lc_esc.2335407225 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 441336758 ps |
| CPU time | 8.45 seconds |
| Started | Aug 23 05:44:49 PM UTC 24 |
| Finished | Aug 23 05:44:59 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335407225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.2335407225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/165.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_init_fail.1264252286 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 2176371326 ps |
| CPU time | 4.28 seconds |
| Started | Aug 23 05:44:49 PM UTC 24 |
| Finished | Aug 23 05:44:55 PM UTC 24 |
| Peak memory | 250284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264252286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.1264252286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/166.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_parallel_lc_esc.166416492 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 7229663307 ps |
| CPU time | 9.88 seconds |
| Started | Aug 23 05:44:49 PM UTC 24 |
| Finished | Aug 23 05:45:01 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166416492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.166416492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/166.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_init_fail.140201031 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 747879799 ps |
| CPU time | 4.24 seconds |
| Started | Aug 23 05:44:49 PM UTC 24 |
| Finished | Aug 23 05:44:55 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140201031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.140201031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/167.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_parallel_lc_esc.680608795 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 212442306 ps |
| CPU time | 3.94 seconds |
| Started | Aug 23 05:44:49 PM UTC 24 |
| Finished | Aug 23 05:44:55 PM UTC 24 |
| Peak memory | 250624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680608795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.680608795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/167.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_init_fail.1942031841 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 358607645 ps |
| CPU time | 3.65 seconds |
| Started | Aug 23 05:44:49 PM UTC 24 |
| Finished | Aug 23 05:44:54 PM UTC 24 |
| Peak memory | 249876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942031841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.1942031841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/168.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_parallel_lc_esc.3077896156 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 527724360 ps |
| CPU time | 5.11 seconds |
| Started | Aug 23 05:44:49 PM UTC 24 |
| Finished | Aug 23 05:44:56 PM UTC 24 |
| Peak memory | 250780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077896156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.3077896156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/168.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_init_fail.1447952944 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 196975163 ps |
| CPU time | 3.34 seconds |
| Started | Aug 23 05:44:49 PM UTC 24 |
| Finished | Aug 23 05:44:54 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447952944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.1447952944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/169.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_parallel_lc_esc.2000977944 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 265324235 ps |
| CPU time | 5.37 seconds |
| Started | Aug 23 05:44:49 PM UTC 24 |
| Finished | Aug 23 05:44:56 PM UTC 24 |
| Peak memory | 250616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000977944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.2000977944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/169.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_alert_test.1374207748 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 98395129 ps |
| CPU time | 1.56 seconds |
| Started | Aug 23 05:34:41 PM UTC 24 |
| Finished | Aug 23 05:34:44 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374207748 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.1374207748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/17.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_check_fail.4209046128 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2762250266 ps |
| CPU time | 11.89 seconds |
| Started | Aug 23 05:34:34 PM UTC 24 |
| Finished | Aug 23 05:34:48 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209046128 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.4209046128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/17.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_errs.1739756951 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 800418948 ps |
| CPU time | 19.44 seconds |
| Started | Aug 23 05:34:34 PM UTC 24 |
| Finished | Aug 23 05:34:55 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739756951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.1739756951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/17.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_lock.738396639 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 10658687808 ps |
| CPU time | 14.12 seconds |
| Started | Aug 23 05:34:32 PM UTC 24 |
| Finished | Aug 23 05:34:47 PM UTC 24 |
| Peak memory | 253468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738396639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.738396639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/17.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_init_fail.4274633215 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 204598843 ps |
| CPU time | 3.31 seconds |
| Started | Aug 23 05:34:31 PM UTC 24 |
| Finished | Aug 23 05:34:35 PM UTC 24 |
| Peak memory | 250912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274633215 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.4274633215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/17.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_macro_errs.3596299358 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 6857418526 ps |
| CPU time | 53.28 seconds |
| Started | Aug 23 05:34:37 PM UTC 24 |
| Finished | Aug 23 05:35:31 PM UTC 24 |
| Peak memory | 255472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596299358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.3596299358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/17.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_key_req.821442640 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 2013527912 ps |
| CPU time | 18.53 seconds |
| Started | Aug 23 05:34:37 PM UTC 24 |
| Finished | Aug 23 05:34:56 PM UTC 24 |
| Peak memory | 257688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821442640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.821442640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_esc.4020810155 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 797882444 ps |
| CPU time | 6.06 seconds |
| Started | Aug 23 05:34:31 PM UTC 24 |
| Finished | Aug 23 05:34:38 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020810155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.4020810155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_req.727898597 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 2810063560 ps |
| CPU time | 5.17 seconds |
| Started | Aug 23 05:34:31 PM UTC 24 |
| Finished | Aug 23 05:34:37 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727898597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.727898597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_regwen.3467174257 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 173504571 ps |
| CPU time | 4.35 seconds |
| Started | Aug 23 05:34:37 PM UTC 24 |
| Finished | Aug 23 05:34:42 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467174257 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.3467174257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/17.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_smoke.540544702 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 453877154 ps |
| CPU time | 3.17 seconds |
| Started | Aug 23 05:34:29 PM UTC 24 |
| Finished | Aug 23 05:34:33 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540544702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.540544702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/17.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all.2479058655 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 3632678371 ps |
| CPU time | 71.64 seconds |
| Started | Aug 23 05:34:39 PM UTC 24 |
| Finished | Aug 23 05:35:52 PM UTC 24 |
| Peak memory | 267896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479058655 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.2479058655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_test_access.852629228 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 797749477 ps |
| CPU time | 12.56 seconds |
| Started | Aug 23 05:34:38 PM UTC 24 |
| Finished | Aug 23 05:34:51 PM UTC 24 |
| Peak memory | 251404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852629228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.852629228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/17.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_init_fail.1777605701 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 147035665 ps |
| CPU time | 3.12 seconds |
| Started | Aug 23 05:44:49 PM UTC 24 |
| Finished | Aug 23 05:44:54 PM UTC 24 |
| Peak memory | 250416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777605701 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.1777605701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/170.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_init_fail.3295218936 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 1556681086 ps |
| CPU time | 4.07 seconds |
| Started | Aug 23 05:44:50 PM UTC 24 |
| Finished | Aug 23 05:44:55 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295218936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.3295218936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/171.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_parallel_lc_esc.2672025249 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 2106904473 ps |
| CPU time | 5.19 seconds |
| Started | Aug 23 05:44:52 PM UTC 24 |
| Finished | Aug 23 05:44:59 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672025249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.2672025249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/171.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_init_fail.1715984205 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 1341389589 ps |
| CPU time | 3.39 seconds |
| Started | Aug 23 05:44:52 PM UTC 24 |
| Finished | Aug 23 05:44:57 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715984205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.1715984205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/172.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_parallel_lc_esc.3079227639 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 175822740 ps |
| CPU time | 4.02 seconds |
| Started | Aug 23 05:44:52 PM UTC 24 |
| Finished | Aug 23 05:44:58 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079227639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.3079227639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/172.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_init_fail.3633574718 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 178972912 ps |
| CPU time | 2.97 seconds |
| Started | Aug 23 05:44:52 PM UTC 24 |
| Finished | Aug 23 05:44:57 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633574718 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.3633574718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/173.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_parallel_lc_esc.893339795 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 1292756454 ps |
| CPU time | 3.84 seconds |
| Started | Aug 23 05:44:52 PM UTC 24 |
| Finished | Aug 23 05:44:58 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893339795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.893339795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/173.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_init_fail.1354313593 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 2149803952 ps |
| CPU time | 4.92 seconds |
| Started | Aug 23 05:44:56 PM UTC 24 |
| Finished | Aug 23 05:45:02 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354313593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.1354313593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/174.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_parallel_lc_esc.2509051551 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 185407083 ps |
| CPU time | 7.77 seconds |
| Started | Aug 23 05:44:56 PM UTC 24 |
| Finished | Aug 23 05:45:05 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509051551 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.2509051551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/174.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_init_fail.3228816758 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 217089549 ps |
| CPU time | 3.8 seconds |
| Started | Aug 23 05:44:56 PM UTC 24 |
| Finished | Aug 23 05:45:01 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228816758 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.3228816758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/175.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_parallel_lc_esc.2110469502 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 581697596 ps |
| CPU time | 6.25 seconds |
| Started | Aug 23 05:44:56 PM UTC 24 |
| Finished | Aug 23 05:45:04 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110469502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.2110469502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/175.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_init_fail.2147394420 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 633124691 ps |
| CPU time | 3.37 seconds |
| Started | Aug 23 05:44:56 PM UTC 24 |
| Finished | Aug 23 05:45:01 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147394420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.2147394420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/176.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_parallel_lc_esc.2710365067 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 375705694 ps |
| CPU time | 2.66 seconds |
| Started | Aug 23 05:44:56 PM UTC 24 |
| Finished | Aug 23 05:45:00 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710365067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.2710365067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/176.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_init_fail.3668229576 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 428833301 ps |
| CPU time | 2.94 seconds |
| Started | Aug 23 05:45:02 PM UTC 24 |
| Finished | Aug 23 05:45:06 PM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668229576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.3668229576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/177.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_parallel_lc_esc.3565609356 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 908544302 ps |
| CPU time | 6.11 seconds |
| Started | Aug 23 05:45:02 PM UTC 24 |
| Finished | Aug 23 05:45:09 PM UTC 24 |
| Peak memory | 251024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565609356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.3565609356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/177.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_init_fail.2470436246 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 505463852 ps |
| CPU time | 3.37 seconds |
| Started | Aug 23 05:45:02 PM UTC 24 |
| Finished | Aug 23 05:45:06 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470436246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.2470436246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/178.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_parallel_lc_esc.587444990 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 226759644 ps |
| CPU time | 4.17 seconds |
| Started | Aug 23 05:45:02 PM UTC 24 |
| Finished | Aug 23 05:45:07 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587444990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.587444990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/178.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_init_fail.2698434071 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1552321400 ps |
| CPU time | 2.73 seconds |
| Started | Aug 23 05:45:02 PM UTC 24 |
| Finished | Aug 23 05:45:06 PM UTC 24 |
| Peak memory | 252596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698434071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.2698434071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/179.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_parallel_lc_esc.1082292948 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 600664098 ps |
| CPU time | 6 seconds |
| Started | Aug 23 05:45:02 PM UTC 24 |
| Finished | Aug 23 05:45:09 PM UTC 24 |
| Peak memory | 250976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082292948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.1082292948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/179.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_alert_test.284440182 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 1016306869 ps |
| CPU time | 1.64 seconds |
| Started | Aug 23 05:34:52 PM UTC 24 |
| Finished | Aug 23 05:34:55 PM UTC 24 |
| Peak memory | 250708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284440182 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.284440182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/18.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_errs.51943511 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 10743649927 ps |
| CPU time | 19.99 seconds |
| Started | Aug 23 05:34:46 PM UTC 24 |
| Finished | Aug 23 05:35:07 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51943511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.51943511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/18.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_lock.1507136913 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 258063551 ps |
| CPU time | 4.81 seconds |
| Started | Aug 23 05:34:46 PM UTC 24 |
| Finished | Aug 23 05:34:52 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507136913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.1507136913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/18.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_macro_errs.1518557264 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 1321106817 ps |
| CPU time | 32.64 seconds |
| Started | Aug 23 05:34:46 PM UTC 24 |
| Finished | Aug 23 05:35:20 PM UTC 24 |
| Peak memory | 255328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518557264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.1518557264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/18.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_key_req.2478197103 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 920600891 ps |
| CPU time | 10.69 seconds |
| Started | Aug 23 05:34:48 PM UTC 24 |
| Finished | Aug 23 05:35:00 PM UTC 24 |
| Peak memory | 250804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478197103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.2478197103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_req.2978053728 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 1039757452 ps |
| CPU time | 21.96 seconds |
| Started | Aug 23 05:34:43 PM UTC 24 |
| Finished | Aug 23 05:35:06 PM UTC 24 |
| Peak memory | 257364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978053728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.2978053728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_regwen.1041733500 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 234654623 ps |
| CPU time | 7.15 seconds |
| Started | Aug 23 05:34:48 PM UTC 24 |
| Finished | Aug 23 05:34:56 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041733500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.1041733500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/18.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_smoke.8516281 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 472562463 ps |
| CPU time | 4.99 seconds |
| Started | Aug 23 05:34:43 PM UTC 24 |
| Finished | Aug 23 05:34:49 PM UTC 24 |
| Peak memory | 251020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8516281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.8516281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/18.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all.426788934 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 9281941494 ps |
| CPU time | 78.56 seconds |
| Started | Aug 23 05:34:50 PM UTC 24 |
| Finished | Aug 23 05:36:10 PM UTC 24 |
| Peak memory | 257496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426788934 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.426788934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_test_access.1249212560 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1615900137 ps |
| CPU time | 23.07 seconds |
| Started | Aug 23 05:34:48 PM UTC 24 |
| Finished | Aug 23 05:35:13 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249212560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.1249212560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/18.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_init_fail.3073806540 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 249687771 ps |
| CPU time | 3.44 seconds |
| Started | Aug 23 05:45:02 PM UTC 24 |
| Finished | Aug 23 05:45:06 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073806540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.3073806540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/180.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_parallel_lc_esc.3184163973 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 210188513 ps |
| CPU time | 4.46 seconds |
| Started | Aug 23 05:45:02 PM UTC 24 |
| Finished | Aug 23 05:45:07 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184163973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.3184163973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/180.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_parallel_lc_esc.269498860 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 5844623076 ps |
| CPU time | 10.26 seconds |
| Started | Aug 23 05:45:02 PM UTC 24 |
| Finished | Aug 23 05:45:13 PM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269498860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.269498860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/181.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_init_fail.1501763528 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 108318495 ps |
| CPU time | 2.84 seconds |
| Started | Aug 23 05:45:02 PM UTC 24 |
| Finished | Aug 23 05:45:06 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501763528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.1501763528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/182.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_parallel_lc_esc.471015524 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 1039839533 ps |
| CPU time | 5.45 seconds |
| Started | Aug 23 05:45:02 PM UTC 24 |
| Finished | Aug 23 05:45:09 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471015524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.471015524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/182.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_init_fail.469966440 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 2010230852 ps |
| CPU time | 3.86 seconds |
| Started | Aug 23 05:45:02 PM UTC 24 |
| Finished | Aug 23 05:45:07 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469966440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.469966440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/183.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_parallel_lc_esc.2522081753 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 305413206 ps |
| CPU time | 5.56 seconds |
| Started | Aug 23 05:45:02 PM UTC 24 |
| Finished | Aug 23 05:45:09 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522081753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.2522081753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/183.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_init_fail.1008358765 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 171788534 ps |
| CPU time | 3.56 seconds |
| Started | Aug 23 05:45:02 PM UTC 24 |
| Finished | Aug 23 05:45:07 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008358765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.1008358765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/184.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_parallel_lc_esc.3988892579 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 250548578 ps |
| CPU time | 5.8 seconds |
| Started | Aug 23 05:45:02 PM UTC 24 |
| Finished | Aug 23 05:45:09 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988892579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.3988892579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/184.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_init_fail.4179267966 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 107643041 ps |
| CPU time | 2.93 seconds |
| Started | Aug 23 05:45:02 PM UTC 24 |
| Finished | Aug 23 05:45:06 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179267966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.4179267966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/185.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_parallel_lc_esc.609397931 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 671008132 ps |
| CPU time | 13.21 seconds |
| Started | Aug 23 05:45:02 PM UTC 24 |
| Finished | Aug 23 05:45:17 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609397931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.609397931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/185.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_init_fail.2177741247 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 286741923 ps |
| CPU time | 3.34 seconds |
| Started | Aug 23 05:45:09 PM UTC 24 |
| Finished | Aug 23 05:45:14 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177741247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.2177741247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/186.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_parallel_lc_esc.3832351153 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 362813512 ps |
| CPU time | 7.54 seconds |
| Started | Aug 23 05:45:09 PM UTC 24 |
| Finished | Aug 23 05:45:18 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832351153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.3832351153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/186.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_init_fail.3138098070 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 154184548 ps |
| CPU time | 2.93 seconds |
| Started | Aug 23 05:45:09 PM UTC 24 |
| Finished | Aug 23 05:45:14 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138098070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.3138098070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/187.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_parallel_lc_esc.1561896482 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 211874692 ps |
| CPU time | 2.75 seconds |
| Started | Aug 23 05:45:09 PM UTC 24 |
| Finished | Aug 23 05:45:14 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561896482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.1561896482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/187.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_init_fail.2734540537 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 235580485 ps |
| CPU time | 3.9 seconds |
| Started | Aug 23 05:45:09 PM UTC 24 |
| Finished | Aug 23 05:45:15 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734540537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.2734540537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/188.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.165235619 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 3732139200 ps |
| CPU time | 6.69 seconds |
| Started | Aug 23 05:45:10 PM UTC 24 |
| Finished | Aug 23 05:45:17 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165235619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.165235619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/188.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_init_fail.3957836362 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 653956927 ps |
| CPU time | 3.41 seconds |
| Started | Aug 23 05:45:10 PM UTC 24 |
| Finished | Aug 23 05:45:14 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957836362 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.3957836362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/189.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.3444311909 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 98089606 ps |
| CPU time | 2.32 seconds |
| Started | Aug 23 05:45:10 PM UTC 24 |
| Finished | Aug 23 05:45:13 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444311909 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.3444311909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/189.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_alert_test.307549062 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 96069620 ps |
| CPU time | 1.46 seconds |
| Started | Aug 23 05:35:05 PM UTC 24 |
| Finished | Aug 23 05:35:07 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307549062 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.307549062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_check_fail.3534277256 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 11490016919 ps |
| CPU time | 19.04 seconds |
| Started | Aug 23 05:34:58 PM UTC 24 |
| Finished | Aug 23 05:35:18 PM UTC 24 |
| Peak memory | 253552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534277256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.3534277256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_errs.2789534014 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 6258532672 ps |
| CPU time | 20.77 seconds |
| Started | Aug 23 05:34:56 PM UTC 24 |
| Finished | Aug 23 05:35:18 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789534014 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.2789534014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_lock.722776750 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 1688748026 ps |
| CPU time | 7.47 seconds |
| Started | Aug 23 05:34:56 PM UTC 24 |
| Finished | Aug 23 05:35:05 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722776750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.722776750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_init_fail.864389626 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 2528506179 ps |
| CPU time | 6.17 seconds |
| Started | Aug 23 05:34:53 PM UTC 24 |
| Finished | Aug 23 05:35:01 PM UTC 24 |
| Peak memory | 251264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864389626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.864389626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_key_req.2251121911 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 875078959 ps |
| CPU time | 24.4 seconds |
| Started | Aug 23 05:35:02 PM UTC 24 |
| Finished | Aug 23 05:35:28 PM UTC 24 |
| Peak memory | 253340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251121911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.2251121911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_esc.3842467840 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 3561522850 ps |
| CPU time | 12.29 seconds |
| Started | Aug 23 05:34:56 PM UTC 24 |
| Finished | Aug 23 05:35:09 PM UTC 24 |
| Peak memory | 257364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842467840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.3842467840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_req.3747006641 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1247053787 ps |
| CPU time | 8.91 seconds |
| Started | Aug 23 05:34:55 PM UTC 24 |
| Finished | Aug 23 05:35:05 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747006641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.3747006641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_smoke.2882672947 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 750389073 ps |
| CPU time | 10.2 seconds |
| Started | Aug 23 05:34:52 PM UTC 24 |
| Finished | Aug 23 05:35:04 PM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882672947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.2882672947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all.1996724027 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 4632987085 ps |
| CPU time | 56.27 seconds |
| Started | Aug 23 05:35:04 PM UTC 24 |
| Finished | Aug 23 05:36:01 PM UTC 24 |
| Peak memory | 257560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996724027 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.1996724027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.516896492 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 11153103249 ps |
| CPU time | 56.21 seconds |
| Started | Aug 23 05:35:02 PM UTC 24 |
| Finished | Aug 23 05:36:00 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=516896492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.516896492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_test_access.1121372737 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 218523591 ps |
| CPU time | 4.47 seconds |
| Started | Aug 23 05:35:02 PM UTC 24 |
| Finished | Aug 23 05:35:08 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121372737 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.1121372737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/19.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_init_fail.2543726514 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 441169332 ps |
| CPU time | 3.56 seconds |
| Started | Aug 23 05:45:10 PM UTC 24 |
| Finished | Aug 23 05:45:14 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543726514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.2543726514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/190.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.3334869891 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 809327971 ps |
| CPU time | 8.57 seconds |
| Started | Aug 23 05:45:10 PM UTC 24 |
| Finished | Aug 23 05:45:20 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334869891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.3334869891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/190.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_init_fail.3705830836 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 109915740 ps |
| CPU time | 2.95 seconds |
| Started | Aug 23 05:45:10 PM UTC 24 |
| Finished | Aug 23 05:45:14 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705830836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.3705830836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/191.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.2734353595 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 240504865 ps |
| CPU time | 5.83 seconds |
| Started | Aug 23 05:45:10 PM UTC 24 |
| Finished | Aug 23 05:45:17 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734353595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.2734353595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/191.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_init_fail.2185730889 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 607764383 ps |
| CPU time | 3.65 seconds |
| Started | Aug 23 05:45:10 PM UTC 24 |
| Finished | Aug 23 05:45:15 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185730889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.2185730889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/192.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.3718707167 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 409790248 ps |
| CPU time | 3.85 seconds |
| Started | Aug 23 05:45:10 PM UTC 24 |
| Finished | Aug 23 05:45:15 PM UTC 24 |
| Peak memory | 253212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718707167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.3718707167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/192.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_init_fail.3333939267 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 1848740858 ps |
| CPU time | 2.67 seconds |
| Started | Aug 23 05:45:10 PM UTC 24 |
| Finished | Aug 23 05:45:14 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333939267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.3333939267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/193.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.2954113477 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 382675771 ps |
| CPU time | 6.82 seconds |
| Started | Aug 23 05:45:10 PM UTC 24 |
| Finished | Aug 23 05:45:18 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954113477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.2954113477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/193.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_init_fail.3153746153 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 174485237 ps |
| CPU time | 3.31 seconds |
| Started | Aug 23 05:45:10 PM UTC 24 |
| Finished | Aug 23 05:45:14 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153746153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.3153746153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/194.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.1946262866 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 549658051 ps |
| CPU time | 6.44 seconds |
| Started | Aug 23 05:45:10 PM UTC 24 |
| Finished | Aug 23 05:45:18 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946262866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.1946262866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/194.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.2801547318 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 301014394 ps |
| CPU time | 3.28 seconds |
| Started | Aug 23 05:45:10 PM UTC 24 |
| Finished | Aug 23 05:45:15 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801547318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.2801547318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/195.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.1122205651 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 180620051 ps |
| CPU time | 6.79 seconds |
| Started | Aug 23 05:45:10 PM UTC 24 |
| Finished | Aug 23 05:45:18 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122205651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.1122205651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/195.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.2629540228 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 260424349 ps |
| CPU time | 4.25 seconds |
| Started | Aug 23 05:45:10 PM UTC 24 |
| Finished | Aug 23 05:45:16 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629540228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.2629540228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/196.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.24518606 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 500660368 ps |
| CPU time | 9.08 seconds |
| Started | Aug 23 05:45:10 PM UTC 24 |
| Finished | Aug 23 05:45:20 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24518606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.24518606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/196.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.3283247843 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 565071307 ps |
| CPU time | 3.8 seconds |
| Started | Aug 23 05:45:13 PM UTC 24 |
| Finished | Aug 23 05:45:18 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283247843 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.3283247843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/197.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.2534102007 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 205902977 ps |
| CPU time | 3.8 seconds |
| Started | Aug 23 05:45:13 PM UTC 24 |
| Finished | Aug 23 05:45:18 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534102007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.2534102007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/197.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.4076987939 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 3641217018 ps |
| CPU time | 10.95 seconds |
| Started | Aug 23 05:45:13 PM UTC 24 |
| Finished | Aug 23 05:45:25 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076987939 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.4076987939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/198.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.1765676518 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 312947699 ps |
| CPU time | 3.82 seconds |
| Started | Aug 23 05:45:13 PM UTC 24 |
| Finished | Aug 23 05:45:18 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765676518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.1765676518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/199.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.109253291 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 84768399 ps |
| CPU time | 4.12 seconds |
| Started | Aug 23 05:45:13 PM UTC 24 |
| Finished | Aug 23 05:45:18 PM UTC 24 |
| Peak memory | 251092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109253291 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.109253291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/199.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_alert_test.2916940403 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 51107687 ps |
| CPU time | 1.44 seconds |
| Started | Aug 23 05:31:15 PM UTC 24 |
| Finished | Aug 23 05:31:17 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916940403 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.2916940403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_background_chks.199002086 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 2768251642 ps |
| CPU time | 11.83 seconds |
| Started | Aug 23 05:31:01 PM UTC 24 |
| Finished | Aug 23 05:31:14 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199002086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.199002086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_errs.2378285303 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 514483415 ps |
| CPU time | 12.02 seconds |
| Started | Aug 23 05:31:04 PM UTC 24 |
| Finished | Aug 23 05:31:17 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378285303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.2378285303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_init_fail.128620902 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 134272437 ps |
| CPU time | 2.94 seconds |
| Started | Aug 23 05:31:01 PM UTC 24 |
| Finished | Aug 23 05:31:05 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128620902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.128620902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_key_req.120939635 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 358447024 ps |
| CPU time | 10.04 seconds |
| Started | Aug 23 05:31:05 PM UTC 24 |
| Finished | Aug 23 05:31:16 PM UTC 24 |
| Peak memory | 253332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120939635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.120939635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_esc.1004053400 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 1310074899 ps |
| CPU time | 11.11 seconds |
| Started | Aug 23 05:31:02 PM UTC 24 |
| Finished | Aug 23 05:31:15 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004053400 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.1004053400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_req.1641654447 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 2753149432 ps |
| CPU time | 16.8 seconds |
| Started | Aug 23 05:31:02 PM UTC 24 |
| Finished | Aug 23 05:31:20 PM UTC 24 |
| Peak memory | 257688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641654447 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.1641654447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_regwen.270889798 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 621457814 ps |
| CPU time | 5.52 seconds |
| Started | Aug 23 05:31:06 PM UTC 24 |
| Finished | Aug 23 05:31:13 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270889798 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.270889798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_sec_cm.3367513443 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 15175990914 ps |
| CPU time | 178.29 seconds |
| Started | Aug 23 05:31:14 PM UTC 24 |
| Finished | Aug 23 05:34:16 PM UTC 24 |
| Peak memory | 285820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367513443 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.3367513443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_smoke.1658204233 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 412159193 ps |
| CPU time | 2.56 seconds |
| Started | Aug 23 05:31:01 PM UTC 24 |
| Finished | Aug 23 05:31:05 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658204233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.1658204233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_test_access.2636834036 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 1779881689 ps |
| CPU time | 15.7 seconds |
| Started | Aug 23 05:31:07 PM UTC 24 |
| Finished | Aug 23 05:31:24 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636834036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.2636834036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/2.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_alert_test.3204854004 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 56701395 ps |
| CPU time | 1.57 seconds |
| Started | Aug 23 05:35:20 PM UTC 24 |
| Finished | Aug 23 05:35:23 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204854004 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.3204854004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/20.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_errs.3424118297 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 390459842 ps |
| CPU time | 8.98 seconds |
| Started | Aug 23 05:35:08 PM UTC 24 |
| Finished | Aug 23 05:35:19 PM UTC 24 |
| Peak memory | 251100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424118297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.3424118297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/20.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_lock.4278330971 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 16615660966 ps |
| CPU time | 30.21 seconds |
| Started | Aug 23 05:35:08 PM UTC 24 |
| Finished | Aug 23 05:35:40 PM UTC 24 |
| Peak memory | 257784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278330971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.4278330971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/20.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_init_fail.105492042 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 148317471 ps |
| CPU time | 2.97 seconds |
| Started | Aug 23 05:35:06 PM UTC 24 |
| Finished | Aug 23 05:35:10 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105492042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.105492042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/20.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_macro_errs.992135411 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 1953046898 ps |
| CPU time | 26.49 seconds |
| Started | Aug 23 05:35:11 PM UTC 24 |
| Finished | Aug 23 05:35:38 PM UTC 24 |
| Peak memory | 268088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992135411 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.992135411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/20.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_key_req.550225998 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 489317107 ps |
| CPU time | 8.25 seconds |
| Started | Aug 23 05:35:11 PM UTC 24 |
| Finished | Aug 23 05:35:20 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550225998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.550225998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_esc.3337808117 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 746871844 ps |
| CPU time | 4.9 seconds |
| Started | Aug 23 05:35:08 PM UTC 24 |
| Finished | Aug 23 05:35:14 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337808117 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.3337808117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_req.3634728043 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 9211867911 ps |
| CPU time | 19.17 seconds |
| Started | Aug 23 05:35:08 PM UTC 24 |
| Finished | Aug 23 05:35:29 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634728043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.3634728043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_regwen.94131461 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 1001873376 ps |
| CPU time | 7.61 seconds |
| Started | Aug 23 05:35:12 PM UTC 24 |
| Finished | Aug 23 05:35:21 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94131461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ot p_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.94131461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/20.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_smoke.2559909555 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 329917445 ps |
| CPU time | 3.88 seconds |
| Started | Aug 23 05:35:06 PM UTC 24 |
| Finished | Aug 23 05:35:11 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559909555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.2559909555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/20.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_test_access.1687590522 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 421302374 ps |
| CPU time | 7.23 seconds |
| Started | Aug 23 05:35:14 PM UTC 24 |
| Finished | Aug 23 05:35:22 PM UTC 24 |
| Peak memory | 251568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687590522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.1687590522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/20.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.2159153050 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 172398398 ps |
| CPU time | 3.52 seconds |
| Started | Aug 23 05:45:19 PM UTC 24 |
| Finished | Aug 23 05:45:23 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159153050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.2159153050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/200.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.982411972 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 154857154 ps |
| CPU time | 3.13 seconds |
| Started | Aug 23 05:45:19 PM UTC 24 |
| Finished | Aug 23 05:45:23 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982411972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.982411972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/202.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.2034038425 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 160858907 ps |
| CPU time | 2.82 seconds |
| Started | Aug 23 05:45:19 PM UTC 24 |
| Finished | Aug 23 05:45:23 PM UTC 24 |
| Peak memory | 251060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034038425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.2034038425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/203.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.2862802599 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 2306301386 ps |
| CPU time | 4.87 seconds |
| Started | Aug 23 05:45:19 PM UTC 24 |
| Finished | Aug 23 05:45:25 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862802599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.2862802599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/204.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.1122467898 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 139846614 ps |
| CPU time | 3.59 seconds |
| Started | Aug 23 05:45:19 PM UTC 24 |
| Finished | Aug 23 05:45:24 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122467898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.1122467898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/205.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.264468947 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 2424022370 ps |
| CPU time | 4.3 seconds |
| Started | Aug 23 05:45:19 PM UTC 24 |
| Finished | Aug 23 05:45:24 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264468947 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.264468947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/206.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.1886864057 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 440372124 ps |
| CPU time | 3.65 seconds |
| Started | Aug 23 05:45:19 PM UTC 24 |
| Finished | Aug 23 05:45:24 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886864057 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.1886864057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/207.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.1598326208 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 148750366 ps |
| CPU time | 3.19 seconds |
| Started | Aug 23 05:45:19 PM UTC 24 |
| Finished | Aug 23 05:45:23 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598326208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.1598326208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/208.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.1251889728 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 140044869 ps |
| CPU time | 3.12 seconds |
| Started | Aug 23 05:45:19 PM UTC 24 |
| Finished | Aug 23 05:45:23 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251889728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.1251889728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/209.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_alert_test.2468135526 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 97839829 ps |
| CPU time | 1.51 seconds |
| Started | Aug 23 05:35:32 PM UTC 24 |
| Finished | Aug 23 05:35:34 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468135526 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.2468135526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/21.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_check_fail.4206890599 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 935695127 ps |
| CPU time | 10.11 seconds |
| Started | Aug 23 05:35:24 PM UTC 24 |
| Finished | Aug 23 05:35:35 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206890599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.4206890599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/21.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_errs.2160290410 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 678979926 ps |
| CPU time | 18.86 seconds |
| Started | Aug 23 05:35:23 PM UTC 24 |
| Finished | Aug 23 05:35:43 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160290410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.2160290410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/21.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_lock.1466215254 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 2048187384 ps |
| CPU time | 15.13 seconds |
| Started | Aug 23 05:35:22 PM UTC 24 |
| Finished | Aug 23 05:35:38 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466215254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.1466215254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/21.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_init_fail.4080526525 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 518729413 ps |
| CPU time | 3.18 seconds |
| Started | Aug 23 05:35:20 PM UTC 24 |
| Finished | Aug 23 05:35:24 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080526525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.4080526525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/21.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_macro_errs.443645423 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 1134940529 ps |
| CPU time | 10.96 seconds |
| Started | Aug 23 05:35:25 PM UTC 24 |
| Finished | Aug 23 05:35:37 PM UTC 24 |
| Peak memory | 251616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443645423 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.443645423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/21.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_key_req.2324105366 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 5093072188 ps |
| CPU time | 7.5 seconds |
| Started | Aug 23 05:35:27 PM UTC 24 |
| Finished | Aug 23 05:35:36 PM UTC 24 |
| Peak memory | 257788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324105366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.2324105366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_esc.256423929 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 196889206 ps |
| CPU time | 4.26 seconds |
| Started | Aug 23 05:35:22 PM UTC 24 |
| Finished | Aug 23 05:35:27 PM UTC 24 |
| Peak memory | 251304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256423929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.256423929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_req.2749518822 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 6510979930 ps |
| CPU time | 12.53 seconds |
| Started | Aug 23 05:35:21 PM UTC 24 |
| Finished | Aug 23 05:35:35 PM UTC 24 |
| Peak memory | 257432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749518822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.2749518822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_regwen.1022507177 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 1142143871 ps |
| CPU time | 6.56 seconds |
| Started | Aug 23 05:35:27 PM UTC 24 |
| Finished | Aug 23 05:35:35 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022507177 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.1022507177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/21.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_smoke.1518328347 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 724909278 ps |
| CPU time | 5.13 seconds |
| Started | Aug 23 05:35:20 PM UTC 24 |
| Finished | Aug 23 05:35:26 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518328347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.1518328347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/21.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all.2954006564 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 5111391480 ps |
| CPU time | 66.87 seconds |
| Started | Aug 23 05:35:29 PM UTC 24 |
| Finished | Aug 23 05:36:38 PM UTC 24 |
| Peak memory | 268028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954006564 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.2954006564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.2919491942 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 4230951298 ps |
| CPU time | 81.24 seconds |
| Started | Aug 23 05:35:29 PM UTC 24 |
| Finished | Aug 23 05:36:52 PM UTC 24 |
| Peak memory | 261808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2919491942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 21.otp_ctrl_stress_all_with_rand_reset.2919491942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_test_access.2303526221 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 866451611 ps |
| CPU time | 11.52 seconds |
| Started | Aug 23 05:35:27 PM UTC 24 |
| Finished | Aug 23 05:35:40 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303526221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.2303526221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/21.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.267169635 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 129922315 ps |
| CPU time | 2.64 seconds |
| Started | Aug 23 05:45:19 PM UTC 24 |
| Finished | Aug 23 05:45:23 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267169635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.267169635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/210.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.2419096026 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 239226785 ps |
| CPU time | 3.23 seconds |
| Started | Aug 23 05:45:19 PM UTC 24 |
| Finished | Aug 23 05:45:24 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419096026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.2419096026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/211.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.2757936648 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 551912990 ps |
| CPU time | 3.85 seconds |
| Started | Aug 23 05:45:19 PM UTC 24 |
| Finished | Aug 23 05:45:24 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757936648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.2757936648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/213.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.72199083 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 458842370 ps |
| CPU time | 4.06 seconds |
| Started | Aug 23 05:45:19 PM UTC 24 |
| Finished | Aug 23 05:45:24 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72199083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.72199083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/214.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.2661842806 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 298525174 ps |
| CPU time | 3.48 seconds |
| Started | Aug 23 05:45:19 PM UTC 24 |
| Finished | Aug 23 05:45:24 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661842806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.2661842806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/215.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.2130064766 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 260756593 ps |
| CPU time | 3.22 seconds |
| Started | Aug 23 05:45:28 PM UTC 24 |
| Finished | Aug 23 05:45:33 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130064766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.2130064766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/216.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.2586070837 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 2202955933 ps |
| CPU time | 4.48 seconds |
| Started | Aug 23 05:45:28 PM UTC 24 |
| Finished | Aug 23 05:45:34 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586070837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.2586070837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/219.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_alert_test.3008546578 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 173089170 ps |
| CPU time | 1.43 seconds |
| Started | Aug 23 05:35:44 PM UTC 24 |
| Finished | Aug 23 05:35:46 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008546578 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.3008546578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/22.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_check_fail.976329530 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 1458953103 ps |
| CPU time | 12.41 seconds |
| Started | Aug 23 05:35:37 PM UTC 24 |
| Finished | Aug 23 05:35:50 PM UTC 24 |
| Peak memory | 253376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976329530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.976329530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/22.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_errs.2277001699 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 776555756 ps |
| CPU time | 14.01 seconds |
| Started | Aug 23 05:35:37 PM UTC 24 |
| Finished | Aug 23 05:35:52 PM UTC 24 |
| Peak memory | 253236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277001699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.2277001699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/22.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_lock.3606246204 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 15410139687 ps |
| CPU time | 15.41 seconds |
| Started | Aug 23 05:35:37 PM UTC 24 |
| Finished | Aug 23 05:35:53 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606246204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.3606246204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/22.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_init_fail.3994757681 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 139264438 ps |
| CPU time | 3.1 seconds |
| Started | Aug 23 05:35:34 PM UTC 24 |
| Finished | Aug 23 05:35:38 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994757681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.3994757681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/22.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_macro_errs.2850246680 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 5877528725 ps |
| CPU time | 8.74 seconds |
| Started | Aug 23 05:35:38 PM UTC 24 |
| Finished | Aug 23 05:35:48 PM UTC 24 |
| Peak memory | 255472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850246680 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.2850246680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/22.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_key_req.1191971464 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 2691686900 ps |
| CPU time | 15.9 seconds |
| Started | Aug 23 05:35:40 PM UTC 24 |
| Finished | Aug 23 05:35:57 PM UTC 24 |
| Peak memory | 257532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191971464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.1191971464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_esc.336512111 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 1037351281 ps |
| CPU time | 20.25 seconds |
| Started | Aug 23 05:35:37 PM UTC 24 |
| Finished | Aug 23 05:35:58 PM UTC 24 |
| Peak memory | 257324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336512111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.336512111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_req.112820648 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1395937344 ps |
| CPU time | 8.42 seconds |
| Started | Aug 23 05:35:35 PM UTC 24 |
| Finished | Aug 23 05:35:45 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112820648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.112820648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_regwen.492387265 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 219503929 ps |
| CPU time | 3.9 seconds |
| Started | Aug 23 05:35:40 PM UTC 24 |
| Finished | Aug 23 05:35:45 PM UTC 24 |
| Peak memory | 257356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492387265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.492387265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/22.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_smoke.1130095083 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 1667836906 ps |
| CPU time | 9.51 seconds |
| Started | Aug 23 05:35:33 PM UTC 24 |
| Finished | Aug 23 05:35:43 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130095083 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.1130095083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/22.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all.207346007 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 40524019418 ps |
| CPU time | 207.77 seconds |
| Started | Aug 23 05:35:41 PM UTC 24 |
| Finished | Aug 23 05:39:12 PM UTC 24 |
| Peak memory | 261588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207346007 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.207346007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all_with_rand_reset.3483426289 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 5637783879 ps |
| CPU time | 42.97 seconds |
| Started | Aug 23 05:35:41 PM UTC 24 |
| Finished | Aug 23 05:36:26 PM UTC 24 |
| Peak memory | 267856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3483426289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 22.otp_ctrl_stress_all_with_rand_reset.3483426289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_test_access.1710695711 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 3120467610 ps |
| CPU time | 21.24 seconds |
| Started | Aug 23 05:35:40 PM UTC 24 |
| Finished | Aug 23 05:36:02 PM UTC 24 |
| Peak memory | 251696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710695711 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.1710695711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/22.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.1978416990 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 568788873 ps |
| CPU time | 3.74 seconds |
| Started | Aug 23 05:45:28 PM UTC 24 |
| Finished | Aug 23 05:45:33 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978416990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.1978416990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/220.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.3841569600 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 134203143 ps |
| CPU time | 4.07 seconds |
| Started | Aug 23 05:45:28 PM UTC 24 |
| Finished | Aug 23 05:45:34 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841569600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.3841569600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/221.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.3061228306 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 120286498 ps |
| CPU time | 3.41 seconds |
| Started | Aug 23 05:45:28 PM UTC 24 |
| Finished | Aug 23 05:45:33 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061228306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.3061228306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/222.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.2749272436 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 170910066 ps |
| CPU time | 3.38 seconds |
| Started | Aug 23 05:45:28 PM UTC 24 |
| Finished | Aug 23 05:45:33 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749272436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.2749272436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/223.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.1921656777 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 562881429 ps |
| CPU time | 3.78 seconds |
| Started | Aug 23 05:45:28 PM UTC 24 |
| Finished | Aug 23 05:45:33 PM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921656777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.1921656777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/224.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.4195432388 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 352569684 ps |
| CPU time | 3.18 seconds |
| Started | Aug 23 05:45:28 PM UTC 24 |
| Finished | Aug 23 05:45:33 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195432388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.4195432388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/225.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.2349468740 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 124003719 ps |
| CPU time | 3.29 seconds |
| Started | Aug 23 05:45:28 PM UTC 24 |
| Finished | Aug 23 05:45:33 PM UTC 24 |
| Peak memory | 252856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349468740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.2349468740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/226.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.3099762454 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 310720229 ps |
| CPU time | 3.71 seconds |
| Started | Aug 23 05:45:28 PM UTC 24 |
| Finished | Aug 23 05:45:33 PM UTC 24 |
| Peak memory | 250844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099762454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.3099762454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/227.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.170407540 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 296710606 ps |
| CPU time | 4.2 seconds |
| Started | Aug 23 05:45:28 PM UTC 24 |
| Finished | Aug 23 05:45:34 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170407540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.170407540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/228.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.3024987477 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 575571342 ps |
| CPU time | 3.61 seconds |
| Started | Aug 23 05:45:28 PM UTC 24 |
| Finished | Aug 23 05:45:33 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024987477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.3024987477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/229.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_alert_test.509073718 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 702584526 ps |
| CPU time | 1.61 seconds |
| Started | Aug 23 05:35:56 PM UTC 24 |
| Finished | Aug 23 05:35:58 PM UTC 24 |
| Peak memory | 251116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509073718 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.509073718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/23.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_check_fail.3871469730 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 3951981183 ps |
| CPU time | 23.58 seconds |
| Started | Aug 23 05:35:51 PM UTC 24 |
| Finished | Aug 23 05:36:16 PM UTC 24 |
| Peak memory | 253252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871469730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.3871469730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/23.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_errs.3340887159 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 5853859552 ps |
| CPU time | 34.13 seconds |
| Started | Aug 23 05:35:49 PM UTC 24 |
| Finished | Aug 23 05:36:24 PM UTC 24 |
| Peak memory | 263860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340887159 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.3340887159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/23.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_lock.24316044 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2328499701 ps |
| CPU time | 22.71 seconds |
| Started | Aug 23 05:35:47 PM UTC 24 |
| Finished | Aug 23 05:36:12 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24316044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.24316044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/23.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_init_fail.377490892 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 2423668605 ps |
| CPU time | 5.62 seconds |
| Started | Aug 23 05:35:45 PM UTC 24 |
| Finished | Aug 23 05:35:52 PM UTC 24 |
| Peak memory | 251576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377490892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.377490892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/23.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_key_req.745151109 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 12935681302 ps |
| CPU time | 25.19 seconds |
| Started | Aug 23 05:35:52 PM UTC 24 |
| Finished | Aug 23 05:36:19 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745151109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.745151109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_esc.427984138 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 891817725 ps |
| CPU time | 15.42 seconds |
| Started | Aug 23 05:35:46 PM UTC 24 |
| Finished | Aug 23 05:36:03 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427984138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.427984138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_req.400776938 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 204274386 ps |
| CPU time | 4.45 seconds |
| Started | Aug 23 05:35:45 PM UTC 24 |
| Finished | Aug 23 05:35:51 PM UTC 24 |
| Peak memory | 257588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400776938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.400776938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_regwen.2257645706 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 477151642 ps |
| CPU time | 3.41 seconds |
| Started | Aug 23 05:35:54 PM UTC 24 |
| Finished | Aug 23 05:35:59 PM UTC 24 |
| Peak memory | 257420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257645706 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.2257645706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/23.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_smoke.2341970509 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 1428941030 ps |
| CPU time | 8.39 seconds |
| Started | Aug 23 05:35:45 PM UTC 24 |
| Finished | Aug 23 05:35:55 PM UTC 24 |
| Peak memory | 251648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341970509 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.2341970509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/23.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_test_access.2085424871 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 4687889878 ps |
| CPU time | 23.95 seconds |
| Started | Aug 23 05:35:54 PM UTC 24 |
| Finished | Aug 23 05:36:20 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085424871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.2085424871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/23.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.786420122 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 630784084 ps |
| CPU time | 3.4 seconds |
| Started | Aug 23 05:45:28 PM UTC 24 |
| Finished | Aug 23 05:45:33 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786420122 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.786420122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/230.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.2902003540 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 1549714206 ps |
| CPU time | 3.78 seconds |
| Started | Aug 23 05:45:29 PM UTC 24 |
| Finished | Aug 23 05:45:34 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902003540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.2902003540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/231.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.3550904527 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 1263197402 ps |
| CPU time | 2.44 seconds |
| Started | Aug 23 05:45:29 PM UTC 24 |
| Finished | Aug 23 05:45:32 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550904527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.3550904527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/232.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.1263550045 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 144607346 ps |
| CPU time | 3.34 seconds |
| Started | Aug 23 05:45:29 PM UTC 24 |
| Finished | Aug 23 05:45:33 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263550045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.1263550045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/233.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.2298342003 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 264123787 ps |
| CPU time | 4.04 seconds |
| Started | Aug 23 05:45:29 PM UTC 24 |
| Finished | Aug 23 05:45:34 PM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298342003 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.2298342003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/234.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.1948687207 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 259827192 ps |
| CPU time | 2.94 seconds |
| Started | Aug 23 05:45:29 PM UTC 24 |
| Finished | Aug 23 05:45:33 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948687207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.1948687207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/235.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.1196624987 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 464078830 ps |
| CPU time | 3.44 seconds |
| Started | Aug 23 05:45:29 PM UTC 24 |
| Finished | Aug 23 05:45:33 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196624987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.1196624987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/236.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.2176125987 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 282199370 ps |
| CPU time | 3.12 seconds |
| Started | Aug 23 05:45:29 PM UTC 24 |
| Finished | Aug 23 05:45:33 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176125987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.2176125987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/237.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.729804576 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 112555588 ps |
| CPU time | 3.92 seconds |
| Started | Aug 23 05:45:29 PM UTC 24 |
| Finished | Aug 23 05:45:34 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729804576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.729804576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/238.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.99415224 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 641234635 ps |
| CPU time | 3.78 seconds |
| Started | Aug 23 05:45:29 PM UTC 24 |
| Finished | Aug 23 05:45:34 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99415224 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.99415224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/239.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_alert_test.2570324279 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 64025239 ps |
| CPU time | 1.61 seconds |
| Started | Aug 23 05:36:13 PM UTC 24 |
| Finished | Aug 23 05:36:16 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570324279 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.2570324279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/24.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_check_fail.3347177075 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1626387194 ps |
| CPU time | 23.12 seconds |
| Started | Aug 23 05:36:03 PM UTC 24 |
| Finished | Aug 23 05:36:28 PM UTC 24 |
| Peak memory | 253360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347177075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.3347177075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/24.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_errs.562336673 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 634602992 ps |
| CPU time | 15.13 seconds |
| Started | Aug 23 05:36:01 PM UTC 24 |
| Finished | Aug 23 05:36:17 PM UTC 24 |
| Peak memory | 253188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562336673 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.562336673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/24.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_lock.165279042 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 28718297827 ps |
| CPU time | 38.97 seconds |
| Started | Aug 23 05:36:00 PM UTC 24 |
| Finished | Aug 23 05:36:40 PM UTC 24 |
| Peak memory | 253468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165279042 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.165279042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/24.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_init_fail.3503911825 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 301986907 ps |
| CPU time | 3.43 seconds |
| Started | Aug 23 05:36:00 PM UTC 24 |
| Finished | Aug 23 05:36:04 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503911825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.3503911825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/24.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_macro_errs.2238894690 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 427762046 ps |
| CPU time | 11.57 seconds |
| Started | Aug 23 05:36:03 PM UTC 24 |
| Finished | Aug 23 05:36:16 PM UTC 24 |
| Peak memory | 253420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238894690 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.2238894690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/24.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_key_req.1611893417 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 870379361 ps |
| CPU time | 16.5 seconds |
| Started | Aug 23 05:36:05 PM UTC 24 |
| Finished | Aug 23 05:36:22 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611893417 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.1611893417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_esc.57502221 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 442078055 ps |
| CPU time | 8.96 seconds |
| Started | Aug 23 05:36:00 PM UTC 24 |
| Finished | Aug 23 05:36:10 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57502221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.57502221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_req.2341053822 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 440859940 ps |
| CPU time | 11.13 seconds |
| Started | Aug 23 05:36:00 PM UTC 24 |
| Finished | Aug 23 05:36:12 PM UTC 24 |
| Peak memory | 257372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341053822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.2341053822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_regwen.3687889427 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 1172570781 ps |
| CPU time | 10.57 seconds |
| Started | Aug 23 05:36:06 PM UTC 24 |
| Finished | Aug 23 05:36:17 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687889427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.3687889427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/24.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_smoke.1354177308 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 258576105 ps |
| CPU time | 8.28 seconds |
| Started | Aug 23 05:36:00 PM UTC 24 |
| Finished | Aug 23 05:36:09 PM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354177308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.1354177308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/24.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all.1984968544 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 8346960541 ps |
| CPU time | 109.29 seconds |
| Started | Aug 23 05:36:13 PM UTC 24 |
| Finished | Aug 23 05:38:04 PM UTC 24 |
| Peak memory | 273256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984968544 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all.1984968544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.1887755742 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 11994298076 ps |
| CPU time | 146.75 seconds |
| Started | Aug 23 05:36:13 PM UTC 24 |
| Finished | Aug 23 05:38:42 PM UTC 24 |
| Peak memory | 274092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1887755742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 24.otp_ctrl_stress_all_with_rand_reset.1887755742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_test_access.2231482456 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 1404900513 ps |
| CPU time | 21.4 seconds |
| Started | Aug 23 05:36:10 PM UTC 24 |
| Finished | Aug 23 05:36:33 PM UTC 24 |
| Peak memory | 253616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231482456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.2231482456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/24.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.3168489554 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 212075473 ps |
| CPU time | 3.17 seconds |
| Started | Aug 23 05:45:29 PM UTC 24 |
| Finished | Aug 23 05:45:33 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168489554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.3168489554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/240.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.1168740241 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 182166376 ps |
| CPU time | 2.53 seconds |
| Started | Aug 23 05:45:29 PM UTC 24 |
| Finished | Aug 23 05:45:33 PM UTC 24 |
| Peak memory | 250796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168740241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.1168740241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/241.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.2070994370 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 211607163 ps |
| CPU time | 2.64 seconds |
| Started | Aug 23 05:45:29 PM UTC 24 |
| Finished | Aug 23 05:45:33 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070994370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.2070994370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/242.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.1772742352 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 249822633 ps |
| CPU time | 3.95 seconds |
| Started | Aug 23 05:45:29 PM UTC 24 |
| Finished | Aug 23 05:45:34 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772742352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.1772742352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/243.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.946302054 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 136783133 ps |
| CPU time | 3.15 seconds |
| Started | Aug 23 05:45:29 PM UTC 24 |
| Finished | Aug 23 05:45:33 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946302054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.946302054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/244.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.1904792382 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 2044801931 ps |
| CPU time | 5.01 seconds |
| Started | Aug 23 05:45:30 PM UTC 24 |
| Finished | Aug 23 05:45:37 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904792382 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.1904792382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/246.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.1651432262 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 2550385085 ps |
| CPU time | 4.91 seconds |
| Started | Aug 23 05:45:40 PM UTC 24 |
| Finished | Aug 23 05:45:46 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651432262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.1651432262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/247.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.3052346658 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 1753077908 ps |
| CPU time | 4.4 seconds |
| Started | Aug 23 05:45:40 PM UTC 24 |
| Finished | Aug 23 05:45:46 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052346658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.3052346658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/248.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.401001694 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 424175504 ps |
| CPU time | 3.91 seconds |
| Started | Aug 23 05:45:40 PM UTC 24 |
| Finished | Aug 23 05:45:45 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401001694 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.401001694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/249.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_alert_test.1308782301 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 216375753 ps |
| CPU time | 1.59 seconds |
| Started | Aug 23 05:36:27 PM UTC 24 |
| Finished | Aug 23 05:36:29 PM UTC 24 |
| Peak memory | 250968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308782301 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.1308782301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/25.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_check_fail.2105341980 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 710034230 ps |
| CPU time | 8.61 seconds |
| Started | Aug 23 05:36:23 PM UTC 24 |
| Finished | Aug 23 05:36:32 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105341980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.2105341980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/25.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_errs.4110956594 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 947465732 ps |
| CPU time | 12.45 seconds |
| Started | Aug 23 05:36:23 PM UTC 24 |
| Finished | Aug 23 05:36:36 PM UTC 24 |
| Peak memory | 251100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110956594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.4110956594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/25.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_lock.1435122491 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 196765686 ps |
| CPU time | 3.81 seconds |
| Started | Aug 23 05:36:23 PM UTC 24 |
| Finished | Aug 23 05:36:28 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435122491 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.1435122491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/25.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_init_fail.3536156102 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 166310414 ps |
| CPU time | 2.92 seconds |
| Started | Aug 23 05:36:23 PM UTC 24 |
| Finished | Aug 23 05:36:26 PM UTC 24 |
| Peak memory | 251052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536156102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.3536156102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/25.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_macro_errs.1167401198 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 1259988030 ps |
| CPU time | 23.73 seconds |
| Started | Aug 23 05:36:23 PM UTC 24 |
| Finished | Aug 23 05:36:48 PM UTC 24 |
| Peak memory | 257560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167401198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.1167401198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/25.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_key_req.2185423426 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 380640178 ps |
| CPU time | 4.54 seconds |
| Started | Aug 23 05:36:23 PM UTC 24 |
| Finished | Aug 23 05:36:28 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185423426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.2185423426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_esc.3982222609 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 2085924190 ps |
| CPU time | 7.38 seconds |
| Started | Aug 23 05:36:23 PM UTC 24 |
| Finished | Aug 23 05:36:31 PM UTC 24 |
| Peak memory | 250980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982222609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.3982222609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_req.2677357149 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 2048838071 ps |
| CPU time | 12.96 seconds |
| Started | Aug 23 05:36:23 PM UTC 24 |
| Finished | Aug 23 05:36:37 PM UTC 24 |
| Peak memory | 257396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677357149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.2677357149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_regwen.2629913455 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 1110122585 ps |
| CPU time | 5.03 seconds |
| Started | Aug 23 05:36:23 PM UTC 24 |
| Finished | Aug 23 05:36:29 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629913455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.2629913455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/25.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_smoke.2635058076 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1632049353 ps |
| CPU time | 9 seconds |
| Started | Aug 23 05:36:13 PM UTC 24 |
| Finished | Aug 23 05:36:23 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635058076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.2635058076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/25.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all.1199587663 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 21705843143 ps |
| CPU time | 234.66 seconds |
| Started | Aug 23 05:36:26 PM UTC 24 |
| Finished | Aug 23 05:40:23 PM UTC 24 |
| Peak memory | 275180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199587663 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all.1199587663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all_with_rand_reset.2671670963 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 20668891377 ps |
| CPU time | 127.22 seconds |
| Started | Aug 23 05:36:24 PM UTC 24 |
| Finished | Aug 23 05:38:34 PM UTC 24 |
| Peak memory | 269608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2671670963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 25.otp_ctrl_stress_all_with_rand_reset.2671670963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_test_access.2796452153 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 786325336 ps |
| CPU time | 8.17 seconds |
| Started | Aug 23 05:36:24 PM UTC 24 |
| Finished | Aug 23 05:36:33 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796452153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.2796452153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/25.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.2801638957 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 258394506 ps |
| CPU time | 2.76 seconds |
| Started | Aug 23 05:45:40 PM UTC 24 |
| Finished | Aug 23 05:45:44 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801638957 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.2801638957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/250.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.1268101687 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 171090308 ps |
| CPU time | 4.01 seconds |
| Started | Aug 23 05:45:40 PM UTC 24 |
| Finished | Aug 23 05:45:46 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268101687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.1268101687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/251.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.1467214292 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 2262289182 ps |
| CPU time | 4.79 seconds |
| Started | Aug 23 05:45:40 PM UTC 24 |
| Finished | Aug 23 05:45:47 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467214292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.1467214292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/252.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.3413725451 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 378910871 ps |
| CPU time | 3.55 seconds |
| Started | Aug 23 05:45:40 PM UTC 24 |
| Finished | Aug 23 05:45:45 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413725451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.3413725451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/253.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.3277253597 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 225525713 ps |
| CPU time | 3.13 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:45 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277253597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.3277253597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/254.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.3074568621 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 455857417 ps |
| CPU time | 3.58 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:45 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074568621 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.3074568621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/255.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.2661825143 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 141117259 ps |
| CPU time | 3.25 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:45 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661825143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.2661825143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/256.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.3433784482 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 575596268 ps |
| CPU time | 4.06 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:46 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433784482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.3433784482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/257.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.270291418 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 173301708 ps |
| CPU time | 3.7 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:46 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270291418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.270291418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/258.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_alert_test.2011095178 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 196011125 ps |
| CPU time | 2.44 seconds |
| Started | Aug 23 05:36:37 PM UTC 24 |
| Finished | Aug 23 05:36:40 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011095178 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.2011095178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/26.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_check_fail.265151311 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 715104888 ps |
| CPU time | 16.71 seconds |
| Started | Aug 23 05:36:33 PM UTC 24 |
| Finished | Aug 23 05:36:51 PM UTC 24 |
| Peak memory | 257880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265151311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.265151311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/26.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_errs.2726722052 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 700268976 ps |
| CPU time | 16.63 seconds |
| Started | Aug 23 05:36:33 PM UTC 24 |
| Finished | Aug 23 05:36:51 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726722052 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.2726722052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/26.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_lock.1449281828 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 1389586693 ps |
| CPU time | 5.65 seconds |
| Started | Aug 23 05:36:30 PM UTC 24 |
| Finished | Aug 23 05:36:36 PM UTC 24 |
| Peak memory | 253360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449281828 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.1449281828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/26.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_init_fail.2693166508 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 125609072 ps |
| CPU time | 2.62 seconds |
| Started | Aug 23 05:36:28 PM UTC 24 |
| Finished | Aug 23 05:36:32 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693166508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.2693166508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/26.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_macro_errs.157537895 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 157016436 ps |
| CPU time | 4 seconds |
| Started | Aug 23 05:36:33 PM UTC 24 |
| Finished | Aug 23 05:36:38 PM UTC 24 |
| Peak memory | 257560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157537895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.157537895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/26.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_key_req.1856630271 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 662776734 ps |
| CPU time | 6.55 seconds |
| Started | Aug 23 05:36:33 PM UTC 24 |
| Finished | Aug 23 05:36:41 PM UTC 24 |
| Peak memory | 253372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856630271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.1856630271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_esc.2103292245 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 546424199 ps |
| CPU time | 11.92 seconds |
| Started | Aug 23 05:36:30 PM UTC 24 |
| Finished | Aug 23 05:36:43 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103292245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.2103292245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_req.2039370747 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 599805545 ps |
| CPU time | 5.87 seconds |
| Started | Aug 23 05:36:28 PM UTC 24 |
| Finished | Aug 23 05:36:35 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039370747 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.2039370747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_regwen.307436457 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 681596815 ps |
| CPU time | 4.64 seconds |
| Started | Aug 23 05:36:33 PM UTC 24 |
| Finished | Aug 23 05:36:39 PM UTC 24 |
| Peak memory | 257424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307436457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.307436457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/26.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_smoke.885632171 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 477114869 ps |
| CPU time | 4.37 seconds |
| Started | Aug 23 05:36:27 PM UTC 24 |
| Finished | Aug 23 05:36:32 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885632171 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.885632171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/26.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all.2747566403 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 17655913792 ps |
| CPU time | 133.59 seconds |
| Started | Aug 23 05:36:37 PM UTC 24 |
| Finished | Aug 23 05:38:52 PM UTC 24 |
| Peak memory | 274136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747566403 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.2747566403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all_with_rand_reset.3016276292 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 4613944603 ps |
| CPU time | 31.18 seconds |
| Started | Aug 23 05:36:37 PM UTC 24 |
| Finished | Aug 23 05:37:09 PM UTC 24 |
| Peak memory | 257620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3016276292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 26.otp_ctrl_stress_all_with_rand_reset.3016276292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_test_access.3465729534 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 575366306 ps |
| CPU time | 13.65 seconds |
| Started | Aug 23 05:36:33 PM UTC 24 |
| Finished | Aug 23 05:36:48 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465729534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.3465729534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/26.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.2113541564 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 342705799 ps |
| CPU time | 3.15 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:45 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113541564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.2113541564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/260.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.1881460644 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 2031461809 ps |
| CPU time | 5.32 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:47 PM UTC 24 |
| Peak memory | 253332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881460644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.1881460644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/261.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.3050188107 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 454134149 ps |
| CPU time | 3.86 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:46 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050188107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.3050188107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/262.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.3917723360 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 149443646 ps |
| CPU time | 2.85 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:45 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917723360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.3917723360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/263.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.65532080 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 166669358 ps |
| CPU time | 3.53 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:46 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65532080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.65532080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/264.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.2147788098 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 386895219 ps |
| CPU time | 3.11 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:45 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147788098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.2147788098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/265.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.1516505593 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 151849464 ps |
| CPU time | 3.48 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:46 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516505593 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.1516505593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/266.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.1517582535 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 163272697 ps |
| CPU time | 3.41 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:46 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517582535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.1517582535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/267.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.3163402994 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 554742460 ps |
| CPU time | 4.08 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:46 PM UTC 24 |
| Peak memory | 250968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163402994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.3163402994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/268.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.834222881 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 2157524904 ps |
| CPU time | 4.34 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:47 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834222881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.834222881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/269.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_alert_test.3926547605 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 95395642 ps |
| CPU time | 1.78 seconds |
| Started | Aug 23 05:36:45 PM UTC 24 |
| Finished | Aug 23 05:36:48 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926547605 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.3926547605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/27.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_check_fail.656765533 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 950463067 ps |
| CPU time | 7.92 seconds |
| Started | Aug 23 05:36:40 PM UTC 24 |
| Finished | Aug 23 05:36:49 PM UTC 24 |
| Peak memory | 257816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656765533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.656765533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/27.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_errs.1670085749 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 167477280 ps |
| CPU time | 7.09 seconds |
| Started | Aug 23 05:36:40 PM UTC 24 |
| Finished | Aug 23 05:36:49 PM UTC 24 |
| Peak memory | 250704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670085749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.1670085749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/27.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_lock.1006870982 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 301563728 ps |
| CPU time | 6.28 seconds |
| Started | Aug 23 05:36:40 PM UTC 24 |
| Finished | Aug 23 05:36:48 PM UTC 24 |
| Peak memory | 253620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006870982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.1006870982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/27.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_init_fail.1615282955 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 214971728 ps |
| CPU time | 2.59 seconds |
| Started | Aug 23 05:36:40 PM UTC 24 |
| Finished | Aug 23 05:36:44 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615282955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.1615282955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/27.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_macro_errs.313990144 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 9660726957 ps |
| CPU time | 14.74 seconds |
| Started | Aug 23 05:36:40 PM UTC 24 |
| Finished | Aug 23 05:36:56 PM UTC 24 |
| Peak memory | 253696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313990144 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.313990144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/27.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_key_req.3305821299 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 2907558841 ps |
| CPU time | 27.08 seconds |
| Started | Aug 23 05:36:42 PM UTC 24 |
| Finished | Aug 23 05:37:10 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305821299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.3305821299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_esc.3655045455 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 172113485 ps |
| CPU time | 4.02 seconds |
| Started | Aug 23 05:36:40 PM UTC 24 |
| Finished | Aug 23 05:36:45 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655045455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.3655045455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_req.437521713 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 581078281 ps |
| CPU time | 15.43 seconds |
| Started | Aug 23 05:36:40 PM UTC 24 |
| Finished | Aug 23 05:36:57 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437521713 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.437521713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_regwen.2261088377 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 245668123 ps |
| CPU time | 5.52 seconds |
| Started | Aug 23 05:36:42 PM UTC 24 |
| Finished | Aug 23 05:36:49 PM UTC 24 |
| Peak memory | 251272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261088377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.2261088377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/27.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_smoke.794385115 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 2035536572 ps |
| CPU time | 4.32 seconds |
| Started | Aug 23 05:36:37 PM UTC 24 |
| Finished | Aug 23 05:36:42 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794385115 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.794385115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/27.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all.503786280 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 2027574894 ps |
| CPU time | 26.85 seconds |
| Started | Aug 23 05:36:44 PM UTC 24 |
| Finished | Aug 23 05:37:12 PM UTC 24 |
| Peak memory | 253360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503786280 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.503786280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.2846669995 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1807890490 ps |
| CPU time | 68.77 seconds |
| Started | Aug 23 05:36:44 PM UTC 24 |
| Finished | Aug 23 05:37:54 PM UTC 24 |
| Peak memory | 267860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2846669995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 27.otp_ctrl_stress_all_with_rand_reset.2846669995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_test_access.2156822031 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 9152711840 ps |
| CPU time | 16.68 seconds |
| Started | Aug 23 05:36:42 PM UTC 24 |
| Finished | Aug 23 05:37:00 PM UTC 24 |
| Peak memory | 251632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156822031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.2156822031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/27.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.770089081 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 2224484726 ps |
| CPU time | 4.2 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:47 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770089081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.770089081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/270.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.907433677 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 209673836 ps |
| CPU time | 2.89 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:45 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907433677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.907433677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/271.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.4037465658 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 102502619 ps |
| CPU time | 2.7 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:45 PM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037465658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.4037465658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/272.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.4115215369 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 184382005 ps |
| CPU time | 3.3 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:46 PM UTC 24 |
| Peak memory | 251272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115215369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.4115215369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/273.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.337385872 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 249610770 ps |
| CPU time | 3.97 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:46 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337385872 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.337385872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/274.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.3727240437 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 499407078 ps |
| CPU time | 3.34 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:46 PM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727240437 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.3727240437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/275.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.2422754808 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 210891309 ps |
| CPU time | 4.19 seconds |
| Started | Aug 23 05:45:41 PM UTC 24 |
| Finished | Aug 23 05:45:47 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422754808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.2422754808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/276.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.16243891 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 289612589 ps |
| CPU time | 3.63 seconds |
| Started | Aug 23 05:45:42 PM UTC 24 |
| Finished | Aug 23 05:45:47 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16243891 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.16243891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/277.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.207639996 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 102333833 ps |
| CPU time | 3.04 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:57 PM UTC 24 |
| Peak memory | 250796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207639996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.207639996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/278.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.3560075634 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 2224911806 ps |
| CPU time | 4.04 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:58 PM UTC 24 |
| Peak memory | 250748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560075634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.3560075634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/279.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_alert_test.1500516678 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 70972780 ps |
| CPU time | 1.28 seconds |
| Started | Aug 23 05:36:57 PM UTC 24 |
| Finished | Aug 23 05:37:00 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500516678 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.1500516678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/28.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_check_fail.1130960791 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 1590683427 ps |
| CPU time | 13.79 seconds |
| Started | Aug 23 05:36:50 PM UTC 24 |
| Finished | Aug 23 05:37:06 PM UTC 24 |
| Peak memory | 253524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130960791 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.1130960791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/28.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_errs.3282219357 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 1132740473 ps |
| CPU time | 23.74 seconds |
| Started | Aug 23 05:36:50 PM UTC 24 |
| Finished | Aug 23 05:37:15 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282219357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.3282219357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/28.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_lock.2640678836 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 862413485 ps |
| CPU time | 5.04 seconds |
| Started | Aug 23 05:36:50 PM UTC 24 |
| Finished | Aug 23 05:36:57 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640678836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.2640678836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/28.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_macro_errs.2256936890 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 8594162355 ps |
| CPU time | 14.41 seconds |
| Started | Aug 23 05:36:51 PM UTC 24 |
| Finished | Aug 23 05:37:07 PM UTC 24 |
| Peak memory | 255576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256936890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.2256936890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/28.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_key_req.2468304228 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 1180025073 ps |
| CPU time | 23.43 seconds |
| Started | Aug 23 05:36:53 PM UTC 24 |
| Finished | Aug 23 05:37:18 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468304228 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.2468304228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_esc.2309204910 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 943005215 ps |
| CPU time | 12.5 seconds |
| Started | Aug 23 05:36:50 PM UTC 24 |
| Finished | Aug 23 05:37:04 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309204910 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.2309204910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_req.595732290 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 2319738800 ps |
| CPU time | 5.63 seconds |
| Started | Aug 23 05:36:50 PM UTC 24 |
| Finished | Aug 23 05:36:57 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595732290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.595732290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_regwen.1562311479 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 263918449 ps |
| CPU time | 6.86 seconds |
| Started | Aug 23 05:36:53 PM UTC 24 |
| Finished | Aug 23 05:37:01 PM UTC 24 |
| Peak memory | 257424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562311479 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.1562311479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/28.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_smoke.3205113327 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 4706602579 ps |
| CPU time | 8.58 seconds |
| Started | Aug 23 05:36:46 PM UTC 24 |
| Finished | Aug 23 05:36:56 PM UTC 24 |
| Peak memory | 253792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205113327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.3205113327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/28.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all.837913113 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 3776455333 ps |
| CPU time | 40.28 seconds |
| Started | Aug 23 05:36:56 PM UTC 24 |
| Finished | Aug 23 05:37:38 PM UTC 24 |
| Peak memory | 255476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837913113 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.837913113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_test_access.1127497960 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 5380604498 ps |
| CPU time | 29.43 seconds |
| Started | Aug 23 05:36:55 PM UTC 24 |
| Finished | Aug 23 05:37:26 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127497960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.1127497960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/28.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.2766933380 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 569216226 ps |
| CPU time | 3.29 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:57 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766933380 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.2766933380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/280.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.91678050 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 604035822 ps |
| CPU time | 3.52 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:57 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91678050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.91678050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/281.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.2251304676 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 117726321 ps |
| CPU time | 3.84 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:58 PM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251304676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.2251304676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/282.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.1031764571 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 2431929685 ps |
| CPU time | 4.03 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:58 PM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031764571 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.1031764571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/283.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.465923695 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 192270228 ps |
| CPU time | 4.12 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:58 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465923695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.465923695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/284.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.2841163880 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 142894457 ps |
| CPU time | 2.96 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:57 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841163880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.2841163880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/285.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.574921172 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 337568989 ps |
| CPU time | 3.59 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:58 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574921172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.574921172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/286.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.1136103318 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 250197868 ps |
| CPU time | 3.39 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:58 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136103318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.1136103318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/287.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.731397323 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 549594812 ps |
| CPU time | 3.87 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:58 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731397323 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.731397323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/288.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.2933502954 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 315339938 ps |
| CPU time | 3.56 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:58 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933502954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.2933502954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/289.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_alert_test.4197872458 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 176037694 ps |
| CPU time | 1.56 seconds |
| Started | Aug 23 05:37:10 PM UTC 24 |
| Finished | Aug 23 05:37:12 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197872458 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.4197872458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/29.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_check_fail.1716998988 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 517298097 ps |
| CPU time | 14.76 seconds |
| Started | Aug 23 05:37:03 PM UTC 24 |
| Finished | Aug 23 05:37:19 PM UTC 24 |
| Peak memory | 253420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716998988 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.1716998988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/29.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_errs.1683580847 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 1690537391 ps |
| CPU time | 26.01 seconds |
| Started | Aug 23 05:37:02 PM UTC 24 |
| Finished | Aug 23 05:37:30 PM UTC 24 |
| Peak memory | 255392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683580847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.1683580847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/29.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_lock.3099267536 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 9617421968 ps |
| CPU time | 18.63 seconds |
| Started | Aug 23 05:37:01 PM UTC 24 |
| Finished | Aug 23 05:37:21 PM UTC 24 |
| Peak memory | 257588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099267536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.3099267536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/29.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_init_fail.3636145499 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2281339283 ps |
| CPU time | 5.14 seconds |
| Started | Aug 23 05:36:59 PM UTC 24 |
| Finished | Aug 23 05:37:05 PM UTC 24 |
| Peak memory | 250984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636145499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.3636145499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/29.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_macro_errs.1529604705 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 2624763806 ps |
| CPU time | 19.82 seconds |
| Started | Aug 23 05:37:05 PM UTC 24 |
| Finished | Aug 23 05:37:26 PM UTC 24 |
| Peak memory | 255448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529604705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.1529604705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/29.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_key_req.858528633 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 5093560873 ps |
| CPU time | 8.15 seconds |
| Started | Aug 23 05:37:06 PM UTC 24 |
| Finished | Aug 23 05:37:15 PM UTC 24 |
| Peak memory | 253684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858528633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.858528633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_esc.869700151 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 583091933 ps |
| CPU time | 13.63 seconds |
| Started | Aug 23 05:37:01 PM UTC 24 |
| Finished | Aug 23 05:37:16 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869700151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.869700151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_req.2099419966 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 409223157 ps |
| CPU time | 8.25 seconds |
| Started | Aug 23 05:36:59 PM UTC 24 |
| Finished | Aug 23 05:37:08 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099419966 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.2099419966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_regwen.3866469710 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 768472575 ps |
| CPU time | 5.89 seconds |
| Started | Aug 23 05:37:07 PM UTC 24 |
| Finished | Aug 23 05:37:14 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866469710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.3866469710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/29.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_smoke.269306374 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 558590043 ps |
| CPU time | 3.65 seconds |
| Started | Aug 23 05:36:57 PM UTC 24 |
| Finished | Aug 23 05:37:02 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269306374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.269306374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/29.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all.1949632011 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 9746571502 ps |
| CPU time | 57.26 seconds |
| Started | Aug 23 05:37:09 PM UTC 24 |
| Finished | Aug 23 05:38:08 PM UTC 24 |
| Peak memory | 255612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949632011 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.1949632011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_test_access.3217483352 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 791038885 ps |
| CPU time | 7.73 seconds |
| Started | Aug 23 05:37:09 PM UTC 24 |
| Finished | Aug 23 05:37:18 PM UTC 24 |
| Peak memory | 251404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217483352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.3217483352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/29.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.3383538405 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 219452296 ps |
| CPU time | 3.23 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:57 PM UTC 24 |
| Peak memory | 253332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383538405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.3383538405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/290.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.3207979590 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 126171604 ps |
| CPU time | 2.78 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:57 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207979590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.3207979590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/291.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.638574440 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 2735624254 ps |
| CPU time | 5 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:59 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638574440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.638574440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/292.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.787209312 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 282292115 ps |
| CPU time | 3.46 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:58 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787209312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.787209312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/293.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.4200571324 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 123004080 ps |
| CPU time | 2.93 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:57 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200571324 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.4200571324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/294.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.509879178 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 126912546 ps |
| CPU time | 2.65 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:57 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509879178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.509879178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/295.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.2961447240 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 1702767779 ps |
| CPU time | 5.36 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:46:00 PM UTC 24 |
| Peak memory | 251612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961447240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.2961447240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/296.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.3110046455 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 514721627 ps |
| CPU time | 3.41 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:58 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110046455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.3110046455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/297.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.2671621398 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 541451627 ps |
| CPU time | 3.48 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:58 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671621398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.2671621398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/298.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.1894092013 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 404425867 ps |
| CPU time | 2.86 seconds |
| Started | Aug 23 05:45:53 PM UTC 24 |
| Finished | Aug 23 05:45:57 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894092013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.1894092013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/299.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_alert_test.1827021071 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 168329840 ps |
| CPU time | 1.55 seconds |
| Started | Aug 23 05:31:25 PM UTC 24 |
| Finished | Aug 23 05:31:27 PM UTC 24 |
| Peak memory | 251120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827021071 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.1827021071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_background_chks.4263158665 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1096096330 ps |
| CPU time | 15.5 seconds |
| Started | Aug 23 05:31:16 PM UTC 24 |
| Finished | Aug 23 05:31:33 PM UTC 24 |
| Peak memory | 253684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263158665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.4263158665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_check_fail.103737073 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 635242528 ps |
| CPU time | 16.59 seconds |
| Started | Aug 23 05:31:19 PM UTC 24 |
| Finished | Aug 23 05:31:36 PM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103737073 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.103737073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_errs.2731027886 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 997797592 ps |
| CPU time | 13.49 seconds |
| Started | Aug 23 05:31:17 PM UTC 24 |
| Finished | Aug 23 05:31:32 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731027886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.2731027886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_lock.1085297570 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 7011379491 ps |
| CPU time | 13.84 seconds |
| Started | Aug 23 05:31:17 PM UTC 24 |
| Finished | Aug 23 05:31:32 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085297570 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.1085297570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_init_fail.716099053 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 1865376396 ps |
| CPU time | 4.02 seconds |
| Started | Aug 23 05:31:16 PM UTC 24 |
| Finished | Aug 23 05:31:21 PM UTC 24 |
| Peak memory | 251456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716099053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.716099053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_macro_errs.788159981 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 1332340988 ps |
| CPU time | 30.64 seconds |
| Started | Aug 23 05:31:20 PM UTC 24 |
| Finished | Aug 23 05:31:52 PM UTC 24 |
| Peak memory | 253344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788159981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.788159981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_key_req.2384233892 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 18408652099 ps |
| CPU time | 26.23 seconds |
| Started | Aug 23 05:31:21 PM UTC 24 |
| Finished | Aug 23 05:31:49 PM UTC 24 |
| Peak memory | 257556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384233892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.2384233892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_esc.1261540307 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 304455870 ps |
| CPU time | 4.74 seconds |
| Started | Aug 23 05:31:16 PM UTC 24 |
| Finished | Aug 23 05:31:22 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261540307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.1261540307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_req.3478204153 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 265376796 ps |
| CPU time | 6.59 seconds |
| Started | Aug 23 05:31:16 PM UTC 24 |
| Finished | Aug 23 05:31:24 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478204153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.3478204153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_regwen.1821030710 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 128101910 ps |
| CPU time | 2.78 seconds |
| Started | Aug 23 05:31:22 PM UTC 24 |
| Finished | Aug 23 05:31:26 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821030710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.1821030710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_sec_cm.1294724489 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 38312835311 ps |
| CPU time | 146.65 seconds |
| Started | Aug 23 05:31:24 PM UTC 24 |
| Finished | Aug 23 05:33:53 PM UTC 24 |
| Peak memory | 285948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294724489 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.1294724489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_test_access.1142025063 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 150002208 ps |
| CPU time | 4.13 seconds |
| Started | Aug 23 05:31:24 PM UTC 24 |
| Finished | Aug 23 05:31:29 PM UTC 24 |
| Peak memory | 251632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142025063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.1142025063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/3.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_alert_test.1876113542 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 162313305 ps |
| CPU time | 1.44 seconds |
| Started | Aug 23 05:37:21 PM UTC 24 |
| Finished | Aug 23 05:37:23 PM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876113542 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.1876113542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/30.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_check_fail.3824367361 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 539211586 ps |
| CPU time | 9.19 seconds |
| Started | Aug 23 05:37:19 PM UTC 24 |
| Finished | Aug 23 05:37:29 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824367361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.3824367361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/30.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_errs.3982820377 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 288511219 ps |
| CPU time | 13.09 seconds |
| Started | Aug 23 05:37:19 PM UTC 24 |
| Finished | Aug 23 05:37:33 PM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982820377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.3982820377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/30.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_lock.911964836 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1155232890 ps |
| CPU time | 17.29 seconds |
| Started | Aug 23 05:37:19 PM UTC 24 |
| Finished | Aug 23 05:37:37 PM UTC 24 |
| Peak memory | 257468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911964836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.911964836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/30.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_init_fail.1081381925 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 210601722 ps |
| CPU time | 2.93 seconds |
| Started | Aug 23 05:37:13 PM UTC 24 |
| Finished | Aug 23 05:37:17 PM UTC 24 |
| Peak memory | 253308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081381925 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.1081381925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/30.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_macro_errs.3502121031 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 291454012 ps |
| CPU time | 2.91 seconds |
| Started | Aug 23 05:37:19 PM UTC 24 |
| Finished | Aug 23 05:37:23 PM UTC 24 |
| Peak memory | 253336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502121031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.3502121031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/30.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_key_req.4192945611 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 8756559344 ps |
| CPU time | 13.31 seconds |
| Started | Aug 23 05:37:19 PM UTC 24 |
| Finished | Aug 23 05:37:33 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192945611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.4192945611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_esc.3356718591 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 85537521 ps |
| CPU time | 3.87 seconds |
| Started | Aug 23 05:37:14 PM UTC 24 |
| Finished | Aug 23 05:37:19 PM UTC 24 |
| Peak memory | 251092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356718591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.3356718591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_req.3688546688 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 393745008 ps |
| CPU time | 8.79 seconds |
| Started | Aug 23 05:37:13 PM UTC 24 |
| Finished | Aug 23 05:37:23 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688546688 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.3688546688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_regwen.1426453511 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 185128885 ps |
| CPU time | 3.99 seconds |
| Started | Aug 23 05:37:19 PM UTC 24 |
| Finished | Aug 23 05:37:24 PM UTC 24 |
| Peak memory | 251596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426453511 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.1426453511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/30.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_smoke.1620496326 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 2054907553 ps |
| CPU time | 18.11 seconds |
| Started | Aug 23 05:37:11 PM UTC 24 |
| Finished | Aug 23 05:37:31 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620496326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.1620496326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/30.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all.3288085046 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 5703657611 ps |
| CPU time | 44.91 seconds |
| Started | Aug 23 05:37:21 PM UTC 24 |
| Finished | Aug 23 05:38:07 PM UTC 24 |
| Peak memory | 255512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288085046 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.3288085046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all_with_rand_reset.649075335 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 4079693314 ps |
| CPU time | 36.32 seconds |
| Started | Aug 23 05:37:21 PM UTC 24 |
| Finished | Aug 23 05:37:58 PM UTC 24 |
| Peak memory | 271988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=649075335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.649075335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_test_access.2003093961 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 17542519567 ps |
| CPU time | 86.73 seconds |
| Started | Aug 23 05:37:19 PM UTC 24 |
| Finished | Aug 23 05:38:47 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003093961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.2003093961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/30.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_alert_test.2256527920 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 202071216 ps |
| CPU time | 1.62 seconds |
| Started | Aug 23 05:37:32 PM UTC 24 |
| Finished | Aug 23 05:37:35 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256527920 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.2256527920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/31.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_check_fail.1926419580 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 554580534 ps |
| CPU time | 8.44 seconds |
| Started | Aug 23 05:37:27 PM UTC 24 |
| Finished | Aug 23 05:37:37 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926419580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.1926419580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/31.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_errs.1315775670 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 197650773 ps |
| CPU time | 8.63 seconds |
| Started | Aug 23 05:37:25 PM UTC 24 |
| Finished | Aug 23 05:37:35 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315775670 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.1315775670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/31.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_lock.991202343 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 513509893 ps |
| CPU time | 6.8 seconds |
| Started | Aug 23 05:37:25 PM UTC 24 |
| Finished | Aug 23 05:37:33 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991202343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.991202343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/31.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_init_fail.953267185 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 135261969 ps |
| CPU time | 2.42 seconds |
| Started | Aug 23 05:37:25 PM UTC 24 |
| Finished | Aug 23 05:37:28 PM UTC 24 |
| Peak memory | 251268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953267185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.953267185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/31.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_macro_errs.214419801 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 503455010 ps |
| CPU time | 5.91 seconds |
| Started | Aug 23 05:37:28 PM UTC 24 |
| Finished | Aug 23 05:37:35 PM UTC 24 |
| Peak memory | 251328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214419801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.214419801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/31.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_key_req.3221865398 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 241409778 ps |
| CPU time | 8.21 seconds |
| Started | Aug 23 05:37:28 PM UTC 24 |
| Finished | Aug 23 05:37:37 PM UTC 24 |
| Peak memory | 251616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221865398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.3221865398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_esc.1384211914 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 259895372 ps |
| CPU time | 6.62 seconds |
| Started | Aug 23 05:37:25 PM UTC 24 |
| Finished | Aug 23 05:37:33 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384211914 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.1384211914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_req.3294329897 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 880286270 ps |
| CPU time | 10.7 seconds |
| Started | Aug 23 05:37:25 PM UTC 24 |
| Finished | Aug 23 05:37:37 PM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294329897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.3294329897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_regwen.1958078876 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 276358829 ps |
| CPU time | 4.04 seconds |
| Started | Aug 23 05:37:29 PM UTC 24 |
| Finished | Aug 23 05:37:34 PM UTC 24 |
| Peak memory | 251600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958078876 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.1958078876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/31.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_smoke.1852156613 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 531291243 ps |
| CPU time | 7 seconds |
| Started | Aug 23 05:37:22 PM UTC 24 |
| Finished | Aug 23 05:37:30 PM UTC 24 |
| Peak memory | 251488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852156613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.1852156613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/31.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all.4291803093 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 52576929709 ps |
| CPU time | 82.54 seconds |
| Started | Aug 23 05:37:32 PM UTC 24 |
| Finished | Aug 23 05:38:56 PM UTC 24 |
| Peak memory | 257520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291803093 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.4291803093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.1483790085 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 10096284340 ps |
| CPU time | 44.59 seconds |
| Started | Aug 23 05:37:32 PM UTC 24 |
| Finished | Aug 23 05:38:18 PM UTC 24 |
| Peak memory | 267796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1483790085 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 31.otp_ctrl_stress_all_with_rand_reset.1483790085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_test_access.1741132444 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 638965917 ps |
| CPU time | 16.28 seconds |
| Started | Aug 23 05:37:30 PM UTC 24 |
| Finished | Aug 23 05:37:47 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741132444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.1741132444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/31.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_alert_test.2566566035 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 203697417 ps |
| CPU time | 1.55 seconds |
| Started | Aug 23 05:37:40 PM UTC 24 |
| Finished | Aug 23 05:37:43 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566566035 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.2566566035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/32.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_check_fail.1707443074 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 613065720 ps |
| CPU time | 16.39 seconds |
| Started | Aug 23 05:37:36 PM UTC 24 |
| Finished | Aug 23 05:37:54 PM UTC 24 |
| Peak memory | 253464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707443074 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.1707443074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/32.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_errs.2279569501 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 5601645954 ps |
| CPU time | 32.05 seconds |
| Started | Aug 23 05:37:35 PM UTC 24 |
| Finished | Aug 23 05:38:08 PM UTC 24 |
| Peak memory | 259612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279569501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.2279569501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/32.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_lock.3111991444 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 603813882 ps |
| CPU time | 5.29 seconds |
| Started | Aug 23 05:37:35 PM UTC 24 |
| Finished | Aug 23 05:37:41 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111991444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.3111991444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/32.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_init_fail.4110727930 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 269673752 ps |
| CPU time | 3.32 seconds |
| Started | Aug 23 05:37:33 PM UTC 24 |
| Finished | Aug 23 05:37:37 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4110727930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.4110727930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/32.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_macro_errs.2026942404 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 1868541421 ps |
| CPU time | 16.19 seconds |
| Started | Aug 23 05:37:36 PM UTC 24 |
| Finished | Aug 23 05:37:54 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026942404 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.2026942404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/32.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_key_req.1201491977 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 13765090542 ps |
| CPU time | 15.35 seconds |
| Started | Aug 23 05:37:36 PM UTC 24 |
| Finished | Aug 23 05:37:53 PM UTC 24 |
| Peak memory | 253436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201491977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.1201491977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_esc.2392528781 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 362687985 ps |
| CPU time | 4.77 seconds |
| Started | Aug 23 05:37:35 PM UTC 24 |
| Finished | Aug 23 05:37:41 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392528781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.2392528781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_req.1193452094 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1901825693 ps |
| CPU time | 17.13 seconds |
| Started | Aug 23 05:37:35 PM UTC 24 |
| Finished | Aug 23 05:37:53 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193452094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.1193452094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_regwen.997448613 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 556642344 ps |
| CPU time | 8.17 seconds |
| Started | Aug 23 05:37:38 PM UTC 24 |
| Finished | Aug 23 05:37:47 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997448613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.997448613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/32.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_smoke.1185745310 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 314706950 ps |
| CPU time | 4.18 seconds |
| Started | Aug 23 05:37:33 PM UTC 24 |
| Finished | Aug 23 05:37:38 PM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185745310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.1185745310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/32.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all.478334077 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 24648348391 ps |
| CPU time | 161.84 seconds |
| Started | Aug 23 05:37:38 PM UTC 24 |
| Finished | Aug 23 05:40:22 PM UTC 24 |
| Peak memory | 267740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478334077 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.478334077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_test_access.4089554457 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 219757011 ps |
| CPU time | 6.02 seconds |
| Started | Aug 23 05:37:38 PM UTC 24 |
| Finished | Aug 23 05:37:45 PM UTC 24 |
| Peak memory | 251632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089554457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.4089554457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/32.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_alert_test.3164853296 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 770656890 ps |
| CPU time | 1.77 seconds |
| Started | Aug 23 05:38:00 PM UTC 24 |
| Finished | Aug 23 05:38:03 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164853296 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.3164853296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/33.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_errs.3197468952 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 219893317 ps |
| CPU time | 9.37 seconds |
| Started | Aug 23 05:37:45 PM UTC 24 |
| Finished | Aug 23 05:37:55 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197468952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.3197468952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/33.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_lock.3808222840 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 1140799487 ps |
| CPU time | 15.08 seconds |
| Started | Aug 23 05:37:43 PM UTC 24 |
| Finished | Aug 23 05:38:00 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808222840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.3808222840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/33.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_init_fail.3015640902 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 395173952 ps |
| CPU time | 2.85 seconds |
| Started | Aug 23 05:37:40 PM UTC 24 |
| Finished | Aug 23 05:37:44 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015640902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.3015640902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/33.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_macro_errs.312063738 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 930686345 ps |
| CPU time | 16.13 seconds |
| Started | Aug 23 05:37:46 PM UTC 24 |
| Finished | Aug 23 05:38:03 PM UTC 24 |
| Peak memory | 255704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312063738 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.312063738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/33.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_key_req.8932544 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 6495249115 ps |
| CPU time | 15.64 seconds |
| Started | Aug 23 05:37:48 PM UTC 24 |
| Finished | Aug 23 05:38:05 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8932544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.8932544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_esc.2147049366 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 491645452 ps |
| CPU time | 6.16 seconds |
| Started | Aug 23 05:37:42 PM UTC 24 |
| Finished | Aug 23 05:37:50 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147049366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.2147049366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_req.4143018619 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 3332923509 ps |
| CPU time | 21.66 seconds |
| Started | Aug 23 05:37:41 PM UTC 24 |
| Finished | Aug 23 05:38:04 PM UTC 24 |
| Peak memory | 257564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143018619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.4143018619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_regwen.1567221877 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 435473093 ps |
| CPU time | 4.66 seconds |
| Started | Aug 23 05:37:48 PM UTC 24 |
| Finished | Aug 23 05:37:54 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567221877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.1567221877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/33.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_smoke.188435591 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 486647763 ps |
| CPU time | 3.78 seconds |
| Started | Aug 23 05:37:40 PM UTC 24 |
| Finished | Aug 23 05:37:45 PM UTC 24 |
| Peak memory | 257432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188435591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.188435591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/33.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all.999039113 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 5846620354 ps |
| CPU time | 87.18 seconds |
| Started | Aug 23 05:37:54 PM UTC 24 |
| Finished | Aug 23 05:39:23 PM UTC 24 |
| Peak memory | 257756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999039113 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all.999039113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_test_access.2258429945 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 427121276 ps |
| CPU time | 7.61 seconds |
| Started | Aug 23 05:37:51 PM UTC 24 |
| Finished | Aug 23 05:37:59 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258429945 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.2258429945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/33.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_alert_test.3526669727 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 282213713 ps |
| CPU time | 2.09 seconds |
| Started | Aug 23 05:38:08 PM UTC 24 |
| Finished | Aug 23 05:38:11 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526669727 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.3526669727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/34.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_check_fail.1292803748 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 814613476 ps |
| CPU time | 6.45 seconds |
| Started | Aug 23 05:38:00 PM UTC 24 |
| Finished | Aug 23 05:38:08 PM UTC 24 |
| Peak memory | 251568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292803748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.1292803748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/34.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_errs.600892445 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 3732905322 ps |
| CPU time | 11.02 seconds |
| Started | Aug 23 05:38:00 PM UTC 24 |
| Finished | Aug 23 05:38:13 PM UTC 24 |
| Peak memory | 253340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600892445 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.600892445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/34.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_lock.1720310361 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 838894350 ps |
| CPU time | 11.21 seconds |
| Started | Aug 23 05:38:00 PM UTC 24 |
| Finished | Aug 23 05:38:13 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720310361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.1720310361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/34.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_init_fail.579046786 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 105867227 ps |
| CPU time | 2.7 seconds |
| Started | Aug 23 05:38:00 PM UTC 24 |
| Finished | Aug 23 05:38:04 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579046786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.579046786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/34.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_macro_errs.3257982028 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 667000063 ps |
| CPU time | 15.17 seconds |
| Started | Aug 23 05:38:02 PM UTC 24 |
| Finished | Aug 23 05:38:18 PM UTC 24 |
| Peak memory | 253332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257982028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.3257982028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/34.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_key_req.1235714820 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 503773555 ps |
| CPU time | 5.7 seconds |
| Started | Aug 23 05:38:04 PM UTC 24 |
| Finished | Aug 23 05:38:11 PM UTC 24 |
| Peak memory | 250936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235714820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.1235714820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_esc.534287934 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 2711523909 ps |
| CPU time | 9.27 seconds |
| Started | Aug 23 05:38:00 PM UTC 24 |
| Finished | Aug 23 05:38:11 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534287934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.534287934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_req.2944132264 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 275221266 ps |
| CPU time | 4.13 seconds |
| Started | Aug 23 05:38:00 PM UTC 24 |
| Finished | Aug 23 05:38:06 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944132264 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.2944132264 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_regwen.2921484343 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 4293355442 ps |
| CPU time | 9.53 seconds |
| Started | Aug 23 05:38:04 PM UTC 24 |
| Finished | Aug 23 05:38:15 PM UTC 24 |
| Peak memory | 253024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921484343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.2921484343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/34.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_smoke.3531316832 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 655726369 ps |
| CPU time | 5.11 seconds |
| Started | Aug 23 05:38:00 PM UTC 24 |
| Finished | Aug 23 05:38:06 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531316832 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.3531316832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/34.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all.2539293473 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 9788837238 ps |
| CPU time | 55.34 seconds |
| Started | Aug 23 05:38:08 PM UTC 24 |
| Finished | Aug 23 05:39:05 PM UTC 24 |
| Peak memory | 257592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539293473 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.2539293473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.619307794 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 40766966111 ps |
| CPU time | 73.76 seconds |
| Started | Aug 23 05:38:08 PM UTC 24 |
| Finished | Aug 23 05:39:23 PM UTC 24 |
| Peak memory | 267804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=619307794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.619307794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_test_access.2416686199 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 1113344887 ps |
| CPU time | 20.86 seconds |
| Started | Aug 23 05:38:04 PM UTC 24 |
| Finished | Aug 23 05:38:26 PM UTC 24 |
| Peak memory | 251632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416686199 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.2416686199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/34.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_alert_test.1782996405 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 335078481 ps |
| CPU time | 2.09 seconds |
| Started | Aug 23 05:38:15 PM UTC 24 |
| Finished | Aug 23 05:38:18 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782996405 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.1782996405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/35.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_errs.2287444799 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 856563458 ps |
| CPU time | 18.29 seconds |
| Started | Aug 23 05:38:11 PM UTC 24 |
| Finished | Aug 23 05:38:31 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287444799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.2287444799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/35.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_lock.923220997 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 4656149896 ps |
| CPU time | 7.41 seconds |
| Started | Aug 23 05:38:11 PM UTC 24 |
| Finished | Aug 23 05:38:20 PM UTC 24 |
| Peak memory | 253532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923220997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.923220997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/35.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_macro_errs.3691184434 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 1015029431 ps |
| CPU time | 7.73 seconds |
| Started | Aug 23 05:38:11 PM UTC 24 |
| Finished | Aug 23 05:38:20 PM UTC 24 |
| Peak memory | 257548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691184434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.3691184434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/35.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_key_req.4194812781 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 344607654 ps |
| CPU time | 7.09 seconds |
| Started | Aug 23 05:38:13 PM UTC 24 |
| Finished | Aug 23 05:38:21 PM UTC 24 |
| Peak memory | 257468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194812781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.4194812781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_esc.2936036339 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 872421053 ps |
| CPU time | 10.95 seconds |
| Started | Aug 23 05:38:11 PM UTC 24 |
| Finished | Aug 23 05:38:23 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936036339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.2936036339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_req.1025171344 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 331858525 ps |
| CPU time | 6.61 seconds |
| Started | Aug 23 05:38:08 PM UTC 24 |
| Finished | Aug 23 05:38:15 PM UTC 24 |
| Peak memory | 257496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025171344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.1025171344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_regwen.2380334948 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 4645178735 ps |
| CPU time | 11.46 seconds |
| Started | Aug 23 05:38:13 PM UTC 24 |
| Finished | Aug 23 05:38:26 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380334948 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.2380334948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/35.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_smoke.163867636 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 387332866 ps |
| CPU time | 2.92 seconds |
| Started | Aug 23 05:38:08 PM UTC 24 |
| Finished | Aug 23 05:38:12 PM UTC 24 |
| Peak memory | 257624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163867636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.163867636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/35.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all.2977717047 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 846349761 ps |
| CPU time | 17.41 seconds |
| Started | Aug 23 05:38:13 PM UTC 24 |
| Finished | Aug 23 05:38:32 PM UTC 24 |
| Peak memory | 257432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977717047 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.2977717047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.1652228823 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 23483213202 ps |
| CPU time | 186.72 seconds |
| Started | Aug 23 05:38:13 PM UTC 24 |
| Finished | Aug 23 05:41:23 PM UTC 24 |
| Peak memory | 275388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1652228823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 35.otp_ctrl_stress_all_with_rand_reset.1652228823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_test_access.2316902313 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 1600602787 ps |
| CPU time | 12.53 seconds |
| Started | Aug 23 05:38:13 PM UTC 24 |
| Finished | Aug 23 05:38:27 PM UTC 24 |
| Peak memory | 257712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316902313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.2316902313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/35.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_alert_test.1576192556 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 108314215 ps |
| CPU time | 1.54 seconds |
| Started | Aug 23 05:38:25 PM UTC 24 |
| Finished | Aug 23 05:38:27 PM UTC 24 |
| Peak memory | 251132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576192556 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.1576192556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/36.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_check_fail.2684833216 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 4356723996 ps |
| CPU time | 10.08 seconds |
| Started | Aug 23 05:38:20 PM UTC 24 |
| Finished | Aug 23 05:38:31 PM UTC 24 |
| Peak memory | 251760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684833216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.2684833216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/36.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_errs.1452772108 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 797665535 ps |
| CPU time | 18.38 seconds |
| Started | Aug 23 05:38:20 PM UTC 24 |
| Finished | Aug 23 05:38:40 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452772108 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.1452772108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/36.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_lock.1559694628 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 271821915 ps |
| CPU time | 3.05 seconds |
| Started | Aug 23 05:38:19 PM UTC 24 |
| Finished | Aug 23 05:38:23 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559694628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.1559694628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/36.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_init_fail.3739349112 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 505796781 ps |
| CPU time | 2.74 seconds |
| Started | Aug 23 05:38:16 PM UTC 24 |
| Finished | Aug 23 05:38:20 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739349112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.3739349112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/36.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_macro_errs.3055815141 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 2482196665 ps |
| CPU time | 28.81 seconds |
| Started | Aug 23 05:38:21 PM UTC 24 |
| Finished | Aug 23 05:38:52 PM UTC 24 |
| Peak memory | 257880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055815141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.3055815141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/36.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_key_req.857087124 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 169516840 ps |
| CPU time | 2.52 seconds |
| Started | Aug 23 05:38:21 PM UTC 24 |
| Finished | Aug 23 05:38:25 PM UTC 24 |
| Peak memory | 251608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857087124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.857087124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_esc.3830027507 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 224181343 ps |
| CPU time | 5.23 seconds |
| Started | Aug 23 05:38:19 PM UTC 24 |
| Finished | Aug 23 05:38:25 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830027507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.3830027507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_req.2453395665 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 1461468150 ps |
| CPU time | 20.38 seconds |
| Started | Aug 23 05:38:16 PM UTC 24 |
| Finished | Aug 23 05:38:38 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453395665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.2453395665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_regwen.2105655015 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 218476007 ps |
| CPU time | 3.43 seconds |
| Started | Aug 23 05:38:23 PM UTC 24 |
| Finished | Aug 23 05:38:27 PM UTC 24 |
| Peak memory | 250868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105655015 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.2105655015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/36.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_smoke.102931719 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 264459565 ps |
| CPU time | 5.4 seconds |
| Started | Aug 23 05:38:15 PM UTC 24 |
| Finished | Aug 23 05:38:21 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102931719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.102931719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/36.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all.3536282252 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 18242859554 ps |
| CPU time | 93.18 seconds |
| Started | Aug 23 05:38:25 PM UTC 24 |
| Finished | Aug 23 05:40:00 PM UTC 24 |
| Peak memory | 257720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536282252 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.3536282252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_test_access.1248253819 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 831077121 ps |
| CPU time | 6.5 seconds |
| Started | Aug 23 05:38:23 PM UTC 24 |
| Finished | Aug 23 05:38:30 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248253819 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.1248253819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/36.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_alert_test.3146170087 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 238499188 ps |
| CPU time | 1.51 seconds |
| Started | Aug 23 05:38:35 PM UTC 24 |
| Finished | Aug 23 05:38:38 PM UTC 24 |
| Peak memory | 251116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146170087 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.3146170087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/37.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_check_fail.1802091432 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 4217640353 ps |
| CPU time | 28.48 seconds |
| Started | Aug 23 05:38:28 PM UTC 24 |
| Finished | Aug 23 05:38:59 PM UTC 24 |
| Peak memory | 253552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802091432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.1802091432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/37.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_errs.867675611 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 956778731 ps |
| CPU time | 10.85 seconds |
| Started | Aug 23 05:38:28 PM UTC 24 |
| Finished | Aug 23 05:38:41 PM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867675611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.867675611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/37.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_lock.509983752 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 5273977445 ps |
| CPU time | 9.03 seconds |
| Started | Aug 23 05:38:28 PM UTC 24 |
| Finished | Aug 23 05:38:39 PM UTC 24 |
| Peak memory | 253468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509983752 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.509983752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/37.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_macro_errs.2097410123 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 2560066972 ps |
| CPU time | 13.37 seconds |
| Started | Aug 23 05:38:32 PM UTC 24 |
| Finished | Aug 23 05:38:47 PM UTC 24 |
| Peak memory | 253528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097410123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.2097410123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/37.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_key_req.2130367528 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 681982523 ps |
| CPU time | 24.34 seconds |
| Started | Aug 23 05:38:32 PM UTC 24 |
| Finished | Aug 23 05:38:58 PM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130367528 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.2130367528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_esc.190092151 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 226853587 ps |
| CPU time | 5.19 seconds |
| Started | Aug 23 05:38:28 PM UTC 24 |
| Finished | Aug 23 05:38:34 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190092151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.190092151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_req.3903494306 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 900493443 ps |
| CPU time | 12.23 seconds |
| Started | Aug 23 05:38:28 PM UTC 24 |
| Finished | Aug 23 05:38:41 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903494306 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.3903494306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_regwen.3450292908 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 897902219 ps |
| CPU time | 5.03 seconds |
| Started | Aug 23 05:38:32 PM UTC 24 |
| Finished | Aug 23 05:38:38 PM UTC 24 |
| Peak memory | 251028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450292908 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.3450292908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/37.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_smoke.3596508336 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 737387811 ps |
| CPU time | 3.88 seconds |
| Started | Aug 23 05:38:26 PM UTC 24 |
| Finished | Aug 23 05:38:31 PM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596508336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.3596508336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/37.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.3774629909 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 7743157034 ps |
| CPU time | 46.66 seconds |
| Started | Aug 23 05:38:34 PM UTC 24 |
| Finished | Aug 23 05:39:22 PM UTC 24 |
| Peak memory | 255420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774629909 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.3774629909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.2541683453 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 10806144314 ps |
| CPU time | 103.59 seconds |
| Started | Aug 23 05:38:32 PM UTC 24 |
| Finished | Aug 23 05:40:18 PM UTC 24 |
| Peak memory | 272024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2541683453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 37.otp_ctrl_stress_all_with_rand_reset.2541683453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_test_access.3380566693 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 4326044684 ps |
| CPU time | 24.24 seconds |
| Started | Aug 23 05:38:32 PM UTC 24 |
| Finished | Aug 23 05:38:58 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380566693 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.3380566693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/37.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_alert_test.1596919327 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 219864803 ps |
| CPU time | 1.57 seconds |
| Started | Aug 23 05:38:49 PM UTC 24 |
| Finished | Aug 23 05:38:51 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596919327 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.1596919327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/38.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_check_fail.2313590625 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 4473881196 ps |
| CPU time | 28.17 seconds |
| Started | Aug 23 05:38:42 PM UTC 24 |
| Finished | Aug 23 05:39:12 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313590625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.2313590625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/38.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_errs.3203210103 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 1305577884 ps |
| CPU time | 25.62 seconds |
| Started | Aug 23 05:38:42 PM UTC 24 |
| Finished | Aug 23 05:39:09 PM UTC 24 |
| Peak memory | 253276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203210103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.3203210103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/38.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_lock.4154242901 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 5847146051 ps |
| CPU time | 9.47 seconds |
| Started | Aug 23 05:38:40 PM UTC 24 |
| Finished | Aug 23 05:38:51 PM UTC 24 |
| Peak memory | 251764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154242901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.4154242901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/38.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_init_fail.1257154167 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 603625957 ps |
| CPU time | 3.44 seconds |
| Started | Aug 23 05:38:39 PM UTC 24 |
| Finished | Aug 23 05:38:43 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257154167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.1257154167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/38.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_macro_errs.3278777870 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 1964746035 ps |
| CPU time | 16.63 seconds |
| Started | Aug 23 05:38:42 PM UTC 24 |
| Finished | Aug 23 05:39:00 PM UTC 24 |
| Peak memory | 257556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278777870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.3278777870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/38.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_key_req.3903498263 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 1402920134 ps |
| CPU time | 7.5 seconds |
| Started | Aug 23 05:38:45 PM UTC 24 |
| Finished | Aug 23 05:38:53 PM UTC 24 |
| Peak memory | 257724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903498263 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.3903498263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_esc.2317421553 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 223242483 ps |
| CPU time | 9.64 seconds |
| Started | Aug 23 05:38:40 PM UTC 24 |
| Finished | Aug 23 05:38:51 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317421553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.2317421553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_req.3990766821 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 304498403 ps |
| CPU time | 5.27 seconds |
| Started | Aug 23 05:38:39 PM UTC 24 |
| Finished | Aug 23 05:38:45 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990766821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.3990766821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_regwen.3351911924 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 3928878708 ps |
| CPU time | 9.9 seconds |
| Started | Aug 23 05:38:45 PM UTC 24 |
| Finished | Aug 23 05:38:56 PM UTC 24 |
| Peak memory | 251336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351911924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.3351911924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/38.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_smoke.3293233385 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 820845234 ps |
| CPU time | 4.65 seconds |
| Started | Aug 23 05:38:35 PM UTC 24 |
| Finished | Aug 23 05:38:41 PM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293233385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.3293233385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/38.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all.724209574 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 2133982772 ps |
| CPU time | 18.04 seconds |
| Started | Aug 23 05:38:48 PM UTC 24 |
| Finished | Aug 23 05:39:08 PM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724209574 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.724209574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all_with_rand_reset.4251995396 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 9361848542 ps |
| CPU time | 119.61 seconds |
| Started | Aug 23 05:38:46 PM UTC 24 |
| Finished | Aug 23 05:40:48 PM UTC 24 |
| Peak memory | 269932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4251995396 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 38.otp_ctrl_stress_all_with_rand_reset.4251995396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_test_access.13138503 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 2231653969 ps |
| CPU time | 10.26 seconds |
| Started | Aug 23 05:38:45 PM UTC 24 |
| Finished | Aug 23 05:38:56 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13138503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.13138503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/38.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_alert_test.3952135569 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 656423430 ps |
| CPU time | 1.52 seconds |
| Started | Aug 23 05:39:01 PM UTC 24 |
| Finished | Aug 23 05:39:04 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952135569 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.3952135569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/39.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_check_fail.3056041111 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 803108062 ps |
| CPU time | 12.5 seconds |
| Started | Aug 23 05:38:58 PM UTC 24 |
| Finished | Aug 23 05:39:12 PM UTC 24 |
| Peak memory | 251568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056041111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.3056041111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/39.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_errs.1519750259 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 726933858 ps |
| CPU time | 14.9 seconds |
| Started | Aug 23 05:38:55 PM UTC 24 |
| Finished | Aug 23 05:39:11 PM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519750259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.1519750259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/39.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_lock.3264530336 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 544224818 ps |
| CPU time | 12.32 seconds |
| Started | Aug 23 05:38:55 PM UTC 24 |
| Finished | Aug 23 05:39:09 PM UTC 24 |
| Peak memory | 257784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264530336 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.3264530336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/39.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_macro_errs.1829191420 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1786579567 ps |
| CPU time | 26.9 seconds |
| Started | Aug 23 05:38:58 PM UTC 24 |
| Finished | Aug 23 05:39:27 PM UTC 24 |
| Peak memory | 257432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829191420 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.1829191420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/39.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_key_req.4102515687 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 660014439 ps |
| CPU time | 22.29 seconds |
| Started | Aug 23 05:38:58 PM UTC 24 |
| Finished | Aug 23 05:39:22 PM UTC 24 |
| Peak memory | 253340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102515687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.4102515687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_esc.1174481027 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 133464413 ps |
| CPU time | 2.94 seconds |
| Started | Aug 23 05:38:55 PM UTC 24 |
| Finished | Aug 23 05:38:59 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174481027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.1174481027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_req.2654796032 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 526655023 ps |
| CPU time | 12.05 seconds |
| Started | Aug 23 05:38:52 PM UTC 24 |
| Finished | Aug 23 05:39:06 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654796032 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.2654796032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_regwen.4247026078 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 360499683 ps |
| CPU time | 5.72 seconds |
| Started | Aug 23 05:38:59 PM UTC 24 |
| Finished | Aug 23 05:39:06 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247026078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.4247026078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/39.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_smoke.644173887 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 268417394 ps |
| CPU time | 4.04 seconds |
| Started | Aug 23 05:38:52 PM UTC 24 |
| Finished | Aug 23 05:38:58 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644173887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.644173887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/39.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all.769797174 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 943085606 ps |
| CPU time | 18.82 seconds |
| Started | Aug 23 05:39:01 PM UTC 24 |
| Finished | Aug 23 05:39:21 PM UTC 24 |
| Peak memory | 253340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769797174 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all.769797174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_test_access.1695005075 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 529411607 ps |
| CPU time | 9.55 seconds |
| Started | Aug 23 05:38:59 PM UTC 24 |
| Finished | Aug 23 05:39:09 PM UTC 24 |
| Peak memory | 257460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695005075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.1695005075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/39.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_alert_test.3908810285 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 133298094 ps |
| CPU time | 1.42 seconds |
| Started | Aug 23 05:31:36 PM UTC 24 |
| Finished | Aug 23 05:31:39 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908810285 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.3908810285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_background_chks.640039452 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1452023886 ps |
| CPU time | 7.8 seconds |
| Started | Aug 23 05:31:26 PM UTC 24 |
| Finished | Aug 23 05:31:35 PM UTC 24 |
| Peak memory | 257708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640039452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.640039452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_check_fail.4149920092 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1011026419 ps |
| CPU time | 13.55 seconds |
| Started | Aug 23 05:31:31 PM UTC 24 |
| Finished | Aug 23 05:31:46 PM UTC 24 |
| Peak memory | 257784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149920092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.4149920092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_errs.4287572187 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 6631083522 ps |
| CPU time | 11.79 seconds |
| Started | Aug 23 05:31:29 PM UTC 24 |
| Finished | Aug 23 05:31:42 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287572187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.4287572187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_lock.446982750 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3034907158 ps |
| CPU time | 4.52 seconds |
| Started | Aug 23 05:31:28 PM UTC 24 |
| Finished | Aug 23 05:31:34 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446982750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.446982750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_init_fail.1921407708 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 161921127 ps |
| CPU time | 3.12 seconds |
| Started | Aug 23 05:31:26 PM UTC 24 |
| Finished | Aug 23 05:31:30 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921407708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.1921407708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_macro_errs.4061569230 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 10193654411 ps |
| CPU time | 21.6 seconds |
| Started | Aug 23 05:31:32 PM UTC 24 |
| Finished | Aug 23 05:31:55 PM UTC 24 |
| Peak memory | 257756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061569230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.4061569230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_esc.2894487969 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 679690400 ps |
| CPU time | 7.57 seconds |
| Started | Aug 23 05:31:28 PM UTC 24 |
| Finished | Aug 23 05:31:37 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894487969 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.2894487969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_req.2615706605 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 258517066 ps |
| CPU time | 5.94 seconds |
| Started | Aug 23 05:31:27 PM UTC 24 |
| Finished | Aug 23 05:31:34 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615706605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.2615706605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_regwen.2067735478 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 141392467 ps |
| CPU time | 4.8 seconds |
| Started | Aug 23 05:31:33 PM UTC 24 |
| Finished | Aug 23 05:31:39 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067735478 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.2067735478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_sec_cm.747237431 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 13887835429 ps |
| CPU time | 160.85 seconds |
| Started | Aug 23 05:31:35 PM UTC 24 |
| Finished | Aug 23 05:34:18 PM UTC 24 |
| Peak memory | 289980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747237431 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.747237431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_smoke.62610318 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 1742912129 ps |
| CPU time | 6.72 seconds |
| Started | Aug 23 05:31:25 PM UTC 24 |
| Finished | Aug 23 05:31:33 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62610318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.62610318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all.3710286737 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 18868017794 ps |
| CPU time | 156.72 seconds |
| Started | Aug 23 05:31:35 PM UTC 24 |
| Finished | Aug 23 05:34:14 PM UTC 24 |
| Peak memory | 278384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710286737 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.3710286737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_test_access.2538357011 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 616755509 ps |
| CPU time | 8.99 seconds |
| Started | Aug 23 05:31:33 PM UTC 24 |
| Finished | Aug 23 05:31:43 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538357011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.2538357011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/4.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_alert_test.3972031338 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 50688037 ps |
| CPU time | 1.54 seconds |
| Started | Aug 23 05:39:16 PM UTC 24 |
| Finished | Aug 23 05:39:19 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972031338 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.3972031338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/40.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_check_fail.1078778279 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 554821233 ps |
| CPU time | 12.4 seconds |
| Started | Aug 23 05:39:08 PM UTC 24 |
| Finished | Aug 23 05:39:22 PM UTC 24 |
| Peak memory | 257588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078778279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.1078778279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/40.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_errs.279189714 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 1271179266 ps |
| CPU time | 9.71 seconds |
| Started | Aug 23 05:39:07 PM UTC 24 |
| Finished | Aug 23 05:39:18 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279189714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.279189714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/40.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_lock.3751045617 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 24049118959 ps |
| CPU time | 33.25 seconds |
| Started | Aug 23 05:39:07 PM UTC 24 |
| Finished | Aug 23 05:39:41 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751045617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.3751045617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/40.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_init_fail.626699105 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 2449555615 ps |
| CPU time | 4.64 seconds |
| Started | Aug 23 05:39:01 PM UTC 24 |
| Finished | Aug 23 05:39:07 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626699105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.626699105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/40.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_macro_errs.2502671806 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 1871611005 ps |
| CPU time | 23.39 seconds |
| Started | Aug 23 05:39:08 PM UTC 24 |
| Finished | Aug 23 05:39:33 PM UTC 24 |
| Peak memory | 257816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502671806 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.2502671806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/40.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_key_req.1714740544 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 892018288 ps |
| CPU time | 9.88 seconds |
| Started | Aug 23 05:39:10 PM UTC 24 |
| Finished | Aug 23 05:39:21 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714740544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.1714740544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_esc.481763516 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 3651860455 ps |
| CPU time | 6.72 seconds |
| Started | Aug 23 05:39:07 PM UTC 24 |
| Finished | Aug 23 05:39:15 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481763516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.481763516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_req.93096846 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 397794414 ps |
| CPU time | 9.03 seconds |
| Started | Aug 23 05:39:04 PM UTC 24 |
| Finished | Aug 23 05:39:15 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93096846 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.93096846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_regwen.2606567280 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 143443627 ps |
| CPU time | 4.28 seconds |
| Started | Aug 23 05:39:10 PM UTC 24 |
| Finished | Aug 23 05:39:15 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606567280 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.2606567280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/40.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_smoke.3591384165 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 3684839810 ps |
| CPU time | 5.1 seconds |
| Started | Aug 23 05:39:01 PM UTC 24 |
| Finished | Aug 23 05:39:08 PM UTC 24 |
| Peak memory | 251744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591384165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.3591384165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/40.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all.3754302783 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 34019595638 ps |
| CPU time | 105.55 seconds |
| Started | Aug 23 05:39:16 PM UTC 24 |
| Finished | Aug 23 05:41:03 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754302783 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.3754302783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all_with_rand_reset.873113189 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 8076140723 ps |
| CPU time | 116.5 seconds |
| Started | Aug 23 05:39:12 PM UTC 24 |
| Finished | Aug 23 05:41:10 PM UTC 24 |
| Peak memory | 274100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=873113189 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.873113189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_test_access.2783123955 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 668251325 ps |
| CPU time | 12.07 seconds |
| Started | Aug 23 05:39:10 PM UTC 24 |
| Finished | Aug 23 05:39:23 PM UTC 24 |
| Peak memory | 257716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783123955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.2783123955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/40.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_alert_test.3886870796 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 106259709 ps |
| CPU time | 1.43 seconds |
| Started | Aug 23 05:39:28 PM UTC 24 |
| Finished | Aug 23 05:39:30 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886870796 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.3886870796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/41.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_check_fail.2498616474 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 2669267807 ps |
| CPU time | 24.4 seconds |
| Started | Aug 23 05:39:18 PM UTC 24 |
| Finished | Aug 23 05:39:44 PM UTC 24 |
| Peak memory | 253744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498616474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.2498616474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/41.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_errs.1796724836 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 859789927 ps |
| CPU time | 10.35 seconds |
| Started | Aug 23 05:39:16 PM UTC 24 |
| Finished | Aug 23 05:39:28 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796724836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.1796724836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/41.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_lock.2408976242 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 6781329897 ps |
| CPU time | 15.5 seconds |
| Started | Aug 23 05:39:16 PM UTC 24 |
| Finished | Aug 23 05:39:33 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408976242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.2408976242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/41.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_init_fail.1048704729 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 1782813625 ps |
| CPU time | 4.53 seconds |
| Started | Aug 23 05:39:16 PM UTC 24 |
| Finished | Aug 23 05:39:22 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048704729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.1048704729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/41.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_macro_errs.1822573214 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 1140591605 ps |
| CPU time | 20.84 seconds |
| Started | Aug 23 05:39:20 PM UTC 24 |
| Finished | Aug 23 05:39:42 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822573214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.1822573214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/41.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_key_req.3887467655 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 2567505627 ps |
| CPU time | 30 seconds |
| Started | Aug 23 05:39:23 PM UTC 24 |
| Finished | Aug 23 05:39:54 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887467655 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.3887467655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_esc.2981571963 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 440648015 ps |
| CPU time | 9.58 seconds |
| Started | Aug 23 05:39:16 PM UTC 24 |
| Finished | Aug 23 05:39:27 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981571963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.2981571963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_req.2192787243 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 344928062 ps |
| CPU time | 4.74 seconds |
| Started | Aug 23 05:39:16 PM UTC 24 |
| Finished | Aug 23 05:39:22 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192787243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.2192787243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_regwen.1608772867 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 132898139 ps |
| CPU time | 4.25 seconds |
| Started | Aug 23 05:39:23 PM UTC 24 |
| Finished | Aug 23 05:39:28 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608772867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.1608772867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/41.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_smoke.2295702560 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 700898133 ps |
| CPU time | 6.58 seconds |
| Started | Aug 23 05:39:16 PM UTC 24 |
| Finished | Aug 23 05:39:24 PM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295702560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.2295702560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/41.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all.4002811247 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 19028223737 ps |
| CPU time | 157.25 seconds |
| Started | Aug 23 05:39:23 PM UTC 24 |
| Finished | Aug 23 05:42:03 PM UTC 24 |
| Peak memory | 284468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002811247 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all.4002811247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.2395583130 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 17233487447 ps |
| CPU time | 66.97 seconds |
| Started | Aug 23 05:39:23 PM UTC 24 |
| Finished | Aug 23 05:40:31 PM UTC 24 |
| Peak memory | 274068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2395583130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 41.otp_ctrl_stress_all_with_rand_reset.2395583130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_test_access.3980042226 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 1694688280 ps |
| CPU time | 23.63 seconds |
| Started | Aug 23 05:39:23 PM UTC 24 |
| Finished | Aug 23 05:39:48 PM UTC 24 |
| Peak memory | 253356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980042226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.3980042226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/41.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_alert_test.1377829890 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 258731814 ps |
| CPU time | 1.82 seconds |
| Started | Aug 23 05:39:34 PM UTC 24 |
| Finished | Aug 23 05:39:37 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377829890 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.1377829890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/42.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_check_fail.1464660483 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 357901579 ps |
| CPU time | 6.91 seconds |
| Started | Aug 23 05:39:32 PM UTC 24 |
| Finished | Aug 23 05:39:40 PM UTC 24 |
| Peak memory | 256956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464660483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.1464660483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/42.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_errs.2330625851 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 22836111881 ps |
| CPU time | 51.61 seconds |
| Started | Aug 23 05:39:28 PM UTC 24 |
| Finished | Aug 23 05:40:21 PM UTC 24 |
| Peak memory | 261532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330625851 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.2330625851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/42.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_lock.3568265114 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 741525195 ps |
| CPU time | 19.15 seconds |
| Started | Aug 23 05:39:28 PM UTC 24 |
| Finished | Aug 23 05:39:48 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568265114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.3568265114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/42.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_init_fail.1864240836 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 150980253 ps |
| CPU time | 3.21 seconds |
| Started | Aug 23 05:39:28 PM UTC 24 |
| Finished | Aug 23 05:39:32 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864240836 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.1864240836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/42.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_macro_errs.3957190244 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 298359645 ps |
| CPU time | 4.37 seconds |
| Started | Aug 23 05:39:32 PM UTC 24 |
| Finished | Aug 23 05:39:37 PM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957190244 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.3957190244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/42.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_key_req.3065741839 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 2353511854 ps |
| CPU time | 5.53 seconds |
| Started | Aug 23 05:39:32 PM UTC 24 |
| Finished | Aug 23 05:39:39 PM UTC 24 |
| Peak memory | 251624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065741839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.3065741839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_esc.2289702869 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3766963747 ps |
| CPU time | 20.87 seconds |
| Started | Aug 23 05:39:28 PM UTC 24 |
| Finished | Aug 23 05:39:50 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289702869 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.2289702869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_req.2044507692 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 878268623 ps |
| CPU time | 20.33 seconds |
| Started | Aug 23 05:39:28 PM UTC 24 |
| Finished | Aug 23 05:39:49 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044507692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.2044507692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_regwen.1795321134 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 503907756 ps |
| CPU time | 5.87 seconds |
| Started | Aug 23 05:39:32 PM UTC 24 |
| Finished | Aug 23 05:39:39 PM UTC 24 |
| Peak memory | 250664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795321134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.1795321134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/42.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_smoke.905902626 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 218532750 ps |
| CPU time | 4.44 seconds |
| Started | Aug 23 05:39:28 PM UTC 24 |
| Finished | Aug 23 05:39:33 PM UTC 24 |
| Peak memory | 257816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905902626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.905902626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/42.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all.3505297960 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 39734462090 ps |
| CPU time | 290.03 seconds |
| Started | Aug 23 05:39:34 PM UTC 24 |
| Finished | Aug 23 05:44:28 PM UTC 24 |
| Peak memory | 326744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505297960 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.3505297960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_test_access.485632395 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 305034758 ps |
| CPU time | 7.98 seconds |
| Started | Aug 23 05:39:32 PM UTC 24 |
| Finished | Aug 23 05:39:41 PM UTC 24 |
| Peak memory | 253716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485632395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.485632395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/42.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_alert_test.3526870263 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 53592659 ps |
| CPU time | 1.5 seconds |
| Started | Aug 23 05:39:46 PM UTC 24 |
| Finished | Aug 23 05:39:49 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526870263 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.3526870263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/43.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_check_fail.4015272645 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 401745650 ps |
| CPU time | 10.81 seconds |
| Started | Aug 23 05:39:41 PM UTC 24 |
| Finished | Aug 23 05:39:53 PM UTC 24 |
| Peak memory | 257516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015272645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.4015272645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/43.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_errs.1471502005 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 336195395 ps |
| CPU time | 13.84 seconds |
| Started | Aug 23 05:39:40 PM UTC 24 |
| Finished | Aug 23 05:39:55 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471502005 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.1471502005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/43.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_lock.3062743402 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 270747711 ps |
| CPU time | 6.4 seconds |
| Started | Aug 23 05:39:40 PM UTC 24 |
| Finished | Aug 23 05:39:47 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062743402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.3062743402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/43.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_init_fail.3430147253 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 578449322 ps |
| CPU time | 3.79 seconds |
| Started | Aug 23 05:39:35 PM UTC 24 |
| Finished | Aug 23 05:39:40 PM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430147253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.3430147253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/43.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_macro_errs.2654668882 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 448155540 ps |
| CPU time | 3.37 seconds |
| Started | Aug 23 05:39:41 PM UTC 24 |
| Finished | Aug 23 05:39:46 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654668882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.2654668882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/43.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_key_req.3453119357 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 2625284147 ps |
| CPU time | 23.19 seconds |
| Started | Aug 23 05:39:43 PM UTC 24 |
| Finished | Aug 23 05:40:08 PM UTC 24 |
| Peak memory | 251616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453119357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.3453119357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_esc.771167361 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 177883675 ps |
| CPU time | 4.14 seconds |
| Started | Aug 23 05:39:38 PM UTC 24 |
| Finished | Aug 23 05:39:44 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771167361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.771167361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_req.3618388272 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 1257482429 ps |
| CPU time | 14.15 seconds |
| Started | Aug 23 05:39:37 PM UTC 24 |
| Finished | Aug 23 05:39:53 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618388272 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.3618388272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_regwen.2884080882 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 2037530499 ps |
| CPU time | 6.16 seconds |
| Started | Aug 23 05:39:43 PM UTC 24 |
| Finished | Aug 23 05:39:51 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884080882 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.2884080882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/43.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_smoke.4145911996 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 4548480530 ps |
| CPU time | 13.49 seconds |
| Started | Aug 23 05:39:34 PM UTC 24 |
| Finished | Aug 23 05:39:49 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145911996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.4145911996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/43.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all.3537873641 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 2015991165 ps |
| CPU time | 25.52 seconds |
| Started | Aug 23 05:39:45 PM UTC 24 |
| Finished | Aug 23 05:40:12 PM UTC 24 |
| Peak memory | 253396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537873641 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.3537873641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_test_access.3592219079 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 2486238342 ps |
| CPU time | 23.37 seconds |
| Started | Aug 23 05:39:43 PM UTC 24 |
| Finished | Aug 23 05:40:08 PM UTC 24 |
| Peak memory | 251632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592219079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.3592219079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/43.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_alert_test.1290167349 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 713825751 ps |
| CPU time | 2.34 seconds |
| Started | Aug 23 05:39:57 PM UTC 24 |
| Finished | Aug 23 05:40:00 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290167349 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.1290167349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/44.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_check_fail.3694271462 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 247952685 ps |
| CPU time | 7.02 seconds |
| Started | Aug 23 05:39:52 PM UTC 24 |
| Finished | Aug 23 05:40:01 PM UTC 24 |
| Peak memory | 257712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694271462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.3694271462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/44.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_errs.1263057208 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 4178245740 ps |
| CPU time | 30.61 seconds |
| Started | Aug 23 05:39:52 PM UTC 24 |
| Finished | Aug 23 05:40:24 PM UTC 24 |
| Peak memory | 257716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263057208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.1263057208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/44.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_lock.3548572839 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 1032077541 ps |
| CPU time | 6.64 seconds |
| Started | Aug 23 05:39:50 PM UTC 24 |
| Finished | Aug 23 05:39:57 PM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548572839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.3548572839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/44.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_init_fail.725233653 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 133435955 ps |
| CPU time | 3.11 seconds |
| Started | Aug 23 05:39:50 PM UTC 24 |
| Finished | Aug 23 05:39:54 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725233653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.725233653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/44.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_macro_errs.4197340689 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 2192248721 ps |
| CPU time | 12.59 seconds |
| Started | Aug 23 05:39:52 PM UTC 24 |
| Finished | Aug 23 05:40:06 PM UTC 24 |
| Peak memory | 251240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197340689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.4197340689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/44.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_key_req.2738270182 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 891647927 ps |
| CPU time | 16.25 seconds |
| Started | Aug 23 05:39:53 PM UTC 24 |
| Finished | Aug 23 05:40:10 PM UTC 24 |
| Peak memory | 251644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738270182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.2738270182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_esc.660870928 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 125668328 ps |
| CPU time | 4.94 seconds |
| Started | Aug 23 05:39:50 PM UTC 24 |
| Finished | Aug 23 05:39:56 PM UTC 24 |
| Peak memory | 251108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660870928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.660870928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_req.698401534 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 1272529763 ps |
| CPU time | 16.62 seconds |
| Started | Aug 23 05:39:50 PM UTC 24 |
| Finished | Aug 23 05:40:08 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698401534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.698401534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_regwen.1958310332 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2481778351 ps |
| CPU time | 5.66 seconds |
| Started | Aug 23 05:39:54 PM UTC 24 |
| Finished | Aug 23 05:40:01 PM UTC 24 |
| Peak memory | 251336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958310332 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.1958310332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/44.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_smoke.2042856825 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 362180092 ps |
| CPU time | 2.67 seconds |
| Started | Aug 23 05:39:50 PM UTC 24 |
| Finished | Aug 23 05:39:53 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042856825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.2042856825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/44.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all.3944079328 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 24356548497 ps |
| CPU time | 145.36 seconds |
| Started | Aug 23 05:39:54 PM UTC 24 |
| Finished | Aug 23 05:42:22 PM UTC 24 |
| Peak memory | 271896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944079328 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.3944079328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_test_access.2318482633 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 213002613 ps |
| CPU time | 3.89 seconds |
| Started | Aug 23 05:39:54 PM UTC 24 |
| Finished | Aug 23 05:39:59 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318482633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.2318482633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/44.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_alert_test.797853782 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 51439970 ps |
| CPU time | 1.46 seconds |
| Started | Aug 23 05:40:10 PM UTC 24 |
| Finished | Aug 23 05:40:13 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797853782 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.797853782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/45.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_check_fail.184404114 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 3198604245 ps |
| CPU time | 15.97 seconds |
| Started | Aug 23 05:40:02 PM UTC 24 |
| Finished | Aug 23 05:40:19 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184404114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.184404114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/45.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_errs.1539329039 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 2289490882 ps |
| CPU time | 27.11 seconds |
| Started | Aug 23 05:40:02 PM UTC 24 |
| Finished | Aug 23 05:40:30 PM UTC 24 |
| Peak memory | 255224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539329039 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.1539329039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/45.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_lock.3876108547 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 3969832180 ps |
| CPU time | 29.15 seconds |
| Started | Aug 23 05:40:02 PM UTC 24 |
| Finished | Aug 23 05:40:32 PM UTC 24 |
| Peak memory | 253752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876108547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.3876108547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/45.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_init_fail.923046379 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 346743832 ps |
| CPU time | 2.81 seconds |
| Started | Aug 23 05:39:57 PM UTC 24 |
| Finished | Aug 23 05:40:00 PM UTC 24 |
| Peak memory | 251492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923046379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.923046379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/45.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_macro_errs.3266435503 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 357986273 ps |
| CPU time | 3.68 seconds |
| Started | Aug 23 05:40:02 PM UTC 24 |
| Finished | Aug 23 05:40:07 PM UTC 24 |
| Peak memory | 251672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266435503 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.3266435503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/45.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_key_req.2156117857 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 3365499598 ps |
| CPU time | 16.8 seconds |
| Started | Aug 23 05:40:03 PM UTC 24 |
| Finished | Aug 23 05:40:21 PM UTC 24 |
| Peak memory | 253628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156117857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.2156117857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_esc.2948948928 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 796769726 ps |
| CPU time | 5.75 seconds |
| Started | Aug 23 05:40:02 PM UTC 24 |
| Finished | Aug 23 05:40:09 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948948928 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.2948948928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_req.3485338790 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1226219814 ps |
| CPU time | 18.37 seconds |
| Started | Aug 23 05:39:59 PM UTC 24 |
| Finished | Aug 23 05:40:18 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3485338790 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.3485338790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_regwen.2188897466 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 2336764138 ps |
| CPU time | 5.88 seconds |
| Started | Aug 23 05:40:06 PM UTC 24 |
| Finished | Aug 23 05:40:13 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188897466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.2188897466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/45.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_smoke.3978516066 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 304605980 ps |
| CPU time | 8 seconds |
| Started | Aug 23 05:39:57 PM UTC 24 |
| Finished | Aug 23 05:40:06 PM UTC 24 |
| Peak memory | 257440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978516066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.3978516066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/45.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all.68981882 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 4168511135 ps |
| CPU time | 43.87 seconds |
| Started | Aug 23 05:40:10 PM UTC 24 |
| Finished | Aug 23 05:40:56 PM UTC 24 |
| Peak memory | 255644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68981882 -assert nopostproc +UVM_TESTNAME= otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.68981882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.157768773 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 45601563510 ps |
| CPU time | 83.66 seconds |
| Started | Aug 23 05:40:08 PM UTC 24 |
| Finished | Aug 23 05:41:34 PM UTC 24 |
| Peak memory | 267860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=157768773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.157768773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_test_access.3218691142 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 3810156048 ps |
| CPU time | 20.43 seconds |
| Started | Aug 23 05:40:08 PM UTC 24 |
| Finished | Aug 23 05:40:30 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218691142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.3218691142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/45.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_alert_test.3116246882 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 182222902 ps |
| CPU time | 1.46 seconds |
| Started | Aug 23 05:40:23 PM UTC 24 |
| Finished | Aug 23 05:40:25 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116246882 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.3116246882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/46.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_check_fail.2472073924 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 2505932898 ps |
| CPU time | 19.08 seconds |
| Started | Aug 23 05:40:16 PM UTC 24 |
| Finished | Aug 23 05:40:36 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472073924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.2472073924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/46.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_errs.1344490030 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 369851125 ps |
| CPU time | 7.09 seconds |
| Started | Aug 23 05:40:15 PM UTC 24 |
| Finished | Aug 23 05:40:23 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344490030 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.1344490030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/46.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_lock.4096944663 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 13448939816 ps |
| CPU time | 23.44 seconds |
| Started | Aug 23 05:40:13 PM UTC 24 |
| Finished | Aug 23 05:40:38 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096944663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.4096944663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/46.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_init_fail.1010265107 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 427732932 ps |
| CPU time | 3.36 seconds |
| Started | Aug 23 05:40:10 PM UTC 24 |
| Finished | Aug 23 05:40:15 PM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010265107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.1010265107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/46.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_macro_errs.2169851834 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 5094785566 ps |
| CPU time | 23.46 seconds |
| Started | Aug 23 05:40:17 PM UTC 24 |
| Finished | Aug 23 05:40:42 PM UTC 24 |
| Peak memory | 257776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169851834 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.2169851834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/46.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_key_req.4049010857 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 1380741695 ps |
| CPU time | 4.62 seconds |
| Started | Aug 23 05:40:20 PM UTC 24 |
| Finished | Aug 23 05:40:26 PM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049010857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.4049010857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_req.229147525 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 912173779 ps |
| CPU time | 10.23 seconds |
| Started | Aug 23 05:40:12 PM UTC 24 |
| Finished | Aug 23 05:40:23 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229147525 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.229147525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_regwen.3203637333 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 116242056 ps |
| CPU time | 3.39 seconds |
| Started | Aug 23 05:40:20 PM UTC 24 |
| Finished | Aug 23 05:40:25 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203637333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.3203637333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/46.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_smoke.1051328354 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 569356421 ps |
| CPU time | 6.91 seconds |
| Started | Aug 23 05:40:10 PM UTC 24 |
| Finished | Aug 23 05:40:18 PM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051328354 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.1051328354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/46.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all.4039100850 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 21886023359 ps |
| CPU time | 173.23 seconds |
| Started | Aug 23 05:40:23 PM UTC 24 |
| Finished | Aug 23 05:43:19 PM UTC 24 |
| Peak memory | 267860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039100850 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.4039100850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.2434453567 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 8804936744 ps |
| CPU time | 63.98 seconds |
| Started | Aug 23 05:40:21 PM UTC 24 |
| Finished | Aug 23 05:41:26 PM UTC 24 |
| Peak memory | 267900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2434453567 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 46.otp_ctrl_stress_all_with_rand_reset.2434453567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_test_access.1412976870 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 361589801 ps |
| CPU time | 4.07 seconds |
| Started | Aug 23 05:40:21 PM UTC 24 |
| Finished | Aug 23 05:40:26 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412976870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.1412976870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/46.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_alert_test.1425995147 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 797292706 ps |
| CPU time | 1.48 seconds |
| Started | Aug 23 05:40:34 PM UTC 24 |
| Finished | Aug 23 05:40:37 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425995147 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.1425995147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/47.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_check_fail.3336468230 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 1604759658 ps |
| CPU time | 12.45 seconds |
| Started | Aug 23 05:40:28 PM UTC 24 |
| Finished | Aug 23 05:40:42 PM UTC 24 |
| Peak memory | 257692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336468230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.3336468230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/47.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_errs.1419384866 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 220160563 ps |
| CPU time | 8.43 seconds |
| Started | Aug 23 05:40:28 PM UTC 24 |
| Finished | Aug 23 05:40:38 PM UTC 24 |
| Peak memory | 251096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419384866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.1419384866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/47.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_lock.3989004847 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 9134292597 ps |
| CPU time | 28.83 seconds |
| Started | Aug 23 05:40:28 PM UTC 24 |
| Finished | Aug 23 05:40:58 PM UTC 24 |
| Peak memory | 257780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989004847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.3989004847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/47.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_init_fail.4288775012 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 524688635 ps |
| CPU time | 3.35 seconds |
| Started | Aug 23 05:40:27 PM UTC 24 |
| Finished | Aug 23 05:40:32 PM UTC 24 |
| Peak memory | 251068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288775012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.4288775012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/47.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_macro_errs.3904444315 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 1018271257 ps |
| CPU time | 12.28 seconds |
| Started | Aug 23 05:40:28 PM UTC 24 |
| Finished | Aug 23 05:40:42 PM UTC 24 |
| Peak memory | 257420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904444315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.3904444315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/47.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_key_req.2594017720 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 1002388436 ps |
| CPU time | 14.24 seconds |
| Started | Aug 23 05:40:28 PM UTC 24 |
| Finished | Aug 23 05:40:44 PM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594017720 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.2594017720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_esc.1620968046 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 1657675959 ps |
| CPU time | 6.4 seconds |
| Started | Aug 23 05:40:28 PM UTC 24 |
| Finished | Aug 23 05:40:35 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620968046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.1620968046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_req.4219892612 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 164911900 ps |
| CPU time | 3.89 seconds |
| Started | Aug 23 05:40:27 PM UTC 24 |
| Finished | Aug 23 05:40:33 PM UTC 24 |
| Peak memory | 250948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219892612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.4219892612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_regwen.2131729484 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 1141567865 ps |
| CPU time | 7.08 seconds |
| Started | Aug 23 05:40:33 PM UTC 24 |
| Finished | Aug 23 05:40:42 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131729484 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.2131729484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/47.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_smoke.2052917650 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 473472096 ps |
| CPU time | 5.04 seconds |
| Started | Aug 23 05:40:23 PM UTC 24 |
| Finished | Aug 23 05:40:29 PM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052917650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.2052917650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/47.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all.2180859909 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 12958408474 ps |
| CPU time | 89.7 seconds |
| Started | Aug 23 05:40:33 PM UTC 24 |
| Finished | Aug 23 05:42:06 PM UTC 24 |
| Peak memory | 257448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180859909 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.2180859909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all_with_rand_reset.1457794952 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 60330087053 ps |
| CPU time | 166.39 seconds |
| Started | Aug 23 05:40:33 PM UTC 24 |
| Finished | Aug 23 05:43:23 PM UTC 24 |
| Peak memory | 290672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1457794952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 47.otp_ctrl_stress_all_with_rand_reset.1457794952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_test_access.3581821080 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 1406456803 ps |
| CPU time | 20.25 seconds |
| Started | Aug 23 05:40:33 PM UTC 24 |
| Finished | Aug 23 05:40:55 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581821080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.3581821080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/47.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_alert_test.1170923110 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 46125695 ps |
| CPU time | 1.35 seconds |
| Started | Aug 23 05:40:43 PM UTC 24 |
| Finished | Aug 23 05:40:46 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170923110 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.1170923110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/48.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_check_fail.2840155524 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 17678866000 ps |
| CPU time | 37.33 seconds |
| Started | Aug 23 05:40:39 PM UTC 24 |
| Finished | Aug 23 05:41:17 PM UTC 24 |
| Peak memory | 257776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840155524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.2840155524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/48.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_errs.485110854 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 629696410 ps |
| CPU time | 15.25 seconds |
| Started | Aug 23 05:40:39 PM UTC 24 |
| Finished | Aug 23 05:40:55 PM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485110854 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.485110854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/48.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_lock.4219034310 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 5479647099 ps |
| CPU time | 18.54 seconds |
| Started | Aug 23 05:40:39 PM UTC 24 |
| Finished | Aug 23 05:40:58 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219034310 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.4219034310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/48.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_init_fail.3629359965 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 237686723 ps |
| CPU time | 2.85 seconds |
| Started | Aug 23 05:40:34 PM UTC 24 |
| Finished | Aug 23 05:40:38 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629359965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.3629359965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/48.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_macro_errs.16386868 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 16144230230 ps |
| CPU time | 37.83 seconds |
| Started | Aug 23 05:40:39 PM UTC 24 |
| Finished | Aug 23 05:41:18 PM UTC 24 |
| Peak memory | 255832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16386868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.16386868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/48.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_key_req.695315068 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 4014099327 ps |
| CPU time | 6.7 seconds |
| Started | Aug 23 05:40:40 PM UTC 24 |
| Finished | Aug 23 05:40:48 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695315068 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.695315068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_esc.2046842124 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 452892431 ps |
| CPU time | 11.3 seconds |
| Started | Aug 23 05:40:37 PM UTC 24 |
| Finished | Aug 23 05:40:49 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046842124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.2046842124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_req.2091281723 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 6523691460 ps |
| CPU time | 11.48 seconds |
| Started | Aug 23 05:40:35 PM UTC 24 |
| Finished | Aug 23 05:40:48 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091281723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.2091281723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_regwen.399421824 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 202876703 ps |
| CPU time | 4.26 seconds |
| Started | Aug 23 05:40:40 PM UTC 24 |
| Finished | Aug 23 05:40:46 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399421824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.399421824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/48.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_smoke.2120687016 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 2300575858 ps |
| CPU time | 4.03 seconds |
| Started | Aug 23 05:40:34 PM UTC 24 |
| Finished | Aug 23 05:40:39 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120687016 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.2120687016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/48.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all.1958175887 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 14416794280 ps |
| CPU time | 22.75 seconds |
| Started | Aug 23 05:40:43 PM UTC 24 |
| Finished | Aug 23 05:41:07 PM UTC 24 |
| Peak memory | 251328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958175887 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.1958175887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.3458638076 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 10868077252 ps |
| CPU time | 107.51 seconds |
| Started | Aug 23 05:40:43 PM UTC 24 |
| Finished | Aug 23 05:42:33 PM UTC 24 |
| Peak memory | 257712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3458638076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 48.otp_ctrl_stress_all_with_rand_reset.3458638076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_test_access.1925883554 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 8684316996 ps |
| CPU time | 70.3 seconds |
| Started | Aug 23 05:40:43 PM UTC 24 |
| Finished | Aug 23 05:41:55 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925883554 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.1925883554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/48.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_alert_test.341506222 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 193737007 ps |
| CPU time | 1.64 seconds |
| Started | Aug 23 05:40:58 PM UTC 24 |
| Finished | Aug 23 05:41:01 PM UTC 24 |
| Peak memory | 251096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341506222 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.341506222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/49.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_check_fail.2448992974 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 413295476 ps |
| CPU time | 4.39 seconds |
| Started | Aug 23 05:40:50 PM UTC 24 |
| Finished | Aug 23 05:40:55 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448992974 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.2448992974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/49.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_errs.2756626636 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 477507350 ps |
| CPU time | 9.76 seconds |
| Started | Aug 23 05:40:50 PM UTC 24 |
| Finished | Aug 23 05:41:00 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756626636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.2756626636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/49.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_lock.3219004627 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 769239645 ps |
| CPU time | 6.03 seconds |
| Started | Aug 23 05:40:50 PM UTC 24 |
| Finished | Aug 23 05:40:57 PM UTC 24 |
| Peak memory | 251332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219004627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.3219004627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/49.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_init_fail.3169375207 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 170554228 ps |
| CPU time | 3.24 seconds |
| Started | Aug 23 05:40:46 PM UTC 24 |
| Finished | Aug 23 05:40:50 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169375207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.3169375207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/49.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_macro_errs.3366285933 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 5283098207 ps |
| CPU time | 39.73 seconds |
| Started | Aug 23 05:40:51 PM UTC 24 |
| Finished | Aug 23 05:41:32 PM UTC 24 |
| Peak memory | 257584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366285933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.3366285933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/49.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_key_req.2026162011 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 1104348969 ps |
| CPU time | 21.61 seconds |
| Started | Aug 23 05:40:51 PM UTC 24 |
| Finished | Aug 23 05:41:14 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026162011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.2026162011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_esc.2106407584 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 240092211 ps |
| CPU time | 5.81 seconds |
| Started | Aug 23 05:40:50 PM UTC 24 |
| Finished | Aug 23 05:40:56 PM UTC 24 |
| Peak memory | 251000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106407584 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.2106407584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_req.2772753681 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 1778963367 ps |
| CPU time | 21.13 seconds |
| Started | Aug 23 05:40:47 PM UTC 24 |
| Finished | Aug 23 05:41:10 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772753681 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.2772753681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_regwen.3084402328 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 283687989 ps |
| CPU time | 7.38 seconds |
| Started | Aug 23 05:40:58 PM UTC 24 |
| Finished | Aug 23 05:41:07 PM UTC 24 |
| Peak memory | 251272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084402328 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.3084402328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/49.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_smoke.1509289805 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 1277681795 ps |
| CPU time | 2.99 seconds |
| Started | Aug 23 05:40:45 PM UTC 24 |
| Finished | Aug 23 05:40:49 PM UTC 24 |
| Peak memory | 257656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509289805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.1509289805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/49.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all.2470155667 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 14771575885 ps |
| CPU time | 80.61 seconds |
| Started | Aug 23 05:40:58 PM UTC 24 |
| Finished | Aug 23 05:42:21 PM UTC 24 |
| Peak memory | 273808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470155667 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.2470155667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.2933462786 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 68582173193 ps |
| CPU time | 127.5 seconds |
| Started | Aug 23 05:40:58 PM UTC 24 |
| Finished | Aug 23 05:43:08 PM UTC 24 |
| Peak memory | 274096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2933462786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 49.otp_ctrl_stress_all_with_rand_reset.2933462786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_test_access.2804430429 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 341899244 ps |
| CPU time | 8 seconds |
| Started | Aug 23 05:40:58 PM UTC 24 |
| Finished | Aug 23 05:41:07 PM UTC 24 |
| Peak memory | 257516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804430429 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.2804430429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/49.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_alert_test.1059809424 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 50533596 ps |
| CPU time | 1.46 seconds |
| Started | Aug 23 05:31:53 PM UTC 24 |
| Finished | Aug 23 05:31:56 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059809424 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.1059809424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_background_chks.1424911809 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 752171524 ps |
| CPU time | 19.95 seconds |
| Started | Aug 23 05:31:38 PM UTC 24 |
| Finished | Aug 23 05:31:59 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424911809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.1424911809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_errs.1600378787 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1050162134 ps |
| CPU time | 23.75 seconds |
| Started | Aug 23 05:31:44 PM UTC 24 |
| Finished | Aug 23 05:32:09 PM UTC 24 |
| Peak memory | 251004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600378787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.1600378787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_lock.881554562 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 1397384635 ps |
| CPU time | 14.81 seconds |
| Started | Aug 23 05:31:40 PM UTC 24 |
| Finished | Aug 23 05:31:57 PM UTC 24 |
| Peak memory | 257464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881554562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.881554562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_macro_errs.3652281494 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 836784711 ps |
| CPU time | 18.91 seconds |
| Started | Aug 23 05:31:45 PM UTC 24 |
| Finished | Aug 23 05:32:05 PM UTC 24 |
| Peak memory | 255388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652281494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.3652281494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_key_req.2599185922 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 462740301 ps |
| CPU time | 8.32 seconds |
| Started | Aug 23 05:31:45 PM UTC 24 |
| Finished | Aug 23 05:31:54 PM UTC 24 |
| Peak memory | 252996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599185922 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.2599185922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_esc.2736048591 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 79975236 ps |
| CPU time | 2.14 seconds |
| Started | Aug 23 05:31:40 PM UTC 24 |
| Finished | Aug 23 05:31:44 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736048591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.2736048591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_regwen.2795399727 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 298149783 ps |
| CPU time | 5.09 seconds |
| Started | Aug 23 05:31:45 PM UTC 24 |
| Finished | Aug 23 05:31:51 PM UTC 24 |
| Peak memory | 250876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795399727 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.2795399727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_smoke.3097155075 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 2046797039 ps |
| CPU time | 6.04 seconds |
| Started | Aug 23 05:31:36 PM UTC 24 |
| Finished | Aug 23 05:31:43 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097155075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.3097155075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.2820171385 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 3558920295 ps |
| CPU time | 47.85 seconds |
| Started | Aug 23 05:31:49 PM UTC 24 |
| Finished | Aug 23 05:32:39 PM UTC 24 |
| Peak memory | 257644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2820171385 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 5.otp_ctrl_stress_all_with_rand_reset.2820171385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_test_access.46975023 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 11867702646 ps |
| CPU time | 22.7 seconds |
| Started | Aug 23 05:31:46 PM UTC 24 |
| Finished | Aug 23 05:32:10 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46975023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.46975023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/5.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_init_fail.3721196618 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 163718995 ps |
| CPU time | 3.28 seconds |
| Started | Aug 23 05:40:58 PM UTC 24 |
| Finished | Aug 23 05:41:03 PM UTC 24 |
| Peak memory | 251084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721196618 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.3721196618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/50.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_parallel_lc_esc.2138119149 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 115399966 ps |
| CPU time | 2.66 seconds |
| Started | Aug 23 05:41:00 PM UTC 24 |
| Finished | Aug 23 05:41:04 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138119149 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.2138119149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/50.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.43314652 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 8180189879 ps |
| CPU time | 162.85 seconds |
| Started | Aug 23 05:41:00 PM UTC 24 |
| Finished | Aug 23 05:43:45 PM UTC 24 |
| Peak memory | 274080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=43314652 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.43314652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_init_fail.2407386196 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 442570076 ps |
| CPU time | 3.33 seconds |
| Started | Aug 23 05:41:01 PM UTC 24 |
| Finished | Aug 23 05:41:06 PM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407386196 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.2407386196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/51.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_parallel_lc_esc.3545770438 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 115221098 ps |
| CPU time | 4.13 seconds |
| Started | Aug 23 05:41:01 PM UTC 24 |
| Finished | Aug 23 05:41:07 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545770438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.3545770438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/51.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.1800012649 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 3324606641 ps |
| CPU time | 39.01 seconds |
| Started | Aug 23 05:41:04 PM UTC 24 |
| Finished | Aug 23 05:41:44 PM UTC 24 |
| Peak memory | 267860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1800012649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 51.otp_ctrl_stress_all_with_rand_reset.1800012649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_init_fail.653371592 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 360574149 ps |
| CPU time | 3.05 seconds |
| Started | Aug 23 05:41:06 PM UTC 24 |
| Finished | Aug 23 05:41:10 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653371592 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.653371592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/52.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_parallel_lc_esc.3468696148 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 192017238 ps |
| CPU time | 6.48 seconds |
| Started | Aug 23 05:41:06 PM UTC 24 |
| Finished | Aug 23 05:41:14 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468696148 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.3468696148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/52.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_stress_all_with_rand_reset.256650127 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 29871682584 ps |
| CPU time | 133.29 seconds |
| Started | Aug 23 05:41:08 PM UTC 24 |
| Finished | Aug 23 05:43:23 PM UTC 24 |
| Peak memory | 274356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=256650127 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.256650127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_init_fail.3712937054 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 190393830 ps |
| CPU time | 3.59 seconds |
| Started | Aug 23 05:41:08 PM UTC 24 |
| Finished | Aug 23 05:41:12 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712937054 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.3712937054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/53.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_parallel_lc_esc.3717719797 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 531446141 ps |
| CPU time | 5.71 seconds |
| Started | Aug 23 05:41:08 PM UTC 24 |
| Finished | Aug 23 05:41:14 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717719797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.3717719797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/53.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_init_fail.1105585082 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 206134603 ps |
| CPU time | 4.4 seconds |
| Started | Aug 23 05:41:09 PM UTC 24 |
| Finished | Aug 23 05:41:15 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105585082 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.1105585082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/54.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_parallel_lc_esc.3490060307 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 803515786 ps |
| CPU time | 16.75 seconds |
| Started | Aug 23 05:41:11 PM UTC 24 |
| Finished | Aug 23 05:41:30 PM UTC 24 |
| Peak memory | 257584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490060307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.3490060307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/54.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_init_fail.2023518762 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 332109042 ps |
| CPU time | 3.37 seconds |
| Started | Aug 23 05:41:13 PM UTC 24 |
| Finished | Aug 23 05:41:17 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023518762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.2023518762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/55.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_parallel_lc_esc.749247045 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 654530553 ps |
| CPU time | 7.15 seconds |
| Started | Aug 23 05:41:13 PM UTC 24 |
| Finished | Aug 23 05:41:21 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749247045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.749247045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/55.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_init_fail.770813492 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 156632196 ps |
| CPU time | 3.41 seconds |
| Started | Aug 23 05:41:16 PM UTC 24 |
| Finished | Aug 23 05:41:21 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770813492 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.770813492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/56.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_parallel_lc_esc.1089988735 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 4571750115 ps |
| CPU time | 6.66 seconds |
| Started | Aug 23 05:41:16 PM UTC 24 |
| Finished | Aug 23 05:41:24 PM UTC 24 |
| Peak memory | 251504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089988735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.1089988735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/56.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_stress_all_with_rand_reset.447598110 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 23026102395 ps |
| CPU time | 69.39 seconds |
| Started | Aug 23 05:41:16 PM UTC 24 |
| Finished | Aug 23 05:42:27 PM UTC 24 |
| Peak memory | 257624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=447598110 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.447598110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_init_fail.2553289799 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 321190895 ps |
| CPU time | 4.19 seconds |
| Started | Aug 23 05:41:19 PM UTC 24 |
| Finished | Aug 23 05:41:25 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553289799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.2553289799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/57.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.1341120797 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 16535324354 ps |
| CPU time | 231.43 seconds |
| Started | Aug 23 05:41:19 PM UTC 24 |
| Finished | Aug 23 05:45:14 PM UTC 24 |
| Peak memory | 273844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1341120797 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 57.otp_ctrl_stress_all_with_rand_reset.1341120797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/57.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_init_fail.950145830 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 441512504 ps |
| CPU time | 3.05 seconds |
| Started | Aug 23 05:41:22 PM UTC 24 |
| Finished | Aug 23 05:41:26 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950145830 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.950145830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/58.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_parallel_lc_esc.2198809929 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 3111322173 ps |
| CPU time | 6.46 seconds |
| Started | Aug 23 05:41:23 PM UTC 24 |
| Finished | Aug 23 05:41:30 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198809929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.2198809929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/58.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_stress_all_with_rand_reset.1498813499 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 6744827095 ps |
| CPU time | 65.13 seconds |
| Started | Aug 23 05:41:25 PM UTC 24 |
| Finished | Aug 23 05:42:32 PM UTC 24 |
| Peak memory | 257596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1498813499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 58.otp_ctrl_stress_all_with_rand_reset.1498813499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_init_fail.2318004084 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 2622458081 ps |
| CPU time | 3.45 seconds |
| Started | Aug 23 05:41:25 PM UTC 24 |
| Finished | Aug 23 05:41:30 PM UTC 24 |
| Peak memory | 251492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318004084 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.2318004084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/59.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_parallel_lc_esc.3136274044 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 832152021 ps |
| CPU time | 18.37 seconds |
| Started | Aug 23 05:41:25 PM UTC 24 |
| Finished | Aug 23 05:41:45 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136274044 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.3136274044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/59.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_stress_all_with_rand_reset.930382786 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 29736383158 ps |
| CPU time | 127.95 seconds |
| Started | Aug 23 05:41:28 PM UTC 24 |
| Finished | Aug 23 05:43:38 PM UTC 24 |
| Peak memory | 256848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=930382786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.930382786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/59.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_alert_test.2150615400 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 231714200 ps |
| CPU time | 1.95 seconds |
| Started | Aug 23 05:32:07 PM UTC 24 |
| Finished | Aug 23 05:32:10 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150615400 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.2150615400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_background_chks.960077333 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 2161635942 ps |
| CPU time | 18.01 seconds |
| Started | Aug 23 05:31:56 PM UTC 24 |
| Finished | Aug 23 05:32:15 PM UTC 24 |
| Peak memory | 251628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960077333 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.960077333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_check_fail.930444476 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 4207859280 ps |
| CPU time | 35.5 seconds |
| Started | Aug 23 05:31:59 PM UTC 24 |
| Finished | Aug 23 05:32:37 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930444476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.930444476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_errs.954688069 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 308556400 ps |
| CPU time | 14.91 seconds |
| Started | Aug 23 05:31:58 PM UTC 24 |
| Finished | Aug 23 05:32:14 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954688069 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.954688069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_lock.3297361952 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 453328420 ps |
| CPU time | 11.78 seconds |
| Started | Aug 23 05:31:56 PM UTC 24 |
| Finished | Aug 23 05:32:09 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297361952 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.3297361952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_init_fail.4162157793 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 158946065 ps |
| CPU time | 3.36 seconds |
| Started | Aug 23 05:31:54 PM UTC 24 |
| Finished | Aug 23 05:31:59 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162157793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.4162157793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_macro_errs.3804891609 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 4312982475 ps |
| CPU time | 25 seconds |
| Started | Aug 23 05:31:59 PM UTC 24 |
| Finished | Aug 23 05:32:26 PM UTC 24 |
| Peak memory | 257624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804891609 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.3804891609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_esc.1330125602 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 150271337 ps |
| CPU time | 5.83 seconds |
| Started | Aug 23 05:31:56 PM UTC 24 |
| Finished | Aug 23 05:32:03 PM UTC 24 |
| Peak memory | 251124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330125602 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.1330125602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_req.2092599460 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 275592379 ps |
| CPU time | 3.54 seconds |
| Started | Aug 23 05:31:56 PM UTC 24 |
| Finished | Aug 23 05:32:01 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092599460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.2092599460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_regwen.2067584292 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 105905879 ps |
| CPU time | 3.17 seconds |
| Started | Aug 23 05:32:01 PM UTC 24 |
| Finished | Aug 23 05:32:05 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067584292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.2067584292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_smoke.503213892 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 635750187 ps |
| CPU time | 5.76 seconds |
| Started | Aug 23 05:31:54 PM UTC 24 |
| Finished | Aug 23 05:32:01 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503213892 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.503213892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all.4028499668 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 3725014191 ps |
| CPU time | 32.23 seconds |
| Started | Aug 23 05:32:04 PM UTC 24 |
| Finished | Aug 23 05:32:38 PM UTC 24 |
| Peak memory | 253372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028499668 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.4028499668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_test_access.3052283022 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 8792134641 ps |
| CPU time | 18.27 seconds |
| Started | Aug 23 05:32:02 PM UTC 24 |
| Finished | Aug 23 05:32:22 PM UTC 24 |
| Peak memory | 253488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052283022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.3052283022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/6.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_init_fail.233380605 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 164015138 ps |
| CPU time | 3.43 seconds |
| Started | Aug 23 05:41:28 PM UTC 24 |
| Finished | Aug 23 05:41:33 PM UTC 24 |
| Peak memory | 250380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233380605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.233380605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/60.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_parallel_lc_esc.2231267772 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 257682947 ps |
| CPU time | 3.16 seconds |
| Started | Aug 23 05:41:28 PM UTC 24 |
| Finished | Aug 23 05:41:32 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231267772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.2231267772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/60.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_init_fail.2083822795 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 2187102584 ps |
| CPU time | 3.61 seconds |
| Started | Aug 23 05:41:31 PM UTC 24 |
| Finished | Aug 23 05:41:36 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083822795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.2083822795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/61.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_parallel_lc_esc.4175885863 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 190437643 ps |
| CPU time | 6.41 seconds |
| Started | Aug 23 05:41:31 PM UTC 24 |
| Finished | Aug 23 05:41:39 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175885863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.4175885863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/61.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.329150980 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 1610152407 ps |
| CPU time | 56.98 seconds |
| Started | Aug 23 05:41:31 PM UTC 24 |
| Finished | Aug 23 05:42:30 PM UTC 24 |
| Peak memory | 257844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=329150980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.329150980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_init_fail.125347561 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 575145066 ps |
| CPU time | 3.19 seconds |
| Started | Aug 23 05:41:34 PM UTC 24 |
| Finished | Aug 23 05:41:38 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125347561 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.125347561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/62.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_parallel_lc_esc.1953261011 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 182213649 ps |
| CPU time | 3.26 seconds |
| Started | Aug 23 05:41:34 PM UTC 24 |
| Finished | Aug 23 05:41:38 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953261011 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.1953261011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/62.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_init_fail.2354064454 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 114468314 ps |
| CPU time | 3.46 seconds |
| Started | Aug 23 05:41:35 PM UTC 24 |
| Finished | Aug 23 05:41:40 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354064454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.2354064454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/63.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_parallel_lc_esc.37122347 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 3530381500 ps |
| CPU time | 20.77 seconds |
| Started | Aug 23 05:41:37 PM UTC 24 |
| Finished | Aug 23 05:41:59 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37122347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.37122347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/63.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.2910731934 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 15976105067 ps |
| CPU time | 83.97 seconds |
| Started | Aug 23 05:41:39 PM UTC 24 |
| Finished | Aug 23 05:43:05 PM UTC 24 |
| Peak memory | 267888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2910731934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 63.otp_ctrl_stress_all_with_rand_reset.2910731934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_init_fail.2236158591 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 417018544 ps |
| CPU time | 3.65 seconds |
| Started | Aug 23 05:41:39 PM UTC 24 |
| Finished | Aug 23 05:41:44 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236158591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.2236158591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/64.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_parallel_lc_esc.96633209 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 1620320294 ps |
| CPU time | 20.88 seconds |
| Started | Aug 23 05:41:41 PM UTC 24 |
| Finished | Aug 23 05:42:03 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96633209 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.96633209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/64.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_init_fail.3961468611 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 193858800 ps |
| CPU time | 2.7 seconds |
| Started | Aug 23 05:41:44 PM UTC 24 |
| Finished | Aug 23 05:41:48 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961468611 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.3961468611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/65.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_parallel_lc_esc.210479762 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 428792499 ps |
| CPU time | 3.3 seconds |
| Started | Aug 23 05:41:44 PM UTC 24 |
| Finished | Aug 23 05:41:49 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210479762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.210479762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/65.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_stress_all_with_rand_reset.2085994568 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 7210914938 ps |
| CPU time | 101.37 seconds |
| Started | Aug 23 05:41:46 PM UTC 24 |
| Finished | Aug 23 05:43:29 PM UTC 24 |
| Peak memory | 267888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2085994568 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 65.otp_ctrl_stress_all_with_rand_reset.2085994568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_init_fail.3436059402 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 146762753 ps |
| CPU time | 3.32 seconds |
| Started | Aug 23 05:41:46 PM UTC 24 |
| Finished | Aug 23 05:41:50 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436059402 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.3436059402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/66.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_parallel_lc_esc.445952651 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 3991848215 ps |
| CPU time | 7.93 seconds |
| Started | Aug 23 05:41:49 PM UTC 24 |
| Finished | Aug 23 05:41:59 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445952651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.445952651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/66.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.1029027251 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 6493284428 ps |
| CPU time | 44.55 seconds |
| Started | Aug 23 05:41:49 PM UTC 24 |
| Finished | Aug 23 05:42:36 PM UTC 24 |
| Peak memory | 274008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1029027251 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 66.otp_ctrl_stress_all_with_rand_reset.1029027251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_init_fail.26018537 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 176899407 ps |
| CPU time | 3.8 seconds |
| Started | Aug 23 05:41:52 PM UTC 24 |
| Finished | Aug 23 05:41:57 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26018537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.26018537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/67.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_parallel_lc_esc.3686123113 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 14294824233 ps |
| CPU time | 22.78 seconds |
| Started | Aug 23 05:41:56 PM UTC 24 |
| Finished | Aug 23 05:42:20 PM UTC 24 |
| Peak memory | 257776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686123113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.3686123113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/67.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_init_fail.833611756 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 129369822 ps |
| CPU time | 3.43 seconds |
| Started | Aug 23 05:42:00 PM UTC 24 |
| Finished | Aug 23 05:42:05 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833611756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.833611756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/68.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_parallel_lc_esc.320913750 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 248337128 ps |
| CPU time | 10.81 seconds |
| Started | Aug 23 05:42:00 PM UTC 24 |
| Finished | Aug 23 05:42:12 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320913750 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.320913750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/68.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_stress_all_with_rand_reset.1630629527 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 2410187579 ps |
| CPU time | 82.54 seconds |
| Started | Aug 23 05:42:13 PM UTC 24 |
| Finished | Aug 23 05:43:38 PM UTC 24 |
| Peak memory | 257684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1630629527 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 68.otp_ctrl_stress_all_with_rand_reset.1630629527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_init_fail.4232226212 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 145489607 ps |
| CPU time | 3.12 seconds |
| Started | Aug 23 05:42:13 PM UTC 24 |
| Finished | Aug 23 05:42:18 PM UTC 24 |
| Peak memory | 250840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232226212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.4232226212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/69.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_parallel_lc_esc.1922744911 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 203975093 ps |
| CPU time | 4.44 seconds |
| Started | Aug 23 05:42:13 PM UTC 24 |
| Finished | Aug 23 05:42:19 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922744911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.1922744911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/69.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.1649843523 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 5438030565 ps |
| CPU time | 70.64 seconds |
| Started | Aug 23 05:42:13 PM UTC 24 |
| Finished | Aug 23 05:43:26 PM UTC 24 |
| Peak memory | 257540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1649843523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 69.otp_ctrl_stress_all_with_rand_reset.1649843523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/69.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_alert_test.3522101177 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 163127755 ps |
| CPU time | 1.93 seconds |
| Started | Aug 23 05:32:27 PM UTC 24 |
| Finished | Aug 23 05:32:30 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522101177 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.3522101177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_background_chks.3177571893 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1645096962 ps |
| CPU time | 14.19 seconds |
| Started | Aug 23 05:32:10 PM UTC 24 |
| Finished | Aug 23 05:32:26 PM UTC 24 |
| Peak memory | 251568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177571893 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.3177571893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_check_fail.404328715 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1074211453 ps |
| CPU time | 10.55 seconds |
| Started | Aug 23 05:32:16 PM UTC 24 |
| Finished | Aug 23 05:32:28 PM UTC 24 |
| Peak memory | 257720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404328715 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.404328715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_errs.2565149535 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 1611257484 ps |
| CPU time | 21.13 seconds |
| Started | Aug 23 05:32:15 PM UTC 24 |
| Finished | Aug 23 05:32:37 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565149535 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.2565149535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_lock.1314316023 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 625402282 ps |
| CPU time | 5.02 seconds |
| Started | Aug 23 05:32:14 PM UTC 24 |
| Finished | Aug 23 05:32:20 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314316023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.1314316023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_macro_errs.2330016676 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 8018582180 ps |
| CPU time | 11.82 seconds |
| Started | Aug 23 05:32:16 PM UTC 24 |
| Finished | Aug 23 05:32:29 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330016676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.2330016676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_key_req.4115583176 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 6345130295 ps |
| CPU time | 15.14 seconds |
| Started | Aug 23 05:32:17 PM UTC 24 |
| Finished | Aug 23 05:32:34 PM UTC 24 |
| Peak memory | 257828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115583176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.4115583176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_esc.1582063824 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 170964733 ps |
| CPU time | 6.98 seconds |
| Started | Aug 23 05:32:12 PM UTC 24 |
| Finished | Aug 23 05:32:20 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582063824 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.1582063824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_req.875635959 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 726491642 ps |
| CPU time | 16.09 seconds |
| Started | Aug 23 05:32:10 PM UTC 24 |
| Finished | Aug 23 05:32:28 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875635959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.875635959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_smoke.1821650293 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 4482584520 ps |
| CPU time | 8.45 seconds |
| Started | Aug 23 05:32:07 PM UTC 24 |
| Finished | Aug 23 05:32:16 PM UTC 24 |
| Peak memory | 257692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821650293 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.1821650293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_test_access.2714563650 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 1954463462 ps |
| CPU time | 12.31 seconds |
| Started | Aug 23 05:32:21 PM UTC 24 |
| Finished | Aug 23 05:32:34 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714563650 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.2714563650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/7.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_init_fail.2113633450 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 340429626 ps |
| CPU time | 3.6 seconds |
| Started | Aug 23 05:42:13 PM UTC 24 |
| Finished | Aug 23 05:42:18 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113633450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.2113633450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/70.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_parallel_lc_esc.3131696589 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 176577546 ps |
| CPU time | 2.8 seconds |
| Started | Aug 23 05:42:13 PM UTC 24 |
| Finished | Aug 23 05:42:17 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131696589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.3131696589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/70.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.2989362049 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 20750392473 ps |
| CPU time | 52.25 seconds |
| Started | Aug 23 05:42:17 PM UTC 24 |
| Finished | Aug 23 05:43:11 PM UTC 24 |
| Peak memory | 257592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2989362049 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 70.otp_ctrl_stress_all_with_rand_reset.2989362049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/70.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_init_fail.2821545801 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 572733020 ps |
| CPU time | 3.13 seconds |
| Started | Aug 23 05:42:18 PM UTC 24 |
| Finished | Aug 23 05:42:22 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821545801 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.2821545801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/71.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_parallel_lc_esc.1584558303 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 225195537 ps |
| CPU time | 4.66 seconds |
| Started | Aug 23 05:42:18 PM UTC 24 |
| Finished | Aug 23 05:42:24 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584558303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.1584558303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/71.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_stress_all_with_rand_reset.2552096858 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 18605863607 ps |
| CPU time | 80.07 seconds |
| Started | Aug 23 05:42:20 PM UTC 24 |
| Finished | Aug 23 05:43:42 PM UTC 24 |
| Peak memory | 257684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2552096858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 71.otp_ctrl_stress_all_with_rand_reset.2552096858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/71.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_init_fail.2804499253 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 233317652 ps |
| CPU time | 2.9 seconds |
| Started | Aug 23 05:42:20 PM UTC 24 |
| Finished | Aug 23 05:42:24 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804499253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.2804499253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/72.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_parallel_lc_esc.1881564398 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 1052758011 ps |
| CPU time | 15.84 seconds |
| Started | Aug 23 05:42:20 PM UTC 24 |
| Finished | Aug 23 05:42:37 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881564398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.1881564398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/72.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_init_fail.939582441 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 125550403 ps |
| CPU time | 2.74 seconds |
| Started | Aug 23 05:42:23 PM UTC 24 |
| Finished | Aug 23 05:42:27 PM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939582441 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.939582441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/73.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_parallel_lc_esc.1147500950 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 268721510 ps |
| CPU time | 4.44 seconds |
| Started | Aug 23 05:42:23 PM UTC 24 |
| Finished | Aug 23 05:42:29 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147500950 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.1147500950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/73.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_init_fail.1552446067 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 260772873 ps |
| CPU time | 3.94 seconds |
| Started | Aug 23 05:42:26 PM UTC 24 |
| Finished | Aug 23 05:42:31 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552446067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.1552446067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/74.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_parallel_lc_esc.2203692320 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 740690185 ps |
| CPU time | 14.34 seconds |
| Started | Aug 23 05:42:26 PM UTC 24 |
| Finished | Aug 23 05:42:42 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203692320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.2203692320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/74.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_init_fail.701286112 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 524571519 ps |
| CPU time | 3.63 seconds |
| Started | Aug 23 05:42:30 PM UTC 24 |
| Finished | Aug 23 05:42:35 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701286112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.701286112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/75.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_parallel_lc_esc.328270885 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 1349481365 ps |
| CPU time | 2.9 seconds |
| Started | Aug 23 05:42:30 PM UTC 24 |
| Finished | Aug 23 05:42:34 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328270885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.328270885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/75.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.3096456898 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 3378853550 ps |
| CPU time | 66.92 seconds |
| Started | Aug 23 05:42:30 PM UTC 24 |
| Finished | Aug 23 05:43:39 PM UTC 24 |
| Peak memory | 268208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3096456898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 75.otp_ctrl_stress_all_with_rand_reset.3096456898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/75.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_init_fail.867546254 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 160102614 ps |
| CPU time | 2.73 seconds |
| Started | Aug 23 05:42:32 PM UTC 24 |
| Finished | Aug 23 05:42:36 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867546254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.867546254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/76.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_parallel_lc_esc.1763064076 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 1928300579 ps |
| CPU time | 12.35 seconds |
| Started | Aug 23 05:42:32 PM UTC 24 |
| Finished | Aug 23 05:42:46 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763064076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.1763064076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/76.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_stress_all_with_rand_reset.2843833327 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 3470416678 ps |
| CPU time | 89.45 seconds |
| Started | Aug 23 05:42:37 PM UTC 24 |
| Finished | Aug 23 05:44:09 PM UTC 24 |
| Peak memory | 274004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2843833327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 76.otp_ctrl_stress_all_with_rand_reset.2843833327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/76.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_init_fail.2410180289 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 2459672666 ps |
| CPU time | 4.06 seconds |
| Started | Aug 23 05:42:37 PM UTC 24 |
| Finished | Aug 23 05:42:43 PM UTC 24 |
| Peak memory | 251456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410180289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.2410180289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/77.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_parallel_lc_esc.19790647 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 291248044 ps |
| CPU time | 14.95 seconds |
| Started | Aug 23 05:42:37 PM UTC 24 |
| Finished | Aug 23 05:42:54 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19790647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.19790647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/77.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_init_fail.1417210299 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 285886342 ps |
| CPU time | 3.63 seconds |
| Started | Aug 23 05:42:37 PM UTC 24 |
| Finished | Aug 23 05:42:43 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417210299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.1417210299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/78.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_parallel_lc_esc.3539773062 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 200214176 ps |
| CPU time | 4.57 seconds |
| Started | Aug 23 05:42:37 PM UTC 24 |
| Finished | Aug 23 05:42:43 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539773062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.3539773062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/78.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_init_fail.3407753868 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1901920969 ps |
| CPU time | 4.9 seconds |
| Started | Aug 23 05:42:37 PM UTC 24 |
| Finished | Aug 23 05:42:44 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407753868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.3407753868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/79.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_parallel_lc_esc.603225281 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 122079968 ps |
| CPU time | 4.8 seconds |
| Started | Aug 23 05:42:39 PM UTC 24 |
| Finished | Aug 23 05:42:45 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603225281 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.603225281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/79.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.2756913451 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 18135042890 ps |
| CPU time | 95.6 seconds |
| Started | Aug 23 05:42:45 PM UTC 24 |
| Finished | Aug 23 05:44:23 PM UTC 24 |
| Peak memory | 257236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2756913451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 79.otp_ctrl_stress_all_with_rand_reset.2756913451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_alert_test.3557969 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 722080322 ps |
| CPU time | 2.11 seconds |
| Started | Aug 23 05:32:39 PM UTC 24 |
| Finished | Aug 23 05:32:43 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557969 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.3557969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_check_fail.2088778008 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2616622622 ps |
| CPU time | 21.27 seconds |
| Started | Aug 23 05:32:34 PM UTC 24 |
| Finished | Aug 23 05:32:57 PM UTC 24 |
| Peak memory | 257592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088778008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.2088778008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_errs.3431264589 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 1340077718 ps |
| CPU time | 25.8 seconds |
| Started | Aug 23 05:32:34 PM UTC 24 |
| Finished | Aug 23 05:33:02 PM UTC 24 |
| Peak memory | 253404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431264589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.3431264589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_lock.612179045 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 391991180 ps |
| CPU time | 6.86 seconds |
| Started | Aug 23 05:32:34 PM UTC 24 |
| Finished | Aug 23 05:32:42 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612179045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.612179045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_init_fail.1122493443 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 324650868 ps |
| CPU time | 2.95 seconds |
| Started | Aug 23 05:32:28 PM UTC 24 |
| Finished | Aug 23 05:32:32 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122493443 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.1122493443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_macro_errs.94624102 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 5599038620 ps |
| CPU time | 29.41 seconds |
| Started | Aug 23 05:32:35 PM UTC 24 |
| Finished | Aug 23 05:33:05 PM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94624102 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.94624102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_key_req.1489517968 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 694603222 ps |
| CPU time | 15.36 seconds |
| Started | Aug 23 05:32:35 PM UTC 24 |
| Finished | Aug 23 05:32:51 PM UTC 24 |
| Peak memory | 257724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489517968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.1489517968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_esc.3759291915 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1040448352 ps |
| CPU time | 6.6 seconds |
| Started | Aug 23 05:32:31 PM UTC 24 |
| Finished | Aug 23 05:32:38 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759291915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.3759291915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_req.4162784253 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 1259971617 ps |
| CPU time | 13.54 seconds |
| Started | Aug 23 05:32:30 PM UTC 24 |
| Finished | Aug 23 05:32:44 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162784253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.4162784253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_smoke.3676339558 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 686253905 ps |
| CPU time | 7.21 seconds |
| Started | Aug 23 05:32:27 PM UTC 24 |
| Finished | Aug 23 05:32:35 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676339558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.3676339558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_test_access.1401608169 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 2408589255 ps |
| CPU time | 30.61 seconds |
| Started | Aug 23 05:32:37 PM UTC 24 |
| Finished | Aug 23 05:33:09 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401608169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.1401608169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/8.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_init_fail.3277875277 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 1184069376 ps |
| CPU time | 3.91 seconds |
| Started | Aug 23 05:42:45 PM UTC 24 |
| Finished | Aug 23 05:42:50 PM UTC 24 |
| Peak memory | 250800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277875277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.3277875277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/80.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_parallel_lc_esc.4121763132 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 788079478 ps |
| CPU time | 15.32 seconds |
| Started | Aug 23 05:42:45 PM UTC 24 |
| Finished | Aug 23 05:43:02 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121763132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.4121763132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/80.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_parallel_lc_esc.3238941986 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 361815492 ps |
| CPU time | 7.49 seconds |
| Started | Aug 23 05:42:47 PM UTC 24 |
| Finished | Aug 23 05:42:56 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238941986 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.3238941986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/81.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.2051394241 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 5222758560 ps |
| CPU time | 59.24 seconds |
| Started | Aug 23 05:42:47 PM UTC 24 |
| Finished | Aug 23 05:43:48 PM UTC 24 |
| Peak memory | 272124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2051394241 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 81.otp_ctrl_stress_all_with_rand_reset.2051394241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_init_fail.3138813886 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 558138363 ps |
| CPU time | 3.32 seconds |
| Started | Aug 23 05:42:52 PM UTC 24 |
| Finished | Aug 23 05:42:56 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138813886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.3138813886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/82.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_parallel_lc_esc.45013217 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 551972546 ps |
| CPU time | 10.7 seconds |
| Started | Aug 23 05:42:52 PM UTC 24 |
| Finished | Aug 23 05:43:04 PM UTC 24 |
| Peak memory | 251012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45013217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.45013217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/82.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_init_fail.162397268 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 1709959975 ps |
| CPU time | 4.12 seconds |
| Started | Aug 23 05:42:56 PM UTC 24 |
| Finished | Aug 23 05:43:01 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162397268 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.162397268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/83.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_parallel_lc_esc.4101110394 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 1025663559 ps |
| CPU time | 2.1 seconds |
| Started | Aug 23 05:42:56 PM UTC 24 |
| Finished | Aug 23 05:42:59 PM UTC 24 |
| Peak memory | 251004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101110394 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.4101110394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/83.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_init_fail.2326756605 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 2206481690 ps |
| CPU time | 5.93 seconds |
| Started | Aug 23 05:42:58 PM UTC 24 |
| Finished | Aug 23 05:43:05 PM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326756605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.2326756605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/84.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_parallel_lc_esc.2098388297 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 183745667 ps |
| CPU time | 5.64 seconds |
| Started | Aug 23 05:42:58 PM UTC 24 |
| Finished | Aug 23 05:43:05 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098388297 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.2098388297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/84.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_init_fail.1432901625 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 521018945 ps |
| CPU time | 3.72 seconds |
| Started | Aug 23 05:43:03 PM UTC 24 |
| Finished | Aug 23 05:43:08 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432901625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.1432901625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/85.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_parallel_lc_esc.538098852 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 899862055 ps |
| CPU time | 10.6 seconds |
| Started | Aug 23 05:43:05 PM UTC 24 |
| Finished | Aug 23 05:43:16 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538098852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.538098852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/85.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_init_fail.1245476682 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 195444875 ps |
| CPU time | 3.43 seconds |
| Started | Aug 23 05:43:08 PM UTC 24 |
| Finished | Aug 23 05:43:12 PM UTC 24 |
| Peak memory | 251492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245476682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.1245476682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/86.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_parallel_lc_esc.369830124 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 833800013 ps |
| CPU time | 8.67 seconds |
| Started | Aug 23 05:43:08 PM UTC 24 |
| Finished | Aug 23 05:43:18 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369830124 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.369830124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/86.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.904109709 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 6019927800 ps |
| CPU time | 89.97 seconds |
| Started | Aug 23 05:43:08 PM UTC 24 |
| Finished | Aug 23 05:44:40 PM UTC 24 |
| Peak memory | 267928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=904109709 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.904109709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/86.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_init_fail.3181769282 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 133097897 ps |
| CPU time | 3.18 seconds |
| Started | Aug 23 05:43:08 PM UTC 24 |
| Finished | Aug 23 05:43:12 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181769282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.3181769282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/87.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_parallel_lc_esc.1444676410 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 132834336 ps |
| CPU time | 3.68 seconds |
| Started | Aug 23 05:43:09 PM UTC 24 |
| Finished | Aug 23 05:43:14 PM UTC 24 |
| Peak memory | 250268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444676410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.1444676410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/87.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_init_fail.3938434691 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 354241783 ps |
| CPU time | 2.79 seconds |
| Started | Aug 23 05:43:10 PM UTC 24 |
| Finished | Aug 23 05:43:13 PM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938434691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.3938434691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/88.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_parallel_lc_esc.1704195211 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 400396698 ps |
| CPU time | 2.64 seconds |
| Started | Aug 23 05:43:12 PM UTC 24 |
| Finished | Aug 23 05:43:16 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704195211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.1704195211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/88.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_init_fail.169425422 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 141239799 ps |
| CPU time | 3.36 seconds |
| Started | Aug 23 05:43:13 PM UTC 24 |
| Finished | Aug 23 05:43:18 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169425422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.169425422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/89.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_parallel_lc_esc.226727514 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 868107124 ps |
| CPU time | 5.19 seconds |
| Started | Aug 23 05:43:14 PM UTC 24 |
| Finished | Aug 23 05:43:20 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226727514 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.226727514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/89.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_alert_test.646431006 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 109271342 ps |
| CPU time | 1.5 seconds |
| Started | Aug 23 05:32:58 PM UTC 24 |
| Finished | Aug 23 05:33:01 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646431006 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.646431006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_background_chks.1394486820 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1748605399 ps |
| CPU time | 19.32 seconds |
| Started | Aug 23 05:32:41 PM UTC 24 |
| Finished | Aug 23 05:33:01 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394486820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.1394486820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_check_fail.264137961 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 1597258122 ps |
| CPU time | 20.41 seconds |
| Started | Aug 23 05:32:45 PM UTC 24 |
| Finished | Aug 23 05:33:07 PM UTC 24 |
| Peak memory | 257720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264137961 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.264137961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_errs.3904990045 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 2407171099 ps |
| CPU time | 21.47 seconds |
| Started | Aug 23 05:32:45 PM UTC 24 |
| Finished | Aug 23 05:33:08 PM UTC 24 |
| Peak memory | 253468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904990045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.3904990045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_lock.2903577176 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 6179203912 ps |
| CPU time | 12.63 seconds |
| Started | Aug 23 05:32:44 PM UTC 24 |
| Finished | Aug 23 05:32:58 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903577176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.2903577176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_macro_errs.779078094 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 970861994 ps |
| CPU time | 10.5 seconds |
| Started | Aug 23 05:32:47 PM UTC 24 |
| Finished | Aug 23 05:32:59 PM UTC 24 |
| Peak memory | 253472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779078094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.779078094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_key_req.3338633428 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 851420007 ps |
| CPU time | 9.22 seconds |
| Started | Aug 23 05:32:47 PM UTC 24 |
| Finished | Aug 23 05:32:57 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338633428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.3338633428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_esc.3704108816 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 3068172355 ps |
| CPU time | 18.62 seconds |
| Started | Aug 23 05:32:43 PM UTC 24 |
| Finished | Aug 23 05:33:03 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704108816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.3704108816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_req.1864989579 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 555906905 ps |
| CPU time | 6.24 seconds |
| Started | Aug 23 05:32:43 PM UTC 24 |
| Finished | Aug 23 05:32:50 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864989579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.1864989579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_smoke.3925261137 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 743430686 ps |
| CPU time | 4.99 seconds |
| Started | Aug 23 05:32:40 PM UTC 24 |
| Finished | Aug 23 05:32:46 PM UTC 24 |
| Peak memory | 250824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925261137 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.3925261137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_test_access.1328729098 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1635048930 ps |
| CPU time | 15.78 seconds |
| Started | Aug 23 05:32:52 PM UTC 24 |
| Finished | Aug 23 05:33:09 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328729098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.1328729098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/9.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_init_fail.1754322906 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 594823475 ps |
| CPU time | 3.64 seconds |
| Started | Aug 23 05:43:15 PM UTC 24 |
| Finished | Aug 23 05:43:20 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754322906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.1754322906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/90.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_parallel_lc_esc.65012569 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 1245698918 ps |
| CPU time | 12.55 seconds |
| Started | Aug 23 05:43:16 PM UTC 24 |
| Finished | Aug 23 05:43:30 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65012569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.65012569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/90.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_stress_all_with_rand_reset.3017924335 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 66351566077 ps |
| CPU time | 147.32 seconds |
| Started | Aug 23 05:43:18 PM UTC 24 |
| Finished | Aug 23 05:45:47 PM UTC 24 |
| Peak memory | 274108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3017924335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 90.otp_ctrl_stress_all_with_rand_reset.3017924335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/90.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_init_fail.3964532504 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 1881562050 ps |
| CPU time | 4.03 seconds |
| Started | Aug 23 05:43:22 PM UTC 24 |
| Finished | Aug 23 05:43:27 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964532504 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.3964532504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/91.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_parallel_lc_esc.2785107311 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 575393079 ps |
| CPU time | 13.28 seconds |
| Started | Aug 23 05:43:22 PM UTC 24 |
| Finished | Aug 23 05:43:36 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785107311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.2785107311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/91.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.3420464857 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 17716353591 ps |
| CPU time | 104.23 seconds |
| Started | Aug 23 05:43:22 PM UTC 24 |
| Finished | Aug 23 05:45:08 PM UTC 24 |
| Peak memory | 269936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3420464857 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 91.otp_ctrl_stress_all_with_rand_reset.3420464857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_init_fail.1020114762 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 236090998 ps |
| CPU time | 2.68 seconds |
| Started | Aug 23 05:43:25 PM UTC 24 |
| Finished | Aug 23 05:43:29 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020114762 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.1020114762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/92.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_parallel_lc_esc.2445451365 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 333327099 ps |
| CPU time | 4.49 seconds |
| Started | Aug 23 05:43:25 PM UTC 24 |
| Finished | Aug 23 05:43:31 PM UTC 24 |
| Peak memory | 250640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445451365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.2445451365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/92.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_init_fail.2450672178 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 1922649905 ps |
| CPU time | 4.18 seconds |
| Started | Aug 23 05:43:26 PM UTC 24 |
| Finished | Aug 23 05:43:31 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450672178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.2450672178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/93.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_parallel_lc_esc.384340027 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 6905730884 ps |
| CPU time | 11.89 seconds |
| Started | Aug 23 05:43:26 PM UTC 24 |
| Finished | Aug 23 05:43:39 PM UTC 24 |
| Peak memory | 251564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384340027 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.384340027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/93.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_init_fail.3263537357 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 135236418 ps |
| CPU time | 2.99 seconds |
| Started | Aug 23 05:43:28 PM UTC 24 |
| Finished | Aug 23 05:43:32 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263537357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.3263537357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/94.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_parallel_lc_esc.833802619 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 368144213 ps |
| CPU time | 4.3 seconds |
| Started | Aug 23 05:43:28 PM UTC 24 |
| Finished | Aug 23 05:43:34 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833802619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.833802619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/94.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_parallel_lc_esc.911631981 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 4172868649 ps |
| CPU time | 7.07 seconds |
| Started | Aug 23 05:43:32 PM UTC 24 |
| Finished | Aug 23 05:43:40 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911631981 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.911631981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/95.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_stress_all_with_rand_reset.4213252349 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 2767310652 ps |
| CPU time | 86.68 seconds |
| Started | Aug 23 05:43:32 PM UTC 24 |
| Finished | Aug 23 05:45:01 PM UTC 24 |
| Peak memory | 273940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4213252349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 95.otp_ctrl_stress_all_with_rand_reset.4213252349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/95.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_init_fail.2010913206 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 2371770902 ps |
| CPU time | 6.11 seconds |
| Started | Aug 23 05:43:32 PM UTC 24 |
| Finished | Aug 23 05:43:39 PM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010913206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.2010913206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/96.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_parallel_lc_esc.238835531 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 475684066 ps |
| CPU time | 8.31 seconds |
| Started | Aug 23 05:43:32 PM UTC 24 |
| Finished | Aug 23 05:43:42 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238835531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.238835531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/96.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_stress_all_with_rand_reset.2834687365 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 14751010516 ps |
| CPU time | 43.25 seconds |
| Started | Aug 23 05:43:35 PM UTC 24 |
| Finished | Aug 23 05:44:20 PM UTC 24 |
| Peak memory | 267952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2834687365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 96.otp_ctrl_stress_all_with_rand_reset.2834687365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/96.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_init_fail.2764560174 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 1914487765 ps |
| CPU time | 2.84 seconds |
| Started | Aug 23 05:43:35 PM UTC 24 |
| Finished | Aug 23 05:43:39 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764560174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.2764560174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/97.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_init_fail.4096387218 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 595098525 ps |
| CPU time | 4.09 seconds |
| Started | Aug 23 05:43:35 PM UTC 24 |
| Finished | Aug 23 05:43:41 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096387218 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.4096387218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/98.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_parallel_lc_esc.3121262252 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 194718605 ps |
| CPU time | 3.5 seconds |
| Started | Aug 23 05:43:35 PM UTC 24 |
| Finished | Aug 23 05:43:40 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121262252 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.3121262252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/98.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_stress_all_with_rand_reset.1961407552 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 7010237954 ps |
| CPU time | 50.26 seconds |
| Started | Aug 23 05:43:35 PM UTC 24 |
| Finished | Aug 23 05:44:27 PM UTC 24 |
| Peak memory | 267836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1961407552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 98.otp_ctrl_stress_all_with_rand_reset.1961407552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/98.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_parallel_lc_esc.3374810210 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 2590262504 ps |
| CPU time | 5.12 seconds |
| Started | Aug 23 05:43:42 PM UTC 24 |
| Finished | Aug 23 05:43:48 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374810210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.3374810210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/99.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_stress_all_with_rand_reset.3570231955 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 3092697385 ps |
| CPU time | 57.69 seconds |
| Started | Aug 23 05:43:42 PM UTC 24 |
| Finished | Aug 23 05:44:41 PM UTC 24 |
| Peak memory | 267924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3570231955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 99.otp_ctrl_stress_all_with_rand_reset.3570231955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/otp_ctrl-sim-vcs/99.otp_ctrl_stress_all_with_rand_reset/latest |
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