Summary for Variable dai_access_cmd
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
3 | 
0 | 
3 | 
100.00 | 
User Defined Bins for dai_access_cmd
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| dai_digest | 
1827 | 
1 | 
 | 
 | 
T6 | 
1 | 
 | 
T11 | 
1 | 
 | 
T36 | 
4 | 
| dai_wr | 
3715 | 
1 | 
 | 
 | 
T2 | 
3 | 
 | 
T4 | 
2 | 
 | 
T5 | 
4 | 
| dai_rd | 
5721 | 
1 | 
 | 
 | 
T2 | 
3 | 
 | 
T4 | 
2 | 
 | 
T5 | 
5 | 
Summary for Variable lc_creator_seed_sw_rw_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 
2 | 
0 | 
2 | 
100.00 | 
Automatically Generated Bins for lc_creator_seed_sw_rw_en
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
4473 | 
1 | 
 | 
 | 
T6 | 
2 | 
 | 
T12 | 
2 | 
 | 
T36 | 
14 | 
| auto[1] | 
6790 | 
1 | 
 | 
 | 
T2 | 
6 | 
 | 
T4 | 
4 | 
 | 
T5 | 
9 | 
Summary for Cross dai_access_secret2
Samples crossed: lc_creator_seed_sw_rw_en dai_access_cmd
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 
6 | 
0 | 
6 | 
100.00 | 
 | 
Automatically Generated Cross Bins for dai_access_secret2
Bins
| lc_creator_seed_sw_rw_en | dai_access_cmd | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 
dai_digest | 
865 | 
1 | 
 | 
 | 
T6 | 
1 | 
 | 
T36 | 
3 | 
 | 
T94 | 
1 | 
| auto[0] | 
dai_wr | 
1300 | 
1 | 
 | 
 | 
T6 | 
1 | 
 | 
T12 | 
1 | 
 | 
T36 | 
6 | 
| auto[0] | 
dai_rd | 
2308 | 
1 | 
 | 
 | 
T12 | 
1 | 
 | 
T36 | 
5 | 
 | 
T94 | 
2 | 
| auto[1] | 
dai_digest | 
962 | 
1 | 
 | 
 | 
T11 | 
1 | 
 | 
T36 | 
1 | 
 | 
T94 | 
1 | 
| auto[1] | 
dai_wr | 
2415 | 
1 | 
 | 
 | 
T2 | 
3 | 
 | 
T4 | 
2 | 
 | 
T5 | 
4 | 
| auto[1] | 
dai_rd | 
3413 | 
1 | 
 | 
 | 
T2 | 
3 | 
 | 
T4 | 
2 | 
 | 
T5 | 
5 |