Unified Coverage Report :: Group :: tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

Group : tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv

---

Summary for Group tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group tb.dut.u_otp_ctrl_cov_if::lc_esc_en_condition_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
lc_esc_during_flash_addr_req	2	0	2	100.00	100	1	1	2
lc_esc_during_flash_data_req	2	0	2	100.00	100	1	1	2
lc_esc_during_lc_otp_prog_req	2	0	2	100.00	100	1	1	2
lc_esc_during_otbn_req	2	0	2	100.00	100	1	1	2
lc_esc_during_otp_idle	2	0	2	100.00	100	1	1	2
lc_esc_during_sram_0_req	2	0	2	100.00	100	1	1	2
lc_esc_during_sram_1_req	2	0	2	100.00	100	1	1	2

Summary for Variable lc_esc_during_flash_addr_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_flash_addr_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

312

1

T34

1

T115

2

T278

2

auto[1]

42

1

T34

1

T274

1

T167

1

---

Summary for Variable lc_esc_during_flash_data_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_flash_data_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

311

1

T34

2

T115

2

T278

2

auto[1]

43

1

T399

1

T279

1

T454

1

---

Summary for Variable lc_esc_during_lc_otp_prog_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_lc_otp_prog_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

327

1

T34

2

T115

2

T278

2

auto[1]

27

1

T477

1

T478

1

T168

1

---

Summary for Variable lc_esc_during_otbn_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_otbn_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

319

1

T34

2

T115

2

T278

2

auto[1]

35

1

T231

1

T150

1

T105

1

---

Summary for Variable lc_esc_during_otp_idle

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_otp_idle

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31

1

T34

1

T234

1

T105

1

auto[1]

323

1

T34

1

T115

2

T278

2

---

Summary for Variable lc_esc_during_sram_0_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_sram_0_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298

1

T34

2

T115

1

T278

1

auto[1]

56

1

T115

1

T278

1

T234

2

---

Summary for Variable lc_esc_during_sram_1_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for lc_esc_during_sram_1_req

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301

1

T34

2

T115

1

T278

1

auto[1]

53

1

T115

1

T278

1

T234

2