| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 95.03 | 93.71 | 97.25 | 96.08 | 91.08 | 97.66 | 96.34 | 93.07 |
| T1259 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1063999727 | Sep 09 11:46:02 AM UTC 24 | Sep 09 11:46:08 AM UTC 24 | 364047058 ps | ||
| T1260 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1003265912 | Sep 09 11:46:05 AM UTC 24 | Sep 09 11:46:09 AM UTC 24 | 250819253 ps | ||
| T1261 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3686482343 | Sep 09 11:46:06 AM UTC 24 | Sep 09 11:46:14 AM UTC 24 | 1409173207 ps | ||
| T1262 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3838930776 | Sep 09 11:46:06 AM UTC 24 | Sep 09 11:46:09 AM UTC 24 | 44482008 ps | ||
| T411 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.169034192 | Sep 09 11:45:51 AM UTC 24 | Sep 09 11:46:09 AM UTC 24 | 1168505857 ps | ||
| T1263 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1341395470 | Sep 09 11:46:01 AM UTC 24 | Sep 09 11:46:10 AM UTC 24 | 380273490 ps | ||
| T1264 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.1887011470 | Sep 09 11:46:07 AM UTC 24 | Sep 09 11:46:10 AM UTC 24 | 73320813 ps | ||
| T1265 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.2769228453 | Sep 09 11:46:07 AM UTC 24 | Sep 09 11:46:10 AM UTC 24 | 72478558 ps | ||
| T1266 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.56659218 | Sep 09 11:46:07 AM UTC 24 | Sep 09 11:46:10 AM UTC 24 | 154662769 ps | ||
| T1267 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.1950483964 | Sep 09 11:46:07 AM UTC 24 | Sep 09 11:46:10 AM UTC 24 | 126675808 ps | ||
| T1268 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.97883440 | Sep 09 11:46:07 AM UTC 24 | Sep 09 11:46:10 AM UTC 24 | 74408246 ps | ||
| T1269 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.1285287982 | Sep 09 11:46:07 AM UTC 24 | Sep 09 11:46:10 AM UTC 24 | 506639700 ps | ||
| T1270 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.2517737171 | Sep 09 11:46:00 AM UTC 24 | Sep 09 11:46:10 AM UTC 24 | 1255514712 ps | ||
| T1271 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.1745658510 | Sep 09 11:46:07 AM UTC 24 | Sep 09 11:46:10 AM UTC 24 | 47210067 ps | ||
| T1272 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.1347355540 | Sep 09 11:46:07 AM UTC 24 | Sep 09 11:46:10 AM UTC 24 | 144843842 ps | ||
| T1273 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.952671535 | Sep 09 11:46:07 AM UTC 24 | Sep 09 11:46:10 AM UTC 24 | 69766483 ps | ||
| T1274 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.1448992061 | Sep 09 11:46:07 AM UTC 24 | Sep 09 11:46:10 AM UTC 24 | 139898369 ps | ||
| T1275 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.1221475756 | Sep 09 11:46:08 AM UTC 24 | Sep 09 11:46:11 AM UTC 24 | 89188919 ps | ||
| T1276 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.1228652380 | Sep 09 11:45:45 AM UTC 24 | Sep 09 11:46:11 AM UTC 24 | 149535431 ps | ||
| T316 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3060284260 | Sep 09 11:45:58 AM UTC 24 | Sep 09 11:46:11 AM UTC 24 | 2440427166 ps | ||
| T1277 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.2897135379 | Sep 09 11:46:08 AM UTC 24 | Sep 09 11:46:11 AM UTC 24 | 577285362 ps | ||
| T1278 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.1454305251 | Sep 09 11:46:06 AM UTC 24 | Sep 09 11:46:11 AM UTC 24 | 47089578 ps | ||
| T1279 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.2112718724 | Sep 09 11:46:06 AM UTC 24 | Sep 09 11:46:12 AM UTC 24 | 74219012 ps | ||
| T1280 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.1889441930 | Sep 09 11:46:09 AM UTC 24 | Sep 09 11:46:12 AM UTC 24 | 42674160 ps | ||
| T1281 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.267201029 | Sep 09 11:46:06 AM UTC 24 | Sep 09 11:46:12 AM UTC 24 | 582360510 ps | ||
| T1282 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.4070622446 | Sep 09 11:46:11 AM UTC 24 | Sep 09 11:46:13 AM UTC 24 | 621026684 ps | ||
| T1283 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.1174695428 | Sep 09 11:46:11 AM UTC 24 | Sep 09 11:46:13 AM UTC 24 | 37511523 ps | ||
| T1284 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.3638922581 | Sep 09 11:46:11 AM UTC 24 | Sep 09 11:46:13 AM UTC 24 | 77282368 ps | ||
| T1285 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.1544303596 | Sep 09 11:46:11 AM UTC 24 | Sep 09 11:46:13 AM UTC 24 | 79856594 ps | ||
| T1286 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.114815870 | Sep 09 11:46:11 AM UTC 24 | Sep 09 11:46:13 AM UTC 24 | 85402175 ps | ||
| T1287 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2124568737 | Sep 09 11:46:06 AM UTC 24 | Sep 09 11:46:14 AM UTC 24 | 2101956251 ps | ||
| T1288 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.556625567 | Sep 09 11:46:11 AM UTC 24 | Sep 09 11:46:14 AM UTC 24 | 73893739 ps | ||
| T1289 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.2041141629 | Sep 09 11:46:11 AM UTC 24 | Sep 09 11:46:14 AM UTC 24 | 131050962 ps | ||
| T1290 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.3764768809 | Sep 09 11:46:11 AM UTC 24 | Sep 09 11:46:14 AM UTC 24 | 61590501 ps | ||
| T1291 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.169959550 | Sep 09 11:46:11 AM UTC 24 | Sep 09 11:46:14 AM UTC 24 | 72823103 ps | ||
| T1292 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.2600451718 | Sep 09 11:46:11 AM UTC 24 | Sep 09 11:46:14 AM UTC 24 | 591029117 ps | ||
| T1293 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.1869739609 | Sep 09 11:46:11 AM UTC 24 | Sep 09 11:46:14 AM UTC 24 | 40923373 ps | ||
| T414 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3721505960 | Sep 09 11:45:56 AM UTC 24 | Sep 09 11:46:15 AM UTC 24 | 2644916403 ps | ||
| T1294 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.16997641 | Sep 09 11:45:53 AM UTC 24 | Sep 09 11:46:15 AM UTC 24 | 4556970231 ps | ||
| T1295 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.3823023330 | Sep 09 11:46:12 AM UTC 24 | Sep 09 11:46:15 AM UTC 24 | 45059236 ps | ||
| T312 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.3186120027 | Sep 09 11:45:55 AM UTC 24 | Sep 09 11:46:17 AM UTC 24 | 1236913944 ps | ||
| T412 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2521473605 | Sep 09 11:46:01 AM UTC 24 | Sep 09 11:46:17 AM UTC 24 | 10340363353 ps | ||
| T1296 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1506031871 | Sep 09 11:46:06 AM UTC 24 | Sep 09 11:46:19 AM UTC 24 | 1428063223 ps | ||
| T313 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.3417388855 | Sep 09 11:45:53 AM UTC 24 | Sep 09 11:46:21 AM UTC 24 | 3702561337 ps | ||
| T413 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.1172695178 | Sep 09 11:46:01 AM UTC 24 | Sep 09 11:46:23 AM UTC 24 | 1280875426 ps | ||
| T408 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.469850556 | Sep 09 11:45:45 AM UTC 24 | Sep 09 11:46:40 AM UTC 24 | 20016555474 ps | ||
| T1297 | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1115564551 | Sep 09 11:46:02 AM UTC 24 | Sep 09 11:47:07 AM UTC 24 | 20008519689 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_req.3426587339 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 248246768 ps |
| CPU time | 4.63 seconds |
| Started | Sep 09 07:04:23 PM UTC 24 |
| Finished | Sep 09 07:04:29 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426587339 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.3426587339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_check_fail.2030148170 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 657197801 ps |
| CPU time | 14.83 seconds |
| Started | Sep 09 07:04:24 PM UTC 24 |
| Finished | Sep 09 07:04:40 PM UTC 24 |
| Peak memory | 257436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030148170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.2030148170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_test_access.665696314 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 2276600688 ps |
| CPU time | 24.04 seconds |
| Started | Sep 09 07:04:25 PM UTC 24 |
| Finished | Sep 09 07:04:50 PM UTC 24 |
| Peak memory | 251704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665696314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.665696314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_esc.3244639472 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 842893607 ps |
| CPU time | 5.75 seconds |
| Started | Sep 09 07:04:24 PM UTC 24 |
| Finished | Sep 09 07:04:32 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244639472 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.3244639472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all_with_rand_reset.472854416 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 13802994784 ps |
| CPU time | 186.93 seconds |
| Started | Sep 09 07:04:39 PM UTC 24 |
| Finished | Sep 09 07:07:49 PM UTC 24 |
| Peak memory | 274032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=472854416 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.472854416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_key_req.3030455184 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 10335969805 ps |
| CPU time | 27.2 seconds |
| Started | Sep 09 07:04:25 PM UTC 24 |
| Finished | Sep 09 07:04:54 PM UTC 24 |
| Peak memory | 253400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030455184 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.3030455184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_lock.1255996942 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 514261629 ps |
| CPU time | 7.55 seconds |
| Started | Sep 09 07:04:23 PM UTC 24 |
| Finished | Sep 09 07:04:32 PM UTC 24 |
| Peak memory | 257504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255996942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.1255996942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_stress_all.412048979 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 19508313576 ps |
| CPU time | 97.48 seconds |
| Started | Sep 09 07:04:54 PM UTC 24 |
| Finished | Sep 09 07:06:34 PM UTC 24 |
| Peak memory | 257620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412048979 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all.412048979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_stress_all.1678341135 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 20543966234 ps |
| CPU time | 194.78 seconds |
| Started | Sep 09 07:04:25 PM UTC 24 |
| Finished | Sep 09 07:07:43 PM UTC 24 |
| Peak memory | 270104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678341135 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all.1678341135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_sec_cm.3628078183 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 40422186607 ps |
| CPU time | 151.96 seconds |
| Started | Sep 09 07:04:24 PM UTC 24 |
| Finished | Sep 09 07:06:59 PM UTC 24 |
| Peak memory | 287852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628078183 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.3628078183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_esc.1042813474 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 661111558 ps |
| CPU time | 9.78 seconds |
| Started | Sep 09 07:04:36 PM UTC 24 |
| Finished | Sep 09 07:04:47 PM UTC 24 |
| Peak memory | 250568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042813474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.1042813474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_background_chks.1346541379 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 3372078079 ps |
| CPU time | 28.77 seconds |
| Started | Sep 09 07:04:26 PM UTC 24 |
| Finished | Sep 09 07:04:56 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346541379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.1346541379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_init_fail.2888442356 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 104487727 ps |
| CPU time | 3.33 seconds |
| Started | Sep 09 07:04:24 PM UTC 24 |
| Finished | Sep 09 07:04:29 PM UTC 24 |
| Peak memory | 253336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888442356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.2888442356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_macro_errs.92327583 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 1052003957 ps |
| CPU time | 28.8 seconds |
| Started | Sep 09 07:04:28 PM UTC 24 |
| Finished | Sep 09 07:04:58 PM UTC 24 |
| Peak memory | 253688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92327583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.92327583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_init_fail.1647429817 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 84492108 ps |
| CPU time | 3.36 seconds |
| Started | Sep 09 07:11:57 PM UTC 24 |
| Finished | Sep 09 07:12:02 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647429817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.1647429817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/107.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_stress_all.828121613 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 20243253463 ps |
| CPU time | 126.55 seconds |
| Started | Sep 09 07:04:35 PM UTC 24 |
| Finished | Sep 09 07:06:44 PM UTC 24 |
| Peak memory | 255460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828121613 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all.828121613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all.3315232746 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 832659004 ps |
| CPU time | 17.06 seconds |
| Started | Sep 09 07:04:46 PM UTC 24 |
| Finished | Sep 09 07:05:04 PM UTC 24 |
| Peak memory | 251000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315232746 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all.3315232746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_check_fail.3142859576 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 25189291877 ps |
| CPU time | 47.22 seconds |
| Started | Sep 09 07:04:54 PM UTC 24 |
| Finished | Sep 09 07:05:43 PM UTC 24 |
| Peak memory | 257336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142859576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.3142859576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_intg_err.1188182604 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 2428305341 ps |
| CPU time | 16.66 seconds |
| Started | Sep 09 11:45:32 AM UTC 24 |
| Finished | Sep 09 11:45:50 AM UTC 24 |
| Peak memory | 256860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188182604 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_intg_err.1188182604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_key_req.3530858886 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 1588883114 ps |
| CPU time | 29.22 seconds |
| Started | Sep 09 07:04:24 PM UTC 24 |
| Finished | Sep 09 07:04:55 PM UTC 24 |
| Peak memory | 253468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530858886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.3530858886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_stress_all_with_rand_reset.1662308353 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 3390488939 ps |
| CPU time | 50.34 seconds |
| Started | Sep 09 07:11:23 PM UTC 24 |
| Finished | Sep 09 07:12:15 PM UTC 24 |
| Peak memory | 274352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1662308353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 86.otp_ctrl_stress_all_with_rand_reset.1662308353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/86.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_macro_errs.1770009325 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 1142430839 ps |
| CPU time | 24.92 seconds |
| Started | Sep 09 07:05:05 PM UTC 24 |
| Finished | Sep 09 07:05:32 PM UTC 24 |
| Peak memory | 257716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770009325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.1770009325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_background_chks.2557365870 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2840264575 ps |
| CPU time | 13.27 seconds |
| Started | Sep 09 07:04:33 PM UTC 24 |
| Finished | Sep 09 07:04:48 PM UTC 24 |
| Peak memory | 257652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557365870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.2557365870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_init_fail.3348164413 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1514442854 ps |
| CPU time | 5.1 seconds |
| Started | Sep 09 07:10:49 PM UTC 24 |
| Finished | Sep 09 07:10:55 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348164413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.3348164413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/65.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_req.1170980953 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 701969950 ps |
| CPU time | 17.31 seconds |
| Started | Sep 09 07:05:09 PM UTC 24 |
| Finished | Sep 09 07:05:28 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170980953 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.1170980953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all_with_rand_reset.1182143456 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 3521152036 ps |
| CPU time | 149.75 seconds |
| Started | Sep 09 07:06:21 PM UTC 24 |
| Finished | Sep 09 07:08:54 PM UTC 24 |
| Peak memory | 257596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1182143456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 19.otp_ctrl_stress_all_with_rand_reset.1182143456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_alert_test.1710647217 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 140975133 ps |
| CPU time | 2.97 seconds |
| Started | Sep 09 07:05:02 PM UTC 24 |
| Finished | Sep 09 07:05:06 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710647217 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.1710647217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_check_fail.2246470775 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1953708368 ps |
| CPU time | 14.23 seconds |
| Started | Sep 09 07:04:33 PM UTC 24 |
| Finished | Sep 09 07:04:49 PM UTC 24 |
| Peak memory | 251640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246470775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.2246470775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all.2631609153 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 9345688186 ps |
| CPU time | 113.29 seconds |
| Started | Sep 09 07:05:02 PM UTC 24 |
| Finished | Sep 09 07:06:57 PM UTC 24 |
| Peak memory | 268080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631609153 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all.2631609153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_aliasing.3940324140 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 213365477 ps |
| CPU time | 2.62 seconds |
| Started | Sep 09 11:45:27 AM UTC 24 |
| Finished | Sep 09 11:45:32 AM UTC 24 |
| Peak memory | 252824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940324140 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_aliasing.3940324140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_lock.855954294 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 925847851 ps |
| CPU time | 25.77 seconds |
| Started | Sep 09 07:05:18 PM UTC 24 |
| Finished | Sep 09 07:05:45 PM UTC 24 |
| Peak memory | 251708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855954294 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.855954294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_init_fail.3588714033 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 388294230 ps |
| CPU time | 4.56 seconds |
| Started | Sep 09 07:05:30 PM UTC 24 |
| Finished | Sep 09 07:05:35 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588714033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.3588714033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_check_fail.3714018513 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 1348398365 ps |
| CPU time | 19.33 seconds |
| Started | Sep 09 07:10:20 PM UTC 24 |
| Finished | Sep 09 07:10:41 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714018513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.3714018513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/49.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all_with_rand_reset.3121970705 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 9911763261 ps |
| CPU time | 49.21 seconds |
| Started | Sep 09 07:08:45 PM UTC 24 |
| Finished | Sep 09 07:09:36 PM UTC 24 |
| Peak memory | 257648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3121970705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 36.otp_ctrl_stress_all_with_rand_reset.3121970705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_init_fail.1301643929 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2709110261 ps |
| CPU time | 9.11 seconds |
| Started | Sep 09 07:06:34 PM UTC 24 |
| Finished | Sep 09 07:06:44 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301643929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.1301643929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/21.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all.152893848 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 16479415839 ps |
| CPU time | 192.66 seconds |
| Started | Sep 09 07:04:31 PM UTC 24 |
| Finished | Sep 09 07:07:47 PM UTC 24 |
| Peak memory | 272144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152893848 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all.152893848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_init_fail.103475983 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 2238482540 ps |
| CPU time | 7.2 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:47 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103475983 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.103475983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/145.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_dai_errs.1984056858 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3271900843 ps |
| CPU time | 13.08 seconds |
| Started | Sep 09 07:04:24 PM UTC 24 |
| Finished | Sep 09 07:04:39 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984056858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.1984056858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_key_req.341840353 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 1350743546 ps |
| CPU time | 16.53 seconds |
| Started | Sep 09 07:04:33 PM UTC 24 |
| Finished | Sep 09 07:04:51 PM UTC 24 |
| Peak memory | 257520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341840353 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.341840353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_init_fail.848153965 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 423528791 ps |
| CPU time | 7.47 seconds |
| Started | Sep 09 07:08:25 PM UTC 24 |
| Finished | Sep 09 07:08:34 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848153965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.848153965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/35.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_init_fail.4000966920 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 294608614 ps |
| CPU time | 4.45 seconds |
| Started | Sep 09 07:12:25 PM UTC 24 |
| Finished | Sep 09 07:12:31 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000966920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.4000966920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/135.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_init_fail.9582530 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2259183932 ps |
| CPU time | 6.12 seconds |
| Started | Sep 09 07:04:26 PM UTC 24 |
| Finished | Sep 09 07:04:33 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9582530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.9582530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_regwen.2446757906 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 574597946 ps |
| CPU time | 11.74 seconds |
| Started | Sep 09 07:05:29 PM UTC 24 |
| Finished | Sep 09 07:05:42 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446757906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.2446757906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_check_fail.3766528518 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 2162639242 ps |
| CPU time | 23.41 seconds |
| Started | Sep 09 07:05:27 PM UTC 24 |
| Finished | Sep 09 07:05:52 PM UTC 24 |
| Peak memory | 253488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766528518 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.3766528518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all_with_rand_reset.1453642040 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 7131006794 ps |
| CPU time | 166.28 seconds |
| Started | Sep 09 07:05:09 PM UTC 24 |
| Finished | Sep 09 07:07:58 PM UTC 24 |
| Peak memory | 267884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1453642040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 8.otp_ctrl_stress_all_with_rand_reset.1453642040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_esc.519077134 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 370832834 ps |
| CPU time | 7.08 seconds |
| Started | Sep 09 07:04:33 PM UTC 24 |
| Finished | Sep 09 07:04:41 PM UTC 24 |
| Peak memory | 251124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519077134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.519077134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_stress_all.1193480449 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 6181471741 ps |
| CPU time | 162.97 seconds |
| Started | Sep 09 07:04:39 PM UTC 24 |
| Finished | Sep 09 07:07:25 PM UTC 24 |
| Peak memory | 257464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193480449 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all.1193480449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_init_fail.3459535578 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 129852468 ps |
| CPU time | 4.8 seconds |
| Started | Sep 09 07:05:02 PM UTC 24 |
| Finished | Sep 09 07:05:08 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459535578 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.3459535578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_key_req.4265565120 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 2634459159 ps |
| CPU time | 27.74 seconds |
| Started | Sep 09 07:04:36 PM UTC 24 |
| Finished | Sep 09 07:05:06 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265565120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.4265565120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_check_fail.3725879001 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 1048625310 ps |
| CPU time | 19.18 seconds |
| Started | Sep 09 07:08:54 PM UTC 24 |
| Finished | Sep 09 07:09:14 PM UTC 24 |
| Peak memory | 251568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725879001 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.3725879001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/38.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/266.otp_ctrl_init_fail.4084849916 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 285911029 ps |
| CPU time | 3.87 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:34 PM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084849916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.4084849916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/266.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_background_chks.3515218906 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 449818143 ps |
| CPU time | 12.44 seconds |
| Started | Sep 09 07:04:55 PM UTC 24 |
| Finished | Sep 09 07:05:08 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515218906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.3515218906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_test_access.1951713789 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 824421180 ps |
| CPU time | 12.91 seconds |
| Started | Sep 09 07:04:24 PM UTC 24 |
| Finished | Sep 09 07:04:39 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951713789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.1951713789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all.4071688029 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 14821764344 ps |
| CPU time | 90.48 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:11:27 PM UTC 24 |
| Peak memory | 257664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071688029 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all.4071688029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_init_fail.182838086 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 777079971 ps |
| CPU time | 7.32 seconds |
| Started | Sep 09 07:05:15 PM UTC 24 |
| Finished | Sep 09 07:05:24 PM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182838086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.182838086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_init_fail.2982350454 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 264038183 ps |
| CPU time | 3.3 seconds |
| Started | Sep 09 07:04:23 PM UTC 24 |
| Finished | Sep 09 07:04:27 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982350454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.2982350454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_init_fail.462422279 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 199476111 ps |
| CPU time | 4.44 seconds |
| Started | Sep 09 07:05:56 PM UTC 24 |
| Finished | Sep 09 07:06:01 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462422279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.462422279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_stress_all.390252778 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 69141196709 ps |
| CPU time | 203.36 seconds |
| Started | Sep 09 07:06:54 PM UTC 24 |
| Finished | Sep 09 07:10:21 PM UTC 24 |
| Peak memory | 257620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390252778 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all.390252778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_esc.3681888075 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 280991425 ps |
| CPU time | 7.23 seconds |
| Started | Sep 09 07:07:20 PM UTC 24 |
| Finished | Sep 09 07:07:28 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681888075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.3681888075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_esc.2202710841 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 299384639 ps |
| CPU time | 5.58 seconds |
| Started | Sep 09 07:09:42 PM UTC 24 |
| Finished | Sep 09 07:09:49 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202710841 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.2202710841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_stress_all_with_rand_reset.904311591 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 16494344353 ps |
| CPU time | 96.35 seconds |
| Started | Sep 09 07:10:57 PM UTC 24 |
| Finished | Sep 09 07:12:36 PM UTC 24 |
| Peak memory | 257688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=904311591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.904311591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/72.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_intg_err.2351421908 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 1438527619 ps |
| CPU time | 19.22 seconds |
| Started | Sep 09 11:45:44 AM UTC 24 |
| Finished | Sep 09 11:46:05 AM UTC 24 |
| Peak memory | 252764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351421908 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_intg_err.2351421908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_macro_errs.2479965728 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 31717461063 ps |
| CPU time | 58.88 seconds |
| Started | Sep 09 07:04:24 PM UTC 24 |
| Finished | Sep 09 07:05:25 PM UTC 24 |
| Peak memory | 270200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479965728 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.2479965728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all_with_rand_reset.281476949 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 4906579600 ps |
| CPU time | 75.93 seconds |
| Started | Sep 09 07:05:35 PM UTC 24 |
| Finished | Sep 09 07:06:52 PM UTC 24 |
| Peak memory | 257856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=281476949 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.281476949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/269.otp_ctrl_init_fail.536240764 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 426611935 ps |
| CPU time | 2.72 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:33 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536240764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.536240764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/269.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_check_fail.764438288 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 16156791745 ps |
| CPU time | 25.45 seconds |
| Started | Sep 09 07:09:08 PM UTC 24 |
| Finished | Sep 09 07:09:35 PM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764438288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.764438288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/40.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_regwen.605863822 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 613379832 ps |
| CPU time | 7.99 seconds |
| Started | Sep 09 07:06:07 PM UTC 24 |
| Finished | Sep 09 07:06:16 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605863822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.605863822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/17.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_init_fail.1280130477 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 109474963 ps |
| CPU time | 3.88 seconds |
| Started | Sep 09 07:12:21 PM UTC 24 |
| Finished | Sep 09 07:12:26 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280130477 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.1280130477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/126.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_parallel_lc_esc.3506101545 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 547419844 ps |
| CPU time | 10.99 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:09 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506101545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.3506101545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/171.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_parallel_lc_esc.1850873879 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 3614634280 ps |
| CPU time | 7.2 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:06 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850873879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.1850873879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/178.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_check_fail.469629401 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 1112228732 ps |
| CPU time | 25.38 seconds |
| Started | Sep 09 07:07:23 PM UTC 24 |
| Finished | Sep 09 07:07:49 PM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469629401 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.469629401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/26.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_stress_all.3185977494 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 2454864687 ps |
| CPU time | 26.76 seconds |
| Started | Sep 09 07:09:10 PM UTC 24 |
| Finished | Sep 09 07:09:38 PM UTC 24 |
| Peak memory | 253372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185977494 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all.3185977494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_rw.4089586479 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 75760054 ps |
| CPU time | 1.55 seconds |
| Started | Sep 09 11:45:44 AM UTC 24 |
| Finished | Sep 09 11:45:47 AM UTC 24 |
| Peak memory | 253928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089586479 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_csr_rw.4089586479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_test_access.3379102640 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 313877660 ps |
| CPU time | 9.97 seconds |
| Started | Sep 09 07:04:35 PM UTC 24 |
| Finished | Sep 09 07:04:46 PM UTC 24 |
| Peak memory | 251368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379102640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.3379102640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_regwen.705716081 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 3982105326 ps |
| CPU time | 12.99 seconds |
| Started | Sep 09 07:07:05 PM UTC 24 |
| Finished | Sep 09 07:07:19 PM UTC 24 |
| Peak memory | 257488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705716081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.705716081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/23.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_key_req.257012434 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 1266190096 ps |
| CPU time | 14.44 seconds |
| Started | Sep 09 07:04:54 PM UTC 24 |
| Finished | Sep 09 07:05:10 PM UTC 24 |
| Peak memory | 257560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257012434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.257012434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_init_fail.120963626 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 197857470 ps |
| CPU time | 5.09 seconds |
| Started | Sep 09 07:06:15 PM UTC 24 |
| Finished | Sep 09 07:06:21 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120963626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.120963626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_check_fail.3908862627 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1760904377 ps |
| CPU time | 22.97 seconds |
| Started | Sep 09 07:04:26 PM UTC 24 |
| Finished | Sep 09 07:04:51 PM UTC 24 |
| Peak memory | 257456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908862627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.3908862627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_intg_err.3128975893 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 2573919535 ps |
| CPU time | 9.79 seconds |
| Started | Sep 09 11:45:26 AM UTC 24 |
| Finished | Sep 09 11:45:44 AM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128975893 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_intg_err.3128975893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_req.748650249 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 9425024613 ps |
| CPU time | 29.72 seconds |
| Started | Sep 09 07:04:55 PM UTC 24 |
| Finished | Sep 09 07:05:26 PM UTC 24 |
| Peak memory | 251608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748650249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.748650249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_init_fail.3407326200 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 2618491107 ps |
| CPU time | 6.17 seconds |
| Started | Sep 09 07:11:34 PM UTC 24 |
| Finished | Sep 09 07:11:42 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407326200 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.3407326200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/94.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_check_fail.725839028 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 574786762 ps |
| CPU time | 19.77 seconds |
| Started | Sep 09 07:06:10 PM UTC 24 |
| Finished | Sep 09 07:06:31 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725839028 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.725839028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_init_fail.1153219203 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 91313729 ps |
| CPU time | 3.6 seconds |
| Started | Sep 09 07:08:08 PM UTC 24 |
| Finished | Sep 09 07:08:12 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153219203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.1153219203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/32.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_init_fail.3048403344 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 2353757488 ps |
| CPU time | 9.14 seconds |
| Started | Sep 09 07:11:57 PM UTC 24 |
| Finished | Sep 09 07:12:07 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048403344 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.3048403344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/105.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_lock.3261058164 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 393630644 ps |
| CPU time | 9.69 seconds |
| Started | Sep 09 07:04:24 PM UTC 24 |
| Finished | Sep 09 07:04:36 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3261058164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.3261058164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_intg_err.169034192 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1168505857 ps |
| CPU time | 15.83 seconds |
| Started | Sep 09 11:45:51 AM UTC 24 |
| Finished | Sep 09 11:46:09 AM UTC 24 |
| Peak memory | 257048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169034192 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_intg_err.169034192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all_with_rand_reset.3556559628 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 8386552156 ps |
| CPU time | 83.79 seconds |
| Started | Sep 09 07:05:54 PM UTC 24 |
| Finished | Sep 09 07:07:20 PM UTC 24 |
| Peak memory | 257748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3556559628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 15.otp_ctrl_stress_all_with_rand_reset.3556559628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_regwen.4131777982 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 290839526 ps |
| CPU time | 5.87 seconds |
| Started | Sep 09 07:08:45 PM UTC 24 |
| Finished | Sep 09 07:08:53 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131777982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_regwen.4131777982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/37.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_rw.1465291718 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 572560728 ps |
| CPU time | 1.88 seconds |
| Started | Sep 09 11:45:30 AM UTC 24 |
| Finished | Sep 09 11:45:41 AM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465291718 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.1465291718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_stress_all_with_rand_reset.2892252458 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 76780101483 ps |
| CPU time | 166.13 seconds |
| Started | Sep 09 07:05:01 PM UTC 24 |
| Finished | Sep 09 07:07:50 PM UTC 24 |
| Peak memory | 278120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2892252458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 7.otp_ctrl_stress_all_with_rand_reset.2892252458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all_with_rand_reset.1072823407 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 9879416963 ps |
| CPU time | 184.14 seconds |
| Started | Sep 09 07:08:24 PM UTC 24 |
| Finished | Sep 09 07:11:31 PM UTC 24 |
| Peak memory | 288432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1072823407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 34.otp_ctrl_stress_all_with_rand_reset.1072823407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_wake_up.1970845311 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 61249204 ps |
| CPU time | 1.65 seconds |
| Started | Sep 09 07:04:23 PM UTC 24 |
| Finished | Sep 09 07:04:25 PM UTC 24 |
| Peak memory | 250576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970845311 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_tes t +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.1970845311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_wake_up/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/283.otp_ctrl_init_fail.1802575809 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 259161528 ps |
| CPU time | 2.94 seconds |
| Started | Sep 09 07:13:41 PM UTC 24 |
| Finished | Sep 09 07:13:46 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802575809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.1802575809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/283.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_key_req.3718597635 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 208936478 ps |
| CPU time | 6.37 seconds |
| Started | Sep 09 07:06:07 PM UTC 24 |
| Finished | Sep 09 07:06:14 PM UTC 24 |
| Peak memory | 257464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718597635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_key_req.3718597635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_key_req.782008312 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 558115514 ps |
| CPU time | 21.48 seconds |
| Started | Sep 09 07:04:44 PM UTC 24 |
| Finished | Sep 09 07:05:07 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782008312 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.782008312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_intg_err.3417388855 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 3702561337 ps |
| CPU time | 17.55 seconds |
| Started | Sep 09 11:45:53 AM UTC 24 |
| Finished | Sep 09 11:46:21 AM UTC 24 |
| Peak memory | 258916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417388855 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_intg_err.3417388855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_intg_err.3060284260 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 2440427166 ps |
| CPU time | 12.28 seconds |
| Started | Sep 09 11:45:58 AM UTC 24 |
| Finished | Sep 09 11:46:11 AM UTC 24 |
| Peak memory | 252772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060284260 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_intg_err.3060284260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all_with_rand_reset.1748657350 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 868328223 ps |
| CPU time | 38.83 seconds |
| Started | Sep 09 07:06:43 PM UTC 24 |
| Finished | Sep 09 07:07:23 PM UTC 24 |
| Peak memory | 257648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1748657350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 21.otp_ctrl_stress_all_with_rand_reset.1748657350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_smoke.3852002753 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 1639997921 ps |
| CPU time | 15.09 seconds |
| Started | Sep 09 07:06:03 PM UTC 24 |
| Finished | Sep 09 07:06:19 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852002753 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_smoke.3852002753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/17.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_lock.3832907594 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 1846995586 ps |
| CPU time | 18.26 seconds |
| Started | Sep 09 07:04:33 PM UTC 24 |
| Finished | Sep 09 07:04:53 PM UTC 24 |
| Peak memory | 257436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832907594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.3832907594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_init_fail.4050532630 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1517371488 ps |
| CPU time | 3.3 seconds |
| Started | Sep 09 07:13:02 PM UTC 24 |
| Finished | Sep 09 07:13:07 PM UTC 24 |
| Peak memory | 251520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050532630 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.4050532630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/187.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/279.otp_ctrl_init_fail.2680674088 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 1881278476 ps |
| CPU time | 3.09 seconds |
| Started | Sep 09 07:13:41 PM UTC 24 |
| Finished | Sep 09 07:13:46 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680674088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.2680674088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/279.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_req.1466166282 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 2172013662 ps |
| CPU time | 17.52 seconds |
| Started | Sep 09 07:05:15 PM UTC 24 |
| Finished | Sep 09 07:05:34 PM UTC 24 |
| Peak memory | 257432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466166282 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_req.1466166282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_smoke.2206238719 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 543744870 ps |
| CPU time | 7.25 seconds |
| Started | Sep 09 07:05:15 PM UTC 24 |
| Finished | Sep 09 07:05:24 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206238719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_smoke.2206238719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all.746174343 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 23701088870 ps |
| CPU time | 198.12 seconds |
| Started | Sep 09 07:05:29 PM UTC 24 |
| Finished | Sep 09 07:08:51 PM UTC 24 |
| Peak memory | 257488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746174343 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all.746174343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_parallel_lc_esc.842833689 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 1983408376 ps |
| CPU time | 7.6 seconds |
| Started | Sep 09 07:12:21 PM UTC 24 |
| Finished | Sep 09 07:12:30 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842833689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.842833689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/132.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_bit_bash.2292324188 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 3717374034 ps |
| CPU time | 6.16 seconds |
| Started | Sep 09 11:45:27 AM UTC 24 |
| Finished | Sep 09 11:45:35 AM UTC 24 |
| Peak memory | 252768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292324188 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_bash.2292324188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_hw_reset.3513810232 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 269105659 ps |
| CPU time | 1.78 seconds |
| Started | Sep 09 11:45:27 AM UTC 24 |
| Finished | Sep 09 11:45:31 AM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513810232 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_reset.3513810232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_mem_rw_with_rand_reset.3466256095 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 204027667 ps |
| CPU time | 3.41 seconds |
| Started | Sep 09 11:45:27 AM UTC 24 |
| Finished | Sep 09 11:45:33 AM UTC 24 |
| Peak memory | 259036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3466256095 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_cs r_mem_rw_with_rand_reset.3466256095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_csr_rw.4017168326 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 41004882 ps |
| CPU time | 1.42 seconds |
| Started | Sep 09 11:45:27 AM UTC 24 |
| Finished | Sep 09 11:45:30 AM UTC 24 |
| Peak memory | 253940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017168326 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.4017168326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_intr_test.131732081 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 131542980 ps |
| CPU time | 1.39 seconds |
| Started | Sep 09 11:45:26 AM UTC 24 |
| Finished | Sep 09 11:45:35 AM UTC 24 |
| Peak memory | 241188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131732081 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.131732081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_partial_access.2522891539 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 37284902 ps |
| CPU time | 1.22 seconds |
| Started | Sep 09 11:45:27 AM UTC 24 |
| Finished | Sep 09 11:45:30 AM UTC 24 |
| Peak memory | 240636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522891539 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_partial_access.2522891539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_mem_walk.3013785624 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 41218872 ps |
| CPU time | 1.22 seconds |
| Started | Sep 09 11:45:26 AM UTC 24 |
| Finished | Sep 09 11:45:35 AM UTC 24 |
| Peak memory | 240328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013785624 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.3013785624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_same_csr_outstanding.160429271 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 49515686 ps |
| CPU time | 1.8 seconds |
| Started | Sep 09 11:45:27 AM UTC 24 |
| Finished | Sep 09 11:45:31 AM UTC 24 |
| Peak memory | 251952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160429271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_same_csr_outstanding.160429271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/0.otp_ctrl_tl_errors.4042354186 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 292275965 ps |
| CPU time | 3.88 seconds |
| Started | Sep 09 11:45:26 AM UTC 24 |
| Finished | Sep 09 11:45:38 AM UTC 24 |
| Peak memory | 257200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042354186 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.4042354186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_aliasing.3120869579 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 111703367 ps |
| CPU time | 2.68 seconds |
| Started | Sep 09 11:45:31 AM UTC 24 |
| Finished | Sep 09 11:45:36 AM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120869579 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_aliasing.3120869579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_bit_bash.3425046024 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 473316084 ps |
| CPU time | 8.73 seconds |
| Started | Sep 09 11:45:31 AM UTC 24 |
| Finished | Sep 09 11:45:42 AM UTC 24 |
| Peak memory | 252636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425046024 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_bit_bash.3425046024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_hw_reset.2118747939 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 136461126 ps |
| CPU time | 2.29 seconds |
| Started | Sep 09 11:45:30 AM UTC 24 |
| Finished | Sep 09 11:45:41 AM UTC 24 |
| Peak memory | 252808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118747939 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_hw_reset.2118747939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_csr_mem_rw_with_rand_reset.2387610598 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 1628664754 ps |
| CPU time | 2.8 seconds |
| Started | Sep 09 11:45:31 AM UTC 24 |
| Finished | Sep 09 11:45:36 AM UTC 24 |
| Peak memory | 258972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2387610598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_cs r_mem_rw_with_rand_reset.2387610598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_intr_test.3032636766 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 620259172 ps |
| CPU time | 1.59 seconds |
| Started | Sep 09 11:45:30 AM UTC 24 |
| Finished | Sep 09 11:45:40 AM UTC 24 |
| Peak memory | 241696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032636766 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.3032636766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_partial_access.3926222958 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 65730200 ps |
| CPU time | 1.65 seconds |
| Started | Sep 09 11:45:30 AM UTC 24 |
| Finished | Sep 09 11:45:43 AM UTC 24 |
| Peak memory | 240268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926222958 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_partial_access.3926222958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_mem_walk.2755324058 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 508052222 ps |
| CPU time | 2.44 seconds |
| Started | Sep 09 11:45:30 AM UTC 24 |
| Finished | Sep 09 11:45:44 AM UTC 24 |
| Peak memory | 241220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755324058 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_mem_walk.2755324058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_same_csr_outstanding.2046420236 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 110581008 ps |
| CPU time | 2.8 seconds |
| Started | Sep 09 11:45:31 AM UTC 24 |
| Finished | Sep 09 11:45:36 AM UTC 24 |
| Peak memory | 252776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046420236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_same_csr_outstanding.2046420236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_errors.1902708665 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 396431222 ps |
| CPU time | 3.67 seconds |
| Started | Sep 09 11:45:27 AM UTC 24 |
| Finished | Sep 09 11:45:33 AM UTC 24 |
| Peak memory | 259028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902708665 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.1902708665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/1.otp_ctrl_tl_intg_err.1966087390 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 20202953319 ps |
| CPU time | 16.8 seconds |
| Started | Sep 09 11:45:28 AM UTC 24 |
| Finished | Sep 09 11:45:56 AM UTC 24 |
| Peak memory | 258996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966087390 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_intg_err.1966087390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_mem_rw_with_rand_reset.3074768278 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 75240243 ps |
| CPU time | 2.26 seconds |
| Started | Sep 09 11:45:51 AM UTC 24 |
| Finished | Sep 09 11:45:56 AM UTC 24 |
| Peak memory | 258912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3074768278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_c sr_mem_rw_with_rand_reset.3074768278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_csr_rw.3930427214 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 679832678 ps |
| CPU time | 2.21 seconds |
| Started | Sep 09 11:45:51 AM UTC 24 |
| Finished | Sep 09 11:45:56 AM UTC 24 |
| Peak memory | 254808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930427214 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_csr_rw.3930427214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_intr_test.1244303411 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 604736510 ps |
| CPU time | 1.97 seconds |
| Started | Sep 09 11:45:51 AM UTC 24 |
| Finished | Sep 09 11:45:55 AM UTC 24 |
| Peak memory | 241196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244303411 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_intr_test.1244303411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_same_csr_outstanding.2494641539 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 372721185 ps |
| CPU time | 3.88 seconds |
| Started | Sep 09 11:45:51 AM UTC 24 |
| Finished | Sep 09 11:45:57 AM UTC 24 |
| Peak memory | 254932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494641539 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_same_csr_outstanding.2494641539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/10.otp_ctrl_tl_errors.2097349079 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 118559703 ps |
| CPU time | 2.9 seconds |
| Started | Sep 09 11:45:51 AM UTC 24 |
| Finished | Sep 09 11:45:56 AM UTC 24 |
| Peak memory | 258964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097349079 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.2097349079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_mem_rw_with_rand_reset.3440620391 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 80855022 ps |
| CPU time | 2.13 seconds |
| Started | Sep 09 11:45:53 AM UTC 24 |
| Finished | Sep 09 11:46:06 AM UTC 24 |
| Peak memory | 258948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3440620391 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_c sr_mem_rw_with_rand_reset.3440620391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_csr_rw.1388472663 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 70880123 ps |
| CPU time | 1.57 seconds |
| Started | Sep 09 11:45:53 AM UTC 24 |
| Finished | Sep 09 11:45:55 AM UTC 24 |
| Peak memory | 254020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388472663 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_csr_rw.1388472663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_intr_test.3690864931 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 38686873 ps |
| CPU time | 1.45 seconds |
| Started | Sep 09 11:45:53 AM UTC 24 |
| Finished | Sep 09 11:45:55 AM UTC 24 |
| Peak memory | 241748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690864931 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_intr_test.3690864931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_same_csr_outstanding.1095575542 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 85659768 ps |
| CPU time | 2.37 seconds |
| Started | Sep 09 11:45:53 AM UTC 24 |
| Finished | Sep 09 11:45:56 AM UTC 24 |
| Peak memory | 252724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095575542 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_same_csr_outstanding.1095575542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_errors.1783541930 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 116874499 ps |
| CPU time | 3.74 seconds |
| Started | Sep 09 11:45:51 AM UTC 24 |
| Finished | Sep 09 11:45:57 AM UTC 24 |
| Peak memory | 259028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783541930 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.1783541930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/11.otp_ctrl_tl_intg_err.16997641 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 4556970231 ps |
| CPU time | 20.86 seconds |
| Started | Sep 09 11:45:53 AM UTC 24 |
| Finished | Sep 09 11:46:15 AM UTC 24 |
| Peak memory | 256900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16997641 -assert nopostproc +UVM_TESTN AME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_intg_err.16997641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_mem_rw_with_rand_reset.4206923246 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 73419764 ps |
| CPU time | 2.11 seconds |
| Started | Sep 09 11:45:54 AM UTC 24 |
| Finished | Sep 09 11:46:00 AM UTC 24 |
| Peak memory | 258756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4206923246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_c sr_mem_rw_with_rand_reset.4206923246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_csr_rw.1980057043 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 42108461 ps |
| CPU time | 2.47 seconds |
| Started | Sep 09 11:45:54 AM UTC 24 |
| Finished | Sep 09 11:46:00 AM UTC 24 |
| Peak memory | 252676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980057043 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_csr_rw.1980057043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_intr_test.3245863287 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 141614736 ps |
| CPU time | 2.18 seconds |
| Started | Sep 09 11:45:53 AM UTC 24 |
| Finished | Sep 09 11:46:06 AM UTC 24 |
| Peak memory | 241704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245863287 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_intr_test.3245863287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_same_csr_outstanding.2082832637 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 107305710 ps |
| CPU time | 2.38 seconds |
| Started | Sep 09 11:45:54 AM UTC 24 |
| Finished | Sep 09 11:46:00 AM UTC 24 |
| Peak memory | 252832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082832637 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_same_csr_outstanding.2082832637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/12.otp_ctrl_tl_errors.2126293962 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 206323759 ps |
| CPU time | 3.29 seconds |
| Started | Sep 09 11:45:53 AM UTC 24 |
| Finished | Sep 09 11:45:57 AM UTC 24 |
| Peak memory | 258952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126293962 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.2126293962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_mem_rw_with_rand_reset.1526260572 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 240597053 ps |
| CPU time | 3.17 seconds |
| Started | Sep 09 11:45:56 AM UTC 24 |
| Finished | Sep 09 11:46:02 AM UTC 24 |
| Peak memory | 258908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1526260572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_c sr_mem_rw_with_rand_reset.1526260572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_csr_rw.2415311215 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 695142234 ps |
| CPU time | 2.33 seconds |
| Started | Sep 09 11:45:56 AM UTC 24 |
| Finished | Sep 09 11:46:01 AM UTC 24 |
| Peak memory | 254704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2415311215 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_csr_rw.2415311215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_intr_test.133144769 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 39894711 ps |
| CPU time | 1.45 seconds |
| Started | Sep 09 11:45:55 AM UTC 24 |
| Finished | Sep 09 11:46:01 AM UTC 24 |
| Peak memory | 241452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133144769 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_intr_test.133144769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_same_csr_outstanding.897233626 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 167029223 ps |
| CPU time | 2.24 seconds |
| Started | Sep 09 11:45:56 AM UTC 24 |
| Finished | Sep 09 11:46:00 AM UTC 24 |
| Peak memory | 254680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897233626 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_same_csr_outstanding.897233626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_errors.1539080851 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 101984522 ps |
| CPU time | 3.24 seconds |
| Started | Sep 09 11:45:54 AM UTC 24 |
| Finished | Sep 09 11:46:01 AM UTC 24 |
| Peak memory | 258680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539080851 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.1539080851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/13.otp_ctrl_tl_intg_err.3186120027 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1236913944 ps |
| CPU time | 17.78 seconds |
| Started | Sep 09 11:45:55 AM UTC 24 |
| Finished | Sep 09 11:46:17 AM UTC 24 |
| Peak memory | 256796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186120027 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_intg_err.3186120027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_mem_rw_with_rand_reset.3515777582 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 223086889 ps |
| CPU time | 3.5 seconds |
| Started | Sep 09 11:45:57 AM UTC 24 |
| Finished | Sep 09 11:46:02 AM UTC 24 |
| Peak memory | 258876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3515777582 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_c sr_mem_rw_with_rand_reset.3515777582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/14.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_csr_rw.337415431 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 38293960 ps |
| CPU time | 2.06 seconds |
| Started | Sep 09 11:45:56 AM UTC 24 |
| Finished | Sep 09 11:46:00 AM UTC 24 |
| Peak memory | 254884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337415431 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_csr_rw.337415431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/14.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_intr_test.3582104565 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 571784363 ps |
| CPU time | 2.11 seconds |
| Started | Sep 09 11:45:56 AM UTC 24 |
| Finished | Sep 09 11:46:00 AM UTC 24 |
| Peak memory | 241124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582104565 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_intr_test.3582104565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/14.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_same_csr_outstanding.1271689067 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 66261269 ps |
| CPU time | 2.71 seconds |
| Started | Sep 09 11:45:57 AM UTC 24 |
| Finished | Sep 09 11:46:01 AM UTC 24 |
| Peak memory | 254724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271689067 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_same_csr_outstanding.1271689067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/14.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_errors.3428402413 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 1289728255 ps |
| CPU time | 6 seconds |
| Started | Sep 09 11:45:56 AM UTC 24 |
| Finished | Sep 09 11:46:04 AM UTC 24 |
| Peak memory | 259036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428402413 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.3428402413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/14.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/14.otp_ctrl_tl_intg_err.3721505960 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 2644916403 ps |
| CPU time | 16.13 seconds |
| Started | Sep 09 11:45:56 AM UTC 24 |
| Finished | Sep 09 11:46:15 AM UTC 24 |
| Peak memory | 256976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721505960 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_intg_err.3721505960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/14.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_mem_rw_with_rand_reset.3613597418 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 72342237 ps |
| CPU time | 2.76 seconds |
| Started | Sep 09 11:45:59 AM UTC 24 |
| Finished | Sep 09 11:46:05 AM UTC 24 |
| Peak memory | 258976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3613597418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_c sr_mem_rw_with_rand_reset.3613597418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_csr_rw.3845992403 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 47312151 ps |
| CPU time | 1.76 seconds |
| Started | Sep 09 11:45:59 AM UTC 24 |
| Finished | Sep 09 11:46:01 AM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845992403 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_csr_rw.3845992403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_intr_test.1579269940 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 78125336 ps |
| CPU time | 1.29 seconds |
| Started | Sep 09 11:45:58 AM UTC 24 |
| Finished | Sep 09 11:46:00 AM UTC 24 |
| Peak memory | 241188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579269940 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_intr_test.1579269940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_same_csr_outstanding.3065915432 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 54692868 ps |
| CPU time | 2.58 seconds |
| Started | Sep 09 11:45:59 AM UTC 24 |
| Finished | Sep 09 11:46:05 AM UTC 24 |
| Peak memory | 252764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065915432 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_same_csr_outstanding.3065915432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/15.otp_ctrl_tl_errors.96416080 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 692967236 ps |
| CPU time | 5.55 seconds |
| Started | Sep 09 11:45:57 AM UTC 24 |
| Finished | Sep 09 11:46:04 AM UTC 24 |
| Peak memory | 258960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96416080 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.96416080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_mem_rw_with_rand_reset.760454285 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 281861184 ps |
| CPU time | 2.09 seconds |
| Started | Sep 09 11:46:01 AM UTC 24 |
| Finished | Sep 09 11:46:05 AM UTC 24 |
| Peak memory | 258828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=760454285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_cs r_mem_rw_with_rand_reset.760454285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_csr_rw.3530863891 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 633522945 ps |
| CPU time | 2.26 seconds |
| Started | Sep 09 11:46:01 AM UTC 24 |
| Finished | Sep 09 11:46:07 AM UTC 24 |
| Peak memory | 252632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530863891 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_csr_rw.3530863891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_intr_test.902327969 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 75374143 ps |
| CPU time | 1.78 seconds |
| Started | Sep 09 11:46:01 AM UTC 24 |
| Finished | Sep 09 11:46:05 AM UTC 24 |
| Peak memory | 241140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902327969 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_intr_test.902327969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_same_csr_outstanding.630049627 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 352453139 ps |
| CPU time | 2.56 seconds |
| Started | Sep 09 11:46:01 AM UTC 24 |
| Finished | Sep 09 11:46:06 AM UTC 24 |
| Peak memory | 252632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630049627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_same_csr_outstanding.630049627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_errors.2517737171 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 1255514712 ps |
| CPU time | 6.04 seconds |
| Started | Sep 09 11:46:00 AM UTC 24 |
| Finished | Sep 09 11:46:10 AM UTC 24 |
| Peak memory | 258960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517737171 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.2517737171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/16.otp_ctrl_tl_intg_err.2521473605 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 10340363353 ps |
| CPU time | 12.04 seconds |
| Started | Sep 09 11:46:01 AM UTC 24 |
| Finished | Sep 09 11:46:17 AM UTC 24 |
| Peak memory | 252944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521473605 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_intg_err.2521473605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_mem_rw_with_rand_reset.54861056 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 81745965 ps |
| CPU time | 1.91 seconds |
| Started | Sep 09 11:46:02 AM UTC 24 |
| Finished | Sep 09 11:46:05 AM UTC 24 |
| Peak memory | 255984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=54861056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr _mem_rw_with_rand_reset.54861056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/17.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_csr_rw.1512723626 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 639746108 ps |
| CPU time | 1.89 seconds |
| Started | Sep 09 11:46:01 AM UTC 24 |
| Finished | Sep 09 11:46:05 AM UTC 24 |
| Peak memory | 251844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512723626 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_csr_rw.1512723626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/17.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_intr_test.1602452148 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 564087914 ps |
| CPU time | 2.1 seconds |
| Started | Sep 09 11:46:01 AM UTC 24 |
| Finished | Sep 09 11:46:05 AM UTC 24 |
| Peak memory | 241728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602452148 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_intr_test.1602452148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/17.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_same_csr_outstanding.3865918469 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 77624625 ps |
| CPU time | 2.16 seconds |
| Started | Sep 09 11:46:02 AM UTC 24 |
| Finished | Sep 09 11:46:05 AM UTC 24 |
| Peak memory | 252632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865918469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_same_csr_outstanding.3865918469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/17.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_errors.1341395470 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 380273490 ps |
| CPU time | 6.43 seconds |
| Started | Sep 09 11:46:01 AM UTC 24 |
| Finished | Sep 09 11:46:10 AM UTC 24 |
| Peak memory | 259028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341395470 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1341395470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/17.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/17.otp_ctrl_tl_intg_err.1172695178 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1280875426 ps |
| CPU time | 19.77 seconds |
| Started | Sep 09 11:46:01 AM UTC 24 |
| Finished | Sep 09 11:46:23 AM UTC 24 |
| Peak memory | 256908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172695178 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_intg_err.1172695178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/17.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_mem_rw_with_rand_reset.1003265912 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 250819253 ps |
| CPU time | 3.56 seconds |
| Started | Sep 09 11:46:05 AM UTC 24 |
| Finished | Sep 09 11:46:09 AM UTC 24 |
| Peak memory | 259160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1003265912 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_c sr_mem_rw_with_rand_reset.1003265912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_csr_rw.2356720391 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 46575134 ps |
| CPU time | 2.27 seconds |
| Started | Sep 09 11:46:02 AM UTC 24 |
| Finished | Sep 09 11:46:06 AM UTC 24 |
| Peak memory | 252780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356720391 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_csr_rw.2356720391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_intr_test.2728985509 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 587343844 ps |
| CPU time | 2.23 seconds |
| Started | Sep 09 11:46:02 AM UTC 24 |
| Finished | Sep 09 11:46:06 AM UTC 24 |
| Peak memory | 241672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728985509 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_intr_test.2728985509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_same_csr_outstanding.1019354649 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 65451655 ps |
| CPU time | 2.11 seconds |
| Started | Sep 09 11:46:03 AM UTC 24 |
| Finished | Sep 09 11:46:07 AM UTC 24 |
| Peak memory | 252884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019354649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_same_csr_outstanding.1019354649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_errors.1063999727 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 364047058 ps |
| CPU time | 4.59 seconds |
| Started | Sep 09 11:46:02 AM UTC 24 |
| Finished | Sep 09 11:46:08 AM UTC 24 |
| Peak memory | 258920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063999727 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.1063999727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/18.otp_ctrl_tl_intg_err.1115564551 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 20008519689 ps |
| CPU time | 62.61 seconds |
| Started | Sep 09 11:46:02 AM UTC 24 |
| Finished | Sep 09 11:47:07 AM UTC 24 |
| Peak memory | 256856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115564551 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_intg_err.1115564551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_csr_rw.3838930776 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 44482008 ps |
| CPU time | 1.67 seconds |
| Started | Sep 09 11:46:06 AM UTC 24 |
| Finished | Sep 09 11:46:09 AM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838930776 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_csr_rw.3838930776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_intr_test.267201029 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 582360510 ps |
| CPU time | 2.51 seconds |
| Started | Sep 09 11:46:06 AM UTC 24 |
| Finished | Sep 09 11:46:12 AM UTC 24 |
| Peak memory | 242168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267201029 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_intr_test.267201029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_same_csr_outstanding.3686482343 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 1409173207 ps |
| CPU time | 3.73 seconds |
| Started | Sep 09 11:46:06 AM UTC 24 |
| Finished | Sep 09 11:46:14 AM UTC 24 |
| Peak memory | 252856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686482343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_same_csr_outstanding.3686482343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_errors.2124568737 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 2101956251 ps |
| CPU time | 6 seconds |
| Started | Sep 09 11:46:06 AM UTC 24 |
| Finished | Sep 09 11:46:14 AM UTC 24 |
| Peak memory | 252880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124568737 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.2124568737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/19.otp_ctrl_tl_intg_err.1506031871 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 1428063223 ps |
| CPU time | 11.01 seconds |
| Started | Sep 09 11:46:06 AM UTC 24 |
| Finished | Sep 09 11:46:19 AM UTC 24 |
| Peak memory | 257000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506031871 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_intg_err.1506031871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_aliasing.3902221026 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 302803932 ps |
| CPU time | 4.43 seconds |
| Started | Sep 09 11:45:36 AM UTC 24 |
| Finished | Sep 09 11:45:45 AM UTC 24 |
| Peak memory | 252828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902221026 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_aliasing.3902221026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_bit_bash.1841654782 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 271450360 ps |
| CPU time | 5.12 seconds |
| Started | Sep 09 11:45:36 AM UTC 24 |
| Finished | Sep 09 11:45:45 AM UTC 24 |
| Peak memory | 252760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841654782 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_bit_bash.1841654782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_hw_reset.2314074243 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 99073356 ps |
| CPU time | 2.12 seconds |
| Started | Sep 09 11:45:35 AM UTC 24 |
| Finished | Sep 09 11:45:41 AM UTC 24 |
| Peak memory | 252692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314074243 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_hw_reset.2314074243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_mem_rw_with_rand_reset.3643128242 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 228744707 ps |
| CPU time | 2.27 seconds |
| Started | Sep 09 11:45:36 AM UTC 24 |
| Finished | Sep 09 11:45:43 AM UTC 24 |
| Peak memory | 258880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3643128242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_cs r_mem_rw_with_rand_reset.3643128242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_csr_rw.176283320 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 68364268 ps |
| CPU time | 1.51 seconds |
| Started | Sep 09 11:45:36 AM UTC 24 |
| Finished | Sep 09 11:45:42 AM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176283320 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.176283320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_intr_test.2288455460 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 569846304 ps |
| CPU time | 1.77 seconds |
| Started | Sep 09 11:45:34 AM UTC 24 |
| Finished | Sep 09 11:45:44 AM UTC 24 |
| Peak memory | 241344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288455460 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.2288455460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_partial_access.1113424392 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 136834284 ps |
| CPU time | 1.41 seconds |
| Started | Sep 09 11:45:34 AM UTC 24 |
| Finished | Sep 09 11:45:43 AM UTC 24 |
| Peak memory | 240536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113424392 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_partial_access.1113424392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_mem_walk.2741094841 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 42631633 ps |
| CPU time | 1.64 seconds |
| Started | Sep 09 11:45:34 AM UTC 24 |
| Finished | Sep 09 11:45:44 AM UTC 24 |
| Peak memory | 240596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741094841 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_mem_walk.2741094841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_same_csr_outstanding.732161809 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 557880774 ps |
| CPU time | 3.53 seconds |
| Started | Sep 09 11:45:36 AM UTC 24 |
| Finished | Sep 09 11:45:44 AM UTC 24 |
| Peak memory | 252740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732161809 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_same_csr_outstanding.732161809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/2.otp_ctrl_tl_errors.432683820 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 54996718 ps |
| CPU time | 2.26 seconds |
| Started | Sep 09 11:45:32 AM UTC 24 |
| Finished | Sep 09 11:45:36 AM UTC 24 |
| Peak memory | 258876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432683820 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.432683820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/20.otp_ctrl_intr_test.1454305251 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 47089578 ps |
| CPU time | 1.43 seconds |
| Started | Sep 09 11:46:06 AM UTC 24 |
| Finished | Sep 09 11:46:11 AM UTC 24 |
| Peak memory | 241080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454305251 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_intr_test.1454305251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/20.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/21.otp_ctrl_intr_test.2112718724 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 74219012 ps |
| CPU time | 1.6 seconds |
| Started | Sep 09 11:46:06 AM UTC 24 |
| Finished | Sep 09 11:46:12 AM UTC 24 |
| Peak memory | 241344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112718724 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_intr_test.2112718724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/21.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/22.otp_ctrl_intr_test.97883440 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 74408246 ps |
| CPU time | 1.85 seconds |
| Started | Sep 09 11:46:07 AM UTC 24 |
| Finished | Sep 09 11:46:10 AM UTC 24 |
| Peak memory | 241460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97883440 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_intr_test.97883440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/22.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/23.otp_ctrl_intr_test.2769228453 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 72478558 ps |
| CPU time | 1.66 seconds |
| Started | Sep 09 11:46:07 AM UTC 24 |
| Finished | Sep 09 11:46:10 AM UTC 24 |
| Peak memory | 241068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769228453 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_intr_test.2769228453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/23.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/24.otp_ctrl_intr_test.1285287982 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 506639700 ps |
| CPU time | 1.85 seconds |
| Started | Sep 09 11:46:07 AM UTC 24 |
| Finished | Sep 09 11:46:10 AM UTC 24 |
| Peak memory | 241128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285287982 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_intr_test.1285287982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/24.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/25.otp_ctrl_intr_test.56659218 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 154662769 ps |
| CPU time | 1.75 seconds |
| Started | Sep 09 11:46:07 AM UTC 24 |
| Finished | Sep 09 11:46:10 AM UTC 24 |
| Peak memory | 241460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56659218 -assert nopostproc +UVM_TESTNAME=otp_ctrl _base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_intr_test.56659218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/25.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/26.otp_ctrl_intr_test.1887011470 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 73320813 ps |
| CPU time | 1.48 seconds |
| Started | Sep 09 11:46:07 AM UTC 24 |
| Finished | Sep 09 11:46:10 AM UTC 24 |
| Peak memory | 241188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887011470 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_intr_test.1887011470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/26.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/27.otp_ctrl_intr_test.1347355540 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 144843842 ps |
| CPU time | 1.83 seconds |
| Started | Sep 09 11:46:07 AM UTC 24 |
| Finished | Sep 09 11:46:10 AM UTC 24 |
| Peak memory | 241696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347355540 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_intr_test.1347355540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/27.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/28.otp_ctrl_intr_test.1448992061 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 139898369 ps |
| CPU time | 2.14 seconds |
| Started | Sep 09 11:46:07 AM UTC 24 |
| Finished | Sep 09 11:46:10 AM UTC 24 |
| Peak memory | 241972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448992061 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_intr_test.1448992061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/28.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/29.otp_ctrl_intr_test.1745658510 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 47210067 ps |
| CPU time | 1.68 seconds |
| Started | Sep 09 11:46:07 AM UTC 24 |
| Finished | Sep 09 11:46:10 AM UTC 24 |
| Peak memory | 241696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745658510 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_intr_test.1745658510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/29.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_aliasing.3248050504 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 154087312 ps |
| CPU time | 4.48 seconds |
| Started | Sep 09 11:45:41 AM UTC 24 |
| Finished | Sep 09 11:45:47 AM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248050504 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_aliasing.3248050504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_bit_bash.3153789138 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 894202357 ps |
| CPU time | 5.84 seconds |
| Started | Sep 09 11:45:41 AM UTC 24 |
| Finished | Sep 09 11:45:49 AM UTC 24 |
| Peak memory | 252628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153789138 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_bit_bash.3153789138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_hw_reset.3073082547 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 101690673 ps |
| CPU time | 2.18 seconds |
| Started | Sep 09 11:45:38 AM UTC 24 |
| Finished | Sep 09 11:45:42 AM UTC 24 |
| Peak memory | 252948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073082547 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_hw_reset.3073082547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_mem_rw_with_rand_reset.1318986140 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 177064442 ps |
| CPU time | 2.86 seconds |
| Started | Sep 09 11:45:41 AM UTC 24 |
| Finished | Sep 09 11:45:46 AM UTC 24 |
| Peak memory | 258972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1318986140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_cs r_mem_rw_with_rand_reset.1318986140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_csr_rw.4226240183 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 174224177 ps |
| CPU time | 1.85 seconds |
| Started | Sep 09 11:45:40 AM UTC 24 |
| Finished | Sep 09 11:45:43 AM UTC 24 |
| Peak memory | 251872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226240183 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.4226240183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_intr_test.1006464581 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 39704260 ps |
| CPU time | 1.21 seconds |
| Started | Sep 09 11:45:37 AM UTC 24 |
| Finished | Sep 09 11:45:40 AM UTC 24 |
| Peak memory | 240928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006464581 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.1006464581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_partial_access.2249653503 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 40395325 ps |
| CPU time | 1.19 seconds |
| Started | Sep 09 11:45:37 AM UTC 24 |
| Finished | Sep 09 11:45:40 AM UTC 24 |
| Peak memory | 240268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249653503 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_partial_access.2249653503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_mem_walk.1076149535 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 554498734 ps |
| CPU time | 1.85 seconds |
| Started | Sep 09 11:45:37 AM UTC 24 |
| Finished | Sep 09 11:45:40 AM UTC 24 |
| Peak memory | 240596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076149535 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_mem_walk.1076149535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_same_csr_outstanding.2692086729 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 167319212 ps |
| CPU time | 1.81 seconds |
| Started | Sep 09 11:45:41 AM UTC 24 |
| Finished | Sep 09 11:45:44 AM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692086729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_same_csr_outstanding.2692086729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_errors.452546382 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 172116624 ps |
| CPU time | 3.11 seconds |
| Started | Sep 09 11:45:36 AM UTC 24 |
| Finished | Sep 09 11:45:44 AM UTC 24 |
| Peak memory | 258888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452546382 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.452546382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/3.otp_ctrl_tl_intg_err.128718979 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 10329540623 ps |
| CPU time | 12.49 seconds |
| Started | Sep 09 11:45:37 AM UTC 24 |
| Finished | Sep 09 11:45:52 AM UTC 24 |
| Peak memory | 256720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128718979 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_intg_err.128718979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/30.otp_ctrl_intr_test.952671535 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 69766483 ps |
| CPU time | 1.77 seconds |
| Started | Sep 09 11:46:07 AM UTC 24 |
| Finished | Sep 09 11:46:10 AM UTC 24 |
| Peak memory | 241132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952671535 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_intr_test.952671535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/30.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/31.otp_ctrl_intr_test.1950483964 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 126675808 ps |
| CPU time | 1.56 seconds |
| Started | Sep 09 11:46:07 AM UTC 24 |
| Finished | Sep 09 11:46:10 AM UTC 24 |
| Peak memory | 241748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950483964 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_intr_test.1950483964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/31.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/32.otp_ctrl_intr_test.1221475756 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 89188919 ps |
| CPU time | 1.44 seconds |
| Started | Sep 09 11:46:08 AM UTC 24 |
| Finished | Sep 09 11:46:11 AM UTC 24 |
| Peak memory | 241132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221475756 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_intr_test.1221475756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/32.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/33.otp_ctrl_intr_test.2897135379 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 577285362 ps |
| CPU time | 1.6 seconds |
| Started | Sep 09 11:46:08 AM UTC 24 |
| Finished | Sep 09 11:46:11 AM UTC 24 |
| Peak memory | 241112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897135379 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_intr_test.2897135379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/33.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/34.otp_ctrl_intr_test.1889441930 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 42674160 ps |
| CPU time | 1.81 seconds |
| Started | Sep 09 11:46:09 AM UTC 24 |
| Finished | Sep 09 11:46:12 AM UTC 24 |
| Peak memory | 241196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889441930 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_intr_test.1889441930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/34.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/35.otp_ctrl_intr_test.3638922581 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 77282368 ps |
| CPU time | 1.65 seconds |
| Started | Sep 09 11:46:11 AM UTC 24 |
| Finished | Sep 09 11:46:13 AM UTC 24 |
| Peak memory | 241168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638922581 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_intr_test.3638922581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/35.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/36.otp_ctrl_intr_test.114815870 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 85402175 ps |
| CPU time | 1.72 seconds |
| Started | Sep 09 11:46:11 AM UTC 24 |
| Finished | Sep 09 11:46:13 AM UTC 24 |
| Peak memory | 241452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114815870 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_intr_test.114815870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/36.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/37.otp_ctrl_intr_test.4070622446 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 621026684 ps |
| CPU time | 1.62 seconds |
| Started | Sep 09 11:46:11 AM UTC 24 |
| Finished | Sep 09 11:46:13 AM UTC 24 |
| Peak memory | 241696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070622446 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_intr_test.4070622446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/37.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/38.otp_ctrl_intr_test.1138871154 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 82383403 ps |
| CPU time | 1.97 seconds |
| Started | Sep 09 11:46:11 AM UTC 24 |
| Finished | Sep 09 11:46:14 AM UTC 24 |
| Peak memory | 241748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138871154 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_intr_test.1138871154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/38.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/39.otp_ctrl_intr_test.1174695428 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 37511523 ps |
| CPU time | 1.42 seconds |
| Started | Sep 09 11:46:11 AM UTC 24 |
| Finished | Sep 09 11:46:13 AM UTC 24 |
| Peak memory | 241188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174695428 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_intr_test.1174695428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/39.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_aliasing.1430063407 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 166154268 ps |
| CPU time | 5.47 seconds |
| Started | Sep 09 11:45:44 AM UTC 24 |
| Finished | Sep 09 11:45:51 AM UTC 24 |
| Peak memory | 252660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430063407 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_aliasing.1430063407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_bit_bash.688571600 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 273172368 ps |
| CPU time | 5.21 seconds |
| Started | Sep 09 11:45:44 AM UTC 24 |
| Finished | Sep 09 11:45:50 AM UTC 24 |
| Peak memory | 252644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688571600 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_bit_bash.688571600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_hw_reset.3191420971 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 195366163 ps |
| CPU time | 2.46 seconds |
| Started | Sep 09 11:45:43 AM UTC 24 |
| Finished | Sep 09 11:45:46 AM UTC 24 |
| Peak memory | 252744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191420971 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_hw_reset.3191420971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_mem_rw_with_rand_reset.1554666286 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 235873176 ps |
| CPU time | 2.76 seconds |
| Started | Sep 09 11:45:44 AM UTC 24 |
| Finished | Sep 09 11:45:48 AM UTC 24 |
| Peak memory | 258908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1554666286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_cs r_mem_rw_with_rand_reset.1554666286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_csr_rw.2272450907 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 100038948 ps |
| CPU time | 2.35 seconds |
| Started | Sep 09 11:45:44 AM UTC 24 |
| Finished | Sep 09 11:45:47 AM UTC 24 |
| Peak memory | 252684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272450907 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.2272450907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_intr_test.2271999861 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 42787629 ps |
| CPU time | 1.48 seconds |
| Started | Sep 09 11:45:43 AM UTC 24 |
| Finished | Sep 09 11:45:45 AM UTC 24 |
| Peak memory | 241136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2271999861 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.2271999861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_partial_access.1368549967 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 138458779 ps |
| CPU time | 1.28 seconds |
| Started | Sep 09 11:45:43 AM UTC 24 |
| Finished | Sep 09 11:45:45 AM UTC 24 |
| Peak memory | 240268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368549967 -assert nopostproc + UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_partial_access.1368549967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_mem_walk.3271819394 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 66788346 ps |
| CPU time | 1.48 seconds |
| Started | Sep 09 11:45:43 AM UTC 24 |
| Finished | Sep 09 11:45:45 AM UTC 24 |
| Peak memory | 240332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271819394 -assert nopostproc +UVM_TESTNA ME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_mem_walk.3271819394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_same_csr_outstanding.3492693025 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 99138559 ps |
| CPU time | 2.91 seconds |
| Started | Sep 09 11:45:44 AM UTC 24 |
| Finished | Sep 09 11:45:48 AM UTC 24 |
| Peak memory | 252764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492693025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_same_csr_outstanding.3492693025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_errors.3252932272 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 207200780 ps |
| CPU time | 3.94 seconds |
| Started | Sep 09 11:45:41 AM UTC 24 |
| Finished | Sep 09 11:45:47 AM UTC 24 |
| Peak memory | 259092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252932272 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.3252932272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/4.otp_ctrl_tl_intg_err.1271880725 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 2475342040 ps |
| CPU time | 16.52 seconds |
| Started | Sep 09 11:45:41 AM UTC 24 |
| Finished | Sep 09 11:46:00 AM UTC 24 |
| Peak memory | 252816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271880725 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_intg_err.1271880725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/40.otp_ctrl_intr_test.1544303596 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 79856594 ps |
| CPU time | 1.48 seconds |
| Started | Sep 09 11:46:11 AM UTC 24 |
| Finished | Sep 09 11:46:13 AM UTC 24 |
| Peak memory | 241076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544303596 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_intr_test.1544303596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/40.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/41.otp_ctrl_intr_test.3177311593 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 56234856 ps |
| CPU time | 1.92 seconds |
| Started | Sep 09 11:46:11 AM UTC 24 |
| Finished | Sep 09 11:46:14 AM UTC 24 |
| Peak memory | 241696 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177311593 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_intr_test.3177311593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/41.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/42.otp_ctrl_intr_test.169959550 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 72823103 ps |
| CPU time | 2.08 seconds |
| Started | Sep 09 11:46:11 AM UTC 24 |
| Finished | Sep 09 11:46:14 AM UTC 24 |
| Peak memory | 241688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169959550 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_intr_test.169959550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/42.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/43.otp_ctrl_intr_test.1869739609 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 40923373 ps |
| CPU time | 2.17 seconds |
| Started | Sep 09 11:46:11 AM UTC 24 |
| Finished | Sep 09 11:46:14 AM UTC 24 |
| Peak memory | 242668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869739609 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_intr_test.1869739609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/43.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/44.otp_ctrl_intr_test.3005331215 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 39375053 ps |
| CPU time | 1.52 seconds |
| Started | Sep 09 11:46:11 AM UTC 24 |
| Finished | Sep 09 11:46:14 AM UTC 24 |
| Peak memory | 241168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005331215 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_intr_test.3005331215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/44.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/45.otp_ctrl_intr_test.2041141629 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 131050962 ps |
| CPU time | 1.83 seconds |
| Started | Sep 09 11:46:11 AM UTC 24 |
| Finished | Sep 09 11:46:14 AM UTC 24 |
| Peak memory | 241748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041141629 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_intr_test.2041141629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/45.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/46.otp_ctrl_intr_test.3764768809 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 61590501 ps |
| CPU time | 2.01 seconds |
| Started | Sep 09 11:46:11 AM UTC 24 |
| Finished | Sep 09 11:46:14 AM UTC 24 |
| Peak memory | 242540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764768809 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_intr_test.3764768809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/46.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/47.otp_ctrl_intr_test.556625567 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 73893739 ps |
| CPU time | 1.64 seconds |
| Started | Sep 09 11:46:11 AM UTC 24 |
| Finished | Sep 09 11:46:14 AM UTC 24 |
| Peak memory | 241188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556625567 -assert nopostproc +UVM_TESTNAME=otp_ctr l_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_intr_test.556625567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/47.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/48.otp_ctrl_intr_test.2600451718 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 591029117 ps |
| CPU time | 1.9 seconds |
| Started | Sep 09 11:46:11 AM UTC 24 |
| Finished | Sep 09 11:46:14 AM UTC 24 |
| Peak memory | 241196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600451718 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_intr_test.2600451718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/48.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/49.otp_ctrl_intr_test.3823023330 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 45059236 ps |
| CPU time | 1.55 seconds |
| Started | Sep 09 11:46:12 AM UTC 24 |
| Finished | Sep 09 11:46:15 AM UTC 24 |
| Peak memory | 241340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823023330 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_intr_test.3823023330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/49.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_csr_mem_rw_with_rand_reset.3445636006 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 1679562712 ps |
| CPU time | 4.97 seconds |
| Started | Sep 09 11:45:44 AM UTC 24 |
| Finished | Sep 09 11:45:53 AM UTC 24 |
| Peak memory | 258980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3445636006 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_cs r_mem_rw_with_rand_reset.3445636006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_intr_test.2442279034 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 577913203 ps |
| CPU time | 1.42 seconds |
| Started | Sep 09 11:45:44 AM UTC 24 |
| Finished | Sep 09 11:45:47 AM UTC 24 |
| Peak memory | 241196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442279034 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.2442279034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_same_csr_outstanding.3064104185 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 109033140 ps |
| CPU time | 1.85 seconds |
| Started | Sep 09 11:45:44 AM UTC 24 |
| Finished | Sep 09 11:45:50 AM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064104185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_same_csr_outstanding.3064104185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/5.otp_ctrl_tl_errors.2293152023 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 1583318712 ps |
| CPU time | 4.71 seconds |
| Started | Sep 09 11:45:44 AM UTC 24 |
| Finished | Sep 09 11:45:50 AM UTC 24 |
| Peak memory | 252956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293152023 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.2293152023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_mem_rw_with_rand_reset.2870383431 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 399537833 ps |
| CPU time | 2.71 seconds |
| Started | Sep 09 11:45:45 AM UTC 24 |
| Finished | Sep 09 11:45:55 AM UTC 24 |
| Peak memory | 258888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2870383431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_cs r_mem_rw_with_rand_reset.2870383431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_csr_rw.3538696354 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 45007178 ps |
| CPU time | 2.24 seconds |
| Started | Sep 09 11:45:45 AM UTC 24 |
| Finished | Sep 09 11:45:52 AM UTC 24 |
| Peak memory | 252708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538696354 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_csr_rw.3538696354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_intr_test.1228652380 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 149535431 ps |
| CPU time | 1.5 seconds |
| Started | Sep 09 11:45:45 AM UTC 24 |
| Finished | Sep 09 11:46:11 AM UTC 24 |
| Peak memory | 241460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228652380 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.1228652380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_same_csr_outstanding.1071121661 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 111665735 ps |
| CPU time | 2.87 seconds |
| Started | Sep 09 11:45:45 AM UTC 24 |
| Finished | Sep 09 11:45:52 AM UTC 24 |
| Peak memory | 252640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071121661 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_same_csr_outstanding.1071121661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_errors.1701141107 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 490512720 ps |
| CPU time | 5.75 seconds |
| Started | Sep 09 11:45:44 AM UTC 24 |
| Finished | Sep 09 11:45:51 AM UTC 24 |
| Peak memory | 259080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701141107 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.1701141107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/6.otp_ctrl_tl_intg_err.469850556 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 20016555474 ps |
| CPU time | 30.48 seconds |
| Started | Sep 09 11:45:45 AM UTC 24 |
| Finished | Sep 09 11:46:40 AM UTC 24 |
| Peak memory | 252900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469850556 -assert nopostproc +UVM_TEST NAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_intg_err.469850556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_mem_rw_with_rand_reset.2360432203 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 86373423 ps |
| CPU time | 2.34 seconds |
| Started | Sep 09 11:45:47 AM UTC 24 |
| Finished | Sep 09 11:45:51 AM UTC 24 |
| Peak memory | 259164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2360432203 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_cs r_mem_rw_with_rand_reset.2360432203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_csr_rw.3741778284 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 126840778 ps |
| CPU time | 1.77 seconds |
| Started | Sep 09 11:45:46 AM UTC 24 |
| Finished | Sep 09 11:46:05 AM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741778284 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_csr_rw.3741778284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_intr_test.1852011979 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 50211609 ps |
| CPU time | 1.35 seconds |
| Started | Sep 09 11:45:45 AM UTC 24 |
| Finished | Sep 09 11:45:54 AM UTC 24 |
| Peak memory | 241288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852011979 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.1852011979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_same_csr_outstanding.1132153886 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 119559963 ps |
| CPU time | 2.95 seconds |
| Started | Sep 09 11:45:47 AM UTC 24 |
| Finished | Sep 09 11:45:52 AM UTC 24 |
| Peak memory | 254776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132153886 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_same_csr_outstanding.1132153886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_errors.1554187851 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 189910829 ps |
| CPU time | 5.54 seconds |
| Started | Sep 09 11:45:45 AM UTC 24 |
| Finished | Sep 09 11:45:58 AM UTC 24 |
| Peak memory | 259028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554187851 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.1554187851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/7.otp_ctrl_tl_intg_err.3237257226 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 2558625538 ps |
| CPU time | 12.28 seconds |
| Started | Sep 09 11:45:45 AM UTC 24 |
| Finished | Sep 09 11:46:05 AM UTC 24 |
| Peak memory | 256784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237257226 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_intg_err.3237257226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_mem_rw_with_rand_reset.2181530172 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 144872398 ps |
| CPU time | 2.9 seconds |
| Started | Sep 09 11:45:48 AM UTC 24 |
| Finished | Sep 09 11:45:52 AM UTC 24 |
| Peak memory | 259164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2181530172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_cs r_mem_rw_with_rand_reset.2181530172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_csr_rw.2790756653 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 164252255 ps |
| CPU time | 1.99 seconds |
| Started | Sep 09 11:45:47 AM UTC 24 |
| Finished | Sep 09 11:45:51 AM UTC 24 |
| Peak memory | 253952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790756653 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_csr_rw.2790756653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_intr_test.3309110663 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 38647593 ps |
| CPU time | 1.47 seconds |
| Started | Sep 09 11:45:47 AM UTC 24 |
| Finished | Sep 09 11:45:51 AM UTC 24 |
| Peak memory | 241748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309110663 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.3309110663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_same_csr_outstanding.712731271 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 135875156 ps |
| CPU time | 2.59 seconds |
| Started | Sep 09 11:45:48 AM UTC 24 |
| Finished | Sep 09 11:45:52 AM UTC 24 |
| Peak memory | 252756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712731271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_same_csr_outstanding.712731271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_errors.3651005463 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 295654864 ps |
| CPU time | 3.59 seconds |
| Started | Sep 09 11:45:47 AM UTC 24 |
| Finished | Sep 09 11:45:52 AM UTC 24 |
| Peak memory | 259036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651005463 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.3651005463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/8.otp_ctrl_tl_intg_err.2457162235 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 2590994067 ps |
| CPU time | 9.4 seconds |
| Started | Sep 09 11:45:47 AM UTC 24 |
| Finished | Sep 09 11:45:58 AM UTC 24 |
| Peak memory | 252764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457162235 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_intg_err.2457162235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_mem_rw_with_rand_reset.636606579 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 138370743 ps |
| CPU time | 2.41 seconds |
| Started | Sep 09 11:45:49 AM UTC 24 |
| Finished | Sep 09 11:45:56 AM UTC 24 |
| Peak memory | 258876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en _scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=636606579 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr _mem_rw_with_rand_reset.636606579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_csr_rw.106797069 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 82018183 ps |
| CPU time | 1.54 seconds |
| Started | Sep 09 11:45:49 AM UTC 24 |
| Finished | Sep 09 11:45:55 AM UTC 24 |
| Peak memory | 251912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106797069 -assert nopostproc +UVM_TESTNAME=otp_ ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_csr_rw.106797069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_intr_test.2305243520 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 537715553 ps |
| CPU time | 1.7 seconds |
| Started | Sep 09 11:45:48 AM UTC 24 |
| Finished | Sep 09 11:45:51 AM UTC 24 |
| Peak memory | 241196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305243520 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.2305243520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_same_csr_outstanding.184841024 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 76526292 ps |
| CPU time | 2.19 seconds |
| Started | Sep 09 11:45:49 AM UTC 24 |
| Finished | Sep 09 11:45:55 AM UTC 24 |
| Peak memory | 252768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184841024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_same_csr_outstanding.184841024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_errors.1793729434 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 330997939 ps |
| CPU time | 3.72 seconds |
| Started | Sep 09 11:45:48 AM UTC 24 |
| Finished | Sep 09 11:45:53 AM UTC 24 |
| Peak memory | 259036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793729434 -assert nopostproc +UVM_TESTNAME=otp_ct rl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.1793729434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top/9.otp_ctrl_tl_intg_err.3321982535 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 1728355886 ps |
| CPU time | 10.38 seconds |
| Started | Sep 09 11:45:48 AM UTC 24 |
| Finished | Sep 09 11:46:00 AM UTC 24 |
| Peak memory | 256832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321982535 -assert nopostproc +UVM_TES TNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_intg_err.3321982535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_alert_test.1815437791 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 67079512 ps |
| CPU time | 1.65 seconds |
| Started | Sep 09 07:04:24 PM UTC 24 |
| Finished | Sep 09 07:04:27 PM UTC 24 |
| Peak memory | 251100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815437791 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.1815437791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_background_chks.77263155 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 712667424 ps |
| CPU time | 10.9 seconds |
| Started | Sep 09 07:04:23 PM UTC 24 |
| Finished | Sep 09 07:04:35 PM UTC 24 |
| Peak memory | 257520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77263155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.77263155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_low_freq_read.298319837 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 3454058712 ps |
| CPU time | 11.2 seconds |
| Started | Sep 09 07:04:23 PM UTC 24 |
| Finished | Sep 09 07:04:35 PM UTC 24 |
| Peak memory | 250812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298319837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.298319837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_parallel_lc_esc.4078813889 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 1317165891 ps |
| CPU time | 3.95 seconds |
| Started | Sep 09 07:04:23 PM UTC 24 |
| Finished | Sep 09 07:04:28 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078813889 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.4078813889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_partition_walk.3959144286 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 768878412 ps |
| CPU time | 16.95 seconds |
| Started | Sep 09 07:04:23 PM UTC 24 |
| Finished | Sep 09 07:04:41 PM UTC 24 |
| Peak memory | 250724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959144286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.3959144286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_regwen.602088714 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 3273609694 ps |
| CPU time | 7.73 seconds |
| Started | Sep 09 07:04:24 PM UTC 24 |
| Finished | Sep 09 07:04:33 PM UTC 24 |
| Peak memory | 251268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=602088714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.602088714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_smoke.1175890890 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 506707722 ps |
| CPU time | 3.26 seconds |
| Started | Sep 09 07:04:23 PM UTC 24 |
| Finished | Sep 09 07:04:27 PM UTC 24 |
| Peak memory | 251524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175890890 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.1175890890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all.805367301 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 14743841650 ps |
| CPU time | 183.92 seconds |
| Started | Sep 09 07:04:24 PM UTC 24 |
| Finished | Sep 09 07:07:31 PM UTC 24 |
| Peak memory | 268048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805367301 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all.805367301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/0.otp_ctrl_stress_all_with_rand_reset.2416299091 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 14942082666 ps |
| CPU time | 164.27 seconds |
| Started | Sep 09 07:04:24 PM UTC 24 |
| Finished | Sep 09 07:07:12 PM UTC 24 |
| Peak memory | 273776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2416299091 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 0.otp_ctrl_stress_all_with_rand_reset.2416299091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_alert_test.2296214818 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 74447974 ps |
| CPU time | 2.62 seconds |
| Started | Sep 09 07:04:26 PM UTC 24 |
| Finished | Sep 09 07:04:30 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296214818 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.2296214818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_background_chks.58854748 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 1592841902 ps |
| CPU time | 23.94 seconds |
| Started | Sep 09 07:04:24 PM UTC 24 |
| Finished | Sep 09 07:04:50 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58854748 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.58854748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_check_fail.3776730751 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 572768509 ps |
| CPU time | 14.46 seconds |
| Started | Sep 09 07:04:25 PM UTC 24 |
| Finished | Sep 09 07:04:41 PM UTC 24 |
| Peak memory | 253240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776730751 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.3776730751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_dai_errs.905175588 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1324125119 ps |
| CPU time | 18.86 seconds |
| Started | Sep 09 07:04:25 PM UTC 24 |
| Finished | Sep 09 07:04:45 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905175588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.905175588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_macro_errs.4066451702 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2305703145 ps |
| CPU time | 22.79 seconds |
| Started | Sep 09 07:04:25 PM UTC 24 |
| Finished | Sep 09 07:04:49 PM UTC 24 |
| Peak memory | 257888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066451702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.4066451702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_parallel_lc_req.3218141729 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 8054535891 ps |
| CPU time | 28.47 seconds |
| Started | Sep 09 07:04:24 PM UTC 24 |
| Finished | Sep 09 07:04:55 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218141729 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.3218141729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_regwen.2746845488 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 338699020 ps |
| CPU time | 7.22 seconds |
| Started | Sep 09 07:04:25 PM UTC 24 |
| Finished | Sep 09 07:04:33 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746845488 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.2746845488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_sec_cm.2430226385 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 10410824758 ps |
| CPU time | 172.33 seconds |
| Started | Sep 09 07:04:26 PM UTC 24 |
| Finished | Sep 09 07:07:21 PM UTC 24 |
| Peak memory | 287860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430226385 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.2430226385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/1.otp_ctrl_smoke.3747562289 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 241406521 ps |
| CPU time | 5.3 seconds |
| Started | Sep 09 07:04:24 PM UTC 24 |
| Finished | Sep 09 07:04:31 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747562289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.3747562289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_alert_test.829461916 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 172186029 ps |
| CPU time | 2.28 seconds |
| Started | Sep 09 07:05:24 PM UTC 24 |
| Finished | Sep 09 07:05:27 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829461916 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_alert_test.829461916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_check_fail.3378039258 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 11085860194 ps |
| CPU time | 31.41 seconds |
| Started | Sep 09 07:05:21 PM UTC 24 |
| Finished | Sep 09 07:05:53 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378039258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.3378039258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_dai_errs.424460749 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 2884645301 ps |
| CPU time | 19.26 seconds |
| Started | Sep 09 07:05:18 PM UTC 24 |
| Finished | Sep 09 07:05:38 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424460749 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.424460749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_macro_errs.3699050160 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 334199155 ps |
| CPU time | 11.38 seconds |
| Started | Sep 09 07:05:21 PM UTC 24 |
| Finished | Sep 09 07:05:33 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699050160 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_macro_errs.3699050160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_key_req.3049066246 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 1853569844 ps |
| CPU time | 17.63 seconds |
| Started | Sep 09 07:05:21 PM UTC 24 |
| Finished | Sep 09 07:05:40 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049066246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_key_req.3049066246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_parallel_lc_esc.1905641494 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 1706054962 ps |
| CPU time | 9.79 seconds |
| Started | Sep 09 07:05:17 PM UTC 24 |
| Finished | Sep 09 07:05:28 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905641494 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.1905641494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_regwen.85426155 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 3588014987 ps |
| CPU time | 10.09 seconds |
| Started | Sep 09 07:05:21 PM UTC 24 |
| Finished | Sep 09 07:05:32 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85426155 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_ test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ot p_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.85426155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_stress_all.269030933 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 23545512342 ps |
| CPU time | 203.92 seconds |
| Started | Sep 09 07:05:24 PM UTC 24 |
| Finished | Sep 09 07:08:51 PM UTC 24 |
| Peak memory | 284460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269030933 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all.269030933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/10.otp_ctrl_test_access.1765892240 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 1067039782 ps |
| CPU time | 9.8 seconds |
| Started | Sep 09 07:05:21 PM UTC 24 |
| Finished | Sep 09 07:05:32 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765892240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_test_access.1765892240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/10.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_init_fail.2493811913 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 220761515 ps |
| CPU time | 6.35 seconds |
| Started | Sep 09 07:11:52 PM UTC 24 |
| Finished | Sep 09 07:12:00 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493811913 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.2493811913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/100.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/100.otp_ctrl_parallel_lc_esc.3469410541 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 389474274 ps |
| CPU time | 10.04 seconds |
| Started | Sep 09 07:11:52 PM UTC 24 |
| Finished | Sep 09 07:12:04 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469410541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.3469410541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/100.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_init_fail.1547334595 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 181373898 ps |
| CPU time | 7.11 seconds |
| Started | Sep 09 07:11:52 PM UTC 24 |
| Finished | Sep 09 07:12:01 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547334595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.1547334595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/101.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/101.otp_ctrl_parallel_lc_esc.1680520096 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 163208273 ps |
| CPU time | 6.33 seconds |
| Started | Sep 09 07:11:52 PM UTC 24 |
| Finished | Sep 09 07:12:00 PM UTC 24 |
| Peak memory | 251032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680520096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.1680520096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/101.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_init_fail.1113720923 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 435685357 ps |
| CPU time | 4.3 seconds |
| Started | Sep 09 07:11:52 PM UTC 24 |
| Finished | Sep 09 07:11:58 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113720923 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.1113720923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/102.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/102.otp_ctrl_parallel_lc_esc.1789165164 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 582918459 ps |
| CPU time | 6.36 seconds |
| Started | Sep 09 07:11:52 PM UTC 24 |
| Finished | Sep 09 07:12:00 PM UTC 24 |
| Peak memory | 250456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789165164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.1789165164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/102.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_init_fail.2140774283 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 285069637 ps |
| CPU time | 4.85 seconds |
| Started | Sep 09 07:11:52 PM UTC 24 |
| Finished | Sep 09 07:11:59 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140774283 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.2140774283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/103.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/103.otp_ctrl_parallel_lc_esc.3418979887 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 198408034 ps |
| CPU time | 6.55 seconds |
| Started | Sep 09 07:11:53 PM UTC 24 |
| Finished | Sep 09 07:12:01 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418979887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.3418979887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/103.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_init_fail.2390454822 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 292687614 ps |
| CPU time | 5.57 seconds |
| Started | Sep 09 07:11:53 PM UTC 24 |
| Finished | Sep 09 07:12:00 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390454822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.2390454822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/104.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/104.otp_ctrl_parallel_lc_esc.3245818991 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 372323643 ps |
| CPU time | 14.21 seconds |
| Started | Sep 09 07:11:53 PM UTC 24 |
| Finished | Sep 09 07:12:08 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245818991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.3245818991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/104.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/105.otp_ctrl_parallel_lc_esc.3855259865 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 658675948 ps |
| CPU time | 9.28 seconds |
| Started | Sep 09 07:11:57 PM UTC 24 |
| Finished | Sep 09 07:12:08 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855259865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.3855259865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/105.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_init_fail.3618371188 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 372090447 ps |
| CPU time | 4.41 seconds |
| Started | Sep 09 07:11:57 PM UTC 24 |
| Finished | Sep 09 07:12:03 PM UTC 24 |
| Peak memory | 250856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618371188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.3618371188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/106.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/106.otp_ctrl_parallel_lc_esc.2870649398 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 171892145 ps |
| CPU time | 5.77 seconds |
| Started | Sep 09 07:11:57 PM UTC 24 |
| Finished | Sep 09 07:12:04 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870649398 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.2870649398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/106.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/107.otp_ctrl_parallel_lc_esc.652646682 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 951893521 ps |
| CPU time | 13.72 seconds |
| Started | Sep 09 07:12:06 PM UTC 24 |
| Finished | Sep 09 07:12:21 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652646682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.652646682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/107.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_init_fail.1695451037 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 655515600 ps |
| CPU time | 4.55 seconds |
| Started | Sep 09 07:12:06 PM UTC 24 |
| Finished | Sep 09 07:12:12 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695451037 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.1695451037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/108.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/108.otp_ctrl_parallel_lc_esc.4034886671 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 414977441 ps |
| CPU time | 8.04 seconds |
| Started | Sep 09 07:12:06 PM UTC 24 |
| Finished | Sep 09 07:12:15 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034886671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.4034886671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/108.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_init_fail.3965752107 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 107109560 ps |
| CPU time | 5.01 seconds |
| Started | Sep 09 07:12:06 PM UTC 24 |
| Finished | Sep 09 07:12:12 PM UTC 24 |
| Peak memory | 253268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965752107 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.3965752107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/109.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/109.otp_ctrl_parallel_lc_esc.2410060782 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 566590096 ps |
| CPU time | 8.37 seconds |
| Started | Sep 09 07:12:06 PM UTC 24 |
| Finished | Sep 09 07:12:16 PM UTC 24 |
| Peak memory | 253212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410060782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.2410060782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/109.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_alert_test.3596647647 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 846409971 ps |
| CPU time | 2.62 seconds |
| Started | Sep 09 07:05:30 PM UTC 24 |
| Finished | Sep 09 07:05:33 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596647647 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_alert_test.3596647647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_errs.1972001825 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 6075142616 ps |
| CPU time | 40.74 seconds |
| Started | Sep 09 07:05:27 PM UTC 24 |
| Finished | Sep 09 07:06:09 PM UTC 24 |
| Peak memory | 265656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972001825 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.1972001825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_dai_lock.2923675278 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 360379157 ps |
| CPU time | 10.33 seconds |
| Started | Sep 09 07:05:27 PM UTC 24 |
| Finished | Sep 09 07:05:38 PM UTC 24 |
| Peak memory | 257724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923675278 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.2923675278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_init_fail.639432769 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 232569243 ps |
| CPU time | 3.6 seconds |
| Started | Sep 09 07:05:24 PM UTC 24 |
| Finished | Sep 09 07:05:29 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639432769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.639432769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_macro_errs.3952311425 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 328718645 ps |
| CPU time | 4.59 seconds |
| Started | Sep 09 07:05:27 PM UTC 24 |
| Finished | Sep 09 07:05:33 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952311425 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_macro_errs.3952311425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_key_req.231572636 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 452503869 ps |
| CPU time | 18.98 seconds |
| Started | Sep 09 07:05:27 PM UTC 24 |
| Finished | Sep 09 07:05:47 PM UTC 24 |
| Peak memory | 253328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231572636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_key_req.231572636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_esc.1283539106 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 124807461 ps |
| CPU time | 3.81 seconds |
| Started | Sep 09 07:05:24 PM UTC 24 |
| Finished | Sep 09 07:05:29 PM UTC 24 |
| Peak memory | 251060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283539106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.1283539106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_parallel_lc_req.3726240975 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 706219167 ps |
| CPU time | 14.25 seconds |
| Started | Sep 09 07:05:24 PM UTC 24 |
| Finished | Sep 09 07:05:40 PM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726240975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_req.3726240975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_smoke.560157522 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 750034417 ps |
| CPU time | 8.28 seconds |
| Started | Sep 09 07:05:24 PM UTC 24 |
| Finished | Sep 09 07:05:33 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560157522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_smoke.560157522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_stress_all_with_rand_reset.2585489033 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 5686920230 ps |
| CPU time | 98.4 seconds |
| Started | Sep 09 07:05:29 PM UTC 24 |
| Finished | Sep 09 07:07:10 PM UTC 24 |
| Peak memory | 268180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2585489033 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 11.otp_ctrl_stress_all_with_rand_reset.2585489033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/11.otp_ctrl_test_access.1123191136 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2205682942 ps |
| CPU time | 18.95 seconds |
| Started | Sep 09 07:05:29 PM UTC 24 |
| Finished | Sep 09 07:05:50 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123191136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_test_access.1123191136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/11.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_init_fail.2053985055 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 592611509 ps |
| CPU time | 3.99 seconds |
| Started | Sep 09 07:12:06 PM UTC 24 |
| Finished | Sep 09 07:12:11 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053985055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.2053985055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/110.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/110.otp_ctrl_parallel_lc_esc.111185105 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 572462626 ps |
| CPU time | 9.39 seconds |
| Started | Sep 09 07:12:06 PM UTC 24 |
| Finished | Sep 09 07:12:17 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111185105 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.111185105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/110.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_init_fail.4249149540 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 165400433 ps |
| CPU time | 4.06 seconds |
| Started | Sep 09 07:12:06 PM UTC 24 |
| Finished | Sep 09 07:12:11 PM UTC 24 |
| Peak memory | 253264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249149540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.4249149540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/111.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/111.otp_ctrl_parallel_lc_esc.2722217900 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 103795528 ps |
| CPU time | 5.37 seconds |
| Started | Sep 09 07:12:06 PM UTC 24 |
| Finished | Sep 09 07:12:13 PM UTC 24 |
| Peak memory | 253216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722217900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.2722217900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/111.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_init_fail.4032694219 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 142875909 ps |
| CPU time | 4.91 seconds |
| Started | Sep 09 07:12:06 PM UTC 24 |
| Finished | Sep 09 07:12:12 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032694219 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.4032694219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/112.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/112.otp_ctrl_parallel_lc_esc.2674527808 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 800436195 ps |
| CPU time | 19.93 seconds |
| Started | Sep 09 07:12:06 PM UTC 24 |
| Finished | Sep 09 07:12:27 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674527808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.2674527808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/112.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_init_fail.1203007327 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 325133119 ps |
| CPU time | 5.2 seconds |
| Started | Sep 09 07:12:06 PM UTC 24 |
| Finished | Sep 09 07:12:13 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203007327 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.1203007327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/113.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/113.otp_ctrl_parallel_lc_esc.4242389178 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 2250045550 ps |
| CPU time | 16.82 seconds |
| Started | Sep 09 07:12:06 PM UTC 24 |
| Finished | Sep 09 07:12:24 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242389178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.4242389178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/113.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_init_fail.4161598114 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 503997922 ps |
| CPU time | 4.95 seconds |
| Started | Sep 09 07:12:06 PM UTC 24 |
| Finished | Sep 09 07:12:13 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161598114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.4161598114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/114.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/114.otp_ctrl_parallel_lc_esc.1177948987 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 1599988980 ps |
| CPU time | 6.25 seconds |
| Started | Sep 09 07:12:06 PM UTC 24 |
| Finished | Sep 09 07:12:14 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177948987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.1177948987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/114.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_init_fail.2567923540 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 1952765285 ps |
| CPU time | 7.1 seconds |
| Started | Sep 09 07:12:07 PM UTC 24 |
| Finished | Sep 09 07:12:15 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567923540 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.2567923540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/115.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/115.otp_ctrl_parallel_lc_esc.777836659 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 1974864195 ps |
| CPU time | 7.46 seconds |
| Started | Sep 09 07:12:07 PM UTC 24 |
| Finished | Sep 09 07:12:15 PM UTC 24 |
| Peak memory | 251120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777836659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.777836659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/115.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_init_fail.550350920 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 273340322 ps |
| CPU time | 4.67 seconds |
| Started | Sep 09 07:12:10 PM UTC 24 |
| Finished | Sep 09 07:12:16 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=550350920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.550350920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/116.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/116.otp_ctrl_parallel_lc_esc.3164900545 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 101007105 ps |
| CPU time | 3.46 seconds |
| Started | Sep 09 07:12:10 PM UTC 24 |
| Finished | Sep 09 07:12:15 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164900545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.3164900545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/116.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_init_fail.1484264470 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 146375724 ps |
| CPU time | 4.02 seconds |
| Started | Sep 09 07:12:10 PM UTC 24 |
| Finished | Sep 09 07:12:15 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484264470 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.1484264470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/117.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/117.otp_ctrl_parallel_lc_esc.2295754894 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 966807497 ps |
| CPU time | 20.25 seconds |
| Started | Sep 09 07:12:10 PM UTC 24 |
| Finished | Sep 09 07:12:32 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295754894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.2295754894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/117.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_init_fail.1007430256 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 184216425 ps |
| CPU time | 4.41 seconds |
| Started | Sep 09 07:12:10 PM UTC 24 |
| Finished | Sep 09 07:12:16 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007430256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.1007430256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/118.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/118.otp_ctrl_parallel_lc_esc.3683338307 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 4024688440 ps |
| CPU time | 12.05 seconds |
| Started | Sep 09 07:12:10 PM UTC 24 |
| Finished | Sep 09 07:12:24 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683338307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.3683338307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/118.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_init_fail.2471456622 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 1982566806 ps |
| CPU time | 4.18 seconds |
| Started | Sep 09 07:12:15 PM UTC 24 |
| Finished | Sep 09 07:12:21 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471456622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.2471456622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/119.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/119.otp_ctrl_parallel_lc_esc.1912475279 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 1286824393 ps |
| CPU time | 26.96 seconds |
| Started | Sep 09 07:12:15 PM UTC 24 |
| Finished | Sep 09 07:12:44 PM UTC 24 |
| Peak memory | 253240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912475279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.1912475279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/119.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_alert_test.571164045 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 77419931 ps |
| CPU time | 2.11 seconds |
| Started | Sep 09 07:05:35 PM UTC 24 |
| Finished | Sep 09 07:05:38 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571164045 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_alert_test.571164045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_check_fail.717968712 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 2069089085 ps |
| CPU time | 19.86 seconds |
| Started | Sep 09 07:05:34 PM UTC 24 |
| Finished | Sep 09 07:05:55 PM UTC 24 |
| Peak memory | 253364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717968712 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.717968712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_errs.3825521929 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 1116360603 ps |
| CPU time | 14.56 seconds |
| Started | Sep 09 07:05:34 PM UTC 24 |
| Finished | Sep 09 07:05:50 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825521929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.3825521929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_dai_lock.419894976 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 1402357037 ps |
| CPU time | 15.26 seconds |
| Started | Sep 09 07:05:31 PM UTC 24 |
| Finished | Sep 09 07:05:47 PM UTC 24 |
| Peak memory | 257468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419894976 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.419894976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_macro_errs.845835916 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 8108527576 ps |
| CPU time | 25.79 seconds |
| Started | Sep 09 07:05:34 PM UTC 24 |
| Finished | Sep 09 07:06:01 PM UTC 24 |
| Peak memory | 255456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845835916 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_macro_errs.845835916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_key_req.3304133376 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 219267183 ps |
| CPU time | 8.96 seconds |
| Started | Sep 09 07:05:34 PM UTC 24 |
| Finished | Sep 09 07:05:44 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304133376 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_key_req.3304133376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_esc.1580138555 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 326778815 ps |
| CPU time | 9.65 seconds |
| Started | Sep 09 07:05:30 PM UTC 24 |
| Finished | Sep 09 07:05:41 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580138555 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.1580138555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_parallel_lc_req.1051044487 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 637162987 ps |
| CPU time | 15.73 seconds |
| Started | Sep 09 07:05:30 PM UTC 24 |
| Finished | Sep 09 07:05:47 PM UTC 24 |
| Peak memory | 257364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051044487 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_req.1051044487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_regwen.4228165663 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 1013464508 ps |
| CPU time | 8.83 seconds |
| Started | Sep 09 07:05:34 PM UTC 24 |
| Finished | Sep 09 07:05:44 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228165663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.4228165663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_smoke.653088631 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 4632910643 ps |
| CPU time | 13.75 seconds |
| Started | Sep 09 07:05:30 PM UTC 24 |
| Finished | Sep 09 07:05:45 PM UTC 24 |
| Peak memory | 251680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653088631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_smoke.653088631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_stress_all.1512952003 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 135815372 ps |
| CPU time | 3.01 seconds |
| Started | Sep 09 07:05:35 PM UTC 24 |
| Finished | Sep 09 07:05:39 PM UTC 24 |
| Peak memory | 251124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512952003 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all.1512952003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/12.otp_ctrl_test_access.2508252288 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 945603834 ps |
| CPU time | 17.58 seconds |
| Started | Sep 09 07:05:34 PM UTC 24 |
| Finished | Sep 09 07:05:53 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508252288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_test_access.2508252288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/12.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_init_fail.2751799143 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 1767320919 ps |
| CPU time | 4.38 seconds |
| Started | Sep 09 07:12:15 PM UTC 24 |
| Finished | Sep 09 07:12:21 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751799143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.2751799143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/120.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/120.otp_ctrl_parallel_lc_esc.484102279 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 1703974112 ps |
| CPU time | 11.55 seconds |
| Started | Sep 09 07:12:15 PM UTC 24 |
| Finished | Sep 09 07:12:28 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484102279 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.484102279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/120.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_init_fail.4019324225 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 2587659447 ps |
| CPU time | 4.91 seconds |
| Started | Sep 09 07:12:16 PM UTC 24 |
| Finished | Sep 09 07:12:22 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019324225 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.4019324225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/121.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/121.otp_ctrl_parallel_lc_esc.2803678785 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 323283992 ps |
| CPU time | 6.36 seconds |
| Started | Sep 09 07:12:16 PM UTC 24 |
| Finished | Sep 09 07:12:23 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803678785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.2803678785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/121.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_init_fail.3085127078 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 160027169 ps |
| CPU time | 3.9 seconds |
| Started | Sep 09 07:12:16 PM UTC 24 |
| Finished | Sep 09 07:12:21 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085127078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.3085127078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/122.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/122.otp_ctrl_parallel_lc_esc.222909783 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 227873492 ps |
| CPU time | 7.5 seconds |
| Started | Sep 09 07:12:16 PM UTC 24 |
| Finished | Sep 09 07:12:24 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222909783 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.222909783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/122.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_init_fail.1387903431 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 277700607 ps |
| CPU time | 4.96 seconds |
| Started | Sep 09 07:12:16 PM UTC 24 |
| Finished | Sep 09 07:12:22 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387903431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.1387903431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/123.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/123.otp_ctrl_parallel_lc_esc.723805446 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 288472979 ps |
| CPU time | 3.69 seconds |
| Started | Sep 09 07:12:16 PM UTC 24 |
| Finished | Sep 09 07:12:21 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723805446 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.723805446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/123.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_init_fail.1612396634 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 437556123 ps |
| CPU time | 2.93 seconds |
| Started | Sep 09 07:12:16 PM UTC 24 |
| Finished | Sep 09 07:12:20 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612396634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.1612396634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/124.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/124.otp_ctrl_parallel_lc_esc.1244188473 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 2058435384 ps |
| CPU time | 13.14 seconds |
| Started | Sep 09 07:12:16 PM UTC 24 |
| Finished | Sep 09 07:12:30 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244188473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.1244188473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/124.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_init_fail.1836889389 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 273728616 ps |
| CPU time | 3.72 seconds |
| Started | Sep 09 07:12:16 PM UTC 24 |
| Finished | Sep 09 07:12:21 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836889389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.1836889389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/125.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/125.otp_ctrl_parallel_lc_esc.1069965316 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 408359230 ps |
| CPU time | 4.68 seconds |
| Started | Sep 09 07:12:21 PM UTC 24 |
| Finished | Sep 09 07:12:27 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069965316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.1069965316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/125.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/126.otp_ctrl_parallel_lc_esc.1066036316 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 871649613 ps |
| CPU time | 10.89 seconds |
| Started | Sep 09 07:12:21 PM UTC 24 |
| Finished | Sep 09 07:12:33 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066036316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.1066036316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/126.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_init_fail.2976800075 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 1737183702 ps |
| CPU time | 4.8 seconds |
| Started | Sep 09 07:12:21 PM UTC 24 |
| Finished | Sep 09 07:12:27 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976800075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.2976800075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/127.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/127.otp_ctrl_parallel_lc_esc.2260680012 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 246921752 ps |
| CPU time | 12.8 seconds |
| Started | Sep 09 07:12:21 PM UTC 24 |
| Finished | Sep 09 07:12:35 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260680012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.2260680012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/127.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_init_fail.3546937770 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 94532409 ps |
| CPU time | 2.88 seconds |
| Started | Sep 09 07:12:21 PM UTC 24 |
| Finished | Sep 09 07:12:25 PM UTC 24 |
| Peak memory | 251520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546937770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.3546937770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/128.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/128.otp_ctrl_parallel_lc_esc.2871213601 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 4851375963 ps |
| CPU time | 11.97 seconds |
| Started | Sep 09 07:12:21 PM UTC 24 |
| Finished | Sep 09 07:12:34 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871213601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.2871213601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/128.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_init_fail.3399149644 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 541338001 ps |
| CPU time | 5.05 seconds |
| Started | Sep 09 07:12:21 PM UTC 24 |
| Finished | Sep 09 07:12:27 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399149644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.3399149644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/129.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/129.otp_ctrl_parallel_lc_esc.697551651 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 1802117816 ps |
| CPU time | 11.55 seconds |
| Started | Sep 09 07:12:21 PM UTC 24 |
| Finished | Sep 09 07:12:34 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697551651 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.697551651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/129.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_alert_test.2081988113 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 45623134 ps |
| CPU time | 2.35 seconds |
| Started | Sep 09 07:05:44 PM UTC 24 |
| Finished | Sep 09 07:05:47 PM UTC 24 |
| Peak memory | 250860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081988113 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_alert_test.2081988113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_check_fail.478395897 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 1383095073 ps |
| CPU time | 17.5 seconds |
| Started | Sep 09 07:05:41 PM UTC 24 |
| Finished | Sep 09 07:05:59 PM UTC 24 |
| Peak memory | 257464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478395897 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.478395897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_errs.2196568458 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 402626329 ps |
| CPU time | 20.21 seconds |
| Started | Sep 09 07:05:40 PM UTC 24 |
| Finished | Sep 09 07:06:02 PM UTC 24 |
| Peak memory | 251620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196568458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.2196568458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_dai_lock.3248601513 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 1237461698 ps |
| CPU time | 14.16 seconds |
| Started | Sep 09 07:05:36 PM UTC 24 |
| Finished | Sep 09 07:05:52 PM UTC 24 |
| Peak memory | 253372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248601513 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.3248601513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_init_fail.167262659 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 132119938 ps |
| CPU time | 3.94 seconds |
| Started | Sep 09 07:05:36 PM UTC 24 |
| Finished | Sep 09 07:05:41 PM UTC 24 |
| Peak memory | 253528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167262659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.167262659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_macro_errs.3862077301 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 10365136702 ps |
| CPU time | 21.8 seconds |
| Started | Sep 09 07:05:41 PM UTC 24 |
| Finished | Sep 09 07:06:04 PM UTC 24 |
| Peak memory | 253532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3862077301 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_macro_errs.3862077301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_key_req.2515137510 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 1319174284 ps |
| CPU time | 10.71 seconds |
| Started | Sep 09 07:05:41 PM UTC 24 |
| Finished | Sep 09 07:05:53 PM UTC 24 |
| Peak memory | 250704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515137510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_key_req.2515137510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_esc.433334313 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 3656866921 ps |
| CPU time | 20.67 seconds |
| Started | Sep 09 07:05:36 PM UTC 24 |
| Finished | Sep 09 07:05:58 PM UTC 24 |
| Peak memory | 257392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433334313 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.433334313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_parallel_lc_req.3779541500 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 956371277 ps |
| CPU time | 24.4 seconds |
| Started | Sep 09 07:05:36 PM UTC 24 |
| Finished | Sep 09 07:06:02 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779541500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_req.3779541500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_regwen.3159273412 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 2368157143 ps |
| CPU time | 8.76 seconds |
| Started | Sep 09 07:05:41 PM UTC 24 |
| Finished | Sep 09 07:05:51 PM UTC 24 |
| Peak memory | 251132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159273412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.3159273412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_smoke.2083637438 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 180346455 ps |
| CPU time | 4.73 seconds |
| Started | Sep 09 07:05:35 PM UTC 24 |
| Finished | Sep 09 07:05:40 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083637438 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_smoke.2083637438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_stress_all.2814086204 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 1405304210 ps |
| CPU time | 13.94 seconds |
| Started | Sep 09 07:05:44 PM UTC 24 |
| Finished | Sep 09 07:05:59 PM UTC 24 |
| Peak memory | 253208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814086204 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all.2814086204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/13.otp_ctrl_test_access.2236666350 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 12520320833 ps |
| CPU time | 30.01 seconds |
| Started | Sep 09 07:05:41 PM UTC 24 |
| Finished | Sep 09 07:06:12 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236666350 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_test_access.2236666350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/13.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_init_fail.2010484190 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 447948794 ps |
| CPU time | 4.6 seconds |
| Started | Sep 09 07:12:21 PM UTC 24 |
| Finished | Sep 09 07:12:27 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010484190 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.2010484190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/130.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/130.otp_ctrl_parallel_lc_esc.2865841019 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 1793059566 ps |
| CPU time | 6.21 seconds |
| Started | Sep 09 07:12:21 PM UTC 24 |
| Finished | Sep 09 07:12:29 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2865841019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.2865841019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/130.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_init_fail.1163380249 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 230243794 ps |
| CPU time | 4.57 seconds |
| Started | Sep 09 07:12:21 PM UTC 24 |
| Finished | Sep 09 07:12:27 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163380249 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.1163380249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/131.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/131.otp_ctrl_parallel_lc_esc.3947335439 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 248045043 ps |
| CPU time | 8.81 seconds |
| Started | Sep 09 07:12:21 PM UTC 24 |
| Finished | Sep 09 07:12:31 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947335439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.3947335439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/131.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/132.otp_ctrl_init_fail.1125200878 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 530283048 ps |
| CPU time | 4.7 seconds |
| Started | Sep 09 07:12:21 PM UTC 24 |
| Finished | Sep 09 07:12:27 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125200878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.1125200878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/132.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_init_fail.2720769056 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 184057544 ps |
| CPU time | 4.27 seconds |
| Started | Sep 09 07:12:25 PM UTC 24 |
| Finished | Sep 09 07:12:30 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720769056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.2720769056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/133.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/133.otp_ctrl_parallel_lc_esc.1689190314 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 1300476493 ps |
| CPU time | 12.27 seconds |
| Started | Sep 09 07:12:25 PM UTC 24 |
| Finished | Sep 09 07:12:38 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689190314 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.1689190314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/133.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_init_fail.2186152779 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 268874021 ps |
| CPU time | 3.34 seconds |
| Started | Sep 09 07:12:25 PM UTC 24 |
| Finished | Sep 09 07:12:29 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186152779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.2186152779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/134.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/134.otp_ctrl_parallel_lc_esc.1242220522 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 13000471418 ps |
| CPU time | 25.76 seconds |
| Started | Sep 09 07:12:25 PM UTC 24 |
| Finished | Sep 09 07:12:52 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242220522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.1242220522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/134.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/135.otp_ctrl_parallel_lc_esc.1175419366 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 206583870 ps |
| CPU time | 3.4 seconds |
| Started | Sep 09 07:12:25 PM UTC 24 |
| Finished | Sep 09 07:12:30 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175419366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.1175419366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/135.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_init_fail.179329156 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 356508865 ps |
| CPU time | 4.18 seconds |
| Started | Sep 09 07:12:25 PM UTC 24 |
| Finished | Sep 09 07:12:30 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179329156 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.179329156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/136.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/136.otp_ctrl_parallel_lc_esc.2902775081 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 209354490 ps |
| CPU time | 7.09 seconds |
| Started | Sep 09 07:12:25 PM UTC 24 |
| Finished | Sep 09 07:12:33 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902775081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.2902775081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/136.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_init_fail.375252553 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 158995723 ps |
| CPU time | 2.89 seconds |
| Started | Sep 09 07:12:25 PM UTC 24 |
| Finished | Sep 09 07:12:29 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375252553 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.375252553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/137.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/137.otp_ctrl_parallel_lc_esc.2967051868 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 113683029 ps |
| CPU time | 4.01 seconds |
| Started | Sep 09 07:12:25 PM UTC 24 |
| Finished | Sep 09 07:12:30 PM UTC 24 |
| Peak memory | 251096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967051868 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.2967051868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/137.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_init_fail.2995925556 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1453004134 ps |
| CPU time | 4.9 seconds |
| Started | Sep 09 07:12:25 PM UTC 24 |
| Finished | Sep 09 07:12:31 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995925556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.2995925556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/138.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/138.otp_ctrl_parallel_lc_esc.3430125558 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 250665783 ps |
| CPU time | 5.83 seconds |
| Started | Sep 09 07:12:38 PM UTC 24 |
| Finished | Sep 09 07:12:45 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430125558 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.3430125558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/138.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_init_fail.1087422610 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 561410690 ps |
| CPU time | 3.86 seconds |
| Started | Sep 09 07:12:38 PM UTC 24 |
| Finished | Sep 09 07:12:43 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087422610 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.1087422610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/139.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/139.otp_ctrl_parallel_lc_esc.508765597 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 1491823545 ps |
| CPU time | 15.84 seconds |
| Started | Sep 09 07:12:38 PM UTC 24 |
| Finished | Sep 09 07:12:56 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508765597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.508765597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/139.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_alert_test.1341024179 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 217528742 ps |
| CPU time | 2.09 seconds |
| Started | Sep 09 07:05:51 PM UTC 24 |
| Finished | Sep 09 07:05:54 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341024179 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_alert_test.1341024179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/14.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_check_fail.449884883 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 709112606 ps |
| CPU time | 18.57 seconds |
| Started | Sep 09 07:05:46 PM UTC 24 |
| Finished | Sep 09 07:06:06 PM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449884883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.449884883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/14.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_errs.1019128860 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 1128880562 ps |
| CPU time | 17.29 seconds |
| Started | Sep 09 07:05:46 PM UTC 24 |
| Finished | Sep 09 07:06:04 PM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019128860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.1019128860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/14.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_dai_lock.3194060366 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 147870548 ps |
| CPU time | 4.25 seconds |
| Started | Sep 09 07:05:44 PM UTC 24 |
| Finished | Sep 09 07:05:49 PM UTC 24 |
| Peak memory | 251644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194060366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.3194060366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/14.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_init_fail.21572094 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 427645182 ps |
| CPU time | 4.6 seconds |
| Started | Sep 09 07:05:44 PM UTC 24 |
| Finished | Sep 09 07:05:49 PM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21572094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.21572094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/14.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_macro_errs.2765819547 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 12843168457 ps |
| CPU time | 35.35 seconds |
| Started | Sep 09 07:05:46 PM UTC 24 |
| Finished | Sep 09 07:06:23 PM UTC 24 |
| Peak memory | 257852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765819547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_macro_errs.2765819547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/14.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_key_req.2278059175 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 1150809810 ps |
| CPU time | 19.16 seconds |
| Started | Sep 09 07:05:46 PM UTC 24 |
| Finished | Sep 09 07:06:06 PM UTC 24 |
| Peak memory | 257756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278059175 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_key_req.2278059175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_esc.596364331 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 145435711 ps |
| CPU time | 6.25 seconds |
| Started | Sep 09 07:05:44 PM UTC 24 |
| Finished | Sep 09 07:05:51 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596364331 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.596364331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_parallel_lc_req.4178778099 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 591264656 ps |
| CPU time | 6.36 seconds |
| Started | Sep 09 07:05:44 PM UTC 24 |
| Finished | Sep 09 07:05:51 PM UTC 24 |
| Peak memory | 257560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178778099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_req.4178778099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_regwen.3794123191 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 291594369 ps |
| CPU time | 6.01 seconds |
| Started | Sep 09 07:05:46 PM UTC 24 |
| Finished | Sep 09 07:05:53 PM UTC 24 |
| Peak memory | 257360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794123191 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.3794123191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/14.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_smoke.642358022 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 290944830 ps |
| CPU time | 5.56 seconds |
| Started | Sep 09 07:05:44 PM UTC 24 |
| Finished | Sep 09 07:05:50 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642358022 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_smoke.642358022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/14.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_stress_all.575183697 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 26138897752 ps |
| CPU time | 78.7 seconds |
| Started | Sep 09 07:05:48 PM UTC 24 |
| Finished | Sep 09 07:07:08 PM UTC 24 |
| Peak memory | 257468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575183697 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all.575183697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/14.otp_ctrl_test_access.3224103483 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 959606767 ps |
| CPU time | 17.68 seconds |
| Started | Sep 09 07:05:46 PM UTC 24 |
| Finished | Sep 09 07:06:05 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224103483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_test_access.3224103483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/14.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_init_fail.3490025025 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 1638669861 ps |
| CPU time | 5.81 seconds |
| Started | Sep 09 07:12:38 PM UTC 24 |
| Finished | Sep 09 07:12:45 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490025025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.3490025025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/140.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/140.otp_ctrl_parallel_lc_esc.1415005515 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 155671937 ps |
| CPU time | 2.75 seconds |
| Started | Sep 09 07:12:38 PM UTC 24 |
| Finished | Sep 09 07:12:42 PM UTC 24 |
| Peak memory | 250832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415005515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.1415005515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/140.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_init_fail.3739016202 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 143488386 ps |
| CPU time | 4.76 seconds |
| Started | Sep 09 07:12:38 PM UTC 24 |
| Finished | Sep 09 07:12:45 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739016202 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.3739016202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/141.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/141.otp_ctrl_parallel_lc_esc.2556534459 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 338522945 ps |
| CPU time | 7.03 seconds |
| Started | Sep 09 07:12:38 PM UTC 24 |
| Finished | Sep 09 07:12:47 PM UTC 24 |
| Peak memory | 250848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556534459 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.2556534459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/141.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_init_fail.3876900061 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 493797679 ps |
| CPU time | 3.47 seconds |
| Started | Sep 09 07:12:38 PM UTC 24 |
| Finished | Sep 09 07:12:43 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876900061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.3876900061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/142.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/142.otp_ctrl_parallel_lc_esc.2469151955 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 753631624 ps |
| CPU time | 5.81 seconds |
| Started | Sep 09 07:12:38 PM UTC 24 |
| Finished | Sep 09 07:12:46 PM UTC 24 |
| Peak memory | 253528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469151955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.2469151955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/142.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_init_fail.1003443048 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 499242517 ps |
| CPU time | 6.58 seconds |
| Started | Sep 09 07:12:38 PM UTC 24 |
| Finished | Sep 09 07:12:47 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003443048 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.1003443048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/143.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/143.otp_ctrl_parallel_lc_esc.2126177936 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 233084819 ps |
| CPU time | 12.2 seconds |
| Started | Sep 09 07:12:38 PM UTC 24 |
| Finished | Sep 09 07:12:52 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126177936 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.2126177936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/143.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_init_fail.275381214 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 214961568 ps |
| CPU time | 4.27 seconds |
| Started | Sep 09 07:12:38 PM UTC 24 |
| Finished | Sep 09 07:12:44 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275381214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.275381214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/144.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/144.otp_ctrl_parallel_lc_esc.1397463103 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 145161933 ps |
| CPU time | 3.25 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:43 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397463103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.1397463103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/144.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/145.otp_ctrl_parallel_lc_esc.2114153026 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 345402459 ps |
| CPU time | 8.6 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:49 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114153026 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.2114153026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/145.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_init_fail.281201047 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 112564536 ps |
| CPU time | 3.5 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:44 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281201047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.281201047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/146.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/146.otp_ctrl_parallel_lc_esc.3949051640 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 260010692 ps |
| CPU time | 6.56 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:47 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949051640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.3949051640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/146.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_init_fail.276059486 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 542002711 ps |
| CPU time | 3.92 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:44 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276059486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.276059486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/147.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/147.otp_ctrl_parallel_lc_esc.2819400442 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 385617898 ps |
| CPU time | 7.47 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:48 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819400442 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.2819400442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/147.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_init_fail.2203431335 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 1798972825 ps |
| CPU time | 4.72 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:45 PM UTC 24 |
| Peak memory | 251264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203431335 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.2203431335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/148.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/148.otp_ctrl_parallel_lc_esc.3999719377 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 192960237 ps |
| CPU time | 8.98 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:49 PM UTC 24 |
| Peak memory | 251396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999719377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.3999719377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/148.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_init_fail.3641773405 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 224349261 ps |
| CPU time | 4.21 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:44 PM UTC 24 |
| Peak memory | 251132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641773405 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.3641773405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/149.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/149.otp_ctrl_parallel_lc_esc.1404022164 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 183719954 ps |
| CPU time | 7.07 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:47 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404022164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.1404022164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/149.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_alert_test.3769951547 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 59673109 ps |
| CPU time | 1.91 seconds |
| Started | Sep 09 07:05:54 PM UTC 24 |
| Finished | Sep 09 07:05:57 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769951547 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_alert_test.3769951547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_check_fail.3662632367 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 212913391 ps |
| CPU time | 5.04 seconds |
| Started | Sep 09 07:05:52 PM UTC 24 |
| Finished | Sep 09 07:05:58 PM UTC 24 |
| Peak memory | 251352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662632367 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.3662632367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_errs.1438753230 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 754975300 ps |
| CPU time | 13.59 seconds |
| Started | Sep 09 07:05:52 PM UTC 24 |
| Finished | Sep 09 07:06:06 PM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438753230 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.1438753230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_dai_lock.4084363644 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 366442625 ps |
| CPU time | 6.93 seconds |
| Started | Sep 09 07:05:52 PM UTC 24 |
| Finished | Sep 09 07:06:00 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084363644 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.4084363644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_init_fail.3087770803 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 110949916 ps |
| CPU time | 4.65 seconds |
| Started | Sep 09 07:05:51 PM UTC 24 |
| Finished | Sep 09 07:05:57 PM UTC 24 |
| Peak memory | 251516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087770803 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.3087770803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_macro_errs.1688909725 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 7521918860 ps |
| CPU time | 12.97 seconds |
| Started | Sep 09 07:05:52 PM UTC 24 |
| Finished | Sep 09 07:06:06 PM UTC 24 |
| Peak memory | 255476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688909725 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_macro_errs.1688909725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_key_req.2819919817 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 2172582308 ps |
| CPU time | 8.07 seconds |
| Started | Sep 09 07:05:54 PM UTC 24 |
| Finished | Sep 09 07:06:03 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819919817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_key_req.2819919817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_esc.3136145075 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 89764657 ps |
| CPU time | 3.32 seconds |
| Started | Sep 09 07:05:52 PM UTC 24 |
| Finished | Sep 09 07:05:56 PM UTC 24 |
| Peak memory | 251116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136145075 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.3136145075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_parallel_lc_req.2562911066 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 548609464 ps |
| CPU time | 17.22 seconds |
| Started | Sep 09 07:05:51 PM UTC 24 |
| Finished | Sep 09 07:06:10 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562911066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_req.2562911066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_regwen.2245033597 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 261526923 ps |
| CPU time | 6.93 seconds |
| Started | Sep 09 07:05:54 PM UTC 24 |
| Finished | Sep 09 07:06:02 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245033597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.2245033597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_smoke.1857096207 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 784031256 ps |
| CPU time | 8.05 seconds |
| Started | Sep 09 07:05:51 PM UTC 24 |
| Finished | Sep 09 07:06:01 PM UTC 24 |
| Peak memory | 257564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857096207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_smoke.1857096207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_stress_all.3327894570 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 67868697099 ps |
| CPU time | 133.9 seconds |
| Started | Sep 09 07:05:54 PM UTC 24 |
| Finished | Sep 09 07:08:10 PM UTC 24 |
| Peak memory | 265692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327894570 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all.3327894570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/15.otp_ctrl_test_access.2376560541 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 981676181 ps |
| CPU time | 14.96 seconds |
| Started | Sep 09 07:05:54 PM UTC 24 |
| Finished | Sep 09 07:06:10 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376560541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_test_access.2376560541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/15.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_init_fail.915733123 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 148118272 ps |
| CPU time | 5.33 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:46 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915733123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.915733123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/150.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/150.otp_ctrl_parallel_lc_esc.475996456 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 555465811 ps |
| CPU time | 7.82 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:48 PM UTC 24 |
| Peak memory | 251112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475996456 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.475996456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/150.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_init_fail.2485417103 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 408456444 ps |
| CPU time | 5.36 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:46 PM UTC 24 |
| Peak memory | 251264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485417103 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.2485417103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/151.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/151.otp_ctrl_parallel_lc_esc.1880620046 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 383666941 ps |
| CPU time | 3 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:43 PM UTC 24 |
| Peak memory | 253148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880620046 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.1880620046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/151.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_init_fail.1939919805 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 493497271 ps |
| CPU time | 4.01 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:44 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939919805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.1939919805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/152.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/152.otp_ctrl_parallel_lc_esc.799559837 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 200661536 ps |
| CPU time | 4.99 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:45 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799559837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.799559837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/152.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_init_fail.1572332822 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 123977199 ps |
| CPU time | 4.09 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:45 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572332822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.1572332822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/153.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/153.otp_ctrl_parallel_lc_esc.103161990 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 285566322 ps |
| CPU time | 2.52 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:43 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103161990 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.103161990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/153.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_init_fail.3899334453 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 578218386 ps |
| CPU time | 4.8 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:45 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899334453 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.3899334453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/154.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/154.otp_ctrl_parallel_lc_esc.1121961775 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 1297268613 ps |
| CPU time | 8.39 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:49 PM UTC 24 |
| Peak memory | 253532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121961775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.1121961775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/154.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_init_fail.2477651449 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 110760169 ps |
| CPU time | 3.75 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:12:44 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477651449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.2477651449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/155.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/155.otp_ctrl_parallel_lc_esc.2526442855 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 1047672502 ps |
| CPU time | 20.62 seconds |
| Started | Sep 09 07:12:39 PM UTC 24 |
| Finished | Sep 09 07:13:01 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526442855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.2526442855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/155.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_init_fail.57172266 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 161163285 ps |
| CPU time | 3.78 seconds |
| Started | Sep 09 07:12:41 PM UTC 24 |
| Finished | Sep 09 07:12:46 PM UTC 24 |
| Peak memory | 251544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57172266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.57172266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/156.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/156.otp_ctrl_parallel_lc_esc.696882721 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 769951939 ps |
| CPU time | 17.84 seconds |
| Started | Sep 09 07:12:41 PM UTC 24 |
| Finished | Sep 09 07:13:00 PM UTC 24 |
| Peak memory | 251140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696882721 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.696882721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/156.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_init_fail.1678980958 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 467258135 ps |
| CPU time | 3.62 seconds |
| Started | Sep 09 07:12:41 PM UTC 24 |
| Finished | Sep 09 07:12:46 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678980958 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.1678980958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/157.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/157.otp_ctrl_parallel_lc_esc.1828385242 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 977802165 ps |
| CPU time | 12.16 seconds |
| Started | Sep 09 07:12:46 PM UTC 24 |
| Finished | Sep 09 07:13:00 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828385242 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.1828385242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/157.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_init_fail.222703842 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 141364684 ps |
| CPU time | 3.14 seconds |
| Started | Sep 09 07:12:46 PM UTC 24 |
| Finished | Sep 09 07:12:50 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222703842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.222703842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/158.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/158.otp_ctrl_parallel_lc_esc.3409906665 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 238054721 ps |
| CPU time | 10.4 seconds |
| Started | Sep 09 07:12:46 PM UTC 24 |
| Finished | Sep 09 07:12:58 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409906665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.3409906665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/158.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_init_fail.2827239317 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 388914333 ps |
| CPU time | 3.55 seconds |
| Started | Sep 09 07:12:46 PM UTC 24 |
| Finished | Sep 09 07:12:51 PM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827239317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.2827239317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/159.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/159.otp_ctrl_parallel_lc_esc.1952936771 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 352147976 ps |
| CPU time | 4.51 seconds |
| Started | Sep 09 07:12:46 PM UTC 24 |
| Finished | Sep 09 07:12:52 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952936771 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.1952936771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/159.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_alert_test.2713379563 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 65111738 ps |
| CPU time | 2.51 seconds |
| Started | Sep 09 07:06:01 PM UTC 24 |
| Finished | Sep 09 07:06:05 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713379563 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_alert_test.2713379563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_check_fail.2233127493 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 895763105 ps |
| CPU time | 25.14 seconds |
| Started | Sep 09 07:05:57 PM UTC 24 |
| Finished | Sep 09 07:06:24 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233127493 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.2233127493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_errs.355047625 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 523463039 ps |
| CPU time | 12.85 seconds |
| Started | Sep 09 07:05:57 PM UTC 24 |
| Finished | Sep 09 07:06:11 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355047625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.355047625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_dai_lock.2270852678 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 733022893 ps |
| CPU time | 26.2 seconds |
| Started | Sep 09 07:05:57 PM UTC 24 |
| Finished | Sep 09 07:06:25 PM UTC 24 |
| Peak memory | 253692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270852678 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.2270852678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_macro_errs.4099093045 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 1264029284 ps |
| CPU time | 12.8 seconds |
| Started | Sep 09 07:05:59 PM UTC 24 |
| Finished | Sep 09 07:06:13 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099093045 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_macro_errs.4099093045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_key_req.3782901474 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 3891217308 ps |
| CPU time | 7.45 seconds |
| Started | Sep 09 07:05:59 PM UTC 24 |
| Finished | Sep 09 07:06:07 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782901474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_key_req.3782901474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_esc.3463427929 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 285184424 ps |
| CPU time | 13.15 seconds |
| Started | Sep 09 07:05:56 PM UTC 24 |
| Finished | Sep 09 07:06:10 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463427929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.3463427929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_parallel_lc_req.2432278977 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 426737885 ps |
| CPU time | 12.33 seconds |
| Started | Sep 09 07:05:56 PM UTC 24 |
| Finished | Sep 09 07:06:09 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432278977 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_req.2432278977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_regwen.4147679873 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 299662845 ps |
| CPU time | 7.3 seconds |
| Started | Sep 09 07:06:01 PM UTC 24 |
| Finished | Sep 09 07:06:09 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147679873 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.4147679873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_smoke.2563445435 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 195148844 ps |
| CPU time | 3.68 seconds |
| Started | Sep 09 07:05:54 PM UTC 24 |
| Finished | Sep 09 07:05:59 PM UTC 24 |
| Peak memory | 257428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563445435 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_smoke.2563445435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all.2540525575 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 12856079962 ps |
| CPU time | 215.3 seconds |
| Started | Sep 09 07:06:01 PM UTC 24 |
| Finished | Sep 09 07:09:40 PM UTC 24 |
| Peak memory | 269508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540525575 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all.2540525575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_stress_all_with_rand_reset.3106105588 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 3597460492 ps |
| CPU time | 66.12 seconds |
| Started | Sep 09 07:06:01 PM UTC 24 |
| Finished | Sep 09 07:07:09 PM UTC 24 |
| Peak memory | 257712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3106105588 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 16.otp_ctrl_stress_all_with_rand_reset.3106105588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/16.otp_ctrl_test_access.307223848 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 426339647 ps |
| CPU time | 12.97 seconds |
| Started | Sep 09 07:06:01 PM UTC 24 |
| Finished | Sep 09 07:06:15 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307223848 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_test_access.307223848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/16.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_init_fail.2767512617 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 161779036 ps |
| CPU time | 4.16 seconds |
| Started | Sep 09 07:12:46 PM UTC 24 |
| Finished | Sep 09 07:12:52 PM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767512617 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.2767512617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/160.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/160.otp_ctrl_parallel_lc_esc.223935461 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 213063561 ps |
| CPU time | 4.95 seconds |
| Started | Sep 09 07:12:46 PM UTC 24 |
| Finished | Sep 09 07:12:53 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223935461 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.223935461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/160.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_init_fail.3164106093 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 143172007 ps |
| CPU time | 3.3 seconds |
| Started | Sep 09 07:12:46 PM UTC 24 |
| Finished | Sep 09 07:12:51 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164106093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.3164106093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/161.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/161.otp_ctrl_parallel_lc_esc.2780267665 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 625406028 ps |
| CPU time | 6.17 seconds |
| Started | Sep 09 07:12:46 PM UTC 24 |
| Finished | Sep 09 07:12:54 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780267665 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.2780267665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/161.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_init_fail.804711418 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 413166921 ps |
| CPU time | 3.36 seconds |
| Started | Sep 09 07:12:46 PM UTC 24 |
| Finished | Sep 09 07:12:51 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804711418 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.804711418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/162.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/162.otp_ctrl_parallel_lc_esc.3785523474 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 259843858 ps |
| CPU time | 9.98 seconds |
| Started | Sep 09 07:12:47 PM UTC 24 |
| Finished | Sep 09 07:12:58 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785523474 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.3785523474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/162.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_init_fail.1663073063 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 2137349714 ps |
| CPU time | 5.18 seconds |
| Started | Sep 09 07:12:47 PM UTC 24 |
| Finished | Sep 09 07:12:53 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663073063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.1663073063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/163.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/163.otp_ctrl_parallel_lc_esc.2543022012 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 279050887 ps |
| CPU time | 5.54 seconds |
| Started | Sep 09 07:12:47 PM UTC 24 |
| Finished | Sep 09 07:12:53 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543022012 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.2543022012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/163.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_init_fail.3427233365 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 276840854 ps |
| CPU time | 3.52 seconds |
| Started | Sep 09 07:12:47 PM UTC 24 |
| Finished | Sep 09 07:12:51 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427233365 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.3427233365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/164.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/164.otp_ctrl_parallel_lc_esc.2652458805 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 1148063031 ps |
| CPU time | 7.41 seconds |
| Started | Sep 09 07:12:47 PM UTC 24 |
| Finished | Sep 09 07:12:55 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652458805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.2652458805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/164.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_init_fail.4129595520 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 1629420085 ps |
| CPU time | 5 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:03 PM UTC 24 |
| Peak memory | 251072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129595520 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.4129595520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/165.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/165.otp_ctrl_parallel_lc_esc.3561929622 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 14743609821 ps |
| CPU time | 37.6 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:36 PM UTC 24 |
| Peak memory | 250848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561929622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.3561929622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/165.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_init_fail.307316955 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 290563055 ps |
| CPU time | 3.61 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:01 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307316955 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.307316955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/166.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/166.otp_ctrl_parallel_lc_esc.1274009781 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 14142699833 ps |
| CPU time | 27.69 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:26 PM UTC 24 |
| Peak memory | 251328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274009781 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.1274009781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/166.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_init_fail.3359513814 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 2151067848 ps |
| CPU time | 6.19 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:04 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359513814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.3359513814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/167.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/167.otp_ctrl_parallel_lc_esc.1495754205 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 512788069 ps |
| CPU time | 5.2 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:03 PM UTC 24 |
| Peak memory | 251112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495754205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.1495754205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/167.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_init_fail.3307310334 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 219159138 ps |
| CPU time | 5.05 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:03 PM UTC 24 |
| Peak memory | 250996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307310334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.3307310334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/168.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/168.otp_ctrl_parallel_lc_esc.1121492060 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 274188075 ps |
| CPU time | 5.03 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:03 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121492060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.1121492060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/168.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_init_fail.3577356877 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 141400827 ps |
| CPU time | 4.11 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:02 PM UTC 24 |
| Peak memory | 251604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577356877 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.3577356877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/169.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/169.otp_ctrl_parallel_lc_esc.2374556176 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 448075820 ps |
| CPU time | 10.9 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:09 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374556176 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.2374556176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/169.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_alert_test.1070354630 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 81040963 ps |
| CPU time | 3.03 seconds |
| Started | Sep 09 07:06:10 PM UTC 24 |
| Finished | Sep 09 07:06:14 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070354630 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_alert_test.1070354630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/17.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_check_fail.2747014019 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 16567509924 ps |
| CPU time | 27.82 seconds |
| Started | Sep 09 07:06:07 PM UTC 24 |
| Finished | Sep 09 07:06:36 PM UTC 24 |
| Peak memory | 253684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747014019 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.2747014019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/17.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_errs.1574033296 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 5320775994 ps |
| CPU time | 45.69 seconds |
| Started | Sep 09 07:06:07 PM UTC 24 |
| Finished | Sep 09 07:06:54 PM UTC 24 |
| Peak memory | 257468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574033296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.1574033296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/17.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_dai_lock.2671359829 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 388118078 ps |
| CPU time | 6.95 seconds |
| Started | Sep 09 07:06:03 PM UTC 24 |
| Finished | Sep 09 07:06:11 PM UTC 24 |
| Peak memory | 251640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671359829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.2671359829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/17.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_init_fail.3856174639 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 1293688191 ps |
| CPU time | 6.24 seconds |
| Started | Sep 09 07:06:03 PM UTC 24 |
| Finished | Sep 09 07:06:10 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856174639 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.3856174639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/17.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_macro_errs.3057622994 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 1158889860 ps |
| CPU time | 25.33 seconds |
| Started | Sep 09 07:06:07 PM UTC 24 |
| Finished | Sep 09 07:06:33 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057622994 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_macro_errs.3057622994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/17.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_esc.3985238601 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 100498949 ps |
| CPU time | 3.45 seconds |
| Started | Sep 09 07:06:03 PM UTC 24 |
| Finished | Sep 09 07:06:07 PM UTC 24 |
| Peak memory | 251408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985238601 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.3985238601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_parallel_lc_req.4004092036 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 627720774 ps |
| CPU time | 16.86 seconds |
| Started | Sep 09 07:06:03 PM UTC 24 |
| Finished | Sep 09 07:06:21 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004092036 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_req.4004092036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_stress_all.1698749056 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 3032569533 ps |
| CPU time | 52.08 seconds |
| Started | Sep 09 07:06:07 PM UTC 24 |
| Finished | Sep 09 07:07:01 PM UTC 24 |
| Peak memory | 255616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698749056 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all.1698749056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/17.otp_ctrl_test_access.4049115361 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 1459727654 ps |
| CPU time | 16.99 seconds |
| Started | Sep 09 07:06:07 PM UTC 24 |
| Finished | Sep 09 07:06:25 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049115361 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_test_access.4049115361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/17.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_init_fail.2771298145 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 322257592 ps |
| CPU time | 3.22 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:01 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771298145 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.2771298145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/170.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/170.otp_ctrl_parallel_lc_esc.1841191366 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 1370727032 ps |
| CPU time | 18.73 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:17 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841191366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.1841191366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/170.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/171.otp_ctrl_init_fail.1023636356 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 133736657 ps |
| CPU time | 4.2 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:02 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023636356 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.1023636356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/171.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_init_fail.113226763 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 156227531 ps |
| CPU time | 3.88 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:02 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113226763 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.113226763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/172.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/172.otp_ctrl_parallel_lc_esc.1490175040 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 164012902 ps |
| CPU time | 4.06 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:02 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490175040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.1490175040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/172.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_init_fail.1253951996 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 124176954 ps |
| CPU time | 2.72 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:01 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253951996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.1253951996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/173.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/173.otp_ctrl_parallel_lc_esc.3924965871 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 2089454782 ps |
| CPU time | 5.61 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:04 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924965871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.3924965871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/173.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_init_fail.3631415141 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 241342224 ps |
| CPU time | 4.2 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:03 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631415141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.3631415141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/174.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/174.otp_ctrl_parallel_lc_esc.2343900545 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 275392477 ps |
| CPU time | 6.89 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:05 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343900545 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.2343900545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/174.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_init_fail.2625094130 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 266023513 ps |
| CPU time | 5.68 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:04 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625094130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.2625094130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/175.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/175.otp_ctrl_parallel_lc_esc.1293540597 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 503823237 ps |
| CPU time | 5.94 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:05 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293540597 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.1293540597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/175.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_init_fail.4108034431 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 366410163 ps |
| CPU time | 4.44 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:03 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108034431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.4108034431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/176.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/176.otp_ctrl_parallel_lc_esc.2106648172 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 1263303813 ps |
| CPU time | 14.94 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:14 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106648172 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.2106648172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/176.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_init_fail.82385764 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 2705367009 ps |
| CPU time | 4.27 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:03 PM UTC 24 |
| Peak memory | 251608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82385764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.82385764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/177.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/177.otp_ctrl_parallel_lc_esc.2384895013 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 374235653 ps |
| CPU time | 6.05 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:05 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384895013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.2384895013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/177.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/178.otp_ctrl_init_fail.264302439 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 164631990 ps |
| CPU time | 3.74 seconds |
| Started | Sep 09 07:12:57 PM UTC 24 |
| Finished | Sep 09 07:13:03 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264302439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.264302439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/178.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_init_fail.374430179 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 1883188393 ps |
| CPU time | 5.29 seconds |
| Started | Sep 09 07:12:58 PM UTC 24 |
| Finished | Sep 09 07:13:04 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374430179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.374430179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/179.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/179.otp_ctrl_parallel_lc_esc.3950140529 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 2141816434 ps |
| CPU time | 12.76 seconds |
| Started | Sep 09 07:12:58 PM UTC 24 |
| Finished | Sep 09 07:13:12 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950140529 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.3950140529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/179.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_alert_test.2765840998 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 144971706 ps |
| CPU time | 2.11 seconds |
| Started | Sep 09 07:06:13 PM UTC 24 |
| Finished | Sep 09 07:06:16 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765840998 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_alert_test.2765840998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_errs.242087823 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 989429930 ps |
| CPU time | 16.06 seconds |
| Started | Sep 09 07:06:10 PM UTC 24 |
| Finished | Sep 09 07:06:28 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242087823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.242087823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_dai_lock.2374903304 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 891052363 ps |
| CPU time | 12.74 seconds |
| Started | Sep 09 07:06:10 PM UTC 24 |
| Finished | Sep 09 07:06:24 PM UTC 24 |
| Peak memory | 251580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374903304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.2374903304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_init_fail.2747482648 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 355010116 ps |
| CPU time | 4.32 seconds |
| Started | Sep 09 07:06:10 PM UTC 24 |
| Finished | Sep 09 07:06:16 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747482648 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.2747482648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_macro_errs.3333503735 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 1087106111 ps |
| CPU time | 13.39 seconds |
| Started | Sep 09 07:06:13 PM UTC 24 |
| Finished | Sep 09 07:06:28 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333503735 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_macro_errs.3333503735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_key_req.38355671 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 21722345540 ps |
| CPU time | 39.92 seconds |
| Started | Sep 09 07:06:13 PM UTC 24 |
| Finished | Sep 09 07:06:54 PM UTC 24 |
| Peak memory | 253404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38355671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_key_req.38355671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_esc.4207033146 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 2260264192 ps |
| CPU time | 9.46 seconds |
| Started | Sep 09 07:06:10 PM UTC 24 |
| Finished | Sep 09 07:06:21 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207033146 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.4207033146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_parallel_lc_req.2760876972 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 9767389178 ps |
| CPU time | 24.75 seconds |
| Started | Sep 09 07:06:10 PM UTC 24 |
| Finished | Sep 09 07:06:36 PM UTC 24 |
| Peak memory | 257432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760876972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_req.2760876972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_regwen.967990169 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 4098975267 ps |
| CPU time | 16.87 seconds |
| Started | Sep 09 07:06:13 PM UTC 24 |
| Finished | Sep 09 07:06:31 PM UTC 24 |
| Peak memory | 251340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967990169 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.967990169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_smoke.2457132804 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 880018342 ps |
| CPU time | 7.06 seconds |
| Started | Sep 09 07:06:10 PM UTC 24 |
| Finished | Sep 09 07:06:18 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457132804 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_smoke.2457132804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all.1474166488 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 10998586167 ps |
| CPU time | 158.29 seconds |
| Started | Sep 09 07:06:13 PM UTC 24 |
| Finished | Sep 09 07:08:54 PM UTC 24 |
| Peak memory | 271892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474166488 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all.1474166488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_stress_all_with_rand_reset.2216841669 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 16646937305 ps |
| CPU time | 118.43 seconds |
| Started | Sep 09 07:06:13 PM UTC 24 |
| Finished | Sep 09 07:08:14 PM UTC 24 |
| Peak memory | 257648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2216841669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 18.otp_ctrl_stress_all_with_rand_reset.2216841669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/18.otp_ctrl_test_access.4211690577 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 15832971928 ps |
| CPU time | 38.46 seconds |
| Started | Sep 09 07:06:13 PM UTC 24 |
| Finished | Sep 09 07:06:53 PM UTC 24 |
| Peak memory | 257500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211690577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_test_access.4211690577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/18.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_init_fail.3842679731 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 137278919 ps |
| CPU time | 2.91 seconds |
| Started | Sep 09 07:12:58 PM UTC 24 |
| Finished | Sep 09 07:13:02 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842679731 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.3842679731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/180.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/180.otp_ctrl_parallel_lc_esc.3625205431 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 2176220276 ps |
| CPU time | 15.05 seconds |
| Started | Sep 09 07:12:58 PM UTC 24 |
| Finished | Sep 09 07:13:14 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625205431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.3625205431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/180.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_init_fail.2451513388 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 251077519 ps |
| CPU time | 3.24 seconds |
| Started | Sep 09 07:12:58 PM UTC 24 |
| Finished | Sep 09 07:13:02 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451513388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.2451513388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/181.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/181.otp_ctrl_parallel_lc_esc.881839793 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 173733845 ps |
| CPU time | 5.15 seconds |
| Started | Sep 09 07:12:58 PM UTC 24 |
| Finished | Sep 09 07:13:04 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881839793 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.881839793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/181.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_init_fail.2502926208 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 266635237 ps |
| CPU time | 4.97 seconds |
| Started | Sep 09 07:12:58 PM UTC 24 |
| Finished | Sep 09 07:13:04 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502926208 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.2502926208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/182.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/182.otp_ctrl_parallel_lc_esc.3591594126 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 250843184 ps |
| CPU time | 13.07 seconds |
| Started | Sep 09 07:12:58 PM UTC 24 |
| Finished | Sep 09 07:13:12 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591594126 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.3591594126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/182.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_init_fail.3244866640 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 313639455 ps |
| CPU time | 5.44 seconds |
| Started | Sep 09 07:12:58 PM UTC 24 |
| Finished | Sep 09 07:13:05 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244866640 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.3244866640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/183.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/183.otp_ctrl_parallel_lc_esc.92628150 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 655437112 ps |
| CPU time | 5.69 seconds |
| Started | Sep 09 07:13:02 PM UTC 24 |
| Finished | Sep 09 07:13:09 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92628150 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.92628150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/183.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_init_fail.1875371823 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 325071235 ps |
| CPU time | 3.28 seconds |
| Started | Sep 09 07:13:02 PM UTC 24 |
| Finished | Sep 09 07:13:06 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875371823 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.1875371823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/184.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/184.otp_ctrl_parallel_lc_esc.1930479993 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 439163073 ps |
| CPU time | 10.12 seconds |
| Started | Sep 09 07:13:02 PM UTC 24 |
| Finished | Sep 09 07:13:13 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930479993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.1930479993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/184.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_init_fail.3008804971 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 270784505 ps |
| CPU time | 3.62 seconds |
| Started | Sep 09 07:13:02 PM UTC 24 |
| Finished | Sep 09 07:13:07 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008804971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.3008804971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/185.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/185.otp_ctrl_parallel_lc_esc.1383922508 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 8728699193 ps |
| CPU time | 17.76 seconds |
| Started | Sep 09 07:13:02 PM UTC 24 |
| Finished | Sep 09 07:13:21 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383922508 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.1383922508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/185.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_init_fail.1070611119 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 164335780 ps |
| CPU time | 3.83 seconds |
| Started | Sep 09 07:13:02 PM UTC 24 |
| Finished | Sep 09 07:13:07 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070611119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.1070611119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/186.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/186.otp_ctrl_parallel_lc_esc.2199981286 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 288829569 ps |
| CPU time | 9.98 seconds |
| Started | Sep 09 07:13:02 PM UTC 24 |
| Finished | Sep 09 07:13:13 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199981286 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.2199981286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/186.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/187.otp_ctrl_parallel_lc_esc.1095017829 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 332377704 ps |
| CPU time | 7 seconds |
| Started | Sep 09 07:13:09 PM UTC 24 |
| Finished | Sep 09 07:13:18 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095017829 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.1095017829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/187.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_init_fail.3660280708 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 409872841 ps |
| CPU time | 3.87 seconds |
| Started | Sep 09 07:13:09 PM UTC 24 |
| Finished | Sep 09 07:13:14 PM UTC 24 |
| Peak memory | 251520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660280708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.3660280708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/188.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/188.otp_ctrl_parallel_lc_esc.2131761358 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 463103174 ps |
| CPU time | 11.92 seconds |
| Started | Sep 09 07:13:09 PM UTC 24 |
| Finished | Sep 09 07:13:23 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131761358 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.2131761358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/188.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_init_fail.3999173098 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 276761000 ps |
| CPU time | 2.9 seconds |
| Started | Sep 09 07:13:09 PM UTC 24 |
| Finished | Sep 09 07:13:14 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999173098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.3999173098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/189.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/189.otp_ctrl_parallel_lc_esc.718318038 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 1056182465 ps |
| CPU time | 4.66 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:15 PM UTC 24 |
| Peak memory | 251088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718318038 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.718318038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/189.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_alert_test.43233742 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 98886723 ps |
| CPU time | 2.28 seconds |
| Started | Sep 09 07:06:25 PM UTC 24 |
| Finished | Sep 09 07:06:28 PM UTC 24 |
| Peak memory | 250728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43233742 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_alert_test.43233742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_check_fail.2771473125 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 2224554080 ps |
| CPU time | 18.56 seconds |
| Started | Sep 09 07:06:17 PM UTC 24 |
| Finished | Sep 09 07:06:36 PM UTC 24 |
| Peak memory | 257588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771473125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.2771473125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_errs.1223868234 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 2194851519 ps |
| CPU time | 33.97 seconds |
| Started | Sep 09 07:06:17 PM UTC 24 |
| Finished | Sep 09 07:06:52 PM UTC 24 |
| Peak memory | 255416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223868234 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.1223868234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_dai_lock.1476304980 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 538352270 ps |
| CPU time | 11.45 seconds |
| Started | Sep 09 07:06:17 PM UTC 24 |
| Finished | Sep 09 07:06:29 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476304980 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.1476304980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_macro_errs.3792493395 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 15627360338 ps |
| CPU time | 50.76 seconds |
| Started | Sep 09 07:06:18 PM UTC 24 |
| Finished | Sep 09 07:07:10 PM UTC 24 |
| Peak memory | 257508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792493395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_macro_errs.3792493395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_key_req.4181980531 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 814590236 ps |
| CPU time | 24.57 seconds |
| Started | Sep 09 07:06:19 PM UTC 24 |
| Finished | Sep 09 07:06:45 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181980531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_key_req.4181980531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_esc.1541828490 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 963165023 ps |
| CPU time | 10.39 seconds |
| Started | Sep 09 07:06:15 PM UTC 24 |
| Finished | Sep 09 07:06:26 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541828490 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.1541828490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_parallel_lc_req.2969400982 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1459529823 ps |
| CPU time | 24.59 seconds |
| Started | Sep 09 07:06:15 PM UTC 24 |
| Finished | Sep 09 07:06:41 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969400982 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_req.2969400982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_regwen.2253340733 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 424747344 ps |
| CPU time | 3.95 seconds |
| Started | Sep 09 07:06:20 PM UTC 24 |
| Finished | Sep 09 07:06:25 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253340733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.2253340733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_smoke.1610490929 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 305111002 ps |
| CPU time | 13.22 seconds |
| Started | Sep 09 07:06:15 PM UTC 24 |
| Finished | Sep 09 07:06:29 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610490929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_smoke.1610490929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_stress_all.4167625719 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 31833510855 ps |
| CPU time | 189.72 seconds |
| Started | Sep 09 07:06:23 PM UTC 24 |
| Finished | Sep 09 07:09:36 PM UTC 24 |
| Peak memory | 267868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167625719 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all.4167625719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/19.otp_ctrl_test_access.530906899 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 543737090 ps |
| CPU time | 7.85 seconds |
| Started | Sep 09 07:06:21 PM UTC 24 |
| Finished | Sep 09 07:06:30 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530906899 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_test_access.530906899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/19.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_init_fail.893684971 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 337782941 ps |
| CPU time | 3.24 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:14 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893684971 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.893684971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/190.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/190.otp_ctrl_parallel_lc_esc.1719211645 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 1703474758 ps |
| CPU time | 3.74 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:15 PM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719211645 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.1719211645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/190.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_init_fail.3357412226 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 147204005 ps |
| CPU time | 3.47 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:14 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357412226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.3357412226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/191.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/191.otp_ctrl_parallel_lc_esc.2834982677 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 2771106483 ps |
| CPU time | 17.03 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:28 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834982677 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.2834982677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/191.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_init_fail.1313975235 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 150870604 ps |
| CPU time | 3.98 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:15 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313975235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.1313975235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/192.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/192.otp_ctrl_parallel_lc_esc.2775332657 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 211830570 ps |
| CPU time | 4.37 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:15 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775332657 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.2775332657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/192.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_init_fail.2985495111 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 292496807 ps |
| CPU time | 3.42 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:14 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985495111 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.2985495111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/193.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/193.otp_ctrl_parallel_lc_esc.888006903 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 5890392739 ps |
| CPU time | 14.23 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:25 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888006903 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.888006903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/193.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_init_fail.793654814 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 121552722 ps |
| CPU time | 3.58 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:15 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793654814 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.793654814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/194.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/194.otp_ctrl_parallel_lc_esc.124894142 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 64931255 ps |
| CPU time | 3.1 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:14 PM UTC 24 |
| Peak memory | 251092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124894142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.124894142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/194.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_init_fail.517988766 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 2178494605 ps |
| CPU time | 6.24 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:18 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517988766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.517988766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/195.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/195.otp_ctrl_parallel_lc_esc.2697440002 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 182761723 ps |
| CPU time | 6.94 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:18 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697440002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.2697440002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/195.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_init_fail.2407834094 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 137856184 ps |
| CPU time | 5.41 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:17 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407834094 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.2407834094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/196.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/196.otp_ctrl_parallel_lc_esc.468906195 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 1048999312 ps |
| CPU time | 4.69 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:16 PM UTC 24 |
| Peak memory | 251096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468906195 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.468906195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/196.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_init_fail.3298259259 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 122385310 ps |
| CPU time | 3.39 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:15 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298259259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.3298259259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/197.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/197.otp_ctrl_parallel_lc_esc.3615927968 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 78624482 ps |
| CPU time | 3.12 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:14 PM UTC 24 |
| Peak memory | 251124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615927968 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.3615927968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/197.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_init_fail.1723079840 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 2266021545 ps |
| CPU time | 5.85 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:17 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723079840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.1723079840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/198.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/198.otp_ctrl_parallel_lc_esc.352038309 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 3499749805 ps |
| CPU time | 8.06 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:20 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352038309 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.352038309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/198.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_init_fail.2431472778 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 189269925 ps |
| CPU time | 3.76 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:15 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431472778 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.2431472778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/199.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/199.otp_ctrl_parallel_lc_esc.1458681787 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 220444050 ps |
| CPU time | 10.11 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:22 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458681787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.1458681787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/199.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_alert_test.3405818487 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 162440791 ps |
| CPU time | 2.17 seconds |
| Started | Sep 09 07:04:31 PM UTC 24 |
| Finished | Sep 09 07:04:34 PM UTC 24 |
| Peak memory | 251232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405818487 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.3405818487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_errs.150381285 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 252146763 ps |
| CPU time | 7.54 seconds |
| Started | Sep 09 07:04:26 PM UTC 24 |
| Finished | Sep 09 07:04:35 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150381285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.150381285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_dai_lock.2131325424 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 1859562018 ps |
| CPU time | 4.58 seconds |
| Started | Sep 09 07:04:26 PM UTC 24 |
| Finished | Sep 09 07:04:32 PM UTC 24 |
| Peak memory | 257468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131325424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.2131325424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_key_req.2374065569 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 385986885 ps |
| CPU time | 10.83 seconds |
| Started | Sep 09 07:04:28 PM UTC 24 |
| Finished | Sep 09 07:04:40 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374065569 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.2374065569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_esc.326289911 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 408266117 ps |
| CPU time | 3.2 seconds |
| Started | Sep 09 07:04:26 PM UTC 24 |
| Finished | Sep 09 07:04:30 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326289911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.326289911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_parallel_lc_req.1705093546 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 630286048 ps |
| CPU time | 10.28 seconds |
| Started | Sep 09 07:04:26 PM UTC 24 |
| Finished | Sep 09 07:04:38 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705093546 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.1705093546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_regwen.1566792850 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 516291413 ps |
| CPU time | 4.97 seconds |
| Started | Sep 09 07:04:28 PM UTC 24 |
| Finished | Sep 09 07:04:34 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566792850 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.1566792850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_sec_cm.2884361477 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 10918826482 ps |
| CPU time | 163.03 seconds |
| Started | Sep 09 07:04:31 PM UTC 24 |
| Finished | Sep 09 07:07:17 PM UTC 24 |
| Peak memory | 296208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884361477 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.2884361477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_smoke.1930630761 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 221355071 ps |
| CPU time | 3.05 seconds |
| Started | Sep 09 07:04:26 PM UTC 24 |
| Finished | Sep 09 07:04:30 PM UTC 24 |
| Peak memory | 257692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1930630761 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.1930630761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_stress_all_with_rand_reset.1012553821 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2101672255 ps |
| CPU time | 64.09 seconds |
| Started | Sep 09 07:04:29 PM UTC 24 |
| Finished | Sep 09 07:05:35 PM UTC 24 |
| Peak memory | 267788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1012553821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 2.otp_ctrl_stress_all_with_rand_reset.1012553821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/2.otp_ctrl_test_access.2443283951 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 1307650403 ps |
| CPU time | 11.09 seconds |
| Started | Sep 09 07:04:29 PM UTC 24 |
| Finished | Sep 09 07:04:42 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443283951 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.2443283951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/2.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_alert_test.637275071 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 724041921 ps |
| CPU time | 2.92 seconds |
| Started | Sep 09 07:06:34 PM UTC 24 |
| Finished | Sep 09 07:06:38 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637275071 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_alert_test.637275071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/20.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_check_fail.2113439205 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 214310368 ps |
| CPU time | 5.32 seconds |
| Started | Sep 09 07:06:29 PM UTC 24 |
| Finished | Sep 09 07:06:35 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113439205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.2113439205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/20.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_errs.2398888808 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 3689152053 ps |
| CPU time | 32.64 seconds |
| Started | Sep 09 07:06:27 PM UTC 24 |
| Finished | Sep 09 07:07:01 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398888808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.2398888808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/20.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_dai_lock.3092310254 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 9937942630 ps |
| CPU time | 40.28 seconds |
| Started | Sep 09 07:06:27 PM UTC 24 |
| Finished | Sep 09 07:07:09 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092310254 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.3092310254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/20.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_init_fail.1183491454 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1794857711 ps |
| CPU time | 6.38 seconds |
| Started | Sep 09 07:06:25 PM UTC 24 |
| Finished | Sep 09 07:06:32 PM UTC 24 |
| Peak memory | 250936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183491454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.1183491454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/20.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_macro_errs.1824058622 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 994615862 ps |
| CPU time | 33.4 seconds |
| Started | Sep 09 07:06:29 PM UTC 24 |
| Finished | Sep 09 07:07:04 PM UTC 24 |
| Peak memory | 257168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824058622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_macro_errs.1824058622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/20.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_key_req.201785719 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 337642551 ps |
| CPU time | 13.57 seconds |
| Started | Sep 09 07:06:29 PM UTC 24 |
| Finished | Sep 09 07:06:44 PM UTC 24 |
| Peak memory | 251272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201785719 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_key_req.201785719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_esc.3400738931 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 312547276 ps |
| CPU time | 7.93 seconds |
| Started | Sep 09 07:06:27 PM UTC 24 |
| Finished | Sep 09 07:06:36 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400738931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.3400738931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_parallel_lc_req.2211282972 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 854294361 ps |
| CPU time | 17.22 seconds |
| Started | Sep 09 07:06:27 PM UTC 24 |
| Finished | Sep 09 07:06:46 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211282972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_req.2211282972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_regwen.448430290 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 4685137681 ps |
| CPU time | 16.95 seconds |
| Started | Sep 09 07:06:30 PM UTC 24 |
| Finished | Sep 09 07:06:49 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448430290 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.448430290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/20.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_smoke.1722854935 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 414569800 ps |
| CPU time | 6.71 seconds |
| Started | Sep 09 07:06:25 PM UTC 24 |
| Finished | Sep 09 07:06:33 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722854935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_smoke.1722854935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/20.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_stress_all.2469839453 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 24366996591 ps |
| CPU time | 76.7 seconds |
| Started | Sep 09 07:06:32 PM UTC 24 |
| Finished | Sep 09 07:07:51 PM UTC 24 |
| Peak memory | 255772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469839453 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all.2469839453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/20.otp_ctrl_test_access.4149041562 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 449110610 ps |
| CPU time | 11.33 seconds |
| Started | Sep 09 07:06:30 PM UTC 24 |
| Finished | Sep 09 07:06:43 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149041562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_test_access.4149041562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/20.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/200.otp_ctrl_init_fail.4269709188 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 310696667 ps |
| CPU time | 3.18 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:15 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269709188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.4269709188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/200.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/201.otp_ctrl_init_fail.3784125625 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 186190813 ps |
| CPU time | 4.55 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:16 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784125625 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.3784125625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/201.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/202.otp_ctrl_init_fail.2028359905 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 1777417744 ps |
| CPU time | 6.17 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:18 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028359905 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.2028359905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/202.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/203.otp_ctrl_init_fail.117247917 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 273388242 ps |
| CPU time | 3.06 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:15 PM UTC 24 |
| Peak memory | 251332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117247917 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.117247917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/203.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/204.otp_ctrl_init_fail.2067573822 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 190488690 ps |
| CPU time | 4.54 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:16 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067573822 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.2067573822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/204.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/205.otp_ctrl_init_fail.2084066502 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 651132692 ps |
| CPU time | 4.5 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:16 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084066502 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.2084066502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/205.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/206.otp_ctrl_init_fail.148598894 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 2762840551 ps |
| CPU time | 5.16 seconds |
| Started | Sep 09 07:13:10 PM UTC 24 |
| Finished | Sep 09 07:13:17 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148598894 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.148598894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/206.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/207.otp_ctrl_init_fail.4104240641 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 180319800 ps |
| CPU time | 4.05 seconds |
| Started | Sep 09 07:13:16 PM UTC 24 |
| Finished | Sep 09 07:13:22 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104240641 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.4104240641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/207.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/208.otp_ctrl_init_fail.430266106 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 125711347 ps |
| CPU time | 3.55 seconds |
| Started | Sep 09 07:13:16 PM UTC 24 |
| Finished | Sep 09 07:13:21 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430266106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.430266106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/208.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/209.otp_ctrl_init_fail.2909874106 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 112522274 ps |
| CPU time | 2.76 seconds |
| Started | Sep 09 07:13:17 PM UTC 24 |
| Finished | Sep 09 07:13:21 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909874106 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.2909874106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/209.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_alert_test.4163067427 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 122408730 ps |
| CPU time | 2.94 seconds |
| Started | Sep 09 07:06:44 PM UTC 24 |
| Finished | Sep 09 07:06:48 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163067427 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_alert_test.4163067427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/21.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_check_fail.2522017070 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 901761175 ps |
| CPU time | 11.69 seconds |
| Started | Sep 09 07:06:39 PM UTC 24 |
| Finished | Sep 09 07:06:52 PM UTC 24 |
| Peak memory | 251672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522017070 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.2522017070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/21.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_errs.3471016355 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 2348391247 ps |
| CPU time | 32.74 seconds |
| Started | Sep 09 07:06:39 PM UTC 24 |
| Finished | Sep 09 07:07:13 PM UTC 24 |
| Peak memory | 257724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471016355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.3471016355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/21.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_dai_lock.1513693979 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1535663123 ps |
| CPU time | 18.06 seconds |
| Started | Sep 09 07:06:36 PM UTC 24 |
| Finished | Sep 09 07:06:56 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513693979 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.1513693979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/21.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_macro_errs.3647139205 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 14597630595 ps |
| CPU time | 44.85 seconds |
| Started | Sep 09 07:06:39 PM UTC 24 |
| Finished | Sep 09 07:07:25 PM UTC 24 |
| Peak memory | 257588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647139205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_macro_errs.3647139205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/21.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_key_req.2118813345 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 1105566586 ps |
| CPU time | 12.6 seconds |
| Started | Sep 09 07:06:39 PM UTC 24 |
| Finished | Sep 09 07:06:53 PM UTC 24 |
| Peak memory | 257464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118813345 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_key_req.2118813345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_esc.4291039880 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 312113976 ps |
| CPU time | 4.21 seconds |
| Started | Sep 09 07:06:36 PM UTC 24 |
| Finished | Sep 09 07:06:42 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291039880 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.4291039880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_parallel_lc_req.1822389600 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1054945939 ps |
| CPU time | 26.25 seconds |
| Started | Sep 09 07:06:36 PM UTC 24 |
| Finished | Sep 09 07:07:04 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822389600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_req.1822389600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_regwen.2663018566 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 291362779 ps |
| CPU time | 8.86 seconds |
| Started | Sep 09 07:06:39 PM UTC 24 |
| Finished | Sep 09 07:06:49 PM UTC 24 |
| Peak memory | 251276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663018566 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.2663018566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/21.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_smoke.1911437198 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 1251858422 ps |
| CPU time | 11.77 seconds |
| Started | Sep 09 07:06:34 PM UTC 24 |
| Finished | Sep 09 07:06:47 PM UTC 24 |
| Peak memory | 257372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911437198 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_smoke.1911437198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/21.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_stress_all.1330809314 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 22472971636 ps |
| CPU time | 49.5 seconds |
| Started | Sep 09 07:06:43 PM UTC 24 |
| Finished | Sep 09 07:07:34 PM UTC 24 |
| Peak memory | 255416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330809314 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all.1330809314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/21.otp_ctrl_test_access.114195436 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 2247776592 ps |
| CPU time | 16.39 seconds |
| Started | Sep 09 07:06:43 PM UTC 24 |
| Finished | Sep 09 07:07:00 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114195436 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_test_access.114195436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/21.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/210.otp_ctrl_init_fail.1299764462 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 105049720 ps |
| CPU time | 2.96 seconds |
| Started | Sep 09 07:13:17 PM UTC 24 |
| Finished | Sep 09 07:13:21 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299764462 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.1299764462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/210.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/211.otp_ctrl_init_fail.1767814247 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 2330426914 ps |
| CPU time | 4.53 seconds |
| Started | Sep 09 07:13:17 PM UTC 24 |
| Finished | Sep 09 07:13:22 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767814247 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.1767814247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/211.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/212.otp_ctrl_init_fail.3746331113 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 628913112 ps |
| CPU time | 3.69 seconds |
| Started | Sep 09 07:13:17 PM UTC 24 |
| Finished | Sep 09 07:13:22 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746331113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.3746331113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/212.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/213.otp_ctrl_init_fail.4006882587 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 538755904 ps |
| CPU time | 3.21 seconds |
| Started | Sep 09 07:13:17 PM UTC 24 |
| Finished | Sep 09 07:13:21 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006882587 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.4006882587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/213.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/214.otp_ctrl_init_fail.1193685942 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 415041924 ps |
| CPU time | 2.91 seconds |
| Started | Sep 09 07:13:17 PM UTC 24 |
| Finished | Sep 09 07:13:21 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193685942 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.1193685942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/214.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/215.otp_ctrl_init_fail.3598343080 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 1788677670 ps |
| CPU time | 3.85 seconds |
| Started | Sep 09 07:13:17 PM UTC 24 |
| Finished | Sep 09 07:13:22 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598343080 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.3598343080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/215.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/216.otp_ctrl_init_fail.1051723975 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 236718003 ps |
| CPU time | 3.02 seconds |
| Started | Sep 09 07:13:17 PM UTC 24 |
| Finished | Sep 09 07:13:21 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051723975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.1051723975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/216.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/217.otp_ctrl_init_fail.4246233837 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 239627298 ps |
| CPU time | 4.09 seconds |
| Started | Sep 09 07:13:17 PM UTC 24 |
| Finished | Sep 09 07:13:22 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246233837 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.4246233837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/217.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/218.otp_ctrl_init_fail.1730730975 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 276354956 ps |
| CPU time | 3.51 seconds |
| Started | Sep 09 07:13:17 PM UTC 24 |
| Finished | Sep 09 07:13:22 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730730975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.1730730975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/218.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/219.otp_ctrl_init_fail.1320361760 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 388207230 ps |
| CPU time | 3.82 seconds |
| Started | Sep 09 07:13:17 PM UTC 24 |
| Finished | Sep 09 07:13:22 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320361760 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.1320361760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/219.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_alert_test.2719792007 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 777053820 ps |
| CPU time | 2.49 seconds |
| Started | Sep 09 07:06:54 PM UTC 24 |
| Finished | Sep 09 07:06:58 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719792007 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_alert_test.2719792007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/22.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_check_fail.1247059460 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 1417810372 ps |
| CPU time | 13.14 seconds |
| Started | Sep 09 07:06:49 PM UTC 24 |
| Finished | Sep 09 07:07:03 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247059460 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.1247059460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/22.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_errs.1604989262 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1249460357 ps |
| CPU time | 30.68 seconds |
| Started | Sep 09 07:06:49 PM UTC 24 |
| Finished | Sep 09 07:07:21 PM UTC 24 |
| Peak memory | 255584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604989262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.1604989262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/22.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_dai_lock.1731122840 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 10369416454 ps |
| CPU time | 16.03 seconds |
| Started | Sep 09 07:06:49 PM UTC 24 |
| Finished | Sep 09 07:07:06 PM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731122840 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.1731122840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/22.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_init_fail.3890872315 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 472686060 ps |
| CPU time | 5.29 seconds |
| Started | Sep 09 07:06:49 PM UTC 24 |
| Finished | Sep 09 07:06:55 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890872315 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.3890872315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/22.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_macro_errs.1948928517 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 1579047631 ps |
| CPU time | 13.49 seconds |
| Started | Sep 09 07:06:51 PM UTC 24 |
| Finished | Sep 09 07:07:06 PM UTC 24 |
| Peak memory | 257460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948928517 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_macro_errs.1948928517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/22.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_key_req.1771750662 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 3011358434 ps |
| CPU time | 11.22 seconds |
| Started | Sep 09 07:06:51 PM UTC 24 |
| Finished | Sep 09 07:07:03 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771750662 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_key_req.1771750662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_esc.3664175222 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 1254143108 ps |
| CPU time | 16.94 seconds |
| Started | Sep 09 07:06:49 PM UTC 24 |
| Finished | Sep 09 07:07:07 PM UTC 24 |
| Peak memory | 250888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664175222 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.3664175222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_parallel_lc_req.3238421216 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 6851383732 ps |
| CPU time | 23.13 seconds |
| Started | Sep 09 07:06:49 PM UTC 24 |
| Finished | Sep 09 07:07:13 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3238421216 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_req.3238421216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_regwen.509851995 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 164890417 ps |
| CPU time | 6.8 seconds |
| Started | Sep 09 07:06:51 PM UTC 24 |
| Finished | Sep 09 07:06:59 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509851995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.509851995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/22.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_smoke.385492180 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 94928731 ps |
| CPU time | 4.56 seconds |
| Started | Sep 09 07:06:49 PM UTC 24 |
| Finished | Sep 09 07:06:54 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385492180 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_smoke.385492180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/22.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/22.otp_ctrl_test_access.4191481452 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1132135820 ps |
| CPU time | 17.98 seconds |
| Started | Sep 09 07:06:54 PM UTC 24 |
| Finished | Sep 09 07:07:14 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191481452 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_test_access.4191481452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/22.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/220.otp_ctrl_init_fail.1946205316 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 231991966 ps |
| CPU time | 3.87 seconds |
| Started | Sep 09 07:13:17 PM UTC 24 |
| Finished | Sep 09 07:13:22 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946205316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.1946205316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/220.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/221.otp_ctrl_init_fail.1414422366 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 124827999 ps |
| CPU time | 4.38 seconds |
| Started | Sep 09 07:13:17 PM UTC 24 |
| Finished | Sep 09 07:13:23 PM UTC 24 |
| Peak memory | 251264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414422366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.1414422366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/221.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/222.otp_ctrl_init_fail.2116772469 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 103754443 ps |
| CPU time | 3.51 seconds |
| Started | Sep 09 07:13:17 PM UTC 24 |
| Finished | Sep 09 07:13:22 PM UTC 24 |
| Peak memory | 251264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116772469 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.2116772469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/222.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/223.otp_ctrl_init_fail.3483371531 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 275395532 ps |
| CPU time | 4.94 seconds |
| Started | Sep 09 07:13:17 PM UTC 24 |
| Finished | Sep 09 07:13:23 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483371531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.3483371531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/223.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/224.otp_ctrl_init_fail.156562541 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 169677658 ps |
| CPU time | 4.02 seconds |
| Started | Sep 09 07:13:17 PM UTC 24 |
| Finished | Sep 09 07:13:23 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156562541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.156562541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/224.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/225.otp_ctrl_init_fail.4011801378 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 1991342590 ps |
| CPU time | 3.6 seconds |
| Started | Sep 09 07:13:17 PM UTC 24 |
| Finished | Sep 09 07:13:22 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011801378 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.4011801378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/225.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/226.otp_ctrl_init_fail.4079635746 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 405248621 ps |
| CPU time | 3.82 seconds |
| Started | Sep 09 07:13:17 PM UTC 24 |
| Finished | Sep 09 07:13:22 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079635746 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.4079635746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/226.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/227.otp_ctrl_init_fail.250233885 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 309928374 ps |
| CPU time | 3.27 seconds |
| Started | Sep 09 07:13:17 PM UTC 24 |
| Finished | Sep 09 07:13:22 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250233885 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.250233885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/227.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/228.otp_ctrl_init_fail.71932482 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 388295549 ps |
| CPU time | 3.95 seconds |
| Started | Sep 09 07:13:27 PM UTC 24 |
| Finished | Sep 09 07:13:32 PM UTC 24 |
| Peak memory | 251264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71932482 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.71932482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/228.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/229.otp_ctrl_init_fail.2778473151 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 257068993 ps |
| CPU time | 4.57 seconds |
| Started | Sep 09 07:13:27 PM UTC 24 |
| Finished | Sep 09 07:13:33 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778473151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.2778473151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/229.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_alert_test.562182365 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 52556920 ps |
| CPU time | 2.51 seconds |
| Started | Sep 09 07:07:05 PM UTC 24 |
| Finished | Sep 09 07:07:09 PM UTC 24 |
| Peak memory | 250964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562182365 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_alert_test.562182365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/23.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_check_fail.93277512 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 254280636 ps |
| CPU time | 8.4 seconds |
| Started | Sep 09 07:06:58 PM UTC 24 |
| Finished | Sep 09 07:07:07 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93277512 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.93277512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/23.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_errs.538593703 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 2267172725 ps |
| CPU time | 31.87 seconds |
| Started | Sep 09 07:06:58 PM UTC 24 |
| Finished | Sep 09 07:07:31 PM UTC 24 |
| Peak memory | 257572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538593703 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.538593703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/23.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_dai_lock.480135800 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 753178694 ps |
| CPU time | 6.75 seconds |
| Started | Sep 09 07:06:57 PM UTC 24 |
| Finished | Sep 09 07:07:05 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480135800 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.480135800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/23.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_init_fail.2898393034 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 191656040 ps |
| CPU time | 4.39 seconds |
| Started | Sep 09 07:06:57 PM UTC 24 |
| Finished | Sep 09 07:07:03 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898393034 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.2898393034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/23.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_macro_errs.3441750658 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 7024962337 ps |
| CPU time | 17.47 seconds |
| Started | Sep 09 07:07:04 PM UTC 24 |
| Finished | Sep 09 07:07:23 PM UTC 24 |
| Peak memory | 253296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441750658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_macro_errs.3441750658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/23.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_key_req.3194842304 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 1317666036 ps |
| CPU time | 12.91 seconds |
| Started | Sep 09 07:07:04 PM UTC 24 |
| Finished | Sep 09 07:07:19 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194842304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_key_req.3194842304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_esc.2628859633 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 221673418 ps |
| CPU time | 11.5 seconds |
| Started | Sep 09 07:06:57 PM UTC 24 |
| Finished | Sep 09 07:07:10 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628859633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.2628859633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_parallel_lc_req.3201105338 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 381292854 ps |
| CPU time | 7.62 seconds |
| Started | Sep 09 07:06:57 PM UTC 24 |
| Finished | Sep 09 07:07:06 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201105338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_req.3201105338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_smoke.3246252004 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 137308881 ps |
| CPU time | 5.07 seconds |
| Started | Sep 09 07:06:54 PM UTC 24 |
| Finished | Sep 09 07:07:01 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3246252004 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_smoke.3246252004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/23.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all.3455774307 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 22451386281 ps |
| CPU time | 245.07 seconds |
| Started | Sep 09 07:07:05 PM UTC 24 |
| Finished | Sep 09 07:11:14 PM UTC 24 |
| Peak memory | 267888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455774307 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all.3455774307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_stress_all_with_rand_reset.3556508231 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 15542484443 ps |
| CPU time | 62.1 seconds |
| Started | Sep 09 07:07:05 PM UTC 24 |
| Finished | Sep 09 07:08:09 PM UTC 24 |
| Peak memory | 267824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3556508231 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 23.otp_ctrl_stress_all_with_rand_reset.3556508231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/23.otp_ctrl_test_access.3628388143 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 2858978266 ps |
| CPU time | 6.88 seconds |
| Started | Sep 09 07:07:05 PM UTC 24 |
| Finished | Sep 09 07:07:13 PM UTC 24 |
| Peak memory | 257780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628388143 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_test_access.3628388143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/23.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/230.otp_ctrl_init_fail.1697381775 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 352360483 ps |
| CPU time | 4.96 seconds |
| Started | Sep 09 07:13:27 PM UTC 24 |
| Finished | Sep 09 07:13:33 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697381775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.1697381775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/230.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/231.otp_ctrl_init_fail.203839390 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 603502381 ps |
| CPU time | 4.51 seconds |
| Started | Sep 09 07:13:27 PM UTC 24 |
| Finished | Sep 09 07:13:33 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203839390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.203839390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/231.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/232.otp_ctrl_init_fail.4143941235 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 121491823 ps |
| CPU time | 4.54 seconds |
| Started | Sep 09 07:13:27 PM UTC 24 |
| Finished | Sep 09 07:13:33 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143941235 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.4143941235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/232.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/233.otp_ctrl_init_fail.3520535973 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 2044950108 ps |
| CPU time | 4.39 seconds |
| Started | Sep 09 07:13:27 PM UTC 24 |
| Finished | Sep 09 07:13:33 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520535973 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.3520535973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/233.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/234.otp_ctrl_init_fail.3279580799 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 132665507 ps |
| CPU time | 2.69 seconds |
| Started | Sep 09 07:13:27 PM UTC 24 |
| Finished | Sep 09 07:13:31 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279580799 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.3279580799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/234.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/235.otp_ctrl_init_fail.256618572 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 203096024 ps |
| CPU time | 2.82 seconds |
| Started | Sep 09 07:13:27 PM UTC 24 |
| Finished | Sep 09 07:13:31 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256618572 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.256618572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/235.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/236.otp_ctrl_init_fail.2335032214 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 1965420976 ps |
| CPU time | 5.9 seconds |
| Started | Sep 09 07:13:27 PM UTC 24 |
| Finished | Sep 09 07:13:35 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335032214 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.2335032214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/236.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/237.otp_ctrl_init_fail.4175674414 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 541605311 ps |
| CPU time | 3.5 seconds |
| Started | Sep 09 07:13:27 PM UTC 24 |
| Finished | Sep 09 07:13:32 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175674414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.4175674414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/237.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/238.otp_ctrl_init_fail.2924548842 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 411343598 ps |
| CPU time | 3.69 seconds |
| Started | Sep 09 07:13:27 PM UTC 24 |
| Finished | Sep 09 07:13:32 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924548842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.2924548842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/238.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/239.otp_ctrl_init_fail.3605857147 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 2050388893 ps |
| CPU time | 6.07 seconds |
| Started | Sep 09 07:13:27 PM UTC 24 |
| Finished | Sep 09 07:13:35 PM UTC 24 |
| Peak memory | 250956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605857147 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.3605857147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/239.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_alert_test.2016152159 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 115010447 ps |
| CPU time | 2.36 seconds |
| Started | Sep 09 07:07:12 PM UTC 24 |
| Finished | Sep 09 07:07:16 PM UTC 24 |
| Peak memory | 251120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016152159 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_alert_test.2016152159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/24.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_check_fail.3597786093 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 615756059 ps |
| CPU time | 13.62 seconds |
| Started | Sep 09 07:07:08 PM UTC 24 |
| Finished | Sep 09 07:07:23 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597786093 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.3597786093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/24.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_errs.2009634058 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1622679777 ps |
| CPU time | 21.72 seconds |
| Started | Sep 09 07:07:08 PM UTC 24 |
| Finished | Sep 09 07:07:32 PM UTC 24 |
| Peak memory | 251260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009634058 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.2009634058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/24.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_dai_lock.4157245723 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 3961528376 ps |
| CPU time | 23.28 seconds |
| Started | Sep 09 07:07:08 PM UTC 24 |
| Finished | Sep 09 07:07:33 PM UTC 24 |
| Peak memory | 257788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157245723 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.4157245723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/24.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_init_fail.3236027035 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 165215336 ps |
| CPU time | 4.64 seconds |
| Started | Sep 09 07:07:05 PM UTC 24 |
| Finished | Sep 09 07:07:11 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236027035 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.3236027035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/24.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_macro_errs.1809168123 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 2744251263 ps |
| CPU time | 15.78 seconds |
| Started | Sep 09 07:07:08 PM UTC 24 |
| Finished | Sep 09 07:07:26 PM UTC 24 |
| Peak memory | 257628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809168123 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_macro_errs.1809168123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/24.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_key_req.2294381248 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 20012583814 ps |
| CPU time | 40.8 seconds |
| Started | Sep 09 07:07:09 PM UTC 24 |
| Finished | Sep 09 07:07:51 PM UTC 24 |
| Peak memory | 253752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294381248 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_key_req.2294381248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_esc.3273912375 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 862570693 ps |
| CPU time | 6.79 seconds |
| Started | Sep 09 07:07:08 PM UTC 24 |
| Finished | Sep 09 07:07:16 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273912375 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.3273912375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_parallel_lc_req.2013709595 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 10712663473 ps |
| CPU time | 24.33 seconds |
| Started | Sep 09 07:07:05 PM UTC 24 |
| Finished | Sep 09 07:07:31 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013709595 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_req.2013709595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_regwen.1778503207 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 1706411659 ps |
| CPU time | 7.04 seconds |
| Started | Sep 09 07:07:09 PM UTC 24 |
| Finished | Sep 09 07:07:17 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778503207 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.1778503207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/24.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_smoke.891367165 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 174061801 ps |
| CPU time | 4.95 seconds |
| Started | Sep 09 07:07:05 PM UTC 24 |
| Finished | Sep 09 07:07:11 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891367165 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_smoke.891367165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/24.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all.2374733512 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 18500166796 ps |
| CPU time | 130.41 seconds |
| Started | Sep 09 07:07:12 PM UTC 24 |
| Finished | Sep 09 07:09:25 PM UTC 24 |
| Peak memory | 257468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374733512 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all.2374733512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_stress_all_with_rand_reset.622462685 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 26649986175 ps |
| CPU time | 87.94 seconds |
| Started | Sep 09 07:07:09 PM UTC 24 |
| Finished | Sep 09 07:08:39 PM UTC 24 |
| Peak memory | 267928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=622462685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.622462685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/24.otp_ctrl_test_access.432382544 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 9251725643 ps |
| CPU time | 14.33 seconds |
| Started | Sep 09 07:07:09 PM UTC 24 |
| Finished | Sep 09 07:07:24 PM UTC 24 |
| Peak memory | 253460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432382544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_test_access.432382544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/24.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/240.otp_ctrl_init_fail.3083096043 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 529918062 ps |
| CPU time | 3.37 seconds |
| Started | Sep 09 07:13:27 PM UTC 24 |
| Finished | Sep 09 07:13:32 PM UTC 24 |
| Peak memory | 251052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083096043 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.3083096043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/240.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/241.otp_ctrl_init_fail.2683058285 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 105243507 ps |
| CPU time | 3.1 seconds |
| Started | Sep 09 07:13:27 PM UTC 24 |
| Finished | Sep 09 07:13:32 PM UTC 24 |
| Peak memory | 250632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683058285 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.2683058285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/241.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/242.otp_ctrl_init_fail.909989810 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 147653179 ps |
| CPU time | 3.01 seconds |
| Started | Sep 09 07:13:27 PM UTC 24 |
| Finished | Sep 09 07:13:32 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909989810 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.909989810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/242.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/243.otp_ctrl_init_fail.1153938390 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 316942527 ps |
| CPU time | 3.83 seconds |
| Started | Sep 09 07:13:27 PM UTC 24 |
| Finished | Sep 09 07:13:33 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153938390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.1153938390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/243.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/244.otp_ctrl_init_fail.11451141 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 316779106 ps |
| CPU time | 4.15 seconds |
| Started | Sep 09 07:13:27 PM UTC 24 |
| Finished | Sep 09 07:13:33 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11451141 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.11451141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/244.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/245.otp_ctrl_init_fail.2715215153 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 591546774 ps |
| CPU time | 3.5 seconds |
| Started | Sep 09 07:13:27 PM UTC 24 |
| Finished | Sep 09 07:13:32 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715215153 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.2715215153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/245.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/246.otp_ctrl_init_fail.525135129 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 318731941 ps |
| CPU time | 2.74 seconds |
| Started | Sep 09 07:13:27 PM UTC 24 |
| Finished | Sep 09 07:13:32 PM UTC 24 |
| Peak memory | 253468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525135129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.525135129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/246.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/247.otp_ctrl_init_fail.3630744140 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 384396305 ps |
| CPU time | 4.22 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:33 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630744140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.3630744140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/247.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/248.otp_ctrl_init_fail.3379164789 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 347157209 ps |
| CPU time | 3.29 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:32 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379164789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.3379164789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/248.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/249.otp_ctrl_init_fail.4105973581 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 265720069 ps |
| CPU time | 4.02 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:33 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105973581 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.4105973581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/249.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_alert_test.2967198736 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 332745004 ps |
| CPU time | 3.15 seconds |
| Started | Sep 09 07:07:18 PM UTC 24 |
| Finished | Sep 09 07:07:22 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967198736 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_alert_test.2967198736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/25.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_check_fail.4268790929 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1334468853 ps |
| CPU time | 26.72 seconds |
| Started | Sep 09 07:07:18 PM UTC 24 |
| Finished | Sep 09 07:07:46 PM UTC 24 |
| Peak memory | 250964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268790929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.4268790929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/25.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_errs.411718589 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 18881640298 ps |
| CPU time | 59.65 seconds |
| Started | Sep 09 07:07:12 PM UTC 24 |
| Finished | Sep 09 07:08:14 PM UTC 24 |
| Peak memory | 257536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411718589 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_errs.411718589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/25.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_dai_lock.1146567692 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 365916874 ps |
| CPU time | 5.61 seconds |
| Started | Sep 09 07:07:12 PM UTC 24 |
| Finished | Sep 09 07:07:19 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146567692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.1146567692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/25.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_init_fail.715074183 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 149920234 ps |
| CPU time | 5.44 seconds |
| Started | Sep 09 07:07:12 PM UTC 24 |
| Finished | Sep 09 07:07:19 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715074183 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.715074183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/25.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_macro_errs.3724885954 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 2180289669 ps |
| CPU time | 36.38 seconds |
| Started | Sep 09 07:07:18 PM UTC 24 |
| Finished | Sep 09 07:07:55 PM UTC 24 |
| Peak memory | 257184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724885954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_macro_errs.3724885954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/25.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_key_req.3914348023 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 1934376684 ps |
| CPU time | 5.18 seconds |
| Started | Sep 09 07:07:18 PM UTC 24 |
| Finished | Sep 09 07:07:24 PM UTC 24 |
| Peak memory | 250656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914348023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_key_req.3914348023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_esc.465028533 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 320377603 ps |
| CPU time | 8.81 seconds |
| Started | Sep 09 07:07:12 PM UTC 24 |
| Finished | Sep 09 07:07:22 PM UTC 24 |
| Peak memory | 251332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465028533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.465028533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_parallel_lc_req.3652575679 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 271733901 ps |
| CPU time | 7.24 seconds |
| Started | Sep 09 07:07:12 PM UTC 24 |
| Finished | Sep 09 07:07:21 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652575679 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_req.3652575679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_regwen.711714598 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 3891819004 ps |
| CPU time | 11.01 seconds |
| Started | Sep 09 07:07:18 PM UTC 24 |
| Finished | Sep 09 07:07:30 PM UTC 24 |
| Peak memory | 250860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711714598 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.711714598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/25.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_smoke.4043146467 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 1070115478 ps |
| CPU time | 12.31 seconds |
| Started | Sep 09 07:07:12 PM UTC 24 |
| Finished | Sep 09 07:07:26 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043146467 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_smoke.4043146467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/25.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_stress_all.1069183116 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 44421069615 ps |
| CPU time | 146.16 seconds |
| Started | Sep 09 07:07:18 PM UTC 24 |
| Finished | Sep 09 07:09:47 PM UTC 24 |
| Peak memory | 257472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069183116 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all.1069183116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/25.otp_ctrl_test_access.3226774499 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 596795722 ps |
| CPU time | 10.14 seconds |
| Started | Sep 09 07:07:18 PM UTC 24 |
| Finished | Sep 09 07:07:29 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226774499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_test_access.3226774499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/25.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/250.otp_ctrl_init_fail.451282360 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 165660853 ps |
| CPU time | 3.4 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:32 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451282360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.451282360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/250.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/251.otp_ctrl_init_fail.1161341253 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 119207280 ps |
| CPU time | 2.84 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:32 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161341253 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.1161341253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/251.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/252.otp_ctrl_init_fail.1117132029 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 164499150 ps |
| CPU time | 4.38 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:34 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117132029 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.1117132029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/252.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/253.otp_ctrl_init_fail.3795451287 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 2095580707 ps |
| CPU time | 3.95 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:33 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795451287 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.3795451287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/253.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/254.otp_ctrl_init_fail.853303041 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 120450016 ps |
| CPU time | 4.09 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:33 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853303041 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.853303041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/254.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/255.otp_ctrl_init_fail.2736337787 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 335707748 ps |
| CPU time | 3.62 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:33 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736337787 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.2736337787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/255.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/256.otp_ctrl_init_fail.4271394329 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 154801169 ps |
| CPU time | 4.78 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:34 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271394329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.4271394329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/256.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/257.otp_ctrl_init_fail.3316969463 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 528042457 ps |
| CPU time | 2.9 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:32 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316969463 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.3316969463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/257.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/258.otp_ctrl_init_fail.1766080870 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 1521064187 ps |
| CPU time | 4.86 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:34 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766080870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.1766080870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/258.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/259.otp_ctrl_init_fail.845603887 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 389440253 ps |
| CPU time | 3.98 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:33 PM UTC 24 |
| Peak memory | 251440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845603887 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.845603887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/259.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_alert_test.2417449566 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 58941055 ps |
| CPU time | 2.78 seconds |
| Started | Sep 09 07:07:25 PM UTC 24 |
| Finished | Sep 09 07:07:29 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417449566 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_alert_test.2417449566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/26.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_errs.3015209685 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 447673544 ps |
| CPU time | 13.13 seconds |
| Started | Sep 09 07:07:20 PM UTC 24 |
| Finished | Sep 09 07:07:34 PM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015209685 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_errs.3015209685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/26.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_dai_lock.3406819424 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 2482190094 ps |
| CPU time | 26.02 seconds |
| Started | Sep 09 07:07:20 PM UTC 24 |
| Finished | Sep 09 07:07:47 PM UTC 24 |
| Peak memory | 257532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406819424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.3406819424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/26.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_init_fail.4064527121 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 324331589 ps |
| CPU time | 4.51 seconds |
| Started | Sep 09 07:07:20 PM UTC 24 |
| Finished | Sep 09 07:07:25 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064527121 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.4064527121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/26.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_macro_errs.2998707612 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 2098529632 ps |
| CPU time | 51.58 seconds |
| Started | Sep 09 07:07:23 PM UTC 24 |
| Finished | Sep 09 07:08:16 PM UTC 24 |
| Peak memory | 267760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998707612 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_macro_errs.2998707612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/26.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_key_req.3250397 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 819619212 ps |
| CPU time | 19.61 seconds |
| Started | Sep 09 07:07:23 PM UTC 24 |
| Finished | Sep 09 07:07:43 PM UTC 24 |
| Peak memory | 253740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_S EQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_key_req.3250397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_parallel_lc_req.3262073580 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 212644667 ps |
| CPU time | 5.34 seconds |
| Started | Sep 09 07:07:20 PM UTC 24 |
| Finished | Sep 09 07:07:26 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262073580 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_req.3262073580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_regwen.2630248187 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 261355655 ps |
| CPU time | 7.28 seconds |
| Started | Sep 09 07:07:23 PM UTC 24 |
| Finished | Sep 09 07:07:31 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630248187 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.2630248187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/26.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_smoke.883195963 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 320095180 ps |
| CPU time | 5.9 seconds |
| Started | Sep 09 07:07:18 PM UTC 24 |
| Finished | Sep 09 07:07:25 PM UTC 24 |
| Peak memory | 251552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883195963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_smoke.883195963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/26.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_stress_all.304380880 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 10140733259 ps |
| CPU time | 108.38 seconds |
| Started | Sep 09 07:07:25 PM UTC 24 |
| Finished | Sep 09 07:09:15 PM UTC 24 |
| Peak memory | 274004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304380880 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all.304380880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/26.otp_ctrl_test_access.4252742138 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 2384128647 ps |
| CPU time | 25.19 seconds |
| Started | Sep 09 07:07:24 PM UTC 24 |
| Finished | Sep 09 07:07:51 PM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252742138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_test_access.4252742138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/26.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/260.otp_ctrl_init_fail.2160603599 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 289748944 ps |
| CPU time | 3.87 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:34 PM UTC 24 |
| Peak memory | 253268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160603599 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.2160603599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/260.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/261.otp_ctrl_init_fail.693760265 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 2321678360 ps |
| CPU time | 5.47 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:35 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693760265 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.693760265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/261.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/262.otp_ctrl_init_fail.4177751500 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 157025436 ps |
| CPU time | 4.64 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:34 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177751500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.4177751500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/262.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/263.otp_ctrl_init_fail.730583999 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 155624323 ps |
| CPU time | 3.31 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:33 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730583999 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.730583999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/263.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/264.otp_ctrl_init_fail.664088182 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 161042694 ps |
| CPU time | 3.97 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:34 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664088182 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.664088182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/264.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/265.otp_ctrl_init_fail.2369183734 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 240668468 ps |
| CPU time | 5.62 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:35 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369183734 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.2369183734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/265.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/267.otp_ctrl_init_fail.349985352 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 236594011 ps |
| CPU time | 3.77 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:34 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349985352 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.349985352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/267.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/268.otp_ctrl_init_fail.3986156486 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 149054009 ps |
| CPU time | 4.27 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:34 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986156486 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.3986156486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/268.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_alert_test.1827886924 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 67307985 ps |
| CPU time | 2.72 seconds |
| Started | Sep 09 07:07:30 PM UTC 24 |
| Finished | Sep 09 07:07:34 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827886924 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_alert_test.1827886924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/27.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_check_fail.1120591118 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 474712712 ps |
| CPU time | 7.35 seconds |
| Started | Sep 09 07:07:29 PM UTC 24 |
| Finished | Sep 09 07:07:37 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120591118 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.1120591118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/27.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_errs.1916518134 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 2218752706 ps |
| CPU time | 34 seconds |
| Started | Sep 09 07:07:29 PM UTC 24 |
| Finished | Sep 09 07:08:04 PM UTC 24 |
| Peak memory | 257636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916518134 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_errs.1916518134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/27.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_dai_lock.3918440714 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 1039680595 ps |
| CPU time | 12.11 seconds |
| Started | Sep 09 07:07:29 PM UTC 24 |
| Finished | Sep 09 07:07:42 PM UTC 24 |
| Peak memory | 253372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918440714 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.3918440714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/27.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_init_fail.3974827636 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 153866432 ps |
| CPU time | 3.66 seconds |
| Started | Sep 09 07:07:25 PM UTC 24 |
| Finished | Sep 09 07:07:29 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974827636 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.3974827636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/27.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_macro_errs.632658702 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 17044764298 ps |
| CPU time | 29.34 seconds |
| Started | Sep 09 07:07:29 PM UTC 24 |
| Finished | Sep 09 07:07:59 PM UTC 24 |
| Peak memory | 255520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632658702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_macro_errs.632658702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/27.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_key_req.845992827 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 599784715 ps |
| CPU time | 4.47 seconds |
| Started | Sep 09 07:07:29 PM UTC 24 |
| Finished | Sep 09 07:07:34 PM UTC 24 |
| Peak memory | 251632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=845992827 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_key_req.845992827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_esc.327695088 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 413071143 ps |
| CPU time | 8.16 seconds |
| Started | Sep 09 07:07:29 PM UTC 24 |
| Finished | Sep 09 07:07:38 PM UTC 24 |
| Peak memory | 250996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327695088 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.327695088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_parallel_lc_req.2172255161 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 6286780003 ps |
| CPU time | 15.35 seconds |
| Started | Sep 09 07:07:28 PM UTC 24 |
| Finished | Sep 09 07:07:45 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172255161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_req.2172255161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_regwen.101025507 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 4203005137 ps |
| CPU time | 14.11 seconds |
| Started | Sep 09 07:07:29 PM UTC 24 |
| Finished | Sep 09 07:07:44 PM UTC 24 |
| Peak memory | 257744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101025507 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.101025507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/27.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_smoke.4250424704 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 557471230 ps |
| CPU time | 11.41 seconds |
| Started | Sep 09 07:07:25 PM UTC 24 |
| Finished | Sep 09 07:07:37 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250424704 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_smoke.4250424704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/27.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all.185080592 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 17913670226 ps |
| CPU time | 91.27 seconds |
| Started | Sep 09 07:07:30 PM UTC 24 |
| Finished | Sep 09 07:09:04 PM UTC 24 |
| Peak memory | 255672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185080592 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all.185080592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_stress_all_with_rand_reset.361819560 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 25041765967 ps |
| CPU time | 117.56 seconds |
| Started | Sep 09 07:07:30 PM UTC 24 |
| Finished | Sep 09 07:09:30 PM UTC 24 |
| Peak memory | 257600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=361819560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.361819560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/27.otp_ctrl_test_access.3066480782 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 2488005804 ps |
| CPU time | 34.29 seconds |
| Started | Sep 09 07:07:30 PM UTC 24 |
| Finished | Sep 09 07:08:06 PM UTC 24 |
| Peak memory | 257588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066480782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_test_access.3066480782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/27.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/270.otp_ctrl_init_fail.3740597605 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 327813046 ps |
| CPU time | 3.27 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:33 PM UTC 24 |
| Peak memory | 251140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740597605 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.3740597605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/270.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/271.otp_ctrl_init_fail.3776860457 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 120726240 ps |
| CPU time | 3.14 seconds |
| Started | Sep 09 07:13:28 PM UTC 24 |
| Finished | Sep 09 07:13:33 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776860457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.3776860457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/271.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/272.otp_ctrl_init_fail.489960919 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 107632947 ps |
| CPU time | 2.6 seconds |
| Started | Sep 09 07:13:41 PM UTC 24 |
| Finished | Sep 09 07:13:45 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489960919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.489960919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/272.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/273.otp_ctrl_init_fail.3092955647 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 157154570 ps |
| CPU time | 3.36 seconds |
| Started | Sep 09 07:13:41 PM UTC 24 |
| Finished | Sep 09 07:13:46 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092955647 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.3092955647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/273.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/274.otp_ctrl_init_fail.2594078583 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 189095917 ps |
| CPU time | 4.94 seconds |
| Started | Sep 09 07:13:41 PM UTC 24 |
| Finished | Sep 09 07:13:47 PM UTC 24 |
| Peak memory | 251128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594078583 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.2594078583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/274.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/275.otp_ctrl_init_fail.2990857770 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 211071140 ps |
| CPU time | 4.03 seconds |
| Started | Sep 09 07:13:41 PM UTC 24 |
| Finished | Sep 09 07:13:47 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990857770 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.2990857770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/275.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/276.otp_ctrl_init_fail.2551193516 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 1476965341 ps |
| CPU time | 4.81 seconds |
| Started | Sep 09 07:13:41 PM UTC 24 |
| Finished | Sep 09 07:13:47 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551193516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.2551193516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/276.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/277.otp_ctrl_init_fail.233973113 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 211351418 ps |
| CPU time | 3.46 seconds |
| Started | Sep 09 07:13:41 PM UTC 24 |
| Finished | Sep 09 07:13:46 PM UTC 24 |
| Peak memory | 253404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233973113 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.233973113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/277.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/278.otp_ctrl_init_fail.1993769510 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 137401791 ps |
| CPU time | 3.67 seconds |
| Started | Sep 09 07:13:41 PM UTC 24 |
| Finished | Sep 09 07:13:46 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993769510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.1993769510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/278.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_alert_test.1913026766 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 157724078 ps |
| CPU time | 2.28 seconds |
| Started | Sep 09 07:07:41 PM UTC 24 |
| Finished | Sep 09 07:07:45 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913026766 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_alert_test.1913026766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/28.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_check_fail.2087845742 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 16451560868 ps |
| CPU time | 32.8 seconds |
| Started | Sep 09 07:07:41 PM UTC 24 |
| Finished | Sep 09 07:08:15 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087845742 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.2087845742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/28.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_errs.3741334501 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 819970716 ps |
| CPU time | 10.7 seconds |
| Started | Sep 09 07:07:41 PM UTC 24 |
| Finished | Sep 09 07:07:53 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741334501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_errs.3741334501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/28.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_dai_lock.152035817 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 2319586737 ps |
| CPU time | 7.21 seconds |
| Started | Sep 09 07:07:33 PM UTC 24 |
| Finished | Sep 09 07:07:41 PM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152035817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.152035817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/28.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_init_fail.2542696355 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 231829578 ps |
| CPU time | 5.42 seconds |
| Started | Sep 09 07:07:32 PM UTC 24 |
| Finished | Sep 09 07:07:39 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542696355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.2542696355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/28.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_macro_errs.756202920 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 721622851 ps |
| CPU time | 15.1 seconds |
| Started | Sep 09 07:07:41 PM UTC 24 |
| Finished | Sep 09 07:07:57 PM UTC 24 |
| Peak memory | 251296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756202920 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_macro_errs.756202920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/28.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_key_req.2601088522 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 334926584 ps |
| CPU time | 14.03 seconds |
| Started | Sep 09 07:07:41 PM UTC 24 |
| Finished | Sep 09 07:07:56 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601088522 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_key_req.2601088522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_esc.1542556995 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 140493569 ps |
| CPU time | 7.44 seconds |
| Started | Sep 09 07:07:33 PM UTC 24 |
| Finished | Sep 09 07:07:41 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542556995 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.1542556995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_parallel_lc_req.3089902120 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 964094744 ps |
| CPU time | 9.79 seconds |
| Started | Sep 09 07:07:32 PM UTC 24 |
| Finished | Sep 09 07:07:44 PM UTC 24 |
| Peak memory | 257624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089902120 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_req.3089902120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_regwen.3936233170 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 818517925 ps |
| CPU time | 6.27 seconds |
| Started | Sep 09 07:07:41 PM UTC 24 |
| Finished | Sep 09 07:07:49 PM UTC 24 |
| Peak memory | 257616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936233170 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.3936233170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/28.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_smoke.1047991930 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 4828172322 ps |
| CPU time | 9.99 seconds |
| Started | Sep 09 07:07:32 PM UTC 24 |
| Finished | Sep 09 07:07:44 PM UTC 24 |
| Peak memory | 253468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047991930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_smoke.1047991930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/28.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all.944398464 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 7714624921 ps |
| CPU time | 148.55 seconds |
| Started | Sep 09 07:07:41 PM UTC 24 |
| Finished | Sep 09 07:10:13 PM UTC 24 |
| Peak memory | 267732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944398464 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all.944398464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_stress_all_with_rand_reset.1199352606 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 4304537712 ps |
| CPU time | 53.94 seconds |
| Started | Sep 09 07:07:41 PM UTC 24 |
| Finished | Sep 09 07:08:37 PM UTC 24 |
| Peak memory | 267832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1199352606 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 28.otp_ctrl_stress_all_with_rand_reset.1199352606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/28.otp_ctrl_test_access.3995317826 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1610472628 ps |
| CPU time | 21.42 seconds |
| Started | Sep 09 07:07:41 PM UTC 24 |
| Finished | Sep 09 07:08:04 PM UTC 24 |
| Peak memory | 251632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995317826 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_test_access.3995317826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/28.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/280.otp_ctrl_init_fail.1559524338 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 2001955945 ps |
| CPU time | 3.88 seconds |
| Started | Sep 09 07:13:41 PM UTC 24 |
| Finished | Sep 09 07:13:46 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559524338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.1559524338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/280.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/281.otp_ctrl_init_fail.4216251515 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 178282654 ps |
| CPU time | 3.38 seconds |
| Started | Sep 09 07:13:41 PM UTC 24 |
| Finished | Sep 09 07:13:46 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216251515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.4216251515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/281.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/282.otp_ctrl_init_fail.2779048060 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 167682749 ps |
| CPU time | 3.65 seconds |
| Started | Sep 09 07:13:41 PM UTC 24 |
| Finished | Sep 09 07:13:46 PM UTC 24 |
| Peak memory | 253268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779048060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.2779048060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/282.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/284.otp_ctrl_init_fail.2448442161 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 215090169 ps |
| CPU time | 3.89 seconds |
| Started | Sep 09 07:13:41 PM UTC 24 |
| Finished | Sep 09 07:13:47 PM UTC 24 |
| Peak memory | 250540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448442161 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.2448442161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/284.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/285.otp_ctrl_init_fail.3527071524 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 205081387 ps |
| CPU time | 3.19 seconds |
| Started | Sep 09 07:13:42 PM UTC 24 |
| Finished | Sep 09 07:13:46 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527071524 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.3527071524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/285.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/286.otp_ctrl_init_fail.749688174 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 259086481 ps |
| CPU time | 3.64 seconds |
| Started | Sep 09 07:13:42 PM UTC 24 |
| Finished | Sep 09 07:13:46 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749688174 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.749688174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/286.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/287.otp_ctrl_init_fail.3736666329 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 95031816 ps |
| CPU time | 2.75 seconds |
| Started | Sep 09 07:13:42 PM UTC 24 |
| Finished | Sep 09 07:13:46 PM UTC 24 |
| Peak memory | 253264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736666329 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.3736666329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/287.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/288.otp_ctrl_init_fail.3955717548 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 263498714 ps |
| CPU time | 3.72 seconds |
| Started | Sep 09 07:13:42 PM UTC 24 |
| Finished | Sep 09 07:13:47 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955717548 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.3955717548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/288.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/289.otp_ctrl_init_fail.1553041547 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 294081740 ps |
| CPU time | 4 seconds |
| Started | Sep 09 07:13:42 PM UTC 24 |
| Finished | Sep 09 07:13:47 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553041547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.1553041547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/289.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_alert_test.4127937270 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 239598699 ps |
| CPU time | 2 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:00 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127937270 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_alert_test.4127937270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/29.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_check_fail.2161603292 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 5547421802 ps |
| CPU time | 12.43 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:10 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161603292 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.2161603292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/29.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_errs.1441966967 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 3776544622 ps |
| CPU time | 18.56 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:17 PM UTC 24 |
| Peak memory | 251576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441966967 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_errs.1441966967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/29.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_dai_lock.1252824055 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 865065520 ps |
| CPU time | 20.49 seconds |
| Started | Sep 09 07:07:44 PM UTC 24 |
| Finished | Sep 09 07:08:05 PM UTC 24 |
| Peak memory | 251644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252824055 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.1252824055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/29.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_init_fail.634709870 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 422288552 ps |
| CPU time | 5.09 seconds |
| Started | Sep 09 07:07:43 PM UTC 24 |
| Finished | Sep 09 07:07:50 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634709870 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.634709870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/29.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_macro_errs.2066076063 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 3490708382 ps |
| CPU time | 43.21 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:41 PM UTC 24 |
| Peak memory | 267892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066076063 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_macro_errs.2066076063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/29.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_key_req.4172403031 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 449522978 ps |
| CPU time | 12.27 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:10 PM UTC 24 |
| Peak memory | 253336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172403031 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_key_req.4172403031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_esc.629120845 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1344090135 ps |
| CPU time | 10.2 seconds |
| Started | Sep 09 07:07:44 PM UTC 24 |
| Finished | Sep 09 07:07:55 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629120845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.629120845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_parallel_lc_req.478298838 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 272433286 ps |
| CPU time | 6.42 seconds |
| Started | Sep 09 07:07:43 PM UTC 24 |
| Finished | Sep 09 07:07:51 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478298838 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_req.478298838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_regwen.3323343427 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 252846468 ps |
| CPU time | 6.07 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:04 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323343427 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.3323343427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/29.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_smoke.1354954000 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 245520646 ps |
| CPU time | 7.32 seconds |
| Started | Sep 09 07:07:41 PM UTC 24 |
| Finished | Sep 09 07:07:50 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354954000 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_smoke.1354954000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/29.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all.1027913346 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 75556907421 ps |
| CPU time | 179.9 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:11:00 PM UTC 24 |
| Peak memory | 284252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027913346 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all.1027913346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_stress_all_with_rand_reset.457737938 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 5143055784 ps |
| CPU time | 34.68 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:33 PM UTC 24 |
| Peak memory | 257600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=457737938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.457737938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/29.otp_ctrl_test_access.2446184303 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 222620345 ps |
| CPU time | 7.31 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:06 PM UTC 24 |
| Peak memory | 257520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446184303 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_test_access.2446184303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/29.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/290.otp_ctrl_init_fail.3135620379 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 290632400 ps |
| CPU time | 3.72 seconds |
| Started | Sep 09 07:13:42 PM UTC 24 |
| Finished | Sep 09 07:13:47 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135620379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.3135620379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/290.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/291.otp_ctrl_init_fail.2532826173 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 313992173 ps |
| CPU time | 3.64 seconds |
| Started | Sep 09 07:13:42 PM UTC 24 |
| Finished | Sep 09 07:13:47 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532826173 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.2532826173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/291.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/292.otp_ctrl_init_fail.3750569710 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 295232768 ps |
| CPU time | 4.53 seconds |
| Started | Sep 09 07:13:42 PM UTC 24 |
| Finished | Sep 09 07:13:48 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750569710 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.3750569710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/292.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/293.otp_ctrl_init_fail.2592308410 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 394959800 ps |
| CPU time | 3.85 seconds |
| Started | Sep 09 07:13:42 PM UTC 24 |
| Finished | Sep 09 07:13:47 PM UTC 24 |
| Peak memory | 251528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592308410 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.2592308410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/293.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/294.otp_ctrl_init_fail.840006627 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 403564991 ps |
| CPU time | 4.15 seconds |
| Started | Sep 09 07:13:42 PM UTC 24 |
| Finished | Sep 09 07:13:47 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840006627 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.840006627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/294.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/295.otp_ctrl_init_fail.3171751898 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 348323700 ps |
| CPU time | 4.17 seconds |
| Started | Sep 09 07:13:42 PM UTC 24 |
| Finished | Sep 09 07:13:47 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171751898 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.3171751898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/295.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/296.otp_ctrl_init_fail.3708271676 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 1731631324 ps |
| CPU time | 5.06 seconds |
| Started | Sep 09 07:13:42 PM UTC 24 |
| Finished | Sep 09 07:13:48 PM UTC 24 |
| Peak memory | 251136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708271676 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.3708271676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/296.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/297.otp_ctrl_init_fail.305647842 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 159756433 ps |
| CPU time | 3.98 seconds |
| Started | Sep 09 07:13:42 PM UTC 24 |
| Finished | Sep 09 07:13:47 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305647842 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.305647842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/297.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/298.otp_ctrl_init_fail.1323866167 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 2106365799 ps |
| CPU time | 3.58 seconds |
| Started | Sep 09 07:13:42 PM UTC 24 |
| Finished | Sep 09 07:13:47 PM UTC 24 |
| Peak memory | 251476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323866167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.1323866167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/298.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/299.otp_ctrl_init_fail.2632460959 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 141082504 ps |
| CPU time | 3.55 seconds |
| Started | Sep 09 07:13:42 PM UTC 24 |
| Finished | Sep 09 07:13:47 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632460959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.2632460959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/299.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_alert_test.1259631471 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 127006017 ps |
| CPU time | 1.98 seconds |
| Started | Sep 09 07:04:35 PM UTC 24 |
| Finished | Sep 09 07:04:38 PM UTC 24 |
| Peak memory | 251136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259631471 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.1259631471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_dai_errs.746585112 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 17672956284 ps |
| CPU time | 31.11 seconds |
| Started | Sep 09 07:04:33 PM UTC 24 |
| Finished | Sep 09 07:05:06 PM UTC 24 |
| Peak memory | 257500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746585112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.746585112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_init_fail.3556254140 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2546364086 ps |
| CPU time | 5.38 seconds |
| Started | Sep 09 07:04:31 PM UTC 24 |
| Finished | Sep 09 07:04:38 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556254140 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.3556254140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_macro_errs.3011627157 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 456592188 ps |
| CPU time | 12.69 seconds |
| Started | Sep 09 07:04:33 PM UTC 24 |
| Finished | Sep 09 07:04:47 PM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011627157 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.3011627157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_parallel_lc_req.4029702996 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 1062238799 ps |
| CPU time | 8.79 seconds |
| Started | Sep 09 07:04:33 PM UTC 24 |
| Finished | Sep 09 07:04:43 PM UTC 24 |
| Peak memory | 257360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029702996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.4029702996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_regwen.1221079744 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 312445669 ps |
| CPU time | 7.95 seconds |
| Started | Sep 09 07:04:35 PM UTC 24 |
| Finished | Sep 09 07:04:44 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221079744 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.1221079744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_sec_cm.1858653191 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 11563452349 ps |
| CPU time | 193.65 seconds |
| Started | Sep 09 07:04:35 PM UTC 24 |
| Finished | Sep 09 07:07:52 PM UTC 24 |
| Peak memory | 287952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858653191 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.1858653191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/3.otp_ctrl_smoke.2840444516 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 205283375 ps |
| CPU time | 5.84 seconds |
| Started | Sep 09 07:04:31 PM UTC 24 |
| Finished | Sep 09 07:04:38 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840444516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.2840444516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/3.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_alert_test.3823278687 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 216765343 ps |
| CPU time | 2.56 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:01 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823278687 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_alert_test.3823278687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/30.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_check_fail.2372130730 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 2417132540 ps |
| CPU time | 15.39 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:14 PM UTC 24 |
| Peak memory | 257756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372130730 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.2372130730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/30.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_errs.3660520820 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 401937897 ps |
| CPU time | 8.25 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:07 PM UTC 24 |
| Peak memory | 253244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660520820 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_errs.3660520820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/30.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_dai_lock.4085322774 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 604018164 ps |
| CPU time | 7.53 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:06 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085322774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_dai_lock.4085322774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/30.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_init_fail.3775577865 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 449002622 ps |
| CPU time | 4.46 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:03 PM UTC 24 |
| Peak memory | 253592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775577865 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.3775577865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/30.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_macro_errs.2880176086 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 1667156602 ps |
| CPU time | 18.67 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:17 PM UTC 24 |
| Peak memory | 253424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880176086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_macro_errs.2880176086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/30.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_key_req.38500562 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 3239263167 ps |
| CPU time | 40.54 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:39 PM UTC 24 |
| Peak memory | 253552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38500562 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_key_req.38500562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_esc.998724534 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 164417825 ps |
| CPU time | 4.79 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:03 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998724534 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.998724534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_parallel_lc_req.873025634 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 1716585564 ps |
| CPU time | 17.51 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:16 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873025634 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_req.873025634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_regwen.857819258 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 586359826 ps |
| CPU time | 8.11 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:07 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857819258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_regwen.857819258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/30.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_smoke.1288835537 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 697070477 ps |
| CPU time | 6.64 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:05 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288835537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_smoke.1288835537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/30.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_stress_all.314294699 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 6965374669 ps |
| CPU time | 16.91 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:16 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314294699 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all.314294699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/30.otp_ctrl_test_access.1029888959 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 964896325 ps |
| CPU time | 19.73 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:19 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029888959 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_test_access.1029888959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/30.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_alert_test.3105487601 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 38077301 ps |
| CPU time | 2.29 seconds |
| Started | Sep 09 07:08:08 PM UTC 24 |
| Finished | Sep 09 07:08:11 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105487601 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_alert_test.3105487601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/31.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_check_fail.2275229343 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 716572845 ps |
| CPU time | 14.96 seconds |
| Started | Sep 09 07:08:02 PM UTC 24 |
| Finished | Sep 09 07:08:18 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275229343 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.2275229343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/31.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_errs.332633596 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 2592282688 ps |
| CPU time | 32.92 seconds |
| Started | Sep 09 07:08:02 PM UTC 24 |
| Finished | Sep 09 07:08:36 PM UTC 24 |
| Peak memory | 259516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332633596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_errs.332633596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/31.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_dai_lock.3567990260 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 402985344 ps |
| CPU time | 8.71 seconds |
| Started | Sep 09 07:08:02 PM UTC 24 |
| Finished | Sep 09 07:08:12 PM UTC 24 |
| Peak memory | 251580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567990260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_dai_lock.3567990260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/31.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_init_fail.362133789 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 1572938447 ps |
| CPU time | 5.33 seconds |
| Started | Sep 09 07:08:02 PM UTC 24 |
| Finished | Sep 09 07:08:08 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362133789 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.362133789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/31.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_macro_errs.208142210 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 2220302893 ps |
| CPU time | 18.32 seconds |
| Started | Sep 09 07:08:02 PM UTC 24 |
| Finished | Sep 09 07:08:22 PM UTC 24 |
| Peak memory | 253496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208142210 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_macro_errs.208142210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/31.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_key_req.3371838906 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1550456165 ps |
| CPU time | 32.78 seconds |
| Started | Sep 09 07:08:02 PM UTC 24 |
| Finished | Sep 09 07:08:36 PM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371838906 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_key_req.3371838906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_esc.1283487600 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 2333279599 ps |
| CPU time | 6.19 seconds |
| Started | Sep 09 07:08:02 PM UTC 24 |
| Finished | Sep 09 07:08:09 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283487600 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.1283487600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_parallel_lc_req.3063168510 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 1312470780 ps |
| CPU time | 10.33 seconds |
| Started | Sep 09 07:08:02 PM UTC 24 |
| Finished | Sep 09 07:08:13 PM UTC 24 |
| Peak memory | 257596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063168510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_req.3063168510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_regwen.2341566808 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 269296804 ps |
| CPU time | 9.96 seconds |
| Started | Sep 09 07:08:02 PM UTC 24 |
| Finished | Sep 09 07:08:13 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341566808 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_regwen.2341566808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/31.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_smoke.681963845 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 905903540 ps |
| CPU time | 7.92 seconds |
| Started | Sep 09 07:07:57 PM UTC 24 |
| Finished | Sep 09 07:08:07 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681963845 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_smoke.681963845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/31.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all.542883577 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 10285288283 ps |
| CPU time | 142.56 seconds |
| Started | Sep 09 07:08:08 PM UTC 24 |
| Finished | Sep 09 07:10:33 PM UTC 24 |
| Peak memory | 257488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542883577 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all.542883577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_stress_all_with_rand_reset.2519754915 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 22592383872 ps |
| CPU time | 128.28 seconds |
| Started | Sep 09 07:08:04 PM UTC 24 |
| Finished | Sep 09 07:10:14 PM UTC 24 |
| Peak memory | 267700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2519754915 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 31.otp_ctrl_stress_all_with_rand_reset.2519754915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/31.otp_ctrl_test_access.1172742236 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 314411709 ps |
| CPU time | 8.6 seconds |
| Started | Sep 09 07:08:04 PM UTC 24 |
| Finished | Sep 09 07:08:13 PM UTC 24 |
| Peak memory | 251072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172742236 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_test_access.1172742236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/31.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_alert_test.515565425 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 801116441 ps |
| CPU time | 1.95 seconds |
| Started | Sep 09 07:08:14 PM UTC 24 |
| Finished | Sep 09 07:08:17 PM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515565425 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_alert_test.515565425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/32.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_check_fail.3438443874 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2521361926 ps |
| CPU time | 13.01 seconds |
| Started | Sep 09 07:08:08 PM UTC 24 |
| Finished | Sep 09 07:08:22 PM UTC 24 |
| Peak memory | 251348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438443874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.3438443874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/32.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_errs.3720190530 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 1448097878 ps |
| CPU time | 29.41 seconds |
| Started | Sep 09 07:08:08 PM UTC 24 |
| Finished | Sep 09 07:08:39 PM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720190530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_errs.3720190530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/32.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_dai_lock.1306284515 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 2760411272 ps |
| CPU time | 38.92 seconds |
| Started | Sep 09 07:08:08 PM UTC 24 |
| Finished | Sep 09 07:08:48 PM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306284515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_dai_lock.1306284515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/32.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_macro_errs.1975308871 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 629543096 ps |
| CPU time | 9.38 seconds |
| Started | Sep 09 07:08:08 PM UTC 24 |
| Finished | Sep 09 07:08:19 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975308871 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_macro_errs.1975308871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/32.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_key_req.67384139 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 412093039 ps |
| CPU time | 7.35 seconds |
| Started | Sep 09 07:08:11 PM UTC 24 |
| Finished | Sep 09 07:08:19 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67384139 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_key_req.67384139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_esc.246225874 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 4824176349 ps |
| CPU time | 21.16 seconds |
| Started | Sep 09 07:08:08 PM UTC 24 |
| Finished | Sep 09 07:08:30 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246225874 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.246225874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_parallel_lc_req.1432204564 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 10814776373 ps |
| CPU time | 25.08 seconds |
| Started | Sep 09 07:08:08 PM UTC 24 |
| Finished | Sep 09 07:08:34 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432204564 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_req.1432204564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_regwen.876663424 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 4162301010 ps |
| CPU time | 11.86 seconds |
| Started | Sep 09 07:08:11 PM UTC 24 |
| Finished | Sep 09 07:08:24 PM UTC 24 |
| Peak memory | 253644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876663424 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_regwen.876663424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/32.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_smoke.1474683229 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 926934777 ps |
| CPU time | 10.26 seconds |
| Started | Sep 09 07:08:08 PM UTC 24 |
| Finished | Sep 09 07:08:19 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474683229 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_smoke.1474683229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/32.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all.1672128394 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 2512114278 ps |
| CPU time | 26.7 seconds |
| Started | Sep 09 07:08:11 PM UTC 24 |
| Finished | Sep 09 07:08:39 PM UTC 24 |
| Peak memory | 255416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672128394 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all.1672128394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_stress_all_with_rand_reset.2790995996 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 5747982817 ps |
| CPU time | 141.93 seconds |
| Started | Sep 09 07:08:11 PM UTC 24 |
| Finished | Sep 09 07:10:35 PM UTC 24 |
| Peak memory | 267888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2790995996 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 32.otp_ctrl_stress_all_with_rand_reset.2790995996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/32.otp_ctrl_test_access.1513686671 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 728078727 ps |
| CPU time | 15.44 seconds |
| Started | Sep 09 07:08:11 PM UTC 24 |
| Finished | Sep 09 07:08:27 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513686671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_test_access.1513686671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/32.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_alert_test.2613571920 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 175410917 ps |
| CPU time | 2.85 seconds |
| Started | Sep 09 07:08:17 PM UTC 24 |
| Finished | Sep 09 07:08:21 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613571920 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_alert_test.2613571920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/33.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_check_fail.3723133997 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 605663434 ps |
| CPU time | 8.75 seconds |
| Started | Sep 09 07:08:17 PM UTC 24 |
| Finished | Sep 09 07:08:27 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723133997 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.3723133997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/33.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_errs.273776852 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 742545629 ps |
| CPU time | 23.15 seconds |
| Started | Sep 09 07:08:17 PM UTC 24 |
| Finished | Sep 09 07:08:42 PM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273776852 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_errs.273776852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/33.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_dai_lock.270444185 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 3339057365 ps |
| CPU time | 12.97 seconds |
| Started | Sep 09 07:08:14 PM UTC 24 |
| Finished | Sep 09 07:08:28 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270444185 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_dai_lock.270444185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/33.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_init_fail.998441544 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 236930719 ps |
| CPU time | 4.36 seconds |
| Started | Sep 09 07:08:14 PM UTC 24 |
| Finished | Sep 09 07:08:19 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998441544 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.998441544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/33.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_macro_errs.365128431 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 242518157 ps |
| CPU time | 6.25 seconds |
| Started | Sep 09 07:08:17 PM UTC 24 |
| Finished | Sep 09 07:08:24 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365128431 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_macro_errs.365128431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/33.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_key_req.2889228658 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 16298443285 ps |
| CPU time | 52.84 seconds |
| Started | Sep 09 07:08:17 PM UTC 24 |
| Finished | Sep 09 07:09:12 PM UTC 24 |
| Peak memory | 253664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889228658 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_key_req.2889228658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_esc.3018977962 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2639978053 ps |
| CPU time | 31.96 seconds |
| Started | Sep 09 07:08:14 PM UTC 24 |
| Finished | Sep 09 07:08:47 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018977962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.3018977962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_parallel_lc_req.1938241205 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 863494488 ps |
| CPU time | 18.24 seconds |
| Started | Sep 09 07:08:14 PM UTC 24 |
| Finished | Sep 09 07:08:33 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938241205 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_req.1938241205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_regwen.1877818515 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 503499450 ps |
| CPU time | 7.61 seconds |
| Started | Sep 09 07:08:17 PM UTC 24 |
| Finished | Sep 09 07:08:26 PM UTC 24 |
| Peak memory | 251472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877818515 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_regwen.1877818515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/33.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_smoke.263932675 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 221570591 ps |
| CPU time | 6.65 seconds |
| Started | Sep 09 07:08:14 PM UTC 24 |
| Finished | Sep 09 07:08:22 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263932675 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_smoke.263932675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/33.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_stress_all.1641005033 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 10197236593 ps |
| CPU time | 55.68 seconds |
| Started | Sep 09 07:08:17 PM UTC 24 |
| Finished | Sep 09 07:09:15 PM UTC 24 |
| Peak memory | 255512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641005033 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all.1641005033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/33.otp_ctrl_test_access.625869766 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1859549014 ps |
| CPU time | 18.49 seconds |
| Started | Sep 09 07:08:17 PM UTC 24 |
| Finished | Sep 09 07:08:37 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625869766 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_test_access.625869766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/33.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_alert_test.165501869 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 93549559 ps |
| CPU time | 2.58 seconds |
| Started | Sep 09 07:08:24 PM UTC 24 |
| Finished | Sep 09 07:08:27 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165501869 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_alert_test.165501869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/34.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_check_fail.1388276649 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1166488949 ps |
| CPU time | 15.29 seconds |
| Started | Sep 09 07:08:21 PM UTC 24 |
| Finished | Sep 09 07:08:37 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388276649 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.1388276649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/34.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_errs.1076564674 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 2322035420 ps |
| CPU time | 22.85 seconds |
| Started | Sep 09 07:08:21 PM UTC 24 |
| Finished | Sep 09 07:08:45 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076564674 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_errs.1076564674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/34.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_dai_lock.3532722288 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 842780892 ps |
| CPU time | 15.43 seconds |
| Started | Sep 09 07:08:21 PM UTC 24 |
| Finished | Sep 09 07:08:37 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532722288 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_dai_lock.3532722288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/34.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_init_fail.656900271 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 171589551 ps |
| CPU time | 5.84 seconds |
| Started | Sep 09 07:08:20 PM UTC 24 |
| Finished | Sep 09 07:08:27 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656900271 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.656900271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/34.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_macro_errs.747823468 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 907712313 ps |
| CPU time | 23.01 seconds |
| Started | Sep 09 07:08:21 PM UTC 24 |
| Finished | Sep 09 07:08:45 PM UTC 24 |
| Peak memory | 257568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747823468 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_macro_errs.747823468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/34.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_key_req.3178502863 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 1628748809 ps |
| CPU time | 24.21 seconds |
| Started | Sep 09 07:08:21 PM UTC 24 |
| Finished | Sep 09 07:08:46 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178502863 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_key_req.3178502863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_esc.1200698929 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 564587139 ps |
| CPU time | 15.22 seconds |
| Started | Sep 09 07:08:21 PM UTC 24 |
| Finished | Sep 09 07:08:37 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200698929 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.1200698929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_parallel_lc_req.2967330786 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 1001419093 ps |
| CPU time | 17.91 seconds |
| Started | Sep 09 07:08:21 PM UTC 24 |
| Finished | Sep 09 07:08:40 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967330786 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_req.2967330786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_regwen.261894875 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 231555957 ps |
| CPU time | 9.5 seconds |
| Started | Sep 09 07:08:21 PM UTC 24 |
| Finished | Sep 09 07:08:32 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261894875 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_regwen.261894875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/34.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_smoke.2598630421 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 2125947213 ps |
| CPU time | 12.62 seconds |
| Started | Sep 09 07:08:18 PM UTC 24 |
| Finished | Sep 09 07:08:31 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598630421 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_smoke.2598630421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/34.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_stress_all.2802587076 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 54995106619 ps |
| CPU time | 236.31 seconds |
| Started | Sep 09 07:08:24 PM UTC 24 |
| Finished | Sep 09 07:12:24 PM UTC 24 |
| Peak memory | 278104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802587076 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all.2802587076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/34.otp_ctrl_test_access.3365436794 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 429579342 ps |
| CPU time | 8.96 seconds |
| Started | Sep 09 07:08:23 PM UTC 24 |
| Finished | Sep 09 07:08:34 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365436794 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_test_access.3365436794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/34.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_alert_test.3054945886 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 218861370 ps |
| CPU time | 2.28 seconds |
| Started | Sep 09 07:08:36 PM UTC 24 |
| Finished | Sep 09 07:08:39 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054945886 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_alert_test.3054945886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/35.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_check_fail.3533922066 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 738751029 ps |
| CPU time | 10.47 seconds |
| Started | Sep 09 07:08:30 PM UTC 24 |
| Finished | Sep 09 07:08:42 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533922066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.3533922066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/35.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_errs.898118697 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2153977083 ps |
| CPU time | 43.12 seconds |
| Started | Sep 09 07:08:30 PM UTC 24 |
| Finished | Sep 09 07:09:14 PM UTC 24 |
| Peak memory | 261860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898118697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_errs.898118697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/35.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_dai_lock.1568934547 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 245902753 ps |
| CPU time | 8.87 seconds |
| Started | Sep 09 07:08:29 PM UTC 24 |
| Finished | Sep 09 07:08:40 PM UTC 24 |
| Peak memory | 251644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568934547 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_dai_lock.1568934547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/35.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_macro_errs.2237983089 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 3042216791 ps |
| CPU time | 17.19 seconds |
| Started | Sep 09 07:08:30 PM UTC 24 |
| Finished | Sep 09 07:08:49 PM UTC 24 |
| Peak memory | 253304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237983089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_macro_errs.2237983089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/35.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_key_req.3689776965 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 2367854572 ps |
| CPU time | 15.02 seconds |
| Started | Sep 09 07:08:30 PM UTC 24 |
| Finished | Sep 09 07:08:47 PM UTC 24 |
| Peak memory | 251640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689776965 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_key_req.3689776965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_esc.4218928559 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 371793837 ps |
| CPU time | 8.47 seconds |
| Started | Sep 09 07:08:27 PM UTC 24 |
| Finished | Sep 09 07:08:37 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218928559 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.4218928559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_parallel_lc_req.1835444659 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 934671482 ps |
| CPU time | 16.42 seconds |
| Started | Sep 09 07:08:25 PM UTC 24 |
| Finished | Sep 09 07:08:43 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835444659 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_req.1835444659 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_regwen.3620187388 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 5345854572 ps |
| CPU time | 13.11 seconds |
| Started | Sep 09 07:08:31 PM UTC 24 |
| Finished | Sep 09 07:08:46 PM UTC 24 |
| Peak memory | 251344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620187388 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_regwen.3620187388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/35.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_smoke.2592583151 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 3484488878 ps |
| CPU time | 14.65 seconds |
| Started | Sep 09 07:08:24 PM UTC 24 |
| Finished | Sep 09 07:08:40 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592583151 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_smoke.2592583151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/35.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all.3443718192 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 114588545703 ps |
| CPU time | 178.72 seconds |
| Started | Sep 09 07:08:36 PM UTC 24 |
| Finished | Sep 09 07:11:37 PM UTC 24 |
| Peak memory | 269756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443718192 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all.3443718192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_stress_all_with_rand_reset.3502693633 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 771963716 ps |
| CPU time | 21.58 seconds |
| Started | Sep 09 07:08:33 PM UTC 24 |
| Finished | Sep 09 07:08:56 PM UTC 24 |
| Peak memory | 257584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3502693633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 35.otp_ctrl_stress_all_with_rand_reset.3502693633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/35.otp_ctrl_test_access.1366757833 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 2734514931 ps |
| CPU time | 15.81 seconds |
| Started | Sep 09 07:08:33 PM UTC 24 |
| Finished | Sep 09 07:08:50 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366757833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_test_access.1366757833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/35.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_alert_test.2201454961 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 152028217 ps |
| CPU time | 1.93 seconds |
| Started | Sep 09 07:08:45 PM UTC 24 |
| Finished | Sep 09 07:08:48 PM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201454961 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_alert_test.2201454961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/36.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_check_fail.960312300 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1915458372 ps |
| CPU time | 15.75 seconds |
| Started | Sep 09 07:08:39 PM UTC 24 |
| Finished | Sep 09 07:08:56 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960312300 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.960312300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/36.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_errs.388525349 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 592007173 ps |
| CPU time | 8.48 seconds |
| Started | Sep 09 07:08:39 PM UTC 24 |
| Finished | Sep 09 07:08:49 PM UTC 24 |
| Peak memory | 251452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388525349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_errs.388525349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/36.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_dai_lock.3665633795 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 1709575997 ps |
| CPU time | 17.75 seconds |
| Started | Sep 09 07:08:39 PM UTC 24 |
| Finished | Sep 09 07:08:58 PM UTC 24 |
| Peak memory | 251580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665633795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_dai_lock.3665633795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/36.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_init_fail.2655873931 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 713586385 ps |
| CPU time | 5 seconds |
| Started | Sep 09 07:08:36 PM UTC 24 |
| Finished | Sep 09 07:08:42 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655873931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.2655873931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/36.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_macro_errs.2364519765 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 1123292552 ps |
| CPU time | 12.23 seconds |
| Started | Sep 09 07:08:39 PM UTC 24 |
| Finished | Sep 09 07:08:53 PM UTC 24 |
| Peak memory | 253332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364519765 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_macro_errs.2364519765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/36.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_key_req.3497126010 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 9886156956 ps |
| CPU time | 19.64 seconds |
| Started | Sep 09 07:08:39 PM UTC 24 |
| Finished | Sep 09 07:09:00 PM UTC 24 |
| Peak memory | 253408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497126010 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_key_req.3497126010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_esc.3937093449 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 1489122740 ps |
| CPU time | 17.79 seconds |
| Started | Sep 09 07:08:39 PM UTC 24 |
| Finished | Sep 09 07:08:58 PM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937093449 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.3937093449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_parallel_lc_req.3349484628 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 857303326 ps |
| CPU time | 20.48 seconds |
| Started | Sep 09 07:08:36 PM UTC 24 |
| Finished | Sep 09 07:08:58 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349484628 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_req.3349484628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_regwen.3429323338 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 1238996659 ps |
| CPU time | 12.25 seconds |
| Started | Sep 09 07:08:39 PM UTC 24 |
| Finished | Sep 09 07:08:53 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429323338 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_regwen.3429323338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/36.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_smoke.1872510047 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 386233522 ps |
| CPU time | 5.32 seconds |
| Started | Sep 09 07:08:36 PM UTC 24 |
| Finished | Sep 09 07:08:42 PM UTC 24 |
| Peak memory | 251612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872510047 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_smoke.1872510047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/36.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_stress_all.3687951391 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 73476541599 ps |
| CPU time | 110.27 seconds |
| Started | Sep 09 07:08:45 PM UTC 24 |
| Finished | Sep 09 07:10:37 PM UTC 24 |
| Peak memory | 284276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687951391 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all.3687951391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/36.otp_ctrl_test_access.1694444434 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 1690985909 ps |
| CPU time | 14.78 seconds |
| Started | Sep 09 07:08:45 PM UTC 24 |
| Finished | Sep 09 07:09:01 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694444434 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_test_access.1694444434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/36.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_alert_test.3719935009 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 175469018 ps |
| CPU time | 3.11 seconds |
| Started | Sep 09 07:08:49 PM UTC 24 |
| Finished | Sep 09 07:08:54 PM UTC 24 |
| Peak memory | 251396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719935009 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_alert_test.3719935009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/37.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_check_fail.425257322 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 186569106 ps |
| CPU time | 4.22 seconds |
| Started | Sep 09 07:08:45 PM UTC 24 |
| Finished | Sep 09 07:08:51 PM UTC 24 |
| Peak memory | 257336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425257322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.425257322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/37.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_errs.1214105944 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 1439401178 ps |
| CPU time | 25.75 seconds |
| Started | Sep 09 07:08:45 PM UTC 24 |
| Finished | Sep 09 07:09:13 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214105944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_errs.1214105944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/37.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_dai_lock.303786132 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 4705156107 ps |
| CPU time | 24.46 seconds |
| Started | Sep 09 07:08:45 PM UTC 24 |
| Finished | Sep 09 07:09:11 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303786132 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_dai_lock.303786132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/37.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_init_fail.2713741541 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 284158241 ps |
| CPU time | 4.52 seconds |
| Started | Sep 09 07:08:45 PM UTC 24 |
| Finished | Sep 09 07:08:51 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2713741541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.2713741541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/37.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_macro_errs.865402232 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 1693189073 ps |
| CPU time | 18.65 seconds |
| Started | Sep 09 07:08:45 PM UTC 24 |
| Finished | Sep 09 07:09:05 PM UTC 24 |
| Peak memory | 255480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865402232 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_macro_errs.865402232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/37.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_key_req.366958076 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 1769302201 ps |
| CPU time | 29 seconds |
| Started | Sep 09 07:08:45 PM UTC 24 |
| Finished | Sep 09 07:09:16 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366958076 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_key_req.366958076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_esc.3805241530 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 124306647 ps |
| CPU time | 5.72 seconds |
| Started | Sep 09 07:08:45 PM UTC 24 |
| Finished | Sep 09 07:08:52 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805241530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.3805241530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_parallel_lc_req.4215903186 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 270513283 ps |
| CPU time | 7.23 seconds |
| Started | Sep 09 07:08:45 PM UTC 24 |
| Finished | Sep 09 07:08:53 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215903186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_req.4215903186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_smoke.3540418136 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 869399151 ps |
| CPU time | 13.85 seconds |
| Started | Sep 09 07:08:45 PM UTC 24 |
| Finished | Sep 09 07:09:00 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540418136 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_smoke.3540418136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/37.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all.3066492308 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 22450897430 ps |
| CPU time | 126.05 seconds |
| Started | Sep 09 07:08:49 PM UTC 24 |
| Finished | Sep 09 07:10:58 PM UTC 24 |
| Peak memory | 267800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066492308 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all.3066492308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_stress_all_with_rand_reset.3718432009 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 8363992468 ps |
| CPU time | 54.45 seconds |
| Started | Sep 09 07:08:49 PM UTC 24 |
| Finished | Sep 09 07:09:46 PM UTC 24 |
| Peak memory | 267952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3718432009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 37.otp_ctrl_stress_all_with_rand_reset.3718432009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/37.otp_ctrl_test_access.226525305 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 10490376053 ps |
| CPU time | 16.52 seconds |
| Started | Sep 09 07:08:49 PM UTC 24 |
| Finished | Sep 09 07:09:07 PM UTC 24 |
| Peak memory | 253748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226525305 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_test_access.226525305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/37.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_alert_test.1782708112 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 186334852 ps |
| CPU time | 1.9 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:09:07 PM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782708112 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_alert_test.1782708112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/38.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_errs.2914584304 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 1243158461 ps |
| CPU time | 18.8 seconds |
| Started | Sep 09 07:08:53 PM UTC 24 |
| Finished | Sep 09 07:09:13 PM UTC 24 |
| Peak memory | 253240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914584304 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_errs.2914584304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/38.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_dai_lock.1631279451 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 772929801 ps |
| CPU time | 10.16 seconds |
| Started | Sep 09 07:08:53 PM UTC 24 |
| Finished | Sep 09 07:09:05 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631279451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_dai_lock.1631279451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/38.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_init_fail.113822109 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 97581834 ps |
| CPU time | 3.83 seconds |
| Started | Sep 09 07:08:50 PM UTC 24 |
| Finished | Sep 09 07:08:55 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113822109 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.113822109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/38.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_macro_errs.1605806919 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 1162014924 ps |
| CPU time | 19.98 seconds |
| Started | Sep 09 07:08:54 PM UTC 24 |
| Finished | Sep 09 07:09:15 PM UTC 24 |
| Peak memory | 257436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605806919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_macro_errs.1605806919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/38.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_key_req.3460146516 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 1070232144 ps |
| CPU time | 7.4 seconds |
| Started | Sep 09 07:08:54 PM UTC 24 |
| Finished | Sep 09 07:09:02 PM UTC 24 |
| Peak memory | 257668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460146516 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_key_req.3460146516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_esc.1201105779 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 407403024 ps |
| CPU time | 5.32 seconds |
| Started | Sep 09 07:08:50 PM UTC 24 |
| Finished | Sep 09 07:08:56 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201105779 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.1201105779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_parallel_lc_req.3657948643 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 9806362149 ps |
| CPU time | 13.1 seconds |
| Started | Sep 09 07:08:50 PM UTC 24 |
| Finished | Sep 09 07:09:04 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657948643 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_req.3657948643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_regwen.1844971756 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 133224065 ps |
| CPU time | 4.72 seconds |
| Started | Sep 09 07:08:54 PM UTC 24 |
| Finished | Sep 09 07:09:00 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844971756 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_regwen.1844971756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/38.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_smoke.3689841805 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 743582040 ps |
| CPU time | 6.86 seconds |
| Started | Sep 09 07:08:49 PM UTC 24 |
| Finished | Sep 09 07:08:58 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689841805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_smoke.3689841805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/38.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_stress_all.1407832989 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 11445684700 ps |
| CPU time | 148.16 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:11:35 PM UTC 24 |
| Peak memory | 257560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407832989 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all.1407832989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/38.otp_ctrl_test_access.914323066 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 2341260254 ps |
| CPU time | 30.53 seconds |
| Started | Sep 09 07:08:54 PM UTC 24 |
| Finished | Sep 09 07:09:26 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914323066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_test_access.914323066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/38.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_alert_test.1167372195 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 121421423 ps |
| CPU time | 2.78 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:09:09 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167372195 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_alert_test.1167372195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/39.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_check_fail.770974934 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 715128115 ps |
| CPU time | 6.43 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:09:12 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770974934 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.770974934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/39.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_errs.3379982500 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 1642026114 ps |
| CPU time | 18.53 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:09:25 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379982500 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_errs.3379982500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/39.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_dai_lock.4106237774 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 12385011067 ps |
| CPU time | 27.04 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:09:33 PM UTC 24 |
| Peak memory | 253492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106237774 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_dai_lock.4106237774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/39.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_init_fail.526122733 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 245950950 ps |
| CPU time | 3.22 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:09:09 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526122733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.526122733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/39.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_macro_errs.630343454 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 3913452086 ps |
| CPU time | 24.38 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:09:31 PM UTC 24 |
| Peak memory | 255736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630343454 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_macro_errs.630343454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/39.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_key_req.3610289023 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 1136107595 ps |
| CPU time | 26.4 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:09:33 PM UTC 24 |
| Peak memory | 253660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610289023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_key_req.3610289023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_esc.2155095220 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 408907383 ps |
| CPU time | 7.66 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:09:14 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155095220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.2155095220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_parallel_lc_req.2612412440 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 681049820 ps |
| CPU time | 15.42 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:09:21 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612412440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_req.2612412440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_regwen.1002122138 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 965703234 ps |
| CPU time | 8.13 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:09:14 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002122138 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_regwen.1002122138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/39.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_smoke.1634113204 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 236441513 ps |
| CPU time | 4.11 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:09:10 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634113204 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_smoke.1634113204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/39.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_stress_all.2542951480 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 27694656807 ps |
| CPU time | 126.71 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:11:14 PM UTC 24 |
| Peak memory | 267740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542951480 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all.2542951480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/39.otp_ctrl_test_access.3935752866 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 1301944788 ps |
| CPU time | 23.04 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:09:29 PM UTC 24 |
| Peak memory | 251376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935752866 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_test_access.3935752866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/39.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_alert_test.3947532883 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 61688322 ps |
| CPU time | 2.72 seconds |
| Started | Sep 09 07:04:41 PM UTC 24 |
| Finished | Sep 09 07:04:45 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947532883 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.3947532883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_background_chks.2808389773 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 2106404055 ps |
| CPU time | 23.54 seconds |
| Started | Sep 09 07:04:35 PM UTC 24 |
| Finished | Sep 09 07:05:00 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808389773 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.2808389773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_check_fail.1917966347 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1093383785 ps |
| CPU time | 21.32 seconds |
| Started | Sep 09 07:04:36 PM UTC 24 |
| Finished | Sep 09 07:04:59 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1917966347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.1917966347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_errs.93711669 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4921156891 ps |
| CPU time | 21.33 seconds |
| Started | Sep 09 07:04:36 PM UTC 24 |
| Finished | Sep 09 07:04:59 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93711669 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.93711669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_dai_lock.254393370 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 10129671739 ps |
| CPU time | 20.8 seconds |
| Started | Sep 09 07:04:36 PM UTC 24 |
| Finished | Sep 09 07:04:58 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254393370 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.254393370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_init_fail.2249973064 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 484324787 ps |
| CPU time | 5.25 seconds |
| Started | Sep 09 07:04:35 PM UTC 24 |
| Finished | Sep 09 07:04:41 PM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249973064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.2249973064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_macro_errs.1781794933 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 270813728 ps |
| CPU time | 4.68 seconds |
| Started | Sep 09 07:04:36 PM UTC 24 |
| Finished | Sep 09 07:04:42 PM UTC 24 |
| Peak memory | 251384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781794933 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.1781794933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_parallel_lc_req.1792968355 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 940193118 ps |
| CPU time | 25 seconds |
| Started | Sep 09 07:04:36 PM UTC 24 |
| Finished | Sep 09 07:05:03 PM UTC 24 |
| Peak memory | 256936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792968355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.1792968355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_regwen.144201769 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 142775072 ps |
| CPU time | 4.96 seconds |
| Started | Sep 09 07:04:37 PM UTC 24 |
| Finished | Sep 09 07:04:43 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144201769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.144201769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_sec_cm.3618767440 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 12056981241 ps |
| CPU time | 193.96 seconds |
| Started | Sep 09 07:04:39 PM UTC 24 |
| Finished | Sep 09 07:07:56 PM UTC 24 |
| Peak memory | 287888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618767440 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.3618767440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_smoke.1382338769 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 286842433 ps |
| CPU time | 5.55 seconds |
| Started | Sep 09 07:04:35 PM UTC 24 |
| Finished | Sep 09 07:04:41 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382338769 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.1382338769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/4.otp_ctrl_test_access.3627945741 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 898538648 ps |
| CPU time | 11.91 seconds |
| Started | Sep 09 07:04:39 PM UTC 24 |
| Finished | Sep 09 07:04:52 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627945741 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.3627945741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/4.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_alert_test.77408003 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 892183745 ps |
| CPU time | 2.72 seconds |
| Started | Sep 09 07:09:12 PM UTC 24 |
| Finished | Sep 09 07:09:15 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77408003 -assert nopostproc +UVM_TESTNAME=otp _ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_alert_test.77408003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/40.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_errs.2422026112 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 11794934601 ps |
| CPU time | 33.99 seconds |
| Started | Sep 09 07:09:08 PM UTC 24 |
| Finished | Sep 09 07:09:43 PM UTC 24 |
| Peak memory | 251324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422026112 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_errs.2422026112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/40.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_dai_lock.851793867 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 3029356740 ps |
| CPU time | 35.84 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:09:43 PM UTC 24 |
| Peak memory | 251392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851793867 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_dai_lock.851793867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/40.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_init_fail.1349212374 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 1535643632 ps |
| CPU time | 5.3 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:09:12 PM UTC 24 |
| Peak memory | 253272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349212374 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.1349212374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/40.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_macro_errs.3852960099 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 1796502813 ps |
| CPU time | 41.95 seconds |
| Started | Sep 09 07:09:08 PM UTC 24 |
| Finished | Sep 09 07:09:51 PM UTC 24 |
| Peak memory | 257524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852960099 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_macro_errs.3852960099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/40.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_key_req.3493083777 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 2481134439 ps |
| CPU time | 27.2 seconds |
| Started | Sep 09 07:09:08 PM UTC 24 |
| Finished | Sep 09 07:09:36 PM UTC 24 |
| Peak memory | 251576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493083777 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_key_req.3493083777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_esc.173948316 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 251441487 ps |
| CPU time | 10.18 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:09:17 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173948316 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.173948316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_parallel_lc_req.4054466320 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 618157171 ps |
| CPU time | 9.49 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:09:16 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054466320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_req.4054466320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_regwen.1256179444 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 197445916 ps |
| CPU time | 5.83 seconds |
| Started | Sep 09 07:09:08 PM UTC 24 |
| Finished | Sep 09 07:09:15 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256179444 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_regwen.1256179444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/40.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_smoke.1236293081 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 1584467701 ps |
| CPU time | 8.56 seconds |
| Started | Sep 09 07:09:05 PM UTC 24 |
| Finished | Sep 09 07:09:15 PM UTC 24 |
| Peak memory | 257564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236293081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_smoke.1236293081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/40.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/40.otp_ctrl_test_access.780920733 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 4002301514 ps |
| CPU time | 24.02 seconds |
| Started | Sep 09 07:09:10 PM UTC 24 |
| Finished | Sep 09 07:09:35 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780920733 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_test_access.780920733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/40.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_alert_test.1466309315 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 816148553 ps |
| CPU time | 3.16 seconds |
| Started | Sep 09 07:09:19 PM UTC 24 |
| Finished | Sep 09 07:09:24 PM UTC 24 |
| Peak memory | 251416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466309315 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_alert_test.1466309315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/41.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_check_fail.3938984320 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 11594569870 ps |
| CPU time | 25.83 seconds |
| Started | Sep 09 07:09:19 PM UTC 24 |
| Finished | Sep 09 07:09:46 PM UTC 24 |
| Peak memory | 257944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938984320 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.3938984320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/41.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_errs.1210996666 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 914747342 ps |
| CPU time | 22.21 seconds |
| Started | Sep 09 07:09:14 PM UTC 24 |
| Finished | Sep 09 07:09:37 PM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210996666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_errs.1210996666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/41.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_dai_lock.3484098440 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 13368418407 ps |
| CPU time | 33.07 seconds |
| Started | Sep 09 07:09:14 PM UTC 24 |
| Finished | Sep 09 07:09:48 PM UTC 24 |
| Peak memory | 253412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484098440 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_dai_lock.3484098440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/41.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_init_fail.4231700371 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 81468541 ps |
| CPU time | 4.4 seconds |
| Started | Sep 09 07:09:14 PM UTC 24 |
| Finished | Sep 09 07:09:19 PM UTC 24 |
| Peak memory | 251272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231700371 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.4231700371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/41.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_macro_errs.2171336008 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 485715495 ps |
| CPU time | 5.79 seconds |
| Started | Sep 09 07:09:19 PM UTC 24 |
| Finished | Sep 09 07:09:26 PM UTC 24 |
| Peak memory | 257500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171336008 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_macro_errs.2171336008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/41.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_key_req.554045002 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 1132522866 ps |
| CPU time | 23.02 seconds |
| Started | Sep 09 07:09:19 PM UTC 24 |
| Finished | Sep 09 07:09:43 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554045002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_key_req.554045002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_esc.4165960267 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 454072022 ps |
| CPU time | 12.7 seconds |
| Started | Sep 09 07:09:14 PM UTC 24 |
| Finished | Sep 09 07:09:28 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165960267 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.4165960267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_parallel_lc_req.3515877833 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 459441684 ps |
| CPU time | 6.15 seconds |
| Started | Sep 09 07:09:14 PM UTC 24 |
| Finished | Sep 09 07:09:21 PM UTC 24 |
| Peak memory | 257624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515877833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_req.3515877833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_regwen.279038326 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 319306772 ps |
| CPU time | 12.46 seconds |
| Started | Sep 09 07:09:19 PM UTC 24 |
| Finished | Sep 09 07:09:33 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279038326 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_regwen.279038326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/41.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_smoke.2652746938 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 1342648113 ps |
| CPU time | 7.77 seconds |
| Started | Sep 09 07:09:12 PM UTC 24 |
| Finished | Sep 09 07:09:20 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652746938 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_smoke.2652746938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/41.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all.3315857711 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 20572701483 ps |
| CPU time | 76.23 seconds |
| Started | Sep 09 07:09:19 PM UTC 24 |
| Finished | Sep 09 07:10:37 PM UTC 24 |
| Peak memory | 257724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315857711 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all.3315857711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_stress_all_with_rand_reset.1813311895 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 6319572029 ps |
| CPU time | 54.73 seconds |
| Started | Sep 09 07:09:19 PM UTC 24 |
| Finished | Sep 09 07:10:16 PM UTC 24 |
| Peak memory | 257556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1813311895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 41.otp_ctrl_stress_all_with_rand_reset.1813311895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/41.otp_ctrl_test_access.802370574 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 276574847 ps |
| CPU time | 5.51 seconds |
| Started | Sep 09 07:09:19 PM UTC 24 |
| Finished | Sep 09 07:09:26 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802370574 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_test_access.802370574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/41.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_alert_test.3478267249 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 147571926 ps |
| CPU time | 1.95 seconds |
| Started | Sep 09 07:09:32 PM UTC 24 |
| Finished | Sep 09 07:09:35 PM UTC 24 |
| Peak memory | 251212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478267249 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_alert_test.3478267249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/42.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_check_fail.369943941 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 2400363148 ps |
| CPU time | 20.72 seconds |
| Started | Sep 09 07:09:26 PM UTC 24 |
| Finished | Sep 09 07:09:48 PM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369943941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.369943941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/42.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_errs.70464009 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 284915363 ps |
| CPU time | 15.29 seconds |
| Started | Sep 09 07:09:26 PM UTC 24 |
| Finished | Sep 09 07:09:42 PM UTC 24 |
| Peak memory | 251448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70464009 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_errs.70464009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/42.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_dai_lock.1703072972 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 244445358 ps |
| CPU time | 7.77 seconds |
| Started | Sep 09 07:09:26 PM UTC 24 |
| Finished | Sep 09 07:09:35 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703072972 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_dai_lock.1703072972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/42.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_init_fail.567666455 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 2101906226 ps |
| CPU time | 5.25 seconds |
| Started | Sep 09 07:09:20 PM UTC 24 |
| Finished | Sep 09 07:09:26 PM UTC 24 |
| Peak memory | 251008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567666455 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.567666455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/42.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_macro_errs.84824451 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 411488220 ps |
| CPU time | 10.17 seconds |
| Started | Sep 09 07:09:26 PM UTC 24 |
| Finished | Sep 09 07:09:37 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84824451 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_macro_errs.84824451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/42.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_key_req.3657977987 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 1272968301 ps |
| CPU time | 28.82 seconds |
| Started | Sep 09 07:09:26 PM UTC 24 |
| Finished | Sep 09 07:09:56 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657977987 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_key_req.3657977987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_esc.2711098256 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 296602941 ps |
| CPU time | 7.81 seconds |
| Started | Sep 09 07:09:26 PM UTC 24 |
| Finished | Sep 09 07:09:35 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711098256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.2711098256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_parallel_lc_req.1163541369 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 698069178 ps |
| CPU time | 18.23 seconds |
| Started | Sep 09 07:09:20 PM UTC 24 |
| Finished | Sep 09 07:09:39 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163541369 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_req.1163541369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_regwen.2533716079 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 1085732190 ps |
| CPU time | 11.73 seconds |
| Started | Sep 09 07:09:26 PM UTC 24 |
| Finished | Sep 09 07:09:39 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533716079 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_regwen.2533716079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/42.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_smoke.1553587817 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 1801367377 ps |
| CPU time | 12.42 seconds |
| Started | Sep 09 07:09:19 PM UTC 24 |
| Finished | Sep 09 07:09:33 PM UTC 24 |
| Peak memory | 257692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553587817 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_smoke.1553587817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/42.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_stress_all.1671142094 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 46817524829 ps |
| CPU time | 142.89 seconds |
| Started | Sep 09 07:09:32 PM UTC 24 |
| Finished | Sep 09 07:11:57 PM UTC 24 |
| Peak memory | 267712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671142094 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all.1671142094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/42.otp_ctrl_test_access.3724974881 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 2980231574 ps |
| CPU time | 12.62 seconds |
| Started | Sep 09 07:09:26 PM UTC 24 |
| Finished | Sep 09 07:09:40 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724974881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_test_access.3724974881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/42.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_alert_test.2479744120 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 44283809 ps |
| CPU time | 1.79 seconds |
| Started | Sep 09 07:09:36 PM UTC 24 |
| Finished | Sep 09 07:09:38 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479744120 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_alert_test.2479744120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/43.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_check_fail.4258074013 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 924852368 ps |
| CPU time | 18.45 seconds |
| Started | Sep 09 07:09:35 PM UTC 24 |
| Finished | Sep 09 07:09:55 PM UTC 24 |
| Peak memory | 257460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4258074013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.4258074013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/43.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_errs.1424249541 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 588740002 ps |
| CPU time | 17.21 seconds |
| Started | Sep 09 07:09:32 PM UTC 24 |
| Finished | Sep 09 07:09:51 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424249541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_errs.1424249541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/43.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_dai_lock.502387050 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 1900042599 ps |
| CPU time | 21.93 seconds |
| Started | Sep 09 07:09:32 PM UTC 24 |
| Finished | Sep 09 07:09:56 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502387050 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_dai_lock.502387050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/43.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_init_fail.2320263096 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 535203000 ps |
| CPU time | 4.44 seconds |
| Started | Sep 09 07:09:32 PM UTC 24 |
| Finished | Sep 09 07:09:38 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320263096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.2320263096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/43.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_macro_errs.3856686277 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 739790195 ps |
| CPU time | 10.99 seconds |
| Started | Sep 09 07:09:35 PM UTC 24 |
| Finished | Sep 09 07:09:47 PM UTC 24 |
| Peak memory | 253364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856686277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_macro_errs.3856686277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/43.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_key_req.3032250092 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 489025064 ps |
| CPU time | 14.47 seconds |
| Started | Sep 09 07:09:35 PM UTC 24 |
| Finished | Sep 09 07:09:51 PM UTC 24 |
| Peak memory | 251612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032250092 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_key_req.3032250092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_esc.3673058059 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 319293748 ps |
| CPU time | 5.67 seconds |
| Started | Sep 09 07:09:32 PM UTC 24 |
| Finished | Sep 09 07:09:39 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673058059 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.3673058059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_parallel_lc_req.3388790064 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 595394234 ps |
| CPU time | 10.79 seconds |
| Started | Sep 09 07:09:32 PM UTC 24 |
| Finished | Sep 09 07:09:44 PM UTC 24 |
| Peak memory | 251108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388790064 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_req.3388790064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_regwen.3836283181 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 4180250321 ps |
| CPU time | 11.95 seconds |
| Started | Sep 09 07:09:35 PM UTC 24 |
| Finished | Sep 09 07:09:48 PM UTC 24 |
| Peak memory | 251336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836283181 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_regwen.3836283181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/43.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_smoke.4282085577 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 2135954170 ps |
| CPU time | 5.73 seconds |
| Started | Sep 09 07:09:32 PM UTC 24 |
| Finished | Sep 09 07:09:39 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282085577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_smoke.4282085577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/43.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all.3160608815 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 35143829260 ps |
| CPU time | 168.49 seconds |
| Started | Sep 09 07:09:35 PM UTC 24 |
| Finished | Sep 09 07:12:27 PM UTC 24 |
| Peak memory | 274012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160608815 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all.3160608815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_stress_all_with_rand_reset.461096962 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 19205478318 ps |
| CPU time | 106.49 seconds |
| Started | Sep 09 07:09:35 PM UTC 24 |
| Finished | Sep 09 07:11:24 PM UTC 24 |
| Peak memory | 267864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=461096962 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.461096962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/43.otp_ctrl_test_access.2279601422 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 1600782261 ps |
| CPU time | 28 seconds |
| Started | Sep 09 07:09:35 PM UTC 24 |
| Finished | Sep 09 07:10:05 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279601422 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_test_access.2279601422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/43.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_alert_test.4148128822 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 71178420 ps |
| CPU time | 1.66 seconds |
| Started | Sep 09 07:09:42 PM UTC 24 |
| Finished | Sep 09 07:09:45 PM UTC 24 |
| Peak memory | 251144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148128822 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_alert_test.4148128822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/44.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_check_fail.3842677941 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 2984543186 ps |
| CPU time | 27.09 seconds |
| Started | Sep 09 07:09:42 PM UTC 24 |
| Finished | Sep 09 07:10:11 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842677941 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.3842677941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/44.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_errs.4011295457 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 548612056 ps |
| CPU time | 6.99 seconds |
| Started | Sep 09 07:09:42 PM UTC 24 |
| Finished | Sep 09 07:09:50 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011295457 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_errs.4011295457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/44.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_dai_lock.2080439220 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 303429873 ps |
| CPU time | 9.25 seconds |
| Started | Sep 09 07:09:42 PM UTC 24 |
| Finished | Sep 09 07:09:53 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080439220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_dai_lock.2080439220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/44.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_init_fail.778660061 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 1559680501 ps |
| CPU time | 4.01 seconds |
| Started | Sep 09 07:09:42 PM UTC 24 |
| Finished | Sep 09 07:09:47 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778660061 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.778660061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/44.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_macro_errs.3621297040 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 747396118 ps |
| CPU time | 13.48 seconds |
| Started | Sep 09 07:09:42 PM UTC 24 |
| Finished | Sep 09 07:09:57 PM UTC 24 |
| Peak memory | 253372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621297040 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_macro_errs.3621297040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/44.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_key_req.1919798705 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 10088761172 ps |
| CPU time | 37.29 seconds |
| Started | Sep 09 07:09:42 PM UTC 24 |
| Finished | Sep 09 07:10:21 PM UTC 24 |
| Peak memory | 257500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919798705 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_key_req.1919798705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_parallel_lc_req.2331948633 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 3592909043 ps |
| CPU time | 13.15 seconds |
| Started | Sep 09 07:09:42 PM UTC 24 |
| Finished | Sep 09 07:09:56 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331948633 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_req.2331948633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_regwen.3636936666 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 324796542 ps |
| CPU time | 5.69 seconds |
| Started | Sep 09 07:09:42 PM UTC 24 |
| Finished | Sep 09 07:09:49 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636936666 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_regwen.3636936666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/44.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_smoke.50800975 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 518901761 ps |
| CPU time | 4.31 seconds |
| Started | Sep 09 07:09:42 PM UTC 24 |
| Finished | Sep 09 07:09:47 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50800975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_smoke.50800975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/44.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_stress_all.384153362 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 8453307124 ps |
| CPU time | 58.97 seconds |
| Started | Sep 09 07:09:42 PM UTC 24 |
| Finished | Sep 09 07:10:43 PM UTC 24 |
| Peak memory | 257560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384153362 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all.384153362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/44.otp_ctrl_test_access.4008110100 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 3346284804 ps |
| CPU time | 22.9 seconds |
| Started | Sep 09 07:09:42 PM UTC 24 |
| Finished | Sep 09 07:10:07 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008110100 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_test_access.4008110100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/44.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_alert_test.4121437406 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 219617299 ps |
| CPU time | 2.7 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:09:58 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121437406 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_alert_test.4121437406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/45.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_check_fail.1793990211 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 1099077883 ps |
| CPU time | 9.78 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:10:05 PM UTC 24 |
| Peak memory | 251644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793990211 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.1793990211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/45.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_errs.4079768466 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 2488822174 ps |
| CPU time | 16.6 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:10:12 PM UTC 24 |
| Peak memory | 251256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079768466 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_errs.4079768466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/45.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_dai_lock.3019299056 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 978758601 ps |
| CPU time | 12.56 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:10:08 PM UTC 24 |
| Peak memory | 251644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019299056 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_dai_lock.3019299056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/45.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_init_fail.447974654 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 274835218 ps |
| CPU time | 4.72 seconds |
| Started | Sep 09 07:09:43 PM UTC 24 |
| Finished | Sep 09 07:09:49 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447974654 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.447974654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/45.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_macro_errs.1305112489 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 2206724829 ps |
| CPU time | 6.2 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:10:01 PM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305112489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_macro_errs.1305112489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/45.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_key_req.190577060 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 29312262658 ps |
| CPU time | 57.74 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:10:53 PM UTC 24 |
| Peak memory | 257520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190577060 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_key_req.190577060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_esc.3625937740 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 5910973687 ps |
| CPU time | 9 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:10:04 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625937740 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.3625937740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_parallel_lc_req.3776492533 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 1308397352 ps |
| CPU time | 16.05 seconds |
| Started | Sep 09 07:09:43 PM UTC 24 |
| Finished | Sep 09 07:10:00 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776492533 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_req.3776492533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_regwen.2024279776 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 582421443 ps |
| CPU time | 11.82 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:10:07 PM UTC 24 |
| Peak memory | 251540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024279776 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_regwen.2024279776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/45.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_smoke.4265015355 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 304948701 ps |
| CPU time | 5.52 seconds |
| Started | Sep 09 07:09:42 PM UTC 24 |
| Finished | Sep 09 07:09:49 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265015355 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_smoke.4265015355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/45.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_stress_all_with_rand_reset.379610246 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 1188654025 ps |
| CPU time | 45.06 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:10:41 PM UTC 24 |
| Peak memory | 257652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=379610246 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.379610246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/45.otp_ctrl_test_access.4265023795 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 28796382812 ps |
| CPU time | 47.56 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:10:43 PM UTC 24 |
| Peak memory | 251700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265023795 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_test_access.4265023795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/45.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_alert_test.1077314882 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 94234728 ps |
| CPU time | 2.36 seconds |
| Started | Sep 09 07:09:55 PM UTC 24 |
| Finished | Sep 09 07:09:58 PM UTC 24 |
| Peak memory | 251108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077314882 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_alert_test.1077314882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/46.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_check_fail.2929434775 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 1113212967 ps |
| CPU time | 12.95 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:10:09 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929434775 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.2929434775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/46.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_errs.743936960 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 20642097358 ps |
| CPU time | 39.74 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:10:36 PM UTC 24 |
| Peak memory | 261628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743936960 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_errs.743936960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/46.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_dai_lock.3363880855 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 143486483 ps |
| CPU time | 4.9 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:10:00 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363880855 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_dai_lock.3363880855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/46.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_init_fail.576328963 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 1970071504 ps |
| CPU time | 4.11 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:10:00 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576328963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.576328963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/46.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_macro_errs.1172698604 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 676616079 ps |
| CPU time | 6.46 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:10:02 PM UTC 24 |
| Peak memory | 253272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172698604 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_macro_errs.1172698604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/46.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_key_req.3553936930 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 615022025 ps |
| CPU time | 10.06 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:10:06 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553936930 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_key_req.3553936930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_esc.664782226 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 3074354320 ps |
| CPU time | 9.01 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:10:05 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664782226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.664782226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_parallel_lc_req.1722598902 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 2550164182 ps |
| CPU time | 20.83 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:10:16 PM UTC 24 |
| Peak memory | 257432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722598902 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_req.1722598902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_regwen.2150699629 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 230595874 ps |
| CPU time | 10.46 seconds |
| Started | Sep 09 07:09:55 PM UTC 24 |
| Finished | Sep 09 07:10:06 PM UTC 24 |
| Peak memory | 251268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150699629 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_regwen.2150699629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/46.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_smoke.1067243931 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 329650326 ps |
| CPU time | 8.07 seconds |
| Started | Sep 09 07:09:54 PM UTC 24 |
| Finished | Sep 09 07:10:04 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067243931 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_smoke.1067243931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/46.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all.2606038339 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 27649737315 ps |
| CPU time | 164.68 seconds |
| Started | Sep 09 07:09:55 PM UTC 24 |
| Finished | Sep 09 07:12:42 PM UTC 24 |
| Peak memory | 284272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606038339 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all.2606038339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_stress_all_with_rand_reset.3057914785 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 2381556165 ps |
| CPU time | 67.25 seconds |
| Started | Sep 09 07:09:55 PM UTC 24 |
| Finished | Sep 09 07:11:04 PM UTC 24 |
| Peak memory | 257648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3057914785 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 46.otp_ctrl_stress_all_with_rand_reset.3057914785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/46.otp_ctrl_test_access.3243904023 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 1476881729 ps |
| CPU time | 20.68 seconds |
| Started | Sep 09 07:09:55 PM UTC 24 |
| Finished | Sep 09 07:10:17 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243904023 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_test_access.3243904023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/46.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_alert_test.2304045751 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 109222545 ps |
| CPU time | 2.91 seconds |
| Started | Sep 09 07:10:03 PM UTC 24 |
| Finished | Sep 09 07:10:07 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304045751 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_alert_test.2304045751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/47.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_check_fail.1093800363 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 1504052819 ps |
| CPU time | 26.09 seconds |
| Started | Sep 09 07:09:58 PM UTC 24 |
| Finished | Sep 09 07:10:25 PM UTC 24 |
| Peak memory | 253628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093800363 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.1093800363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/47.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_errs.1641365596 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 4420330677 ps |
| CPU time | 31.61 seconds |
| Started | Sep 09 07:09:58 PM UTC 24 |
| Finished | Sep 09 07:10:31 PM UTC 24 |
| Peak memory | 257464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641365596 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_errs.1641365596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/47.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_dai_lock.1684497692 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 5007772538 ps |
| CPU time | 28.12 seconds |
| Started | Sep 09 07:09:58 PM UTC 24 |
| Finished | Sep 09 07:10:27 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684497692 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_dai_lock.1684497692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/47.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_init_fail.4137070359 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 124378108 ps |
| CPU time | 4.71 seconds |
| Started | Sep 09 07:09:58 PM UTC 24 |
| Finished | Sep 09 07:10:04 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137070359 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.4137070359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/47.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_macro_errs.1861227051 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 2424558452 ps |
| CPU time | 31.45 seconds |
| Started | Sep 09 07:09:59 PM UTC 24 |
| Finished | Sep 09 07:10:32 PM UTC 24 |
| Peak memory | 257588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861227051 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_macro_errs.1861227051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/47.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_key_req.2256864166 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 772875533 ps |
| CPU time | 15.2 seconds |
| Started | Sep 09 07:09:59 PM UTC 24 |
| Finished | Sep 09 07:10:16 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256864166 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_key_req.2256864166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_esc.32014342 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 3584625122 ps |
| CPU time | 17.36 seconds |
| Started | Sep 09 07:09:58 PM UTC 24 |
| Finished | Sep 09 07:10:16 PM UTC 24 |
| Peak memory | 251220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32014342 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.32014342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_parallel_lc_req.2634077197 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 581141326 ps |
| CPU time | 17.25 seconds |
| Started | Sep 09 07:09:58 PM UTC 24 |
| Finished | Sep 09 07:10:16 PM UTC 24 |
| Peak memory | 257688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634077197 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_req.2634077197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_regwen.3707814613 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 363981805 ps |
| CPU time | 6.39 seconds |
| Started | Sep 09 07:10:01 PM UTC 24 |
| Finished | Sep 09 07:10:09 PM UTC 24 |
| Peak memory | 251280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707814613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_regwen.3707814613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/47.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_smoke.1755373357 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 356032421 ps |
| CPU time | 6.31 seconds |
| Started | Sep 09 07:09:55 PM UTC 24 |
| Finished | Sep 09 07:10:02 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755373357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_smoke.1755373357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/47.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_stress_all.1156883289 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 12856530097 ps |
| CPU time | 142.96 seconds |
| Started | Sep 09 07:10:03 PM UTC 24 |
| Finished | Sep 09 07:12:29 PM UTC 24 |
| Peak memory | 267868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156883289 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all.1156883289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/47.otp_ctrl_test_access.865132179 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 1241763824 ps |
| CPU time | 17.84 seconds |
| Started | Sep 09 07:10:01 PM UTC 24 |
| Finished | Sep 09 07:10:21 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865132179 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_test_access.865132179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/47.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_alert_test.2408145770 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 233939744 ps |
| CPU time | 4.67 seconds |
| Started | Sep 09 07:10:11 PM UTC 24 |
| Finished | Sep 09 07:10:17 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408145770 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_alert_test.2408145770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/48.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_check_fail.1205819379 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 318848426 ps |
| CPU time | 6.9 seconds |
| Started | Sep 09 07:10:09 PM UTC 24 |
| Finished | Sep 09 07:10:17 PM UTC 24 |
| Peak memory | 257460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205819379 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.1205819379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/48.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_errs.927037428 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 4701073779 ps |
| CPU time | 24.35 seconds |
| Started | Sep 09 07:10:09 PM UTC 24 |
| Finished | Sep 09 07:10:35 PM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927037428 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_errs.927037428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/48.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_dai_lock.3809327086 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 4352614920 ps |
| CPU time | 22.18 seconds |
| Started | Sep 09 07:10:05 PM UTC 24 |
| Finished | Sep 09 07:10:30 PM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809327086 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_dai_lock.3809327086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/48.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_init_fail.1759719164 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 212170568 ps |
| CPU time | 3.64 seconds |
| Started | Sep 09 07:10:05 PM UTC 24 |
| Finished | Sep 09 07:10:11 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759719164 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.1759719164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/48.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_macro_errs.3830863911 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 535996868 ps |
| CPU time | 8.77 seconds |
| Started | Sep 09 07:10:09 PM UTC 24 |
| Finished | Sep 09 07:10:19 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830863911 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_macro_errs.3830863911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/48.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_key_req.2015954635 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 309246725 ps |
| CPU time | 8.7 seconds |
| Started | Sep 09 07:10:09 PM UTC 24 |
| Finished | Sep 09 07:10:19 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015954635 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_key_req.2015954635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_esc.977758501 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 172391841 ps |
| CPU time | 6.76 seconds |
| Started | Sep 09 07:10:05 PM UTC 24 |
| Finished | Sep 09 07:10:14 PM UTC 24 |
| Peak memory | 251168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977758501 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.977758501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_parallel_lc_req.138733697 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 461919472 ps |
| CPU time | 13.29 seconds |
| Started | Sep 09 07:10:05 PM UTC 24 |
| Finished | Sep 09 07:10:20 PM UTC 24 |
| Peak memory | 251008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138733697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_req.138733697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_regwen.1957454096 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 264708436 ps |
| CPU time | 7.78 seconds |
| Started | Sep 09 07:10:09 PM UTC 24 |
| Finished | Sep 09 07:10:18 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957454096 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_regwen.1957454096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/48.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_smoke.1422851212 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 1088042994 ps |
| CPU time | 8.38 seconds |
| Started | Sep 09 07:10:03 PM UTC 24 |
| Finished | Sep 09 07:10:13 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422851212 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_smoke.1422851212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/48.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all.3152508830 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 54370483268 ps |
| CPU time | 190.31 seconds |
| Started | Sep 09 07:10:11 PM UTC 24 |
| Finished | Sep 09 07:13:25 PM UTC 24 |
| Peak memory | 271804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152508830 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all.3152508830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_stress_all_with_rand_reset.407184081 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 6354076127 ps |
| CPU time | 98.65 seconds |
| Started | Sep 09 07:10:09 PM UTC 24 |
| Finished | Sep 09 07:11:50 PM UTC 24 |
| Peak memory | 267864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=407184081 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.407184081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/48.otp_ctrl_test_access.3054120498 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 1112668363 ps |
| CPU time | 21.97 seconds |
| Started | Sep 09 07:10:09 PM UTC 24 |
| Finished | Sep 09 07:10:32 PM UTC 24 |
| Peak memory | 251312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054120498 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_test_access.3054120498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/48.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_alert_test.703243426 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 109580120 ps |
| CPU time | 2.68 seconds |
| Started | Sep 09 07:10:21 PM UTC 24 |
| Finished | Sep 09 07:10:25 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703243426 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_alert_test.703243426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/49.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_errs.205889299 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 3919660984 ps |
| CPU time | 15.53 seconds |
| Started | Sep 09 07:10:20 PM UTC 24 |
| Finished | Sep 09 07:10:37 PM UTC 24 |
| Peak memory | 251360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205889299 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_errs.205889299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/49.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_dai_lock.3274130458 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 1422903402 ps |
| CPU time | 8.95 seconds |
| Started | Sep 09 07:10:14 PM UTC 24 |
| Finished | Sep 09 07:10:24 PM UTC 24 |
| Peak memory | 251320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274130458 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_dai_lock.3274130458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/49.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_init_fail.1340727392 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 272464370 ps |
| CPU time | 5.49 seconds |
| Started | Sep 09 07:10:12 PM UTC 24 |
| Finished | Sep 09 07:10:18 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340727392 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.1340727392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/49.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_macro_errs.2970132813 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 582682555 ps |
| CPU time | 7.84 seconds |
| Started | Sep 09 07:10:20 PM UTC 24 |
| Finished | Sep 09 07:10:30 PM UTC 24 |
| Peak memory | 253340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970132813 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_macro_errs.2970132813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/49.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_key_req.2181535130 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 2017049355 ps |
| CPU time | 17.5 seconds |
| Started | Sep 09 07:10:21 PM UTC 24 |
| Finished | Sep 09 07:10:39 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181535130 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_key_req.2181535130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_esc.998494858 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 883733963 ps |
| CPU time | 20.24 seconds |
| Started | Sep 09 07:10:14 PM UTC 24 |
| Finished | Sep 09 07:10:35 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998494858 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.998494858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_parallel_lc_req.3418074576 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 746145283 ps |
| CPU time | 22.05 seconds |
| Started | Sep 09 07:10:14 PM UTC 24 |
| Finished | Sep 09 07:10:37 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418074576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_req.3418074576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_regwen.2913848078 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 1052847680 ps |
| CPU time | 12.06 seconds |
| Started | Sep 09 07:10:21 PM UTC 24 |
| Finished | Sep 09 07:10:34 PM UTC 24 |
| Peak memory | 251536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913848078 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_regwen.2913848078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/49.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_smoke.2003344935 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 570321239 ps |
| CPU time | 6.29 seconds |
| Started | Sep 09 07:10:11 PM UTC 24 |
| Finished | Sep 09 07:10:19 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003344935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_smoke.2003344935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/49.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all.704493512 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 2097032604 ps |
| CPU time | 56.49 seconds |
| Started | Sep 09 07:10:21 PM UTC 24 |
| Finished | Sep 09 07:11:19 PM UTC 24 |
| Peak memory | 253308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704493512 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all.704493512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_stress_all_with_rand_reset.3115493025 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 788165992 ps |
| CPU time | 37.42 seconds |
| Started | Sep 09 07:10:21 PM UTC 24 |
| Finished | Sep 09 07:11:00 PM UTC 24 |
| Peak memory | 257584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3115493025 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 49.otp_ctrl_stress_all_with_rand_reset.3115493025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/49.otp_ctrl_test_access.1268890399 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 140896942 ps |
| CPU time | 5.27 seconds |
| Started | Sep 09 07:10:21 PM UTC 24 |
| Finished | Sep 09 07:10:27 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268890399 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_test_access.1268890399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/49.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_alert_test.2334195598 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 238481294 ps |
| CPU time | 3.67 seconds |
| Started | Sep 09 07:04:46 PM UTC 24 |
| Finished | Sep 09 07:04:50 PM UTC 24 |
| Peak memory | 251396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334195598 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.2334195598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_background_chks.1887990954 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 1873516529 ps |
| CPU time | 24.33 seconds |
| Started | Sep 09 07:04:41 PM UTC 24 |
| Finished | Sep 09 07:05:07 PM UTC 24 |
| Peak memory | 251640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887990954 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.1887990954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_check_fail.1220049334 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 714413845 ps |
| CPU time | 18.07 seconds |
| Started | Sep 09 07:04:44 PM UTC 24 |
| Finished | Sep 09 07:05:03 PM UTC 24 |
| Peak memory | 253340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220049334 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.1220049334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_errs.1279079576 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 346419167 ps |
| CPU time | 21.05 seconds |
| Started | Sep 09 07:04:44 PM UTC 24 |
| Finished | Sep 09 07:05:06 PM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279079576 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.1279079576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_dai_lock.1362601536 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 1353955191 ps |
| CPU time | 21.49 seconds |
| Started | Sep 09 07:04:44 PM UTC 24 |
| Finished | Sep 09 07:05:07 PM UTC 24 |
| Peak memory | 251388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362601536 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.1362601536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_init_fail.1618063071 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 107242970 ps |
| CPU time | 3.29 seconds |
| Started | Sep 09 07:04:41 PM UTC 24 |
| Finished | Sep 09 07:04:45 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618063071 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.1618063071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_macro_errs.3858434541 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 3530424237 ps |
| CPU time | 29.37 seconds |
| Started | Sep 09 07:04:44 PM UTC 24 |
| Finished | Sep 09 07:05:15 PM UTC 24 |
| Peak memory | 255544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858434541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.3858434541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_esc.3943066526 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 16930561754 ps |
| CPU time | 42.19 seconds |
| Started | Sep 09 07:04:44 PM UTC 24 |
| Finished | Sep 09 07:05:28 PM UTC 24 |
| Peak memory | 251188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943066526 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.3943066526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_parallel_lc_req.4043477993 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 1951671943 ps |
| CPU time | 21.48 seconds |
| Started | Sep 09 07:04:44 PM UTC 24 |
| Finished | Sep 09 07:05:06 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043477993 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.4043477993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_regwen.3240931695 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 834715032 ps |
| CPU time | 7.9 seconds |
| Started | Sep 09 07:04:44 PM UTC 24 |
| Finished | Sep 09 07:04:53 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240931695 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.3240931695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_smoke.3912260240 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 765302788 ps |
| CPU time | 5.65 seconds |
| Started | Sep 09 07:04:41 PM UTC 24 |
| Finished | Sep 09 07:04:48 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912260240 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.3912260240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_stress_all_with_rand_reset.636817622 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2004417697 ps |
| CPU time | 79.85 seconds |
| Started | Sep 09 07:04:46 PM UTC 24 |
| Finished | Sep 09 07:06:07 PM UTC 24 |
| Peak memory | 269904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=636817622 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.636817622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/5.otp_ctrl_test_access.2582329708 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 817374278 ps |
| CPU time | 12.19 seconds |
| Started | Sep 09 07:04:44 PM UTC 24 |
| Finished | Sep 09 07:04:58 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582329708 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.2582329708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/5.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_init_fail.1073588686 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 415516294 ps |
| CPU time | 5.69 seconds |
| Started | Sep 09 07:10:21 PM UTC 24 |
| Finished | Sep 09 07:10:28 PM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073588686 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.1073588686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/50.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_parallel_lc_esc.308442397 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 3093182929 ps |
| CPU time | 18.53 seconds |
| Started | Sep 09 07:10:21 PM UTC 24 |
| Finished | Sep 09 07:10:41 PM UTC 24 |
| Peak memory | 250948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308442397 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.308442397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/50.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/50.otp_ctrl_stress_all_with_rand_reset.1001934594 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 100527046240 ps |
| CPU time | 194.06 seconds |
| Started | Sep 09 07:10:21 PM UTC 24 |
| Finished | Sep 09 07:13:38 PM UTC 24 |
| Peak memory | 284244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1001934594 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 50.otp_ctrl_stress_all_with_rand_reset.1001934594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_init_fail.256667631 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 185020742 ps |
| CPU time | 3.84 seconds |
| Started | Sep 09 07:10:21 PM UTC 24 |
| Finished | Sep 09 07:10:26 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256667631 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.256667631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/51.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_parallel_lc_esc.3398501318 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 1883529935 ps |
| CPU time | 24.69 seconds |
| Started | Sep 09 07:10:21 PM UTC 24 |
| Finished | Sep 09 07:10:47 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398501318 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.3398501318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/51.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/51.otp_ctrl_stress_all_with_rand_reset.892705907 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 1537622713 ps |
| CPU time | 37.72 seconds |
| Started | Sep 09 07:10:21 PM UTC 24 |
| Finished | Sep 09 07:11:01 PM UTC 24 |
| Peak memory | 268184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=892705907 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.892705907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_init_fail.1330172245 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 209345683 ps |
| CPU time | 5.22 seconds |
| Started | Sep 09 07:10:21 PM UTC 24 |
| Finished | Sep 09 07:10:28 PM UTC 24 |
| Peak memory | 253272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330172245 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.1330172245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/52.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/52.otp_ctrl_parallel_lc_esc.3559665098 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 1802003126 ps |
| CPU time | 5.04 seconds |
| Started | Sep 09 07:10:30 PM UTC 24 |
| Finished | Sep 09 07:10:36 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559665098 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.3559665098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/52.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_init_fail.3293155523 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 236136593 ps |
| CPU time | 3.16 seconds |
| Started | Sep 09 07:10:30 PM UTC 24 |
| Finished | Sep 09 07:10:34 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293155523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.3293155523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/53.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_parallel_lc_esc.2983992142 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 1317754239 ps |
| CPU time | 17.88 seconds |
| Started | Sep 09 07:10:30 PM UTC 24 |
| Finished | Sep 09 07:10:49 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983992142 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.2983992142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/53.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/53.otp_ctrl_stress_all_with_rand_reset.3576951691 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 6831768479 ps |
| CPU time | 91.65 seconds |
| Started | Sep 09 07:10:30 PM UTC 24 |
| Finished | Sep 09 07:12:04 PM UTC 24 |
| Peak memory | 274092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3576951691 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 53.otp_ctrl_stress_all_with_rand_reset.3576951691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/53.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_init_fail.1850984114 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 631213059 ps |
| CPU time | 5.48 seconds |
| Started | Sep 09 07:10:30 PM UTC 24 |
| Finished | Sep 09 07:10:37 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850984114 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.1850984114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/54.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_parallel_lc_esc.3856302473 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 318171820 ps |
| CPU time | 8.03 seconds |
| Started | Sep 09 07:10:30 PM UTC 24 |
| Finished | Sep 09 07:10:39 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856302473 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.3856302473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/54.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/54.otp_ctrl_stress_all_with_rand_reset.1035452697 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3685903989 ps |
| CPU time | 36.16 seconds |
| Started | Sep 09 07:10:30 PM UTC 24 |
| Finished | Sep 09 07:11:08 PM UTC 24 |
| Peak memory | 257556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1035452697 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 54.otp_ctrl_stress_all_with_rand_reset.1035452697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/54.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_init_fail.2163084368 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 162233179 ps |
| CPU time | 4.39 seconds |
| Started | Sep 09 07:10:30 PM UTC 24 |
| Finished | Sep 09 07:10:36 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163084368 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.2163084368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/55.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/55.otp_ctrl_parallel_lc_esc.484854296 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 3632839735 ps |
| CPU time | 25.72 seconds |
| Started | Sep 09 07:10:30 PM UTC 24 |
| Finished | Sep 09 07:10:57 PM UTC 24 |
| Peak memory | 251248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484854296 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.484854296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/55.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_init_fail.1962754537 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 2137922360 ps |
| CPU time | 4.75 seconds |
| Started | Sep 09 07:10:30 PM UTC 24 |
| Finished | Sep 09 07:10:36 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962754537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.1962754537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/56.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/56.otp_ctrl_parallel_lc_esc.1351846347 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 1461783462 ps |
| CPU time | 12.09 seconds |
| Started | Sep 09 07:10:30 PM UTC 24 |
| Finished | Sep 09 07:10:44 PM UTC 24 |
| Peak memory | 251412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351846347 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.1351846347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/56.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_init_fail.686301883 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 185273904 ps |
| CPU time | 4.13 seconds |
| Started | Sep 09 07:10:33 PM UTC 24 |
| Finished | Sep 09 07:10:38 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686301883 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.686301883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/57.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_parallel_lc_esc.467068881 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 267363378 ps |
| CPU time | 4.23 seconds |
| Started | Sep 09 07:10:33 PM UTC 24 |
| Finished | Sep 09 07:10:38 PM UTC 24 |
| Peak memory | 251124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467068881 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.467068881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/57.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/57.otp_ctrl_stress_all_with_rand_reset.1426855924 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 4427657649 ps |
| CPU time | 89.12 seconds |
| Started | Sep 09 07:10:42 PM UTC 24 |
| Finished | Sep 09 07:12:13 PM UTC 24 |
| Peak memory | 270192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1426855924 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 57.otp_ctrl_stress_all_with_rand_reset.1426855924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/57.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_init_fail.3315597389 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 265206631 ps |
| CPU time | 3.38 seconds |
| Started | Sep 09 07:10:42 PM UTC 24 |
| Finished | Sep 09 07:10:46 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315597389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.3315597389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/58.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/58.otp_ctrl_parallel_lc_esc.2829913439 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 646455325 ps |
| CPU time | 6.04 seconds |
| Started | Sep 09 07:10:42 PM UTC 24 |
| Finished | Sep 09 07:10:49 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829913439 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.2829913439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/58.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_init_fail.1867974978 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 168793917 ps |
| CPU time | 3.54 seconds |
| Started | Sep 09 07:10:42 PM UTC 24 |
| Finished | Sep 09 07:10:47 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867974978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.1867974978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/59.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/59.otp_ctrl_parallel_lc_esc.226002269 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 3635257925 ps |
| CPU time | 18.6 seconds |
| Started | Sep 09 07:10:42 PM UTC 24 |
| Finished | Sep 09 07:11:02 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226002269 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.226002269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/59.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_alert_test.2497486878 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 88962593 ps |
| CPU time | 2.45 seconds |
| Started | Sep 09 07:04:54 PM UTC 24 |
| Finished | Sep 09 07:04:58 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497486878 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.2497486878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_background_chks.3941223125 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 1557339440 ps |
| CPU time | 22.51 seconds |
| Started | Sep 09 07:04:49 PM UTC 24 |
| Finished | Sep 09 07:05:12 PM UTC 24 |
| Peak memory | 251572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941223125 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.3941223125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_errs.752475943 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 742121933 ps |
| CPU time | 22.92 seconds |
| Started | Sep 09 07:04:54 PM UTC 24 |
| Finished | Sep 09 07:05:18 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752475943 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.752475943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_dai_lock.1284268937 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 4164173680 ps |
| CPU time | 30.42 seconds |
| Started | Sep 09 07:04:49 PM UTC 24 |
| Finished | Sep 09 07:05:21 PM UTC 24 |
| Peak memory | 251636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284268937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.1284268937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_init_fail.3125041839 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 107706127 ps |
| CPU time | 4.79 seconds |
| Started | Sep 09 07:04:49 PM UTC 24 |
| Finished | Sep 09 07:04:54 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125041839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.3125041839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_macro_errs.2286193991 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 301472188 ps |
| CPU time | 9.68 seconds |
| Started | Sep 09 07:04:54 PM UTC 24 |
| Finished | Sep 09 07:05:05 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286193991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.2286193991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_esc.502376277 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 1731041529 ps |
| CPU time | 8.09 seconds |
| Started | Sep 09 07:04:49 PM UTC 24 |
| Finished | Sep 09 07:04:58 PM UTC 24 |
| Peak memory | 251160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502376277 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.502376277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_parallel_lc_req.3098867833 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 1044010791 ps |
| CPU time | 31.79 seconds |
| Started | Sep 09 07:04:49 PM UTC 24 |
| Finished | Sep 09 07:05:22 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098867833 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.3098867833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_regwen.283994991 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 1781333761 ps |
| CPU time | 6.72 seconds |
| Started | Sep 09 07:04:54 PM UTC 24 |
| Finished | Sep 09 07:05:02 PM UTC 24 |
| Peak memory | 251164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283994991 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.283994991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_smoke.1254824002 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 1059110687 ps |
| CPU time | 6.44 seconds |
| Started | Sep 09 07:04:46 PM UTC 24 |
| Finished | Sep 09 07:04:53 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254824002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.1254824002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/6.otp_ctrl_test_access.2833458878 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 623915571 ps |
| CPU time | 7.79 seconds |
| Started | Sep 09 07:04:54 PM UTC 24 |
| Finished | Sep 09 07:05:03 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833458878 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.2833458878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/6.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_init_fail.697727275 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 629283268 ps |
| CPU time | 5.14 seconds |
| Started | Sep 09 07:10:42 PM UTC 24 |
| Finished | Sep 09 07:10:48 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697727275 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.697727275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/60.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_parallel_lc_esc.1197226764 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 289017940 ps |
| CPU time | 8.46 seconds |
| Started | Sep 09 07:10:42 PM UTC 24 |
| Finished | Sep 09 07:10:52 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197226764 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.1197226764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/60.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/60.otp_ctrl_stress_all_with_rand_reset.2981496505 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 8602551421 ps |
| CPU time | 157.82 seconds |
| Started | Sep 09 07:10:42 PM UTC 24 |
| Finished | Sep 09 07:13:23 PM UTC 24 |
| Peak memory | 267952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2981496505 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 60.otp_ctrl_stress_all_with_rand_reset.2981496505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/60.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_init_fail.900722002 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 368816406 ps |
| CPU time | 5.72 seconds |
| Started | Sep 09 07:10:42 PM UTC 24 |
| Finished | Sep 09 07:10:49 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900722002 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.900722002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/61.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_parallel_lc_esc.3021853089 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 2931659899 ps |
| CPU time | 38.09 seconds |
| Started | Sep 09 07:10:42 PM UTC 24 |
| Finished | Sep 09 07:11:22 PM UTC 24 |
| Peak memory | 251372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021853089 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.3021853089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/61.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/61.otp_ctrl_stress_all_with_rand_reset.816875289 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 15608324116 ps |
| CPU time | 61.15 seconds |
| Started | Sep 09 07:10:42 PM UTC 24 |
| Finished | Sep 09 07:11:45 PM UTC 24 |
| Peak memory | 257600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=816875289 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.816875289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_init_fail.3685356154 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 248026199 ps |
| CPU time | 3.75 seconds |
| Started | Sep 09 07:10:42 PM UTC 24 |
| Finished | Sep 09 07:10:47 PM UTC 24 |
| Peak memory | 251240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685356154 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.3685356154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/62.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_parallel_lc_esc.3378499017 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 190121623 ps |
| CPU time | 3.71 seconds |
| Started | Sep 09 07:10:42 PM UTC 24 |
| Finished | Sep 09 07:10:47 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378499017 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.3378499017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/62.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/62.otp_ctrl_stress_all_with_rand_reset.1973632007 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 6926187599 ps |
| CPU time | 82.74 seconds |
| Started | Sep 09 07:10:42 PM UTC 24 |
| Finished | Sep 09 07:12:07 PM UTC 24 |
| Peak memory | 267860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1973632007 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 62.otp_ctrl_stress_all_with_rand_reset.1973632007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/62.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_init_fail.825591489 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 2064627131 ps |
| CPU time | 7.03 seconds |
| Started | Sep 09 07:10:42 PM UTC 24 |
| Finished | Sep 09 07:10:51 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825591489 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.825591489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/63.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_parallel_lc_esc.4216458541 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 187740504 ps |
| CPU time | 8.42 seconds |
| Started | Sep 09 07:10:42 PM UTC 24 |
| Finished | Sep 09 07:10:52 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216458541 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.4216458541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/63.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/63.otp_ctrl_stress_all_with_rand_reset.1309643024 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 73808701762 ps |
| CPU time | 116.35 seconds |
| Started | Sep 09 07:10:42 PM UTC 24 |
| Finished | Sep 09 07:12:41 PM UTC 24 |
| Peak memory | 272048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1309643024 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 63.otp_ctrl_stress_all_with_rand_reset.1309643024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_init_fail.4177208935 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 2032894402 ps |
| CPU time | 5.72 seconds |
| Started | Sep 09 07:10:42 PM UTC 24 |
| Finished | Sep 09 07:10:49 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177208935 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.4177208935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/64.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_parallel_lc_esc.2828468233 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 232834558 ps |
| CPU time | 4.69 seconds |
| Started | Sep 09 07:10:49 PM UTC 24 |
| Finished | Sep 09 07:10:54 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828468233 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.2828468233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/64.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/64.otp_ctrl_stress_all_with_rand_reset.3778728613 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 33988577914 ps |
| CPU time | 117.11 seconds |
| Started | Sep 09 07:10:49 PM UTC 24 |
| Finished | Sep 09 07:12:48 PM UTC 24 |
| Peak memory | 272016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3778728613 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 64.otp_ctrl_stress_all_with_rand_reset.3778728613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/65.otp_ctrl_parallel_lc_esc.328826317 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 1548921381 ps |
| CPU time | 5.24 seconds |
| Started | Sep 09 07:10:49 PM UTC 24 |
| Finished | Sep 09 07:10:55 PM UTC 24 |
| Peak memory | 251116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328826317 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.328826317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/65.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_init_fail.2759856816 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2475762421 ps |
| CPU time | 5.29 seconds |
| Started | Sep 09 07:10:49 PM UTC 24 |
| Finished | Sep 09 07:10:55 PM UTC 24 |
| Peak memory | 251236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759856816 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.2759856816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/66.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_parallel_lc_esc.3403828308 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 317747090 ps |
| CPU time | 10.99 seconds |
| Started | Sep 09 07:10:49 PM UTC 24 |
| Finished | Sep 09 07:11:01 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403828308 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.3403828308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/66.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/66.otp_ctrl_stress_all_with_rand_reset.3749190330 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 5284274448 ps |
| CPU time | 46.12 seconds |
| Started | Sep 09 07:10:49 PM UTC 24 |
| Finished | Sep 09 07:11:37 PM UTC 24 |
| Peak memory | 267952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3749190330 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 66.otp_ctrl_stress_all_with_rand_reset.3749190330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_init_fail.876792537 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 1467399883 ps |
| CPU time | 6.42 seconds |
| Started | Sep 09 07:10:49 PM UTC 24 |
| Finished | Sep 09 07:10:57 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876792537 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.876792537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/67.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/67.otp_ctrl_parallel_lc_esc.3591867072 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 182157625 ps |
| CPU time | 4.81 seconds |
| Started | Sep 09 07:10:49 PM UTC 24 |
| Finished | Sep 09 07:10:55 PM UTC 24 |
| Peak memory | 253204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591867072 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.3591867072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/67.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_init_fail.2719205476 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 342102333 ps |
| CPU time | 5.88 seconds |
| Started | Sep 09 07:10:49 PM UTC 24 |
| Finished | Sep 09 07:10:56 PM UTC 24 |
| Peak memory | 251300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719205476 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.2719205476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/68.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/68.otp_ctrl_parallel_lc_esc.56922523 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 497634540 ps |
| CPU time | 14.93 seconds |
| Started | Sep 09 07:10:52 PM UTC 24 |
| Finished | Sep 09 07:11:08 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56922523 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.56922523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/68.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_init_fail.791240978 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 122628449 ps |
| CPU time | 3.47 seconds |
| Started | Sep 09 07:10:52 PM UTC 24 |
| Finished | Sep 09 07:10:57 PM UTC 24 |
| Peak memory | 251172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791240978 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.791240978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/69.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_parallel_lc_esc.1192146805 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 1861195363 ps |
| CPU time | 4.4 seconds |
| Started | Sep 09 07:10:52 PM UTC 24 |
| Finished | Sep 09 07:10:58 PM UTC 24 |
| Peak memory | 251500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192146805 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.1192146805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/69.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/69.otp_ctrl_stress_all_with_rand_reset.4074481266 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 5100523294 ps |
| CPU time | 66.29 seconds |
| Started | Sep 09 07:10:52 PM UTC 24 |
| Finished | Sep 09 07:12:00 PM UTC 24 |
| Peak memory | 267924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4074481266 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 69.otp_ctrl_stress_all_with_rand_reset.4074481266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/69.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_check_fail.2695091483 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 697491359 ps |
| CPU time | 10.66 seconds |
| Started | Sep 09 07:04:58 PM UTC 24 |
| Finished | Sep 09 07:05:10 PM UTC 24 |
| Peak memory | 257528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695091483 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.2695091483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_errs.1421091258 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 1012362136 ps |
| CPU time | 31.9 seconds |
| Started | Sep 09 07:04:58 PM UTC 24 |
| Finished | Sep 09 07:05:31 PM UTC 24 |
| Peak memory | 255392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421091258 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.1421091258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_dai_lock.4095647937 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 651658760 ps |
| CPU time | 7.06 seconds |
| Started | Sep 09 07:04:58 PM UTC 24 |
| Finished | Sep 09 07:05:06 PM UTC 24 |
| Peak memory | 251512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095647937 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.4095647937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_init_fail.520556243 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 335678213 ps |
| CPU time | 3.93 seconds |
| Started | Sep 09 07:04:55 PM UTC 24 |
| Finished | Sep 09 07:05:00 PM UTC 24 |
| Peak memory | 251108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520556243 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.520556243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_macro_errs.3218484256 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2004775516 ps |
| CPU time | 24.28 seconds |
| Started | Sep 09 07:04:58 PM UTC 24 |
| Finished | Sep 09 07:05:24 PM UTC 24 |
| Peak memory | 255480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218484256 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.3218484256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_key_req.656555307 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 826211113 ps |
| CPU time | 18.87 seconds |
| Started | Sep 09 07:04:58 PM UTC 24 |
| Finished | Sep 09 07:05:18 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656555307 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.656555307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_parallel_lc_esc.3815284255 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 304354398 ps |
| CPU time | 16.22 seconds |
| Started | Sep 09 07:04:58 PM UTC 24 |
| Finished | Sep 09 07:05:15 PM UTC 24 |
| Peak memory | 251068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815284255 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.3815284255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_regwen.3505438699 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1556667160 ps |
| CPU time | 3.76 seconds |
| Started | Sep 09 07:05:01 PM UTC 24 |
| Finished | Sep 09 07:05:06 PM UTC 24 |
| Peak memory | 257100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505438699 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.3505438699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_smoke.3094764530 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 7472298392 ps |
| CPU time | 14.46 seconds |
| Started | Sep 09 07:04:55 PM UTC 24 |
| Finished | Sep 09 07:05:10 PM UTC 24 |
| Peak memory | 251688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094764530 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.3094764530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/7.otp_ctrl_test_access.1383494615 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 1040594830 ps |
| CPU time | 15 seconds |
| Started | Sep 09 07:05:01 PM UTC 24 |
| Finished | Sep 09 07:05:18 PM UTC 24 |
| Peak memory | 251192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383494615 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.1383494615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/7.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_init_fail.713017901 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 520210130 ps |
| CPU time | 5.24 seconds |
| Started | Sep 09 07:10:52 PM UTC 24 |
| Finished | Sep 09 07:10:59 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713017901 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.713017901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/70.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_parallel_lc_esc.409451847 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 367758564 ps |
| CPU time | 8.44 seconds |
| Started | Sep 09 07:10:52 PM UTC 24 |
| Finished | Sep 09 07:11:02 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409451847 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.409451847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/70.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/70.otp_ctrl_stress_all_with_rand_reset.1510660754 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 13987019364 ps |
| CPU time | 79.68 seconds |
| Started | Sep 09 07:10:54 PM UTC 24 |
| Finished | Sep 09 07:12:16 PM UTC 24 |
| Peak memory | 267800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1510660754 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 70.otp_ctrl_stress_all_with_rand_reset.1510660754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/70.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_init_fail.485384062 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 291660224 ps |
| CPU time | 4.25 seconds |
| Started | Sep 09 07:10:54 PM UTC 24 |
| Finished | Sep 09 07:10:59 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485384062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.485384062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/71.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/71.otp_ctrl_parallel_lc_esc.2280772653 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 266097543 ps |
| CPU time | 5.59 seconds |
| Started | Sep 09 07:10:57 PM UTC 24 |
| Finished | Sep 09 07:11:04 PM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280772653 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.2280772653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/71.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_init_fail.2643896259 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 1959644659 ps |
| CPU time | 8.84 seconds |
| Started | Sep 09 07:10:57 PM UTC 24 |
| Finished | Sep 09 07:11:07 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643896259 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.2643896259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/72.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/72.otp_ctrl_parallel_lc_esc.3762519386 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 188766354 ps |
| CPU time | 4.77 seconds |
| Started | Sep 09 07:10:57 PM UTC 24 |
| Finished | Sep 09 07:11:03 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762519386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.3762519386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/72.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_init_fail.1909890684 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 469050934 ps |
| CPU time | 3.81 seconds |
| Started | Sep 09 07:10:57 PM UTC 24 |
| Finished | Sep 09 07:11:02 PM UTC 24 |
| Peak memory | 251428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909890684 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.1909890684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/73.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_parallel_lc_esc.1926354560 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 6374417026 ps |
| CPU time | 16.87 seconds |
| Started | Sep 09 07:10:57 PM UTC 24 |
| Finished | Sep 09 07:11:15 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926354560 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.1926354560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/73.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/73.otp_ctrl_stress_all_with_rand_reset.940168167 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 9667950873 ps |
| CPU time | 67.32 seconds |
| Started | Sep 09 07:11:01 PM UTC 24 |
| Finished | Sep 09 07:12:10 PM UTC 24 |
| Peak memory | 257880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=940168167 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.940168167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_init_fail.1487519062 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 117335029 ps |
| CPU time | 4.61 seconds |
| Started | Sep 09 07:11:01 PM UTC 24 |
| Finished | Sep 09 07:11:06 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487519062 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.1487519062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/74.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/74.otp_ctrl_parallel_lc_esc.1934096135 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 127188737 ps |
| CPU time | 5.88 seconds |
| Started | Sep 09 07:11:01 PM UTC 24 |
| Finished | Sep 09 07:11:08 PM UTC 24 |
| Peak memory | 251148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934096135 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.1934096135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/74.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_init_fail.1293314357 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 538286181 ps |
| CPU time | 4.78 seconds |
| Started | Sep 09 07:11:01 PM UTC 24 |
| Finished | Sep 09 07:11:07 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293314357 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.1293314357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/75.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_parallel_lc_esc.3037356220 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 5551993453 ps |
| CPU time | 16.62 seconds |
| Started | Sep 09 07:11:01 PM UTC 24 |
| Finished | Sep 09 07:11:19 PM UTC 24 |
| Peak memory | 251244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037356220 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.3037356220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/75.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/75.otp_ctrl_stress_all_with_rand_reset.3785318671 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 20191019736 ps |
| CPU time | 158.74 seconds |
| Started | Sep 09 07:11:01 PM UTC 24 |
| Finished | Sep 09 07:13:42 PM UTC 24 |
| Peak memory | 274096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=3785318671 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 75.otp_ctrl_stress_all_with_rand_reset.3785318671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/75.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_init_fail.1107546835 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 2118757168 ps |
| CPU time | 4.23 seconds |
| Started | Sep 09 07:11:01 PM UTC 24 |
| Finished | Sep 09 07:11:06 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107546835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.1107546835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/76.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/76.otp_ctrl_parallel_lc_esc.3623370963 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 2547915909 ps |
| CPU time | 36.31 seconds |
| Started | Sep 09 07:11:06 PM UTC 24 |
| Finished | Sep 09 07:11:44 PM UTC 24 |
| Peak memory | 253292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623370963 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.3623370963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/76.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_init_fail.572762499 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 1971636054 ps |
| CPU time | 8.77 seconds |
| Started | Sep 09 07:11:06 PM UTC 24 |
| Finished | Sep 09 07:11:16 PM UTC 24 |
| Peak memory | 250664 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572762499 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.572762499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/77.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/77.otp_ctrl_parallel_lc_esc.2739907407 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 723109102 ps |
| CPU time | 17.8 seconds |
| Started | Sep 09 07:11:06 PM UTC 24 |
| Finished | Sep 09 07:11:25 PM UTC 24 |
| Peak memory | 250636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739907407 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.2739907407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/77.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_init_fail.2220220414 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 93768071 ps |
| CPU time | 4.22 seconds |
| Started | Sep 09 07:11:06 PM UTC 24 |
| Finished | Sep 09 07:11:11 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220220414 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.2220220414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/78.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_parallel_lc_esc.559187325 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 110925880 ps |
| CPU time | 3.15 seconds |
| Started | Sep 09 07:11:06 PM UTC 24 |
| Finished | Sep 09 07:11:10 PM UTC 24 |
| Peak memory | 251420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559187325 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.559187325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/78.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/78.otp_ctrl_stress_all_with_rand_reset.784607226 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 16382845443 ps |
| CPU time | 77.75 seconds |
| Started | Sep 09 07:11:06 PM UTC 24 |
| Finished | Sep 09 07:12:26 PM UTC 24 |
| Peak memory | 257624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=784607226 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.784607226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/78.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_init_fail.324737178 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 174507293 ps |
| CPU time | 4.5 seconds |
| Started | Sep 09 07:11:06 PM UTC 24 |
| Finished | Sep 09 07:11:12 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324737178 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.324737178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/79.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_parallel_lc_esc.2044252591 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 310275922 ps |
| CPU time | 6.56 seconds |
| Started | Sep 09 07:11:06 PM UTC 24 |
| Finished | Sep 09 07:11:14 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044252591 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.2044252591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/79.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/79.otp_ctrl_stress_all_with_rand_reset.2479773856 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 3860802813 ps |
| CPU time | 64.37 seconds |
| Started | Sep 09 07:11:08 PM UTC 24 |
| Finished | Sep 09 07:12:14 PM UTC 24 |
| Peak memory | 269912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=2479773856 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 79.otp_ctrl_stress_all_with_rand_reset.2479773856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_alert_test.2039122414 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 202472376 ps |
| CPU time | 3.26 seconds |
| Started | Sep 09 07:05:09 PM UTC 24 |
| Finished | Sep 09 07:05:14 PM UTC 24 |
| Peak memory | 251424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039122414 -assert nopostproc +UVM_TESTNAME=o tp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.2039122414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_background_chks.3579822321 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 267620753 ps |
| CPU time | 7.72 seconds |
| Started | Sep 09 07:05:02 PM UTC 24 |
| Finished | Sep 09 07:05:11 PM UTC 24 |
| Peak memory | 251380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579822321 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.3579822321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_check_fail.3272588682 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 632803178 ps |
| CPU time | 5.24 seconds |
| Started | Sep 09 07:05:05 PM UTC 24 |
| Finished | Sep 09 07:05:12 PM UTC 24 |
| Peak memory | 257632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272588682 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.3272588682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_errs.4008062687 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 1172110803 ps |
| CPU time | 30.7 seconds |
| Started | Sep 09 07:05:05 PM UTC 24 |
| Finished | Sep 09 07:05:38 PM UTC 24 |
| Peak memory | 255472 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008062687 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.4008062687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_dai_lock.1289926415 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2378461385 ps |
| CPU time | 13.85 seconds |
| Started | Sep 09 07:05:05 PM UTC 24 |
| Finished | Sep 09 07:05:21 PM UTC 24 |
| Peak memory | 253596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289926415 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.1289926415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_key_req.3844548129 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 442843437 ps |
| CPU time | 8.53 seconds |
| Started | Sep 09 07:05:09 PM UTC 24 |
| Finished | Sep 09 07:05:19 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844548129 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.3844548129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_esc.397434386 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 373602731 ps |
| CPU time | 5.31 seconds |
| Started | Sep 09 07:05:03 PM UTC 24 |
| Finished | Sep 09 07:05:09 PM UTC 24 |
| Peak memory | 251444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397434386 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.397434386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_parallel_lc_req.689563395 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 2021526049 ps |
| CPU time | 15.09 seconds |
| Started | Sep 09 07:05:02 PM UTC 24 |
| Finished | Sep 09 07:05:18 PM UTC 24 |
| Peak memory | 257368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689563395 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.689563395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_regwen.1893331821 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 126477542 ps |
| CPU time | 3.41 seconds |
| Started | Sep 09 07:05:09 PM UTC 24 |
| Finished | Sep 09 07:05:14 PM UTC 24 |
| Peak memory | 251284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893331821 -assert nopostproc +UVM_TESTNAME=otp_ctrl_bas e_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/ otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.1893331821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_smoke.3911701702 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 309264150 ps |
| CPU time | 3.49 seconds |
| Started | Sep 09 07:05:02 PM UTC 24 |
| Finished | Sep 09 07:05:06 PM UTC 24 |
| Peak memory | 251676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911701702 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.3911701702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_stress_all.1461463340 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 45169084749 ps |
| CPU time | 89.07 seconds |
| Started | Sep 09 07:05:09 PM UTC 24 |
| Finished | Sep 09 07:06:40 PM UTC 24 |
| Peak memory | 276076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461463340 -assert nopostproc +UVM_TESTNAM E=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all.1461463340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/8.otp_ctrl_test_access.2301447066 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 5425093162 ps |
| CPU time | 31.53 seconds |
| Started | Sep 09 07:05:09 PM UTC 24 |
| Finished | Sep 09 07:05:42 PM UTC 24 |
| Peak memory | 253428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301447066 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.2301447066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/8.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_init_fail.4247592614 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 398367547 ps |
| CPU time | 5.63 seconds |
| Started | Sep 09 07:11:08 PM UTC 24 |
| Finished | Sep 09 07:11:15 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247592614 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.4247592614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/80.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_parallel_lc_esc.3117235104 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 137372731 ps |
| CPU time | 5.08 seconds |
| Started | Sep 09 07:11:08 PM UTC 24 |
| Finished | Sep 09 07:11:15 PM UTC 24 |
| Peak memory | 251176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117235104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.3117235104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/80.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/80.otp_ctrl_stress_all_with_rand_reset.4048928510 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 8201015191 ps |
| CPU time | 163.64 seconds |
| Started | Sep 09 07:11:08 PM UTC 24 |
| Finished | Sep 09 07:13:55 PM UTC 24 |
| Peak memory | 274004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4048928510 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 80.otp_ctrl_stress_all_with_rand_reset.4048928510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_init_fail.4039640835 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 157155447 ps |
| CPU time | 4.34 seconds |
| Started | Sep 09 07:11:11 PM UTC 24 |
| Finished | Sep 09 07:11:17 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039640835 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.4039640835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/81.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_parallel_lc_esc.1769129390 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 1164767294 ps |
| CPU time | 5.28 seconds |
| Started | Sep 09 07:11:12 PM UTC 24 |
| Finished | Sep 09 07:11:18 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769129390 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.1769129390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/81.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/81.otp_ctrl_stress_all_with_rand_reset.1548368013 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 3721200062 ps |
| CPU time | 62.51 seconds |
| Started | Sep 09 07:11:12 PM UTC 24 |
| Finished | Sep 09 07:12:16 PM UTC 24 |
| Peak memory | 257712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1548368013 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 81.otp_ctrl_stress_all_with_rand_reset.1548368013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_init_fail.3580026104 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 547894102 ps |
| CPU time | 5.92 seconds |
| Started | Sep 09 07:11:12 PM UTC 24 |
| Finished | Sep 09 07:11:19 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580026104 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.3580026104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/82.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/82.otp_ctrl_parallel_lc_esc.2886560377 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 1752284584 ps |
| CPU time | 5.85 seconds |
| Started | Sep 09 07:11:12 PM UTC 24 |
| Finished | Sep 09 07:11:19 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886560377 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.2886560377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/82.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_init_fail.156558895 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 136127931 ps |
| CPU time | 4.67 seconds |
| Started | Sep 09 07:11:13 PM UTC 24 |
| Finished | Sep 09 07:11:19 PM UTC 24 |
| Peak memory | 251224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156558895 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.156558895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/83.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/83.otp_ctrl_parallel_lc_esc.1206233998 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 669952514 ps |
| CPU time | 6.64 seconds |
| Started | Sep 09 07:11:13 PM UTC 24 |
| Finished | Sep 09 07:11:21 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206233998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.1206233998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/83.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_init_fail.2359942975 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 97957550 ps |
| CPU time | 3.64 seconds |
| Started | Sep 09 07:11:23 PM UTC 24 |
| Finished | Sep 09 07:11:28 PM UTC 24 |
| Peak memory | 250912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359942975 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.2359942975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/84.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/84.otp_ctrl_parallel_lc_esc.3409250413 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 653913104 ps |
| CPU time | 10.41 seconds |
| Started | Sep 09 07:11:23 PM UTC 24 |
| Finished | Sep 09 07:11:35 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409250413 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.3409250413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/84.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_init_fail.1393991992 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 1825909645 ps |
| CPU time | 5.49 seconds |
| Started | Sep 09 07:11:23 PM UTC 24 |
| Finished | Sep 09 07:11:30 PM UTC 24 |
| Peak memory | 251200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393991992 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.1393991992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/85.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/85.otp_ctrl_parallel_lc_esc.3137463590 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 496409754 ps |
| CPU time | 9.36 seconds |
| Started | Sep 09 07:11:23 PM UTC 24 |
| Finished | Sep 09 07:11:34 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137463590 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.3137463590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/85.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_init_fail.3063328188 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 207862168 ps |
| CPU time | 4.13 seconds |
| Started | Sep 09 07:11:23 PM UTC 24 |
| Finished | Sep 09 07:11:29 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063328188 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.3063328188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/86.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/86.otp_ctrl_parallel_lc_esc.1932871162 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 435254202 ps |
| CPU time | 3.83 seconds |
| Started | Sep 09 07:11:23 PM UTC 24 |
| Finished | Sep 09 07:11:28 PM UTC 24 |
| Peak memory | 251112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932871162 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.1932871162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/86.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_init_fail.814693586 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 1944877843 ps |
| CPU time | 6.23 seconds |
| Started | Sep 09 07:11:23 PM UTC 24 |
| Finished | Sep 09 07:11:31 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814693586 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.814693586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/87.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/87.otp_ctrl_parallel_lc_esc.2958945217 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 370327309 ps |
| CPU time | 5.15 seconds |
| Started | Sep 09 07:11:23 PM UTC 24 |
| Finished | Sep 09 07:11:30 PM UTC 24 |
| Peak memory | 251152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958945217 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.2958945217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/87.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_init_fail.839897900 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 195943442 ps |
| CPU time | 4.12 seconds |
| Started | Sep 09 07:11:24 PM UTC 24 |
| Finished | Sep 09 07:11:29 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839897900 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.839897900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/88.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/88.otp_ctrl_parallel_lc_esc.2486093667 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 214857743 ps |
| CPU time | 4.82 seconds |
| Started | Sep 09 07:11:24 PM UTC 24 |
| Finished | Sep 09 07:11:30 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486093667 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.2486093667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/88.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_init_fail.2205597879 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 113811534 ps |
| CPU time | 3.25 seconds |
| Started | Sep 09 07:11:26 PM UTC 24 |
| Finished | Sep 09 07:11:31 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205597879 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.2205597879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/89.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/89.otp_ctrl_parallel_lc_esc.704239221 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 1775621299 ps |
| CPU time | 20.86 seconds |
| Started | Sep 09 07:11:26 PM UTC 24 |
| Finished | Sep 09 07:11:49 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704239221 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.704239221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/89.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_alert_test.905653245 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 944158498 ps |
| CPU time | 3.38 seconds |
| Started | Sep 09 07:05:14 PM UTC 24 |
| Finished | Sep 09 07:05:18 PM UTC 24 |
| Peak memory | 251508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905653245 -assert nopostproc +UVM_TESTNAME=ot p_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.905653245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_background_chks.1642762944 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1488035664 ps |
| CPU time | 10.99 seconds |
| Started | Sep 09 07:05:09 PM UTC 24 |
| Finished | Sep 09 07:05:22 PM UTC 24 |
| Peak memory | 251316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642762944 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.1642762944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_background_chks/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_check_fail.987232450 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3117520366 ps |
| CPU time | 17.01 seconds |
| Started | Sep 09 07:05:10 PM UTC 24 |
| Finished | Sep 09 07:05:28 PM UTC 24 |
| Peak memory | 253432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987232450 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.987232450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_errs.3330811186 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 481588661 ps |
| CPU time | 11.77 seconds |
| Started | Sep 09 07:05:09 PM UTC 24 |
| Finished | Sep 09 07:05:23 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330811186 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.3330811186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_dai_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_dai_lock.4286859360 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 3912929387 ps |
| CPU time | 52.16 seconds |
| Started | Sep 09 07:05:09 PM UTC 24 |
| Finished | Sep 09 07:06:04 PM UTC 24 |
| Peak memory | 253416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286859360 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.4286859360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_dai_lock/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_init_fail.2070786919 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 625057593 ps |
| CPU time | 5.73 seconds |
| Started | Sep 09 07:05:09 PM UTC 24 |
| Finished | Sep 09 07:05:16 PM UTC 24 |
| Peak memory | 251204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070786919 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.2070786919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_macro_errs.2481901663 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 785665270 ps |
| CPU time | 15.48 seconds |
| Started | Sep 09 07:05:11 PM UTC 24 |
| Finished | Sep 09 07:05:28 PM UTC 24 |
| Peak memory | 253364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481901663 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.2481901663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_macro_errs/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_key_req.1692651426 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1505076055 ps |
| CPU time | 18.42 seconds |
| Started | Sep 09 07:05:11 PM UTC 24 |
| Finished | Sep 09 07:05:31 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692651426 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.1692651426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_key_req/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_parallel_lc_esc.316957552 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 140688223 ps |
| CPU time | 3.45 seconds |
| Started | Sep 09 07:05:09 PM UTC 24 |
| Finished | Sep 09 07:05:14 PM UTC 24 |
| Peak memory | 251100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316957552 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.316957552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_regwen.639305772 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 983032143 ps |
| CPU time | 8.3 seconds |
| Started | Sep 09 07:05:11 PM UTC 24 |
| Finished | Sep 09 07:05:21 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639305772 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base _test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/o tp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.639305772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_smoke.3356472998 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 1362414992 ps |
| CPU time | 11.1 seconds |
| Started | Sep 09 07:05:09 PM UTC 24 |
| Finished | Sep 09 07:05:22 PM UTC 24 |
| Peak memory | 251292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356472998 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.3356472998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all.230921915 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 629060594 ps |
| CPU time | 11.58 seconds |
| Started | Sep 09 07:05:12 PM UTC 24 |
| Finished | Sep 09 07:05:25 PM UTC 24 |
| Peak memory | 251252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230921915 -assert nopostproc +UVM_TESTNAME =otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all.230921915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_stress_all_with_rand_reset.4214771119 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 18240450498 ps |
| CPU time | 146.88 seconds |
| Started | Sep 09 07:05:11 PM UTC 24 |
| Finished | Sep 09 07:07:41 PM UTC 24 |
| Peak memory | 274088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4214771119 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 9.otp_ctrl_stress_all_with_rand_reset.4214771119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/9.otp_ctrl_test_access.3305638412 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1787529430 ps |
| CPU time | 17.93 seconds |
| Started | Sep 09 07:05:11 PM UTC 24 |
| Finished | Sep 09 07:05:31 PM UTC 24 |
| Peak memory | 251288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305638412 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-s im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.3305638412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/9.otp_ctrl_test_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_init_fail.1208280577 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 183426685 ps |
| CPU time | 6.39 seconds |
| Started | Sep 09 07:11:30 PM UTC 24 |
| Finished | Sep 09 07:11:38 PM UTC 24 |
| Peak memory | 250948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208280577 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.1208280577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/90.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/90.otp_ctrl_parallel_lc_esc.3968684430 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 84484419 ps |
| CPU time | 4.96 seconds |
| Started | Sep 09 07:11:30 PM UTC 24 |
| Finished | Sep 09 07:11:36 PM UTC 24 |
| Peak memory | 250848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968684430 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.3968684430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/90.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_init_fail.2208320349 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 322815126 ps |
| CPU time | 3.9 seconds |
| Started | Sep 09 07:11:31 PM UTC 24 |
| Finished | Sep 09 07:11:36 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208320349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.2208320349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/91.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_parallel_lc_esc.230285322 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 390092011 ps |
| CPU time | 7.68 seconds |
| Started | Sep 09 07:11:31 PM UTC 24 |
| Finished | Sep 09 07:11:39 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230285322 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.230285322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/91.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/91.otp_ctrl_stress_all_with_rand_reset.1923216860 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 1200839470 ps |
| CPU time | 34.53 seconds |
| Started | Sep 09 07:11:31 PM UTC 24 |
| Finished | Sep 09 07:12:07 PM UTC 24 |
| Peak memory | 257904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=1923216860 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 91.otp_ctrl_stress_all_with_rand_reset.1923216860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_init_fail.321229408 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 123644471 ps |
| CPU time | 4.9 seconds |
| Started | Sep 09 07:11:31 PM UTC 24 |
| Finished | Sep 09 07:11:37 PM UTC 24 |
| Peak memory | 251484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321229408 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.321229408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/92.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_parallel_lc_esc.3440750531 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 3288531189 ps |
| CPU time | 13 seconds |
| Started | Sep 09 07:11:34 PM UTC 24 |
| Finished | Sep 09 07:11:49 PM UTC 24 |
| Peak memory | 251216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440750531 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.3440750531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/92.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/92.otp_ctrl_stress_all_with_rand_reset.861388689 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 62474079661 ps |
| CPU time | 205.45 seconds |
| Started | Sep 09 07:11:34 PM UTC 24 |
| Finished | Sep 09 07:15:03 PM UTC 24 |
| Peak memory | 267892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=861388689 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.861388689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/92.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_init_fail.1470527532 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 399354429 ps |
| CPU time | 5.19 seconds |
| Started | Sep 09 07:11:34 PM UTC 24 |
| Finished | Sep 09 07:11:41 PM UTC 24 |
| Peak memory | 251196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470527532 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.1470527532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/93.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/93.otp_ctrl_parallel_lc_esc.697683839 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 2963632803 ps |
| CPU time | 13.62 seconds |
| Started | Sep 09 07:11:34 PM UTC 24 |
| Finished | Sep 09 07:11:50 PM UTC 24 |
| Peak memory | 251480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697683839 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctr l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.697683839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/93.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_parallel_lc_esc.1138555556 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 219431043 ps |
| CPU time | 4.61 seconds |
| Started | Sep 09 07:11:34 PM UTC 24 |
| Finished | Sep 09 07:11:41 PM UTC 24 |
| Peak memory | 251156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138555556 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.1138555556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/94.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/94.otp_ctrl_stress_all_with_rand_reset.4274291782 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 71709386695 ps |
| CPU time | 116.5 seconds |
| Started | Sep 09 07:11:36 PM UTC 24 |
| Finished | Sep 09 07:13:35 PM UTC 24 |
| Peak memory | 267884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_s eq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tool s/sim.tcl +ntb_random_seed=4274291782 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_nam e 94.otp_ctrl_stress_all_with_rand_reset.4274291782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_init_fail.2301833206 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 392108505 ps |
| CPU time | 4.54 seconds |
| Started | Sep 09 07:11:36 PM UTC 24 |
| Finished | Sep 09 07:11:42 PM UTC 24 |
| Peak memory | 251548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301833206 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.2301833206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/95.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/95.otp_ctrl_parallel_lc_esc.3243208366 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 805157920 ps |
| CPU time | 19.66 seconds |
| Started | Sep 09 07:11:36 PM UTC 24 |
| Finished | Sep 09 07:11:57 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243208366 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.3243208366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/95.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_init_fail.449622464 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 194435450 ps |
| CPU time | 4.68 seconds |
| Started | Sep 09 07:11:45 PM UTC 24 |
| Finished | Sep 09 07:11:51 PM UTC 24 |
| Peak memory | 251460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449622464 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.449622464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/96.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/96.otp_ctrl_parallel_lc_esc.2346207349 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 1152564630 ps |
| CPU time | 28 seconds |
| Started | Sep 09 07:11:45 PM UTC 24 |
| Finished | Sep 09 07:12:14 PM UTC 24 |
| Peak memory | 251308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346207349 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.2346207349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/96.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_init_fail.2102050619 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 2552718087 ps |
| CPU time | 10.46 seconds |
| Started | Sep 09 07:11:45 PM UTC 24 |
| Finished | Sep 09 07:11:57 PM UTC 24 |
| Peak memory | 251356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102050619 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.2102050619 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/97.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/97.otp_ctrl_parallel_lc_esc.1833173260 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 1295208379 ps |
| CPU time | 8.96 seconds |
| Started | Sep 09 07:11:45 PM UTC 24 |
| Finished | Sep 09 07:11:55 PM UTC 24 |
| Peak memory | 251436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833173260 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.1833173260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/97.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_init_fail.252918276 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 1333428518 ps |
| CPU time | 4.14 seconds |
| Started | Sep 09 07:11:45 PM UTC 24 |
| Finished | Sep 09 07:11:51 PM UTC 24 |
| Peak memory | 251228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252918276 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST _SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.252918276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/98.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/98.otp_ctrl_parallel_lc_esc.2524095389 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 707743175 ps |
| CPU time | 4.92 seconds |
| Started | Sep 09 07:11:45 PM UTC 24 |
| Finished | Sep 09 07:11:51 PM UTC 24 |
| Peak memory | 251180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524095389 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.2524095389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/98.otp_ctrl_parallel_lc_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_init_fail.3577993053 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 2585846147 ps |
| CPU time | 6.3 seconds |
| Started | Sep 09 07:11:45 PM UTC 24 |
| Finished | Sep 09 07:11:53 PM UTC 24 |
| Peak memory | 251556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577993053 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TES T_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.3577993053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/99.otp_ctrl_init_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/coverage/default/99.otp_ctrl_parallel_lc_esc.83311262 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 424440228 ps |
| CPU time | 9.27 seconds |
| Started | Sep 09 07:11:52 PM UTC 24 |
| Finished | Sep 09 07:12:03 PM UTC 24 |
| Peak memory | 251184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83311262 -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_ SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.83311262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_08/otp_ctrl-sim-vcs/99.otp_ctrl_parallel_lc_esc/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |