Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}
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Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_intr 2 0 2 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=1}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 8 0 8 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_intr

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_values[0] 147875 1 T3 38 T4 78 T5 23
all_values[1] 147875 1 T3 38 T4 78 T5 23


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 167025 1 T3 38 T4 78 T5 1
auto[1] 128725 1 T3 38 T4 78 T5 45


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 151889 1 T3 23 T4 78 T5 24
auto[1] 143861 1 T3 53 T4 78 T5 22


Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for intr_cg_cc

Bins
cp_intr   cp_intr_en   cp_intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_values[0] auto[0] auto[0] 25722 1 T8 1 T7 1 T9 34
all_values[0] auto[0] auto[1] 56071 1 T3 38 T7 5 T9 27
all_values[0] auto[1] auto[0] 18280 1 T5 1 T9 37 T97 1
all_values[0] auto[1] auto[1] 47802 1 T4 78 T5 22 T6 87
all_values[1] auto[0] auto[0] 63606 1 T4 78 T5 1 T6 87
all_values[1] auto[0] auto[1] 21626 1 T9 10 T130 8 T106 2
all_values[1] auto[1] auto[0] 44281 1 T3 23 T5 22 T8 37
all_values[1] auto[1] auto[1] 18362 1 T3 15 T9 9 T95 1