Group : tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg
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Group : tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/otp_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_otp_ctrl_cov_0/otp_ctrl_cov_if.sv


Summary for Group tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group tb.dut.u_otp_ctrl_cov_if::flash_data_req_condition_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
flash_data_req_during_flash_addr_req 2 0 2 100.00 100 1 1 2
flash_data_req_during_lc_esc 2 0 2 100.00 100 1 1 0
flash_data_req_during_otbn_req 2 0 2 100.00 100 1 1 2
flash_data_req_during_otp_idle 2 0 2 100.00 100 1 1 2
flash_data_req_during_sram_0_req 2 0 2 100.00 100 1 1 2
flash_data_req_during_sram_1_req 2 0 2 100.00 100 1 1 2


Summary for Variable flash_data_req_during_flash_addr_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_flash_addr_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 10242 1 T5 2 T8 2 T9 14
auto[1] 794 1 T130 1 T113 1 T115 2


Summary for Variable flash_data_req_during_lc_esc

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for flash_data_req_during_lc_esc

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
lc_esc_off 11007 1 T5 2 T8 2 T9 14
lc_esc_on 29 1 T265 1 T478 1 T374 1


Summary for Variable flash_data_req_during_otbn_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_otbn_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 10211 1 T5 2 T8 2 T9 14
auto[1] 825 1 T130 1 T88 1 T115 3


Summary for Variable flash_data_req_during_otp_idle

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_otp_idle

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1795 1 T130 3 T113 4 T132 2
auto[1] 9241 1 T5 2 T8 2 T9 14


Summary for Variable flash_data_req_during_sram_0_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_sram_0_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 9298 1 T5 1 T8 2 T9 14
auto[1] 1738 1 T5 1 T95 1 T113 2


Summary for Variable flash_data_req_during_sram_1_req

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for flash_data_req_during_sram_1_req

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 10654 1 T5 2 T8 2 T9 14
auto[1] 382 1 T130 1 T284 7 T479 1