Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29600

1

T1

4

T2

58

T6

18

auto[1]

26050

1

T1

2

T2

42

T6

18

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28500

1

T1

3

T2

40

T6

26

auto[1]

27150

1

T1

3

T2

60

T6

10

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27650

1

T1

1

T2

48

T6

20

auto[1]

28000

1

T1

5

T2

52

T6

16

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31450

1

T1

4

T2

50

T6

18

auto[1]

24200

1

T1

2

T2

50

T6

18

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27700

1

T1

2

T2

56

T6

16

auto[1]

27950

1

T1

4

T2

44

T6

20

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28550

1

T1

3

T2

54

T6

10

auto[1]

27100

1

T1

3

T2

46

T6

26

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

800

1

T2

1

T7

1

T8

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

600

1

T2

1

T8

1

T29

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

750

1

T2

3

T6

1

T8

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

650

1

T2

3

T6

1

T8

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1100

1

T2

1

T8

1

T29

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

900

1

T2

1

T8

1

T29

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1750

1

T1

1

T2

3

T7

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1350

1

T1

1

T2

3

T8

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1000

1

T13

11

T102

2

T14

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

850

1

T13

11

T102

2

T14

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1050

1

T6

2

T9

2

T13

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

950

1

T6

2

T9

2

T13

10

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1000

1

T2

2

T6

2

T7

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

700

1

T2

2

T6

2

T8

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

650

1

T6

1

T9

1

T13

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

350

1

T6

1

T9

1

T13

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1000

1

T2

1

T8

1

T29

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

850

1

T2

1

T8

1

T29

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1100

1

T2

4

T8

4

T29

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

950

1

T2

4

T8

4

T29

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1000

1

T2

2

T7

1

T8

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

700

1

T2

2

T8

2

T29

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1100

1

T2

5

T8

5

T29

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

800

1

T2

5

T8

5

T29

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

950

1

T2

3

T8

3

T29

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

900

1

T2

3

T8

3

T29

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

900

1

T2

2

T6

1

T8

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

850

1

T2

2

T6

1

T8

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1400

1

T2

2

T6

2

T8

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

1050

1

T2

2

T6

2

T8

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1000

1

T1

1

T7

1

T13

10

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

600

1

T1

1

T13

6

T36

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

750

1

T6

1

T7

3

T9

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

400

1

T6

1

T9

1

T13

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1250

1

T1

1

T2

2

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

850

1

T2

2

T8

2

T29

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1000

1

T2

1

T6

1

T8

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

850

1

T2

1

T6

1

T8

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1250

1

T2

1

T6

2

T7

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

800

1

T2

1

T6

2

T8

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1550

1

T2

3

T6

2

T7

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1250

1

T2

3

T6

2

T8

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1000

1

T2

2

T8

2

T29

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

900

1

T2

2

T8

2

T29

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

450

1

T2

1

T6

1

T8

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

350

1

T2

1

T6

1

T8

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

700

1

T13

7

T14

7

T31

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

700

1

T13

7

T14

7

T31

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

950

1

T2

2

T7

1

T8

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

600

1

T2

2

T8

2

T29

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1050

1

T7

1

T13

11

T14

11

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

800

1

T13

9

T14

9

T48

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

850

1

T7

2

T13

8

T14

8

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

450

1

T13

5

T14

5

T48

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

650

1

T2

1

T8

1

T29

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

650

1

T2

1

T8

1

T29

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

700

1

T1

1

T2

3

T7

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

500

1

T2

3

T8

3

T29

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

600

1

T2

2

T6

1

T8

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

400

1

T2

2

T6

1

T8

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1350

1

T2

2

T6

1

T7

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

850

1

T2

2

T6

1

T8

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

800

1

T2

1

T8

1

T29

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

800

1

T2

1

T8

1

T29

1