Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	4	12	75.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
debug_cp	2	0	2	100.00	100	1	1	0
dft_cp	2	0	2	100.00	100	1	1	0
done_cp	2	0	2	100.00	100	1	1	0
good_cp	2	0	2	100.00	100	1	1	0

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
blockers_cross	16	4	12	75.00	100	1	1	0

Summary for Variable debug_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for debug_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15200	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

off

209370

1

T1

1

T2

2239

T3

1

on

7000

1

T5

2

T8

138

T19

138

---

Summary for Variable dft_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for dft_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	70250	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

off

151720

1

T1

1

T2

2239

T3

1

on

9600

1

T5

4

T8

188

T19

188

---

Summary for Variable done_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for done_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	182600	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

30400

1

T2

50

T5

4

T8

50

true

18570

1

T1

1

T2

101

T3

1

---

Summary for Variable good_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for good_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	175000	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

18100

1

T2

50

T5

10

T8

50

true

38470

1

T1

1

T2

201

T3

1

---

Summary for Cross blockers_cross

Samples crossed: done_cp good_cp dft_cp debug_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	4	12	75.00	4

Automatically Generated Cross Bins for blockers_cross

Element holes

done_cp	good_cp	dft_cp	debug_cp	COUNT	AT LEAST	NUMBER	STATUS
[false]	[true]	[on]	*	--	--	2

Uncovered bins

done_cp	good_cp	dft_cp	debug_cp	COUNT	AT LEAST	NUMBER	STATUS
[false]	[true]	[off]	[on]	0	1	1
[true]	[false]	[off]	[on]	0	1	1

Covered bins

done_cp

good_cp

dft_cp

debug_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

false

off

off

15250

1

T2

50

T5

1

T8

2

false

false

off

on

50

1

T8

1

T19

1

T118

1

false

false

on

off

50

1

T5

1

T34

1

T38

1

false

false

on

on

50

1

T8

1

T19

1

T118

1

false

true

off

off

12650

1

T5

1

T13

186

T14

186

true

false

off

off

100

1

T5

2

T34

2

T38

2

true

false

on

off

50

1

T5

1

T34

1

T38

1

true

false

on

on

100

1

T5

2

T34

2

T38

2

true

true

off

off

12720

1

T1

1

T2

101

T3

1

true

true

off

on

200

1

T8

4

T19

4

T118

4

true

true

on

off

350

1

T8

7

T19

7

T118

7

true

true

on

on

200

1

T8

4

T19

4

T118

4