Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.39 98.22 95.58 99.44 96.00 96.32 99.73 96.40


Total test records in report: 1070
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T1002 /workspace/coverage/default/6.pwrmgr_stress_all.105601112417841884942239480265863524949044074207606089122843905890916247818085 Nov 22 01:25:51 PM PST 23 Nov 22 01:26:03 PM PST 23 2072030810 ps
T1003 /workspace/coverage/default/35.pwrmgr_aborted_low_power.46790404130313532649980397284993816448144086041168611328942046086601869555886 Nov 22 01:27:20 PM PST 23 Nov 22 01:27:37 PM PST 23 51975542 ps
T1004 /workspace/coverage/default/36.pwrmgr_lowpower_wakeup_race.7368138521209184038813549436676108423449949218895488468281876412480786207471 Nov 22 01:27:40 PM PST 23 Nov 22 01:27:53 PM PST 23 296241445 ps
T1005 /workspace/coverage/default/37.pwrmgr_glitch.38798975371120475923190343865917609221429768286897953425116962607528819163318 Nov 22 01:27:30 PM PST 23 Nov 22 01:27:44 PM PST 23 39672069 ps
T1006 /workspace/coverage/default/47.pwrmgr_reset_invalid.67626433096149978827284767929085157850456147187187334391109870818095747384924 Nov 22 01:27:59 PM PST 23 Nov 22 01:28:06 PM PST 23 108189378 ps
T1007 /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.44223366140603579009893088086368102270121537324586342307585350896701263540851 Nov 22 01:28:11 PM PST 23 Nov 22 01:28:15 PM PST 23 72403950 ps
T1008 /workspace/coverage/default/17.pwrmgr_lowpower_invalid.81753310691071335391938562744006359895024844550122770492220266427279093536607 Nov 22 01:26:48 PM PST 23 Nov 22 01:26:52 PM PST 23 49975558 ps
T1009 /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.24520611399387131495830418290778094264984388003294858495396230096934461673079 Nov 22 01:26:28 PM PST 23 Nov 22 01:26:32 PM PST 23 30368572 ps
T1010 /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.100738707015589503886148266058171351806647207147367283144853010571518937054548 Nov 22 01:27:57 PM PST 23 Nov 22 01:28:05 PM PST 23 91600225 ps
T1011 /workspace/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.26043178988378218991611449812995425979025658686439125721727575421244347984617 Nov 22 01:27:46 PM PST 23 Nov 22 01:27:59 PM PST 23 919450745 ps
T1012 /workspace/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.5003229698569208776391006078889361101228716209910003323597019071826866270238 Nov 22 01:26:43 PM PST 23 Nov 22 01:26:46 PM PST 23 314830582 ps
T1013 /workspace/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.53032097341586593317119391100798703892182458873459888480748477421907251066732 Nov 22 01:27:38 PM PST 23 Nov 22 01:27:52 PM PST 23 314830582 ps
T1014 /workspace/coverage/default/17.pwrmgr_reset_invalid.101872130345897074546092688250876369712924992660839524757715404411784067715319 Nov 22 01:26:33 PM PST 23 Nov 22 01:26:35 PM PST 23 108189378 ps
T1015 /workspace/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.109340088614637651967470434927026679828974839778361071330606383505652920138023 Nov 22 01:27:00 PM PST 23 Nov 22 01:27:19 PM PST 23 919450745 ps
T1016 /workspace/coverage/default/35.pwrmgr_wakeup.8664003268206644334410392224618505788450707267559459232836079632374829741914 Nov 22 01:27:17 PM PST 23 Nov 22 01:27:35 PM PST 23 283777259 ps
T1017 /workspace/coverage/default/38.pwrmgr_smoke.86746536140113807172529677456198810957042989289504217980385408108461695441965 Nov 22 01:27:30 PM PST 23 Nov 22 01:27:44 PM PST 23 35743529 ps
T1018 /workspace/coverage/default/31.pwrmgr_smoke.91258493226880400849949677526314401733397922040964414691525769983461894139162 Nov 22 01:27:36 PM PST 23 Nov 22 01:27:49 PM PST 23 35743529 ps
T1019 /workspace/coverage/default/25.pwrmgr_lowpower_wakeup_race.110571862218980024841974255457165678243775625973932235342970966272019426963239 Nov 22 01:26:57 PM PST 23 Nov 22 01:27:12 PM PST 23 296241445 ps
T1020 /workspace/coverage/default/19.pwrmgr_reset.96188789204836534588462177208708167045039327779558230908042467028310675159401 Nov 22 01:26:51 PM PST 23 Nov 22 01:26:59 PM PST 23 119707143 ps
T1021 /workspace/coverage/default/18.pwrmgr_aborted_low_power.114788625006726006915744040286301475555808787424056917047854942031119894529764 Nov 22 01:26:41 PM PST 23 Nov 22 01:26:43 PM PST 23 51975542 ps
T1022 /workspace/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.51167843789855082851473345486281470069852291623588279202548131040801731649671 Nov 22 01:25:58 PM PST 23 Nov 22 01:26:06 PM PST 23 968503924 ps
T1023 /workspace/coverage/default/18.pwrmgr_glitch.19284432568352103533842812652348947115320425555407325662222531351542431040154 Nov 22 01:26:40 PM PST 23 Nov 22 01:26:43 PM PST 23 39672069 ps
T1024 /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.66412159726734133082563574248206940676443909250652541744361135708586515794241 Nov 22 01:28:22 PM PST 23 Nov 22 01:28:26 PM PST 23 91600225 ps
T1025 /workspace/coverage/default/20.pwrmgr_stress_all.78026916077650379503719719065353798744603040015864084700910960237716211961642 Nov 22 01:26:50 PM PST 23 Nov 22 01:27:00 PM PST 23 2072030810 ps
T1026 /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.12326993913655440873173454045979933553493242801855809398775221721887521546699 Nov 22 01:26:55 PM PST 23 Nov 22 01:27:08 PM PST 23 30368572 ps
T1027 /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.23923752704966633093694188610772006934315553541015694115015125261945543605458 Nov 22 01:27:09 PM PST 23 Nov 22 01:27:27 PM PST 23 91600225 ps
T1028 /workspace/coverage/default/40.pwrmgr_stress_all.14423008843507992736377770571179637444782629449872401870648246980390428546653 Nov 22 01:27:49 PM PST 23 Nov 22 01:28:04 PM PST 23 2072030810 ps
T1029 /workspace/coverage/default/29.pwrmgr_stress_all.13894829603416669460537390287219324043615673180916075115297402449052056976890 Nov 22 01:27:13 PM PST 23 Nov 22 01:27:36 PM PST 23 2072030810 ps
T1030 /workspace/coverage/default/13.pwrmgr_glitch.926819654939365934609904126201884577757945309318591731845432747115565614142 Nov 22 01:26:27 PM PST 23 Nov 22 01:26:31 PM PST 23 39672069 ps
T1031 /workspace/coverage/default/6.pwrmgr_lowpower_invalid.57167047670085484039233914106108549987680994331214651289989006954142455711577 Nov 22 01:26:03 PM PST 23 Nov 22 01:26:09 PM PST 23 49975558 ps
T1032 /workspace/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.82070189660340761426524578692564889936370708293475994639911075313965764604666 Nov 22 01:27:34 PM PST 23 Nov 22 01:27:51 PM PST 23 919450745 ps
T1033 /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.52825781017168988490344164089467325085601815893505548558902467637340183256759 Nov 22 01:27:22 PM PST 23 Nov 22 01:27:38 PM PST 23 72403950 ps
T1034 /workspace/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.99450391672820179811039617031922263713999595966560125869715263830457147269653 Nov 22 01:26:57 PM PST 23 Nov 22 01:27:11 PM PST 23 314830582 ps
T1035 /workspace/coverage/default/6.pwrmgr_lowpower_wakeup_race.51820490516117393854556384138969766753680411009045116440167860222290898746195 Nov 22 01:26:26 PM PST 23 Nov 22 01:26:29 PM PST 23 296241445 ps
T1036 /workspace/coverage/default/38.pwrmgr_stress_all_with_rand_reset.91184123764931965062635543953678962818783024299293557766699392678674095368635 Nov 22 01:27:36 PM PST 23 Nov 22 01:28:00 PM PST 23 4441243999 ps
T1037 /workspace/coverage/default/15.pwrmgr_wakeup.97271184724857221128155955683192316036257033061810596399715722271051460866103 Nov 22 01:26:23 PM PST 23 Nov 22 01:26:27 PM PST 23 283777259 ps
T1038 /workspace/coverage/default/40.pwrmgr_reset_invalid.34758587098228683728711863694213352009827633895607157463587830169103981644029 Nov 22 01:27:52 PM PST 23 Nov 22 01:28:02 PM PST 23 108189378 ps
T21 /workspace/coverage/default/0.pwrmgr_sec_cm.103316430289760705154008139157698704781620945354262055001023053967998568045883 Nov 22 01:25:52 PM PST 23 Nov 22 01:26:00 PM PST 23 344080348 ps
T1039 /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.34553515049257304454272914813608193754400094484463233851787979313684522864238 Nov 22 01:26:08 PM PST 23 Nov 22 01:26:14 PM PST 23 91600225 ps
T1040 /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.59906184679652706687562141692144626674538326949445515734272944744171018522340 Nov 22 01:25:57 PM PST 23 Nov 22 01:26:02 PM PST 23 30368572 ps
T1041 /workspace/coverage/default/5.pwrmgr_stress_all_with_rand_reset.44989308007158884024741173339385196882153063342856389994803088272120584932568 Nov 22 01:26:52 PM PST 23 Nov 22 01:27:09 PM PST 23 4441243999 ps
T1042 /workspace/coverage/default/45.pwrmgr_aborted_low_power.61287626518858428059315949583950863592066970709030267915335396815672383157197 Nov 22 01:27:57 PM PST 23 Nov 22 01:28:05 PM PST 23 51975542 ps
T1043 /workspace/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.48189125144690973671976902511194112199126879062640762963630672155135262252712 Nov 22 01:27:23 PM PST 23 Nov 22 01:27:42 PM PST 23 968503924 ps
T1044 /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.12213270815940785335777782326221693113686120595924959268086022161991775124272 Nov 22 01:25:51 PM PST 23 Nov 22 01:25:58 PM PST 23 72403950 ps
T1045 /workspace/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.108355805451582725196963170317107349538327197176496150079588123420246590510362 Nov 22 01:27:30 PM PST 23 Nov 22 01:27:46 PM PST 23 919450745 ps
T1046 /workspace/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.71607109001816706045756857196144590680916402594065084022690872905641666240819 Nov 22 01:26:01 PM PST 23 Nov 22 01:26:07 PM PST 23 314830582 ps
T1047 /workspace/coverage/default/1.pwrmgr_reset.102710461155532004008917629277287376102614174372543548046970993673787215191530 Nov 22 01:25:50 PM PST 23 Nov 22 01:25:56 PM PST 23 119707143 ps
T1048 /workspace/coverage/default/8.pwrmgr_smoke.47651911780197644728547378872400235668780642668942919100896826827126888993275 Nov 22 01:26:09 PM PST 23 Nov 22 01:26:15 PM PST 23 35743529 ps
T1049 /workspace/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.104447055375664789876511370936980474323076460514791103455117459265525830536355 Nov 22 01:27:37 PM PST 23 Nov 22 01:27:53 PM PST 23 968503924 ps
T1050 /workspace/coverage/default/15.pwrmgr_reset_invalid.42689190214067882561505612594867540949861375297234294734675401522799704170223 Nov 22 01:26:41 PM PST 23 Nov 22 01:26:44 PM PST 23 108189378 ps
T1051 /workspace/coverage/default/34.pwrmgr_wakeup.1270176279593481594232297947413469138100513585133423603932084951902208906235 Nov 22 01:27:34 PM PST 23 Nov 22 01:27:48 PM PST 23 283777259 ps
T1052 /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.114485980670747615153021647708540738555810990984459093141162047535085850565666 Nov 22 01:26:03 PM PST 23 Nov 22 01:26:09 PM PST 23 30368572 ps
T1053 /workspace/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.91086397853436115878941549799686686322176357961429298243243223072753864133075 Nov 22 01:26:06 PM PST 23 Nov 22 01:26:15 PM PST 23 968503924 ps
T1054 /workspace/coverage/default/31.pwrmgr_reset.33123511024147952081600285930094532331104275796914320617365178235434418424544 Nov 22 01:27:15 PM PST 23 Nov 22 01:27:33 PM PST 23 119707143 ps
T1055 /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.79502525145475169199768253918409832875805954709387882276549810886978092776984 Nov 22 01:27:51 PM PST 23 Nov 22 01:28:01 PM PST 23 91600225 ps
T1056 /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.95261098962876578628412475479499523850015612701608983416669255426860051444819 Nov 22 01:28:24 PM PST 23 Nov 22 01:28:27 PM PST 23 30368572 ps
T1057 /workspace/coverage/default/34.pwrmgr_aborted_low_power.106239187861928489184862137332813666606797018882790660329316413107945302024199 Nov 22 01:27:30 PM PST 23 Nov 22 01:27:45 PM PST 23 51975542 ps
T1058 /workspace/coverage/default/32.pwrmgr_reset.57240518321755763149475769923112685487521093800811706842639264146502882517435 Nov 22 01:27:19 PM PST 23 Nov 22 01:27:36 PM PST 23 119707143 ps
T1059 /workspace/coverage/default/44.pwrmgr_wakeup.46500579583852222387678380886918846120099242878611035656675656808331158343708 Nov 22 01:28:04 PM PST 23 Nov 22 01:28:10 PM PST 23 283777259 ps
T1060 /workspace/coverage/default/11.pwrmgr_reset.28348373337749263718577959666260058690021649999149044373265574819842447420237 Nov 22 01:26:01 PM PST 23 Nov 22 01:26:07 PM PST 23 119707143 ps
T1061 /workspace/coverage/default/36.pwrmgr_stress_all.34409798991594460806608737988649921570021877902590595780441017350941084745271 Nov 22 01:27:32 PM PST 23 Nov 22 01:27:51 PM PST 23 2072030810 ps
T1062 /workspace/coverage/default/8.pwrmgr_global_esc.8427075393712326503201325693944612710249121738294081767635317710057846259069 Nov 22 01:26:12 PM PST 23 Nov 22 01:26:18 PM PST 23 33172121 ps
T1063 /workspace/coverage/default/18.pwrmgr_lowpower_wakeup_race.58141111513102282988930530145200025413224344819773883100138863878155770563702 Nov 22 01:26:33 PM PST 23 Nov 22 01:26:36 PM PST 23 296241445 ps
T1064 /workspace/coverage/default/9.pwrmgr_reset.87422236678172556440643397534568468015551088131415525709385023731956219329470 Nov 22 01:26:08 PM PST 23 Nov 22 01:26:14 PM PST 23 119707143 ps
T1065 /workspace/coverage/default/15.pwrmgr_reset.50788833754342594264515431198431806707453937438357220377598860963396246672493 Nov 22 01:27:06 PM PST 23 Nov 22 01:27:21 PM PST 23 119707143 ps
T1066 /workspace/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.80053526842767994897095987111080202648923072114526248056480907719776115489953 Nov 22 01:27:39 PM PST 23 Nov 22 01:27:52 PM PST 23 314830582 ps
T1067 /workspace/coverage/default/44.pwrmgr_reset_invalid.110997973501167178067039658955455523294258440117966800115361777599613518016578 Nov 22 01:28:24 PM PST 23 Nov 22 01:28:27 PM PST 23 108189378 ps
T1068 /workspace/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.44922843326248319054259924071154639706795482460531153990130808383131637848731 Nov 22 01:25:57 PM PST 23 Nov 22 01:26:05 PM PST 23 968503924 ps
T1069 /workspace/coverage/default/47.pwrmgr_glitch.27629314716236005676672812179293787233586223886082268070778903619492956163718 Nov 22 01:28:08 PM PST 23 Nov 22 01:28:11 PM PST 23 39672069 ps
T1070 /workspace/coverage/default/39.pwrmgr_reset_invalid.8144611864972742909894326130207947096383672295400078768374681893083340610244 Nov 22 01:27:35 PM PST 23 Nov 22 01:27:49 PM PST 23 108189378 ps

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.61917544866520266842569878042815185606990528734210584062005469596901269920837
Short name T8
Test name
Test status
Simulation time 919450745 ps
CPU time 2.81 seconds
Started Nov 22 01:27:10 PM PST 23
Finished Nov 22 01:27:30 PM PST 23
Peak memory 201236 kb
Host smart-52fea024-ade2-402a-92f5-64ca08393553
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619175448665202668425698780428151856069905287342105840620054
69596901269920837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.61917544866520266842569878
042815185606990528734210584062005469596901269920837
Directory /workspace/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_stress_all_with_rand_reset.55517911268694230715820044011761057156076651013796612115338990520600169980358
Short name T13
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.66 seconds
Started Nov 22 01:28:10 PM PST 23
Finished Nov 22 01:28:24 PM PST 23
Peak memory 201436 kb
Host smart-f6df75b1-4176-47ca-9de3-32ab5f12c794
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555179112686942307158200
44011761057156076651013796612115338990520600169980358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all_with_rand_reset.55517
911268694230715820044011761057156076651013796612115338990520600169980358
Directory /workspace/48.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.28146024391528230309257987107723481612155614194620374020361517430777877773262
Short name T40
Test name
Test status
Simulation time 108189378 ps
CPU time 0.86 seconds
Started Nov 22 01:27:07 PM PST 23
Finished Nov 22 01:27:22 PM PST 23
Peak memory 209432 kb
Host smart-f22fb80a-e3f0-4af1-98b9-3401fc7d40bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28146024391528230309257987107723481612155614194620374020361517430777877773262 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.28146024391528230309257987107723481612155614194620374020361517430777877773262
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.76896237239275164683627174159151529825137351331803767994339762586366974610852
Short name T42
Test name
Test status
Simulation time 131849903 ps
CPU time 1.08 seconds
Started Nov 22 12:31:55 PM PST 23
Finished Nov 22 12:31:57 PM PST 23
Peak memory 200412 kb
Host smart-382bbc89-2c1f-459c-9975-8aa362d4dfcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76896237239275164683627174159151529825137351331803767994339762586366974610852 -assert n
opostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_err.76896237239275164683627174159151529825137351331803767994339762586366974610852
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.103316430289760705154008139157698704781620945354262055001023053967998568045883
Short name T21
Test name
Test status
Simulation time 344080348 ps
CPU time 1.25 seconds
Started Nov 22 01:25:52 PM PST 23
Finished Nov 22 01:26:00 PM PST 23
Peak memory 214296 kb
Host smart-cbb79410-4e90-4388-b4c1-d9238d1c66ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103316430289760705154008139157698704781620945354262055001023053967998568045883 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.103316430289760705154008139157698704781620945354262055001023053967998568045883
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.21024674342350534469792696749598049339737219437619715669318683797942970215108
Short name T151
Test name
Test status
Simulation time 49975558 ps
CPU time 0.69 seconds
Started Nov 22 01:26:40 PM PST 23
Finished Nov 22 01:26:43 PM PST 23
Peak memory 201284 kb
Host smart-edc93d93-188f-446d-a8a5-5ba9bbc17ad4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21024674342350534469792696749598049339737219437619715669318683797942970215108 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_invalid.21024674342350534469792696749598049339737219437619715669318683797942970215108
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.20089247256693345317030071637199461036617336593006899289259450138100332106433
Short name T46
Test name
Test status
Simulation time 103760842 ps
CPU time 1.38 seconds
Started Nov 22 12:32:08 PM PST 23
Finished Nov 22 12:32:11 PM PST 23
Peak memory 200760 kb
Host smart-91e3fbdf-ed14-44f9-b2c4-8b7b49deeeed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20089247256693345317030071637199461036617336593006899289259450138100332106433 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.20089247256693345317030071637199461036617336593006899289259450138100332106433
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.48538799426747931049370584723637020941787373696763094768926735784022377247486
Short name T83
Test name
Test status
Simulation time 29315009 ps
CPU time 0.64 seconds
Started Nov 22 12:31:29 PM PST 23
Finished Nov 22 12:31:30 PM PST 23
Peak memory 197788 kb
Host smart-a5239b59-0622-4f14-ac6a-84e956c337a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48538799426747931049370584723637020941787373696763094768926735784022377247486 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.48538799426747931049370584723637020941787373696763094768926735784022377247486
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.94085830292575273099664599811861015936171111948923159244123154158840631669950
Short name T116
Test name
Test status
Simulation time 72403950 ps
CPU time 0.94 seconds
Started Nov 22 01:27:18 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 196140 kb
Host smart-695f00d4-e293-4e9f-9af6-bbd8eaa3d874
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94085830292575273099664599811861015936171111948923159244123154158840631669950 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_disable_rom_integrity_check.940858302925752730996645998118610159361711119489231592
44123154158840631669950
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.58770315722769847840486576039954843269145739672899126545565921111853455659464
Short name T65
Test name
Test status
Simulation time 23690054 ps
CPU time 0.6 seconds
Started Nov 22 12:31:46 PM PST 23
Finished Nov 22 12:31:48 PM PST 23
Peak memory 196696 kb
Host smart-27d05c39-8112-4551-8ad4-5206b9a66e3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58770315722769847840486576039954843269145739672899126545565921111853455659464 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.58770315722769847840486576039954843269145739672899126545565921111853455659464
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.57959803634602749125831482596433369949860578581403930119411223444818218037488
Short name T167
Test name
Test status
Simulation time 30368572 ps
CPU time 0.59 seconds
Started Nov 22 01:26:12 PM PST 23
Finished Nov 22 01:26:18 PM PST 23
Peak memory 195484 kb
Host smart-58957422-c35f-4fa0-a32a-74468c61ee91
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57959803634602749125831482596433369949860578581403930119411223444818218037488 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst_malfunc.57959803634602749125831482596433369949860578581403930119411223444818218037488
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.67148410425805877531725479197581246983941573971366470328334424822783581980205
Short name T158
Test name
Test status
Simulation time 314830582 ps
CPU time 1.32 seconds
Started Nov 22 01:26:36 PM PST 23
Finished Nov 22 01:26:39 PM PST 23
Peak memory 199700 kb
Host smart-6328634c-bc7d-4544-aa6e-4776e313fc61
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67148410425805877531725479197581246983941573971366470328334424822783581980205 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_ctrl_config_regwen.671484104258058775317254791975812469839415739713664703283
34424822783581980205
Directory /workspace/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.1273204322457522678617495491173447884728184885337828129733813009567983900695
Short name T87
Test name
Test status
Simulation time 44993455 ps
CPU time 0.79 seconds
Started Nov 22 12:31:51 PM PST 23
Finished Nov 22 12:31:53 PM PST 23
Peak memory 198448 kb
Host smart-88ce6905-9516-4589-8cef-b86aa8f07783
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273204322457522678617495491173447884728184885337828129733813009567983900695 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.1273204322457522678617495491173447884728184885337828129733813009567983900695
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.47280702878533908965297059345187480373895184230698330574990793003448624614912
Short name T99
Test name
Test status
Simulation time 41047058 ps
CPU time 0.7 seconds
Started Nov 22 12:31:41 PM PST 23
Finished Nov 22 12:31:45 PM PST 23
Peak memory 198088 kb
Host smart-a2015b32-756f-43f5-92e7-00f44471823c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47280702878533908965297059345187480373895184230698330574990793003448624614912
-assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_same_csr_outstanding.472807028785339089652970593451874803738951842306983305749907
93003448624614912
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.109618197624252782236810558603236155476573013426194581460687673962760680693772
Short name T217
Test name
Test status
Simulation time 249509676 ps
CPU time 2.01 seconds
Started Nov 22 12:31:37 PM PST 23
Finished Nov 22 12:31:40 PM PST 23
Peak memory 200704 kb
Host smart-cbc5a596-4054-4037-98bf-c2611c9fcf93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109618197624252782236810558603236155476573013426194581460687673962760680693772 -assert nop
ostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.109618197624252782236810558603236155476573013426194581460687673962760680693772
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.29579663383595878788242431612602073150027509136803398546540564955815932392045
Short name T268
Test name
Test status
Simulation time 39797068 ps
CPU time 0.69 seconds
Started Nov 22 12:31:41 PM PST 23
Finished Nov 22 12:31:44 PM PST 23
Peak memory 200380 kb
Host smart-6253cc34-2889-43da-94f3-e3e991af43f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957966338359587878824243161260207315002750
9136803398546540564955815932392045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.2957966338359587878
8242431612602073150027509136803398546540564955815932392045
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.105393492799225395325428764387414616520720056962924001214926503630300063653850
Short name T89
Test name
Test status
Simulation time 24672189 ps
CPU time 0.6 seconds
Started Nov 22 12:31:40 PM PST 23
Finished Nov 22 12:31:44 PM PST 23
Peak memory 197124 kb
Host smart-58ab50a0-c72b-49e1-b643-ef8f15257f24
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105393492799225395325428764387414616520720056962924001214926503630300063653850 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.105393492799225395325428764387414616520720056962924001214926503630300063653850
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.94967062133805779932849830556202724819198617753753986930822899766921872096454
Short name T196
Test name
Test status
Simulation time 23690054 ps
CPU time 0.61 seconds
Started Nov 22 12:31:29 PM PST 23
Finished Nov 22 12:31:30 PM PST 23
Peak memory 196716 kb
Host smart-a3eefa7a-3358-49e7-b44c-db0945260d42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94967062133805779932849830556202724819198617753753986930822899766921872096454 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.94967062133805779932849830556202724819198617753753986930822899766921872096454
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.113334394479870436903517994213095834205325879780243923451849272701384720396479
Short name T282
Test name
Test status
Simulation time 41047058 ps
CPU time 0.71 seconds
Started Nov 22 12:31:53 PM PST 23
Finished Nov 22 12:31:56 PM PST 23
Peak memory 198004 kb
Host smart-f6e548b1-08c2-4721-ae47-f0c9a8962339
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113334394479870436903517994213095834205325879780243923451849272701384720396479
-assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_same_csr_outstanding.11333439447987043690351799421309583420532587978024392345184
9272701384720396479
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.76934620766960136763718626317632962263747197636049167770693243526048492076988
Short name T279
Test name
Test status
Simulation time 103760842 ps
CPU time 1.46 seconds
Started Nov 22 12:31:48 PM PST 23
Finished Nov 22 12:31:52 PM PST 23
Peak memory 200768 kb
Host smart-d21402d2-e587-47e5-8b4b-cb9f155476ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76934620766960136763718626317632962263747197636049167770693243526048492076988 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.76934620766960136763718626317632962263747197636049167770693243526048492076988
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.5866274180099300990630160303476983638548106444087043059176528713380424488080
Short name T233
Test name
Test status
Simulation time 131849903 ps
CPU time 1.09 seconds
Started Nov 22 12:31:32 PM PST 23
Finished Nov 22 12:31:34 PM PST 23
Peak memory 200540 kb
Host smart-a070b959-b2ad-4bc7-90fb-f437821b344d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5866274180099300990630160303476983638548106444087043059176528713380424488080 -assert no
postproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err.5866274180099300990630160303476983638548106444087043059176528713380424488080
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.35181046867134860935346688508834438136748695596581023552666422834524340946391
Short name T95
Test name
Test status
Simulation time 44993455 ps
CPU time 0.81 seconds
Started Nov 22 12:31:37 PM PST 23
Finished Nov 22 12:31:39 PM PST 23
Peak memory 198444 kb
Host smart-4400d528-481a-4972-9dcd-ab0207d82f5a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35181046867134860935346688508834438136748695596581023552666422834524340946391 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.35181046867134860935346688508834438136748695596581023552666422834524340946391
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.29952478379113073036726412169955081478265062253008203421846694830515463935974
Short name T247
Test name
Test status
Simulation time 249509676 ps
CPU time 1.96 seconds
Started Nov 22 12:31:56 PM PST 23
Finished Nov 22 12:31:59 PM PST 23
Peak memory 200684 kb
Host smart-ee10a026-0f1d-4298-9800-0c6e6009f8ed
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29952478379113073036726412169955081478265062253008203421846694830515463935974 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.29952478379113073036726412169955081478265062253008203421846694830515463935974
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.66710369483871965709066715342615312332727234233551107372996814376659402186029
Short name T93
Test name
Test status
Simulation time 29315009 ps
CPU time 0.64 seconds
Started Nov 22 12:31:32 PM PST 23
Finished Nov 22 12:31:34 PM PST 23
Peak memory 197788 kb
Host smart-a0576c51-1053-446a-92f9-e6678866217b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66710369483871965709066715342615312332727234233551107372996814376659402186029 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.66710369483871965709066715342615312332727234233551107372996814376659402186029
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.74836419494228049062993546404440851013552924194782387484709467175927359902529
Short name T74
Test name
Test status
Simulation time 39797068 ps
CPU time 0.7 seconds
Started Nov 22 12:31:41 PM PST 23
Finished Nov 22 12:31:45 PM PST 23
Peak memory 200420 kb
Host smart-de164491-3ec0-4ae6-8e27-b4d752341309
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7483641949422804906299354640444085101355292
4194782387484709467175927359902529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.7483641949422804906
2993546404440851013552924194782387484709467175927359902529
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.61892080262825005948225439553806388041509399206857993565480727076827768881225
Short name T209
Test name
Test status
Simulation time 24672189 ps
CPU time 0.64 seconds
Started Nov 22 12:31:31 PM PST 23
Finished Nov 22 12:31:33 PM PST 23
Peak memory 197192 kb
Host smart-66ac700c-237a-4c07-80a5-cda7f54673f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61892080262825005948225439553806388041509399206857993565480727076827768881225 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.61892080262825005948225439553806388041509399206857993565480727076827768881225
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.29888933288517652272246447955299876093030980059758206976423574922120896850400
Short name T216
Test name
Test status
Simulation time 103760842 ps
CPU time 1.42 seconds
Started Nov 22 12:31:35 PM PST 23
Finished Nov 22 12:31:39 PM PST 23
Peak memory 200616 kb
Host smart-1320223f-e8da-4e40-9bb7-0b400936052a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29888933288517652272246447955299876093030980059758206976423574922120896850400 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.29888933288517652272246447955299876093030980059758206976423574922120896850400
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.34427983596550669858424704627284925936871375423460198557718017466223957109407
Short name T193
Test name
Test status
Simulation time 131849903 ps
CPU time 1.09 seconds
Started Nov 22 12:31:30 PM PST 23
Finished Nov 22 12:31:32 PM PST 23
Peak memory 200540 kb
Host smart-80487f08-2476-4aaf-a514-c0fe5ad616fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34427983596550669858424704627284925936871375423460198557718017466223957109407 -assert n
opostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err.34427983596550669858424704627284925936871375423460198557718017466223957109407
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.7675790873073386545394668702751126435349477623615113568584549019082664351648
Short name T228
Test name
Test status
Simulation time 39797068 ps
CPU time 0.69 seconds
Started Nov 22 12:31:47 PM PST 23
Finished Nov 22 12:31:48 PM PST 23
Peak memory 200412 kb
Host smart-91e09673-3386-48fb-a90c-b6169793583d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7675790873073386545394668702751126435349477
623615113568584549019082664351648 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.7675790873073386545
394668702751126435349477623615113568584549019082664351648
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.76213282899246032586198858377695716824054280867598564097269016736388713027872
Short name T81
Test name
Test status
Simulation time 24672189 ps
CPU time 0.6 seconds
Started Nov 22 12:31:38 PM PST 23
Finished Nov 22 12:31:40 PM PST 23
Peak memory 197304 kb
Host smart-ea712a64-c56f-41dd-a0db-c895f00b23ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76213282899246032586198858377695716824054280867598564097269016736388713027872 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.76213282899246032586198858377695716824054280867598564097269016736388713027872
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.25512067934091854579497525508902201674078728004567311308894518892434293428132
Short name T273
Test name
Test status
Simulation time 23690054 ps
CPU time 0.6 seconds
Started Nov 22 12:31:55 PM PST 23
Finished Nov 22 12:31:57 PM PST 23
Peak memory 196720 kb
Host smart-a5899b97-6ad6-473e-a5d0-c1e552a29cba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25512067934091854579497525508902201674078728004567311308894518892434293428132 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.25512067934091854579497525508902201674078728004567311308894518892434293428132
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.11965891803954693299901703651523480020759503165522272943570836884056327673736
Short name T86
Test name
Test status
Simulation time 41047058 ps
CPU time 0.67 seconds
Started Nov 22 12:31:46 PM PST 23
Finished Nov 22 12:31:47 PM PST 23
Peak memory 198024 kb
Host smart-d1b08ecd-b240-46a9-b22d-c8150b50ccf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11965891803954693299901703651523480020759503165522272943570836884056327673736
-assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_same_csr_outstanding.11965891803954693299901703651523480020759503165522272943570
836884056327673736
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.101854129343557775025737575095821403393303815049549838043619293811681824494381
Short name T71
Test name
Test status
Simulation time 103760842 ps
CPU time 1.38 seconds
Started Nov 22 12:31:46 PM PST 23
Finished Nov 22 12:31:48 PM PST 23
Peak memory 200756 kb
Host smart-40ee1d6d-0ced-43b0-b7e4-8c7d4295675f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101854129343557775025737575095821403393303815049549838043619293811681824494381 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.101854129343557775025737575095821403393303815049549838043619293811681824494381
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.53687883456913728933223194955982378271569140848853482373308240649883589887892
Short name T197
Test name
Test status
Simulation time 131849903 ps
CPU time 1.1 seconds
Started Nov 22 12:31:46 PM PST 23
Finished Nov 22 12:31:48 PM PST 23
Peak memory 200404 kb
Host smart-726e8301-056e-45dc-a4de-f73b0d41b952
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53687883456913728933223194955982378271569140848853482373308240649883589887892 -assert n
opostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err.53687883456913728933223194955982378271569140848853482373308240649883589887892
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.29832270578695022724440352709957909994731229934341581239917308300592347962360
Short name T199
Test name
Test status
Simulation time 39797068 ps
CPU time 0.7 seconds
Started Nov 22 12:32:00 PM PST 23
Finished Nov 22 12:32:03 PM PST 23
Peak memory 200392 kb
Host smart-a390d439-41b6-40b0-9c86-bd56b32140b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983227057869502272444035270995790999473122
9934341581239917308300592347962360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.298322705786950227
24440352709957909994731229934341581239917308300592347962360
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.60935640669044104745507308099179264812704176722917734653986020544545693156287
Short name T253
Test name
Test status
Simulation time 24672189 ps
CPU time 0.62 seconds
Started Nov 22 12:31:56 PM PST 23
Finished Nov 22 12:31:58 PM PST 23
Peak memory 197144 kb
Host smart-9ef197fd-65bb-49b0-bf25-096647752dd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60935640669044104745507308099179264812704176722917734653986020544545693156287 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.60935640669044104745507308099179264812704176722917734653986020544545693156287
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.45064806411386962033692945727764725036583487511162407437009963198979185303067
Short name T210
Test name
Test status
Simulation time 23690054 ps
CPU time 0.6 seconds
Started Nov 22 12:31:57 PM PST 23
Finished Nov 22 12:31:59 PM PST 23
Peak memory 196680 kb
Host smart-880a585a-7604-4bf8-9f5e-be6b020c56ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45064806411386962033692945727764725036583487511162407437009963198979185303067 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.45064806411386962033692945727764725036583487511162407437009963198979185303067
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.78773993097936892974580655965103433562633030523692765094411282695616715902187
Short name T51
Test name
Test status
Simulation time 41047058 ps
CPU time 0.68 seconds
Started Nov 22 12:31:58 PM PST 23
Finished Nov 22 12:32:01 PM PST 23
Peak memory 198016 kb
Host smart-37b8ad8b-a7bc-4381-9fd6-4fea626bd961
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78773993097936892974580655965103433562633030523692765094411282695616715902187
-assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_same_csr_outstanding.78773993097936892974580655965103433562633030523692765094411
282695616715902187
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.37808560871953779236458749373107738744502556099672766564917511516949963989787
Short name T224
Test name
Test status
Simulation time 103760842 ps
CPU time 1.41 seconds
Started Nov 22 12:31:55 PM PST 23
Finished Nov 22 12:31:57 PM PST 23
Peak memory 200792 kb
Host smart-eba3bd07-c649-4e04-a533-ce0169d55771
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37808560871953779236458749373107738744502556099672766564917511516949963989787 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.37808560871953779236458749373107738744502556099672766564917511516949963989787
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.16633944777802905612002252914615586528971084874235045603983423701512004994778
Short name T259
Test name
Test status
Simulation time 131849903 ps
CPU time 1.07 seconds
Started Nov 22 12:31:53 PM PST 23
Finished Nov 22 12:31:56 PM PST 23
Peak memory 200432 kb
Host smart-f3a3280c-45eb-4606-b93b-8e656892fe57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16633944777802905612002252914615586528971084874235045603983423701512004994778 -assert n
opostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_err.16633944777802905612002252914615586528971084874235045603983423701512004994778
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.107345542993123824304834396963304730552444994928708495873885502204160888400134
Short name T260
Test name
Test status
Simulation time 39797068 ps
CPU time 0.7 seconds
Started Nov 22 12:32:00 PM PST 23
Finished Nov 22 12:32:03 PM PST 23
Peak memory 200412 kb
Host smart-dccb114a-157e-4ffd-a6d0-a9c30841d26d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073455429931238243048343969633047305524449
94928708495873885502204160888400134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.10734554299312382
4304834396963304730552444994928708495873885502204160888400134
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.42959498853142698390819916077923812253558911811832197090170092292251558541189
Short name T271
Test name
Test status
Simulation time 24672189 ps
CPU time 0.62 seconds
Started Nov 22 12:33:13 PM PST 23
Finished Nov 22 12:33:16 PM PST 23
Peak memory 197156 kb
Host smart-820db38c-7e9e-4ca3-83f3-5727a875ea49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42959498853142698390819916077923812253558911811832197090170092292251558541189 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.42959498853142698390819916077923812253558911811832197090170092292251558541189
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.81890421370145074147448035219686956995981909029196149716050539362400211533418
Short name T85
Test name
Test status
Simulation time 23690054 ps
CPU time 0.58 seconds
Started Nov 22 12:32:01 PM PST 23
Finished Nov 22 12:32:03 PM PST 23
Peak memory 196512 kb
Host smart-b78fde4b-916f-4e47-8aa1-ca9eb372fb61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81890421370145074147448035219686956995981909029196149716050539362400211533418 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.81890421370145074147448035219686956995981909029196149716050539362400211533418
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.56490574471165207852857327594912825031908721297172336710173118948632008497467
Short name T98
Test name
Test status
Simulation time 41047058 ps
CPU time 0.7 seconds
Started Nov 22 12:32:01 PM PST 23
Finished Nov 22 12:32:03 PM PST 23
Peak memory 198008 kb
Host smart-80b6120a-1630-4c83-bcca-f18dde4351b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56490574471165207852857327594912825031908721297172336710173118948632008497467
-assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_same_csr_outstanding.56490574471165207852857327594912825031908721297172336710173
118948632008497467
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.52821069998074811464391820764466621427916424825745519782584277317320548486659
Short name T285
Test name
Test status
Simulation time 103760842 ps
CPU time 1.48 seconds
Started Nov 22 12:33:12 PM PST 23
Finished Nov 22 12:33:17 PM PST 23
Peak memory 200756 kb
Host smart-525fc7b0-52a0-4ae7-b814-113170218aee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52821069998074811464391820764466621427916424825745519782584277317320548486659 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.52821069998074811464391820764466621427916424825745519782584277317320548486659
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.77368798853743668958845790161159721327569717415653484392025466863271063885430
Short name T77
Test name
Test status
Simulation time 39797068 ps
CPU time 0.7 seconds
Started Nov 22 12:32:00 PM PST 23
Finished Nov 22 12:32:02 PM PST 23
Peak memory 200412 kb
Host smart-bc771acd-7adb-4502-90b4-5c4df8f9161e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7736879885374366895884579016115972132756971
7415653484392025466863271063885430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.773687988537436689
58845790161159721327569717415653484392025466863271063885430
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.68977141825184171199706180218556335813178476840405998319191079659067438734654
Short name T239
Test name
Test status
Simulation time 24672189 ps
CPU time 0.61 seconds
Started Nov 22 12:31:57 PM PST 23
Finished Nov 22 12:32:00 PM PST 23
Peak memory 197176 kb
Host smart-e06d523f-a83f-45cd-9ea5-50224b0ea785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68977141825184171199706180218556335813178476840405998319191079659067438734654 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.68977141825184171199706180218556335813178476840405998319191079659067438734654
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.57619905326074908495606598156708462348562840231340121523427553938050393111429
Short name T64
Test name
Test status
Simulation time 23690054 ps
CPU time 0.58 seconds
Started Nov 22 12:32:06 PM PST 23
Finished Nov 22 12:32:07 PM PST 23
Peak memory 196684 kb
Host smart-65d1e3bf-5dfd-436b-977e-9a61bf2bf7fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57619905326074908495606598156708462348562840231340121523427553938050393111429 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.57619905326074908495606598156708462348562840231340121523427553938050393111429
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.73493733125111544841126842838336571623397820597786188482578651872271942305574
Short name T256
Test name
Test status
Simulation time 41047058 ps
CPU time 0.71 seconds
Started Nov 22 12:31:51 PM PST 23
Finished Nov 22 12:31:53 PM PST 23
Peak memory 198244 kb
Host smart-26cb46d4-deb7-40f4-9fa8-b82ced8ee825
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73493733125111544841126842838336571623397820597786188482578651872271942305574
-assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_same_csr_outstanding.73493733125111544841126842838336571623397820597786188482578
651872271942305574
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.3392718888400017678157680031729464930476488552089874702923868925272422390173
Short name T68
Test name
Test status
Simulation time 103760842 ps
CPU time 1.4 seconds
Started Nov 22 12:31:48 PM PST 23
Finished Nov 22 12:31:52 PM PST 23
Peak memory 200788 kb
Host smart-7d5872bd-99e9-47da-9cd4-de4010982451
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392718888400017678157680031729464930476488552089874702923868925272422390173 -assert nopostproc +UV
M_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.3392718888400017678157680031729464930476488552089874702923868925272422390173
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.106577329034141694734564004129425292122389424651620934297598777039224024555907
Short name T58
Test name
Test status
Simulation time 131849903 ps
CPU time 1.08 seconds
Started Nov 22 12:32:00 PM PST 23
Finished Nov 22 12:32:03 PM PST 23
Peak memory 200384 kb
Host smart-a95656b5-3e63-4f4c-ac12-7934aa633f7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106577329034141694734564004129425292122389424651620934297598777039224024555907 -assert
nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_err.106577329034141694734564004129425292122389424651620934297598777039224024555907
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.77215916629060646211005513921348306487519644377049899423205573263084709564217
Short name T232
Test name
Test status
Simulation time 39797068 ps
CPU time 0.71 seconds
Started Nov 22 12:32:01 PM PST 23
Finished Nov 22 12:32:03 PM PST 23
Peak memory 200404 kb
Host smart-7ad59ffa-ee22-4e2c-8aa5-8bb22c28059a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7721591662906064621100551392134830648751964
4377049899423205573263084709564217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.772159166290606462
11005513921348306487519644377049899423205573263084709564217
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.105579563506835533620897756095843072689611202119471711057322623340521282117980
Short name T191
Test name
Test status
Simulation time 24672189 ps
CPU time 0.6 seconds
Started Nov 22 12:32:00 PM PST 23
Finished Nov 22 12:32:02 PM PST 23
Peak memory 197140 kb
Host smart-b1259793-5992-4d7b-ab81-b5029f248bec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105579563506835533620897756095843072689611202119471711057322623340521282117980 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.105579563506835533620897756095843072689611202119471711057322623340521282117980
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.60714976038055222964246388026345053056793757093991413251510997943239934247335
Short name T281
Test name
Test status
Simulation time 23690054 ps
CPU time 0.58 seconds
Started Nov 22 12:33:22 PM PST 23
Finished Nov 22 12:33:24 PM PST 23
Peak memory 196776 kb
Host smart-d6512994-7634-4fea-92a2-18c326c46567
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60714976038055222964246388026345053056793757093991413251510997943239934247335 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.60714976038055222964246388026345053056793757093991413251510997943239934247335
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.109059871411888907837464306788932784770878790859700313800078458960839246549172
Short name T97
Test name
Test status
Simulation time 41047058 ps
CPU time 0.71 seconds
Started Nov 22 12:31:51 PM PST 23
Finished Nov 22 12:31:53 PM PST 23
Peak memory 198244 kb
Host smart-fb58d3de-3594-474c-9f5f-a96c72ec6382
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109059871411888907837464306788932784770878790859700313800078458960839246549172
-assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_same_csr_outstanding.1090598714118889078374643067889327847708787908597003138000
78458960839246549172
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.22584719970839871122491277103590311783064722332770388249769231182731898913466
Short name T257
Test name
Test status
Simulation time 131849903 ps
CPU time 1.14 seconds
Started Nov 22 12:32:10 PM PST 23
Finished Nov 22 12:32:12 PM PST 23
Peak memory 199588 kb
Host smart-7dadd135-5f3c-48bd-8ad2-3439fcfc3ef1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22584719970839871122491277103590311783064722332770388249769231182731898913466 -assert n
opostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_err.22584719970839871122491277103590311783064722332770388249769231182731898913466
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.56751510423499795733942403232296556976947249175872310067974130276755901186709
Short name T194
Test name
Test status
Simulation time 39797068 ps
CPU time 0.71 seconds
Started Nov 22 12:32:09 PM PST 23
Finished Nov 22 12:32:11 PM PST 23
Peak memory 200416 kb
Host smart-6f88703c-03d6-4bd1-889d-39f5fda61621
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5675151042349979573394240323229655697694724
9175872310067974130276755901186709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.567515104234997957
33942403232296556976947249175872310067974130276755901186709
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.71750205636500512010446127008708782587305909001300840577354713373643737827973
Short name T254
Test name
Test status
Simulation time 24672189 ps
CPU time 0.64 seconds
Started Nov 22 12:31:56 PM PST 23
Finished Nov 22 12:31:57 PM PST 23
Peak memory 197196 kb
Host smart-0dab51b4-9608-46f5-8ab7-0649b34576b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71750205636500512010446127008708782587305909001300840577354713373643737827973 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.71750205636500512010446127008708782587305909001300840577354713373643737827973
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.11101018303085526331967249871415782817375247460209623850418415713701073779230
Short name T205
Test name
Test status
Simulation time 23690054 ps
CPU time 0.59 seconds
Started Nov 22 12:32:01 PM PST 23
Finished Nov 22 12:32:07 PM PST 23
Peak memory 196764 kb
Host smart-e21b49d3-0a55-4909-b4e8-dc2e37965e23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11101018303085526331967249871415782817375247460209623850418415713701073779230 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.11101018303085526331967249871415782817375247460209623850418415713701073779230
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1626155096649196196177378014129284472896660472287972075073962016521185894274
Short name T272
Test name
Test status
Simulation time 41047058 ps
CPU time 0.69 seconds
Started Nov 22 12:31:59 PM PST 23
Finished Nov 22 12:32:02 PM PST 23
Peak memory 198060 kb
Host smart-02fbdb09-2815-4a67-9cff-2edee45f0b21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626155096649196196177378014129284472896660472287972075073962016521185894274 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_same_csr_outstanding.162615509664919619617737801412928447289666047228797207507396
2016521185894274
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.111506067542565374498997533085077553499845120390213601566043423648931417915342
Short name T45
Test name
Test status
Simulation time 103760842 ps
CPU time 1.36 seconds
Started Nov 22 12:31:55 PM PST 23
Finished Nov 22 12:31:58 PM PST 23
Peak memory 200820 kb
Host smart-53d02be4-f182-4fb9-9b29-ba9ea94ac7c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111506067542565374498997533085077553499845120390213601566043423648931417915342 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.111506067542565374498997533085077553499845120390213601566043423648931417915342
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.33232054438914570015159584651327045999860785480826490528801353978255905734153
Short name T60
Test name
Test status
Simulation time 131849903 ps
CPU time 1.07 seconds
Started Nov 22 12:31:57 PM PST 23
Finished Nov 22 12:32:00 PM PST 23
Peak memory 200416 kb
Host smart-ab467a6d-0dc5-4eec-b739-ca153e7e0e0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33232054438914570015159584651327045999860785480826490528801353978255905734153 -assert n
opostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_err.33232054438914570015159584651327045999860785480826490528801353978255905734153
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.71660395875162856510750685842735436537108284363047075654447364049953534492782
Short name T215
Test name
Test status
Simulation time 39797068 ps
CPU time 0.7 seconds
Started Nov 22 12:32:00 PM PST 23
Finished Nov 22 12:32:02 PM PST 23
Peak memory 200416 kb
Host smart-5ae4fb72-8afc-4f2a-a2e3-ca7ec0f42c3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7166039587516285651075068584273543653710828
4363047075654447364049953534492782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.716603958751628565
10750685842735436537108284363047075654447364049953534492782
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1415932487750411958101297394529598611134769337327527699673549814609240731415
Short name T223
Test name
Test status
Simulation time 24672189 ps
CPU time 0.6 seconds
Started Nov 22 12:31:57 PM PST 23
Finished Nov 22 12:32:00 PM PST 23
Peak memory 197172 kb
Host smart-45f1ca0d-9f81-4760-98db-c13e21880e87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415932487750411958101297394529598611134769337327527699673549814609240731415 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.1415932487750411958101297394529598611134769337327527699673549814609240731415
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.96987817035669896461140082508117098159094349295843206944279566163330778587912
Short name T243
Test name
Test status
Simulation time 23690054 ps
CPU time 0.6 seconds
Started Nov 22 12:32:00 PM PST 23
Finished Nov 22 12:32:02 PM PST 23
Peak memory 196700 kb
Host smart-d0155bc7-8502-4774-81d2-16b8b4b58270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96987817035669896461140082508117098159094349295843206944279566163330778587912 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.96987817035669896461140082508117098159094349295843206944279566163330778587912
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.64655831002379429588243028455718968718110644075871090975969781719981560820717
Short name T231
Test name
Test status
Simulation time 41047058 ps
CPU time 0.67 seconds
Started Nov 22 12:32:13 PM PST 23
Finished Nov 22 12:32:16 PM PST 23
Peak memory 198040 kb
Host smart-f5ab3a16-5b5c-47dd-b936-bd6a5c8c4db9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64655831002379429588243028455718968718110644075871090975969781719981560820717
-assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_same_csr_outstanding.64655831002379429588243028455718968718110644075871090975969
781719981560820717
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.47687774082073998671039447320217488509709391048824927810803529918988814858832
Short name T69
Test name
Test status
Simulation time 103760842 ps
CPU time 1.42 seconds
Started Nov 22 12:31:58 PM PST 23
Finished Nov 22 12:32:01 PM PST 23
Peak memory 200784 kb
Host smart-dd91822e-badf-4aec-a858-0d6747f2ad1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47687774082073998671039447320217488509709391048824927810803529918988814858832 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.47687774082073998671039447320217488509709391048824927810803529918988814858832
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.47626510438240730694835306886549644828775424495525583692340263261323608965848
Short name T44
Test name
Test status
Simulation time 131849903 ps
CPU time 1.07 seconds
Started Nov 22 12:32:01 PM PST 23
Finished Nov 22 12:32:04 PM PST 23
Peak memory 200120 kb
Host smart-07081c8a-cb87-43af-a3cc-672bfd4cede4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47626510438240730694835306886549644828775424495525583692340263261323608965848 -assert n
opostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_err.47626510438240730694835306886549644828775424495525583692340263261323608965848
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.101951741957914888088780890482639074785708988610106328495956068156761456974753
Short name T66
Test name
Test status
Simulation time 39797068 ps
CPU time 0.7 seconds
Started Nov 22 12:31:59 PM PST 23
Finished Nov 22 12:32:02 PM PST 23
Peak memory 200436 kb
Host smart-7f9948a5-b3f2-42d5-9e7d-75cda77aa239
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019517419579148880887808904826390747857089
88610106328495956068156761456974753 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.10195174195791488
8088780890482639074785708988610106328495956068156761456974753
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.34245741840302211746671678292058493826487977663599240862783755967044342849339
Short name T280
Test name
Test status
Simulation time 24672189 ps
CPU time 0.62 seconds
Started Nov 22 12:32:10 PM PST 23
Finished Nov 22 12:32:12 PM PST 23
Peak memory 197164 kb
Host smart-5e502355-36b4-44c9-9e36-4124a75f18ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34245741840302211746671678292058493826487977663599240862783755967044342849339 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.34245741840302211746671678292058493826487977663599240862783755967044342849339
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.71567067458878442512954030264865276619971144721906622199968257123527182693717
Short name T237
Test name
Test status
Simulation time 23690054 ps
CPU time 0.58 seconds
Started Nov 22 12:32:01 PM PST 23
Finished Nov 22 12:32:03 PM PST 23
Peak memory 196720 kb
Host smart-74165550-ed8a-4464-9026-cb8f1918fbd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71567067458878442512954030264865276619971144721906622199968257123527182693717 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.71567067458878442512954030264865276619971144721906622199968257123527182693717
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.20045994883949130940357029670691399625029502846823922152528950137488691270034
Short name T278
Test name
Test status
Simulation time 41047058 ps
CPU time 0.67 seconds
Started Nov 22 12:31:56 PM PST 23
Finished Nov 22 12:31:58 PM PST 23
Peak memory 198064 kb
Host smart-51e23472-0d77-41cc-83f2-182122077b67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20045994883949130940357029670691399625029502846823922152528950137488691270034
-assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_same_csr_outstanding.20045994883949130940357029670691399625029502846823922152528
950137488691270034
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.96272941276890728087615706118956053248016380940371222031675512036151068466078
Short name T47
Test name
Test status
Simulation time 103760842 ps
CPU time 1.52 seconds
Started Nov 22 12:31:49 PM PST 23
Finished Nov 22 12:31:52 PM PST 23
Peak memory 200796 kb
Host smart-dd7d215b-d515-42b9-bb16-a4a89827ebc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96272941276890728087615706118956053248016380940371222031675512036151068466078 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.96272941276890728087615706118956053248016380940371222031675512036151068466078
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.36500389957018515700003080479130589205337685064988464902505170449916117575382
Short name T265
Test name
Test status
Simulation time 131849903 ps
CPU time 1.13 seconds
Started Nov 22 12:31:48 PM PST 23
Finished Nov 22 12:31:52 PM PST 23
Peak memory 200536 kb
Host smart-35ba5f4b-51b1-49e1-9b11-b5019071e179
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36500389957018515700003080479130589205337685064988464902505170449916117575382 -assert n
opostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_err.36500389957018515700003080479130589205337685064988464902505170449916117575382
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.113743914518727568792825076736286261027206080906436190997518397890151235774071
Short name T248
Test name
Test status
Simulation time 39797068 ps
CPU time 0.72 seconds
Started Nov 22 12:32:09 PM PST 23
Finished Nov 22 12:32:11 PM PST 23
Peak memory 200408 kb
Host smart-4784c7e7-0056-497e-999e-c24500b2acc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137439145187275687928250767362862610272060
80906436190997518397890151235774071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.11374391451872756
8792825076736286261027206080906436190997518397890151235774071
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.61421051087011258174745856121252056941371337449125892296891535814993764924101
Short name T80
Test name
Test status
Simulation time 24672189 ps
CPU time 0.63 seconds
Started Nov 22 12:32:00 PM PST 23
Finished Nov 22 12:32:02 PM PST 23
Peak memory 197176 kb
Host smart-7fd96267-64b2-464f-a022-ee648b34f788
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61421051087011258174745856121252056941371337449125892296891535814993764924101 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.61421051087011258174745856121252056941371337449125892296891535814993764924101
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.13979111099491504498569127615924112025626842969717021151152918908631627876387
Short name T195
Test name
Test status
Simulation time 23690054 ps
CPU time 0.62 seconds
Started Nov 22 12:32:00 PM PST 23
Finished Nov 22 12:32:03 PM PST 23
Peak memory 196700 kb
Host smart-7537dc20-635f-41c5-a8b7-64ba14542169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13979111099491504498569127615924112025626842969717021151152918908631627876387 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.13979111099491504498569127615924112025626842969717021151152918908631627876387
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.98123206191100646413422624125484054919217993803531265965887761699203169246305
Short name T266
Test name
Test status
Simulation time 41047058 ps
CPU time 0.7 seconds
Started Nov 22 12:31:55 PM PST 23
Finished Nov 22 12:31:56 PM PST 23
Peak memory 198040 kb
Host smart-c79c2ad4-0e14-4d77-8490-c3792f55692e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98123206191100646413422624125484054919217993803531265965887761699203169246305
-assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_same_csr_outstanding.98123206191100646413422624125484054919217993803531265965887
761699203169246305
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.68319851329952428915596277694338485048741294913829345047230108954220507535501
Short name T61
Test name
Test status
Simulation time 103760842 ps
CPU time 1.41 seconds
Started Nov 22 12:32:01 PM PST 23
Finished Nov 22 12:32:04 PM PST 23
Peak memory 200792 kb
Host smart-af6eb5da-ba4f-467d-8eec-8a62ba8959e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68319851329952428915596277694338485048741294913829345047230108954220507535501 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.68319851329952428915596277694338485048741294913829345047230108954220507535501
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.23952244869835289574243423056810423124357551434111600186603641690914071459851
Short name T222
Test name
Test status
Simulation time 131849903 ps
CPU time 1.07 seconds
Started Nov 22 12:32:00 PM PST 23
Finished Nov 22 12:32:02 PM PST 23
Peak memory 200416 kb
Host smart-90c3c9d8-d2c4-4e2d-9a87-ca0318985479
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23952244869835289574243423056810423124357551434111600186603641690914071459851 -assert n
opostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_err.23952244869835289574243423056810423124357551434111600186603641690914071459851
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.49354493447928750730941659181470221836745620317469038445784630877127818743251
Short name T190
Test name
Test status
Simulation time 39797068 ps
CPU time 0.7 seconds
Started Nov 22 12:32:12 PM PST 23
Finished Nov 22 12:32:15 PM PST 23
Peak memory 200428 kb
Host smart-38e5980b-1dd1-4c84-a12f-8b2fbcf61a40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4935449344792875073094165918147022183674562
0317469038445784630877127818743251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.493544934479287507
30941659181470221836745620317469038445784630877127818743251
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.20131411445419002259859887035863180752231651589129596122844387081327722496810
Short name T277
Test name
Test status
Simulation time 24672189 ps
CPU time 0.63 seconds
Started Nov 22 12:32:12 PM PST 23
Finished Nov 22 12:32:14 PM PST 23
Peak memory 197180 kb
Host smart-90544fc7-1783-42fc-bb78-22c623566883
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20131411445419002259859887035863180752231651589129596122844387081327722496810 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.20131411445419002259859887035863180752231651589129596122844387081327722496810
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.615729620854270407872150873300020581571437391382631504378901489451872153258
Short name T75
Test name
Test status
Simulation time 23690054 ps
CPU time 0.59 seconds
Started Nov 22 12:31:57 PM PST 23
Finished Nov 22 12:32:00 PM PST 23
Peak memory 196716 kb
Host smart-720b6f6e-a023-4c94-98dc-bfbe84caca1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615729620854270407872150873300020581571437391382631504378901489451872153258 -assert nopostproc +UVM
_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.615729620854270407872150873300020581571437391382631504378901489451872153258
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2924428807004069318741274421303407488645451519348610120907278246773868559307
Short name T62
Test name
Test status
Simulation time 41047058 ps
CPU time 0.73 seconds
Started Nov 22 12:32:00 PM PST 23
Finished Nov 22 12:32:02 PM PST 23
Peak memory 197980 kb
Host smart-42f8faef-1a7d-4c07-96ec-028724e2b444
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924428807004069318741274421303407488645451519348610120907278246773868559307 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_same_csr_outstanding.292442880700406931874127442130340748864545151934861012090727
8246773868559307
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.30780438869156010910523869909904961142990921324633227826328266568191435253214
Short name T67
Test name
Test status
Simulation time 103760842 ps
CPU time 1.43 seconds
Started Nov 22 12:32:02 PM PST 23
Finished Nov 22 12:32:05 PM PST 23
Peak memory 200832 kb
Host smart-481bbe07-054f-4cd9-88a1-0a0bc3e6b00e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30780438869156010910523869909904961142990921324633227826328266568191435253214 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.30780438869156010910523869909904961142990921324633227826328266568191435253214
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.47781079291559422536439064817743809833959927037503905047102654282457989840710
Short name T264
Test name
Test status
Simulation time 131849903 ps
CPU time 1.11 seconds
Started Nov 22 12:32:07 PM PST 23
Finished Nov 22 12:32:11 PM PST 23
Peak memory 200444 kb
Host smart-cb63ba35-9474-4f9b-8f03-5a7d764d54ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47781079291559422536439064817743809833959927037503905047102654282457989840710 -assert n
opostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_err.47781079291559422536439064817743809833959927037503905047102654282457989840710
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.54438424507906924699746934527060820970904540831802465183840837947732352310325
Short name T91
Test name
Test status
Simulation time 44993455 ps
CPU time 0.8 seconds
Started Nov 22 12:31:37 PM PST 23
Finished Nov 22 12:31:40 PM PST 23
Peak memory 198472 kb
Host smart-38dda361-94cd-41e6-b6de-0946dbbaec8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54438424507906924699746934527060820970904540831802465183840837947732352310325 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.54438424507906924699746934527060820970904540831802465183840837947732352310325
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.61515958965988784510584924057583083599628549842741868548367940576310052195851
Short name T208
Test name
Test status
Simulation time 249509676 ps
CPU time 2.02 seconds
Started Nov 22 12:31:41 PM PST 23
Finished Nov 22 12:31:46 PM PST 23
Peak memory 200664 kb
Host smart-1be40ca0-f9bb-4105-929a-8e6026cc23b2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61515958965988784510584924057583083599628549842741868548367940576310052195851 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.61515958965988784510584924057583083599628549842741868548367940576310052195851
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.9568861849000892948758240773925464511347374925456397266084561516855456016343
Short name T63
Test name
Test status
Simulation time 29315009 ps
CPU time 0.62 seconds
Started Nov 22 12:31:37 PM PST 23
Finished Nov 22 12:31:39 PM PST 23
Peak memory 197812 kb
Host smart-e2b94a81-89f3-442e-b66a-d82a8fc7a1f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9568861849000892948758240773925464511347374925456397266084561516855456016343 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.9568861849000892948758240773925464511347374925456397266084561516855456016343
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.70170464036007397403321720334461409235249557521324633913376944781660783934625
Short name T56
Test name
Test status
Simulation time 39797068 ps
CPU time 0.69 seconds
Started Nov 22 12:31:57 PM PST 23
Finished Nov 22 12:31:59 PM PST 23
Peak memory 200384 kb
Host smart-3ad4215e-620e-429c-add0-6a992cc611d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7017046403600739740332172033446140923524955
7521324633913376944781660783934625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.7017046403600739740
3321720334461409235249557521324633913376944781660783934625
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.69938939955509347280974123791608265168416440108697468903208867289755854544519
Short name T230
Test name
Test status
Simulation time 24672189 ps
CPU time 0.6 seconds
Started Nov 22 12:31:52 PM PST 23
Finished Nov 22 12:31:55 PM PST 23
Peak memory 197156 kb
Host smart-6c5511d2-e0e5-4789-9a3e-827892f5d885
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69938939955509347280974123791608265168416440108697468903208867289755854544519 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.69938939955509347280974123791608265168416440108697468903208867289755854544519
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.105443032229796210728109825862251043324867627944869762119435677522648109706836
Short name T221
Test name
Test status
Simulation time 23690054 ps
CPU time 0.58 seconds
Started Nov 22 12:31:37 PM PST 23
Finished Nov 22 12:31:39 PM PST 23
Peak memory 196684 kb
Host smart-2bac8cf5-a91e-4ae7-a1d4-4456097f785e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105443032229796210728109825862251043324867627944869762119435677522648109706836 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.105443032229796210728109825862251043324867627944869762119435677522648109706836
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.110047652026978229824842745588582273395151064950737968663179195435830048536937
Short name T270
Test name
Test status
Simulation time 41047058 ps
CPU time 0.72 seconds
Started Nov 22 12:31:38 PM PST 23
Finished Nov 22 12:31:41 PM PST 23
Peak memory 198176 kb
Host smart-885a18ed-8509-4166-bc89-d6d71e554dc1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110047652026978229824842745588582273395151064950737968663179195435830048536937
-assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_same_csr_outstanding.11004765202697822982484274558858227339515106495073796866317
9195435830048536937
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.87146134787207658597604085009621882878341300607720972810745913157862364287189
Short name T213
Test name
Test status
Simulation time 103760842 ps
CPU time 1.43 seconds
Started Nov 22 12:31:41 PM PST 23
Finished Nov 22 12:31:45 PM PST 23
Peak memory 200820 kb
Host smart-0c3b1703-89fa-4463-9ae8-013b2dd4cd49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87146134787207658597604085009621882878341300607720972810745913157862364287189 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.87146134787207658597604085009621882878341300607720972810745913157862364287189
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.45593393116643627839253604570310455963376848411396232309711758417096132572325
Short name T180
Test name
Test status
Simulation time 131849903 ps
CPU time 1.08 seconds
Started Nov 22 12:31:49 PM PST 23
Finished Nov 22 12:31:52 PM PST 23
Peak memory 200412 kb
Host smart-993b017b-cb2d-49aa-aadf-995798c29507
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45593393116643627839253604570310455963376848411396232309711758417096132572325 -assert n
opostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err.45593393116643627839253604570310455963376848411396232309711758417096132572325
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.9439224765489535453689833270861128355271572094656198144135519472943616195424
Short name T229
Test name
Test status
Simulation time 23690054 ps
CPU time 0.58 seconds
Started Nov 22 12:32:28 PM PST 23
Finished Nov 22 12:32:30 PM PST 23
Peak memory 196716 kb
Host smart-d98e19e3-53cb-4ed5-87a2-037997d21530
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9439224765489535453689833270861128355271572094656198144135519472943616195424 -assert nopostproc +UV
M_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.9439224765489535453689833270861128355271572094656198144135519472943616195424
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.83773403202695572906604657089200427110780780037831662121684796747342387012039
Short name T235
Test name
Test status
Simulation time 23690054 ps
CPU time 0.59 seconds
Started Nov 22 12:32:07 PM PST 23
Finished Nov 22 12:32:10 PM PST 23
Peak memory 196732 kb
Host smart-6a7404f2-cd5d-44f4-98db-33ffc1bd558c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83773403202695572906604657089200427110780780037831662121684796747342387012039 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.83773403202695572906604657089200427110780780037831662121684796747342387012039
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.99880944734690391643200486266556471169959441509038913923812895162461227638640
Short name T212
Test name
Test status
Simulation time 23690054 ps
CPU time 0.6 seconds
Started Nov 22 12:32:04 PM PST 23
Finished Nov 22 12:32:06 PM PST 23
Peak memory 196748 kb
Host smart-d95b2f76-accc-4d2d-aece-9e588a9622f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99880944734690391643200486266556471169959441509038913923812895162461227638640 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.99880944734690391643200486266556471169959441509038913923812895162461227638640
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.97816996772335469945257372771890667492349321350080032002926131878663032236652
Short name T258
Test name
Test status
Simulation time 23690054 ps
CPU time 0.6 seconds
Started Nov 22 12:32:11 PM PST 23
Finished Nov 22 12:32:13 PM PST 23
Peak memory 196700 kb
Host smart-13d5c3be-0bcd-4c00-a746-c0727da80cca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97816996772335469945257372771890667492349321350080032002926131878663032236652 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.97816996772335469945257372771890667492349321350080032002926131878663032236652
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.81912140409255016905862586314322839978774801788420679637158907467054999983663
Short name T186
Test name
Test status
Simulation time 23690054 ps
CPU time 0.6 seconds
Started Nov 22 12:32:11 PM PST 23
Finished Nov 22 12:32:13 PM PST 23
Peak memory 196600 kb
Host smart-b2f098c2-a6f4-41c9-8155-5097b90f13ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81912140409255016905862586314322839978774801788420679637158907467054999983663 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.81912140409255016905862586314322839978774801788420679637158907467054999983663
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.15402063747754810457244047366498992520074836505517540697296189542006050538396
Short name T284
Test name
Test status
Simulation time 23690054 ps
CPU time 0.61 seconds
Started Nov 22 12:32:07 PM PST 23
Finished Nov 22 12:32:10 PM PST 23
Peak memory 196732 kb
Host smart-9cac9e55-2f03-4cea-9c84-496fc47b9f08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15402063747754810457244047366498992520074836505517540697296189542006050538396 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.15402063747754810457244047366498992520074836505517540697296189542006050538396
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.68447563064225598433799075507459423067003155841897336528833761277817835112733
Short name T189
Test name
Test status
Simulation time 23690054 ps
CPU time 0.59 seconds
Started Nov 22 12:32:08 PM PST 23
Finished Nov 22 12:32:10 PM PST 23
Peak memory 196732 kb
Host smart-cbc1c6f3-ce7e-4aa4-8ca7-1494a48ab6a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68447563064225598433799075507459423067003155841897336528833761277817835112733 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.68447563064225598433799075507459423067003155841897336528833761277817835112733
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.65880777852578170170092950840158754098662446785409155421202832079097850231505
Short name T219
Test name
Test status
Simulation time 23690054 ps
CPU time 0.6 seconds
Started Nov 22 12:32:08 PM PST 23
Finished Nov 22 12:32:10 PM PST 23
Peak memory 196732 kb
Host smart-0f4b43a3-114b-4278-963c-def312ce3155
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65880777852578170170092950840158754098662446785409155421202832079097850231505 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.65880777852578170170092950840158754098662446785409155421202832079097850231505
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.85797551297297127762595759654453223470087354317980238777013364948898340837133
Short name T198
Test name
Test status
Simulation time 23690054 ps
CPU time 0.59 seconds
Started Nov 22 12:32:07 PM PST 23
Finished Nov 22 12:32:08 PM PST 23
Peak memory 196512 kb
Host smart-64fc8222-10b8-4cb5-81e8-5fdea8c3e0ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85797551297297127762595759654453223470087354317980238777013364948898340837133 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.85797551297297127762595759654453223470087354317980238777013364948898340837133
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.108803654969049066975800460755297965993212086433656953139703794809303267635223
Short name T269
Test name
Test status
Simulation time 23690054 ps
CPU time 0.59 seconds
Started Nov 22 12:32:07 PM PST 23
Finished Nov 22 12:32:08 PM PST 23
Peak memory 196484 kb
Host smart-7d86eca2-ff58-44cc-9f47-e501afeeaffe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108803654969049066975800460755297965993212086433656953139703794809303267635223 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.108803654969049066975800460755297965993212086433656953139703794809303267635223
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.49206097419333349949073244803757772415771893279685795894956106720927553849487
Short name T90
Test name
Test status
Simulation time 44993455 ps
CPU time 0.78 seconds
Started Nov 22 12:31:54 PM PST 23
Finished Nov 22 12:31:56 PM PST 23
Peak memory 198464 kb
Host smart-5deffd19-5721-4f6d-b1ac-bba32bb9e590
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49206097419333349949073244803757772415771893279685795894956106720927553849487 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.49206097419333349949073244803757772415771893279685795894956106720927553849487
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.58805963519501744374292966061231050552285659587133737947807984275652284342664
Short name T246
Test name
Test status
Simulation time 249509676 ps
CPU time 1.97 seconds
Started Nov 22 12:31:38 PM PST 23
Finished Nov 22 12:31:42 PM PST 23
Peak memory 200820 kb
Host smart-6a87e442-2e57-4027-b2f4-38a48f8d800d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58805963519501744374292966061231050552285659587133737947807984275652284342664 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.58805963519501744374292966061231050552285659587133737947807984275652284342664
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.52210487752912664027089815223407872333939650710618197723828874826477277592932
Short name T92
Test name
Test status
Simulation time 29315009 ps
CPU time 0.65 seconds
Started Nov 22 12:31:49 PM PST 23
Finished Nov 22 12:31:51 PM PST 23
Peak memory 197792 kb
Host smart-45c1d72e-4d34-4e66-8e56-0603d66a8d04
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52210487752912664027089815223407872333939650710618197723828874826477277592932 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.52210487752912664027089815223407872333939650710618197723828874826477277592932
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.23267138097116232198761279974653841067236189917458139140931329269348290640546
Short name T234
Test name
Test status
Simulation time 39797068 ps
CPU time 0.72 seconds
Started Nov 22 12:31:43 PM PST 23
Finished Nov 22 12:31:46 PM PST 23
Peak memory 200412 kb
Host smart-9f9a358a-5adf-4814-922e-3ec30f49656a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326713809711623219876127997465384106723618
9917458139140931329269348290640546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.2326713809711623219
8761279974653841067236189917458139140931329269348290640546
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.43348410697764577379511029207822604246045313369922659274326210561848180230925
Short name T204
Test name
Test status
Simulation time 24672189 ps
CPU time 0.62 seconds
Started Nov 22 12:31:51 PM PST 23
Finished Nov 22 12:31:53 PM PST 23
Peak memory 197152 kb
Host smart-7509344f-4f75-416f-928f-065e0becfe17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43348410697764577379511029207822604246045313369922659274326210561848180230925 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.43348410697764577379511029207822604246045313369922659274326210561848180230925
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.52334962611572567602497864514915181992292319205317372959944414346812879097840
Short name T242
Test name
Test status
Simulation time 23690054 ps
CPU time 0.58 seconds
Started Nov 22 12:31:50 PM PST 23
Finished Nov 22 12:31:52 PM PST 23
Peak memory 196680 kb
Host smart-ed423383-845b-4ae6-ac1d-c2e6e7499f26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52334962611572567602497864514915181992292319205317372959944414346812879097840 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.52334962611572567602497864514915181992292319205317372959944414346812879097840
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.70371469677367194712581462561037104626504614570128790845575535598049471058621
Short name T276
Test name
Test status
Simulation time 41047058 ps
CPU time 0.69 seconds
Started Nov 22 12:31:41 PM PST 23
Finished Nov 22 12:31:45 PM PST 23
Peak memory 197932 kb
Host smart-6cd0f064-5d74-4e14-8abf-d0ee5f43a5c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70371469677367194712581462561037104626504614570128790845575535598049471058621
-assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_same_csr_outstanding.703714696773671947125814625610371046265046145701287908455755
35598049471058621
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.69824339189853135068598625449306493500827945415219209306736030738351744810436
Short name T240
Test name
Test status
Simulation time 103760842 ps
CPU time 1.45 seconds
Started Nov 22 12:31:55 PM PST 23
Finished Nov 22 12:31:57 PM PST 23
Peak memory 200792 kb
Host smart-2f55d3ad-293b-4c14-97a2-f6d0b539818e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69824339189853135068598625449306493500827945415219209306736030738351744810436 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.69824339189853135068598625449306493500827945415219209306736030738351744810436
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.47872043407494787636046156901317846463913190181715810909299097866442860487118
Short name T43
Test name
Test status
Simulation time 131849903 ps
CPU time 1.05 seconds
Started Nov 22 12:31:41 PM PST 23
Finished Nov 22 12:31:45 PM PST 23
Peak memory 200308 kb
Host smart-e18d5bd3-21d2-4b9d-8797-09b76f01af31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47872043407494787636046156901317846463913190181715810909299097866442860487118 -assert n
opostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err.47872043407494787636046156901317846463913190181715810909299097866442860487118
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.68293799453248178493331438990101976852109561477981209650617391233758523064548
Short name T203
Test name
Test status
Simulation time 23690054 ps
CPU time 0.57 seconds
Started Nov 22 12:32:13 PM PST 23
Finished Nov 22 12:32:16 PM PST 23
Peak memory 196704 kb
Host smart-2c4dc4f1-2ef8-4ccf-9d32-00ddc48da97b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68293799453248178493331438990101976852109561477981209650617391233758523064548 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.68293799453248178493331438990101976852109561477981209650617391233758523064548
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.47788067273210933102075158587118417355054109658642561737896398187076159302163
Short name T244
Test name
Test status
Simulation time 23690054 ps
CPU time 0.57 seconds
Started Nov 22 12:32:07 PM PST 23
Finished Nov 22 12:32:08 PM PST 23
Peak memory 196732 kb
Host smart-f364d06b-e765-4ea6-bb08-49be96b30405
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47788067273210933102075158587118417355054109658642561737896398187076159302163 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.47788067273210933102075158587118417355054109658642561737896398187076159302163
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.8712092132818516413534803068496603928067324479009525335115767944525365381217
Short name T177
Test name
Test status
Simulation time 23690054 ps
CPU time 0.62 seconds
Started Nov 22 12:32:08 PM PST 23
Finished Nov 22 12:32:10 PM PST 23
Peak memory 196700 kb
Host smart-af607466-5d78-4ef8-b931-45d6a34667cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8712092132818516413534803068496603928067324479009525335115767944525365381217 -assert nopostproc +UV
M_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.8712092132818516413534803068496603928067324479009525335115767944525365381217
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.37295073609884575610804690617951712096049332081151398018146743933718313042453
Short name T201
Test name
Test status
Simulation time 23690054 ps
CPU time 0.64 seconds
Started Nov 22 12:32:10 PM PST 23
Finished Nov 22 12:32:12 PM PST 23
Peak memory 195964 kb
Host smart-132f6eab-eda5-436a-a8c8-d25fa68a8c2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37295073609884575610804690617951712096049332081151398018146743933718313042453 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.37295073609884575610804690617951712096049332081151398018146743933718313042453
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.94651522199545690211180167334615701581148241902755553275114171337973496201551
Short name T262
Test name
Test status
Simulation time 23690054 ps
CPU time 0.6 seconds
Started Nov 22 12:32:11 PM PST 23
Finished Nov 22 12:32:14 PM PST 23
Peak memory 196708 kb
Host smart-910411bb-f1d0-4857-bbe2-85430d6f632c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94651522199545690211180167334615701581148241902755553275114171337973496201551 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.94651522199545690211180167334615701581148241902755553275114171337973496201551
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.73143442499567251780427119004316286922147325276301107765413843403819712606120
Short name T255
Test name
Test status
Simulation time 23690054 ps
CPU time 0.58 seconds
Started Nov 22 12:32:10 PM PST 23
Finished Nov 22 12:32:12 PM PST 23
Peak memory 196708 kb
Host smart-33595d49-94da-4419-ace6-35cb6a361f65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73143442499567251780427119004316286922147325276301107765413843403819712606120 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.73143442499567251780427119004316286922147325276301107765413843403819712606120
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3507122441817237106893194972155448175661721645902968524558316198550863283303
Short name T261
Test name
Test status
Simulation time 23690054 ps
CPU time 0.58 seconds
Started Nov 22 12:32:17 PM PST 23
Finished Nov 22 12:32:18 PM PST 23
Peak memory 196700 kb
Host smart-c0b0650b-5cab-4283-b633-9dc4d70cb1f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507122441817237106893194972155448175661721645902968524558316198550863283303 -assert nopostproc +UV
M_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.3507122441817237106893194972155448175661721645902968524558316198550863283303
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.82499970084120299957438040599777674844878105709831927048585448805561109451767
Short name T225
Test name
Test status
Simulation time 23690054 ps
CPU time 0.58 seconds
Started Nov 22 12:32:01 PM PST 23
Finished Nov 22 12:32:04 PM PST 23
Peak memory 196692 kb
Host smart-788a086a-7f4b-4b49-a0ca-2e6f36acf870
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82499970084120299957438040599777674844878105709831927048585448805561109451767 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.82499970084120299957438040599777674844878105709831927048585448805561109451767
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.68705510282589353801424374191706275166561394195835818299505589129816641896835
Short name T183
Test name
Test status
Simulation time 23690054 ps
CPU time 0.64 seconds
Started Nov 22 12:33:19 PM PST 23
Finished Nov 22 12:33:22 PM PST 23
Peak memory 196708 kb
Host smart-34756543-31c6-4f76-913b-6d89bdbd01b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68705510282589353801424374191706275166561394195835818299505589129816641896835 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.68705510282589353801424374191706275166561394195835818299505589129816641896835
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.10100674196026017995883022609247374115530643095907593129471395065903258080876
Short name T236
Test name
Test status
Simulation time 23690054 ps
CPU time 0.61 seconds
Started Nov 22 12:32:15 PM PST 23
Finished Nov 22 12:32:17 PM PST 23
Peak memory 196720 kb
Host smart-0542e1f2-e9a8-40fb-b9bf-5f89b046296e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10100674196026017995883022609247374115530643095907593129471395065903258080876 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.10100674196026017995883022609247374115530643095907593129471395065903258080876
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.98365108996309267278297131370133685618294905500002589287032788479112653619653
Short name T84
Test name
Test status
Simulation time 44993455 ps
CPU time 0.8 seconds
Started Nov 22 12:31:35 PM PST 23
Finished Nov 22 12:31:38 PM PST 23
Peak memory 198476 kb
Host smart-5cb8273d-a654-4057-aeb8-8ee548d44235
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98365108996309267278297131370133685618294905500002589287032788479112653619653 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.98365108996309267278297131370133685618294905500002589287032788479112653619653
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.79080558468471511631813845717512741433575878724299926349213187097279423594850
Short name T185
Test name
Test status
Simulation time 249509676 ps
CPU time 2.01 seconds
Started Nov 22 12:31:45 PM PST 23
Finished Nov 22 12:31:48 PM PST 23
Peak memory 200828 kb
Host smart-ddc800b2-f2b9-4e5c-8e5e-399a6955244e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79080558468471511631813845717512741433575878724299926349213187097279423594850 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.79080558468471511631813845717512741433575878724299926349213187097279423594850
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.70616736553031274754854727838221456703878639846525338005716356460986946012517
Short name T94
Test name
Test status
Simulation time 29315009 ps
CPU time 0.63 seconds
Started Nov 22 12:31:52 PM PST 23
Finished Nov 22 12:31:55 PM PST 23
Peak memory 197796 kb
Host smart-986ecb83-4768-4f32-8ae0-1b56430e31b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70616736553031274754854727838221456703878639846525338005716356460986946012517 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.70616736553031274754854727838221456703878639846525338005716356460986946012517
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.101436172413092925784754866860310692432544323131576602018791970502881078651801
Short name T207
Test name
Test status
Simulation time 39797068 ps
CPU time 0.71 seconds
Started Nov 22 12:31:36 PM PST 23
Finished Nov 22 12:31:39 PM PST 23
Peak memory 200412 kb
Host smart-a37e4537-09d0-43a3-9f76-2c22604d110c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014361724130929257847548668603106924325443
23131576602018791970502881078651801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.101436172413092925
784754866860310692432544323131576602018791970502881078651801
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.63967395316353454909383078047965453538563468363855451353196626489986158254314
Short name T200
Test name
Test status
Simulation time 24672189 ps
CPU time 0.61 seconds
Started Nov 22 12:32:10 PM PST 23
Finished Nov 22 12:32:11 PM PST 23
Peak memory 197184 kb
Host smart-910c8cb3-dfac-4266-a555-b3b7b3a5b600
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63967395316353454909383078047965453538563468363855451353196626489986158254314 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.63967395316353454909383078047965453538563468363855451353196626489986158254314
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.89861056137328263856601236546617312118172783180788714701276255284733710583631
Short name T179
Test name
Test status
Simulation time 23690054 ps
CPU time 0.59 seconds
Started Nov 22 12:31:52 PM PST 23
Finished Nov 22 12:31:55 PM PST 23
Peak memory 196720 kb
Host smart-b6962132-3156-4e14-91cc-4589d8f62986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89861056137328263856601236546617312118172783180788714701276255284733710583631 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.89861056137328263856601236546617312118172783180788714701276255284733710583631
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.6035234356368650103490235647991078267339060143611260224140557572743970066391
Short name T78
Test name
Test status
Simulation time 41047058 ps
CPU time 0.72 seconds
Started Nov 22 12:31:39 PM PST 23
Finished Nov 22 12:31:41 PM PST 23
Peak memory 198148 kb
Host smart-2b64bbb1-d2c6-494f-a02d-b8112328c077
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6035234356368650103490235647991078267339060143611260224140557572743970066391 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_same_csr_outstanding.6035234356368650103490235647991078267339060143611260224140557
572743970066391
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.3866847974836771253874198412291132847871315904714578312450024505880919999332
Short name T238
Test name
Test status
Simulation time 103760842 ps
CPU time 1.41 seconds
Started Nov 22 12:31:56 PM PST 23
Finished Nov 22 12:32:00 PM PST 23
Peak memory 200760 kb
Host smart-077bebaa-f52e-4bb6-818b-0b04fa2b5863
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866847974836771253874198412291132847871315904714578312450024505880919999332 -assert nopostproc +UV
M_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.3866847974836771253874198412291132847871315904714578312450024505880919999332
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.6513918916505160795701173321193793142315003865261232461628943722416170083465
Short name T181
Test name
Test status
Simulation time 131849903 ps
CPU time 1.1 seconds
Started Nov 22 12:31:55 PM PST 23
Finished Nov 22 12:31:57 PM PST 23
Peak memory 200424 kb
Host smart-03af0895-cffe-443f-8518-5a1fc262bfc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6513918916505160795701173321193793142315003865261232461628943722416170083465 -assert no
postproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err.6513918916505160795701173321193793142315003865261232461628943722416170083465
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.54903126309752692386055096242547495538608365716682337768610177484394289054768
Short name T220
Test name
Test status
Simulation time 23690054 ps
CPU time 0.6 seconds
Started Nov 22 12:32:11 PM PST 23
Finished Nov 22 12:32:13 PM PST 23
Peak memory 196536 kb
Host smart-a17d3733-c67e-462d-9525-ee99b574028d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54903126309752692386055096242547495538608365716682337768610177484394289054768 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.54903126309752692386055096242547495538608365716682337768610177484394289054768
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.109298393819797793397998508442077990524841585523292021866683627035436133605229
Short name T53
Test name
Test status
Simulation time 23690054 ps
CPU time 0.58 seconds
Started Nov 22 12:32:09 PM PST 23
Finished Nov 22 12:32:11 PM PST 23
Peak memory 196704 kb
Host smart-7d1cfa80-d1c2-4093-a9aa-6e2060943f7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109298393819797793397998508442077990524841585523292021866683627035436133605229 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.109298393819797793397998508442077990524841585523292021866683627035436133605229
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.58806596051134394273440405877120580430472547441576960708570487898960349724687
Short name T188
Test name
Test status
Simulation time 23690054 ps
CPU time 0.63 seconds
Started Nov 22 12:32:12 PM PST 23
Finished Nov 22 12:32:14 PM PST 23
Peak memory 196708 kb
Host smart-357b612b-0fd7-403e-93fd-d518dea58d1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58806596051134394273440405877120580430472547441576960708570487898960349724687 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.58806596051134394273440405877120580430472547441576960708570487898960349724687
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.19197999264677394788409278771120876002992176244622081339133075511406123582020
Short name T187
Test name
Test status
Simulation time 23690054 ps
CPU time 0.59 seconds
Started Nov 22 12:32:12 PM PST 23
Finished Nov 22 12:32:15 PM PST 23
Peak memory 196704 kb
Host smart-ac6c41f4-86f9-451c-a22b-c98e8071bfb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19197999264677394788409278771120876002992176244622081339133075511406123582020 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.19197999264677394788409278771120876002992176244622081339133075511406123582020
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.67031916533987567855445910518891473758125322638314093361839148616816553101390
Short name T252
Test name
Test status
Simulation time 23690054 ps
CPU time 0.58 seconds
Started Nov 22 12:32:07 PM PST 23
Finished Nov 22 12:32:09 PM PST 23
Peak memory 196732 kb
Host smart-62a14105-2903-4153-84c3-2c2225898c3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67031916533987567855445910518891473758125322638314093361839148616816553101390 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.67031916533987567855445910518891473758125322638314093361839148616816553101390
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.48866832788261021382848971442241180972533943326201692216106000465624769293846
Short name T214
Test name
Test status
Simulation time 23690054 ps
CPU time 0.68 seconds
Started Nov 22 12:33:01 PM PST 23
Finished Nov 22 12:33:06 PM PST 23
Peak memory 195504 kb
Host smart-94c6d460-5e0d-4a6b-85a0-bd6b1a8abde5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48866832788261021382848971442241180972533943326201692216106000465624769293846 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.48866832788261021382848971442241180972533943326201692216106000465624769293846
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.12532552263618183976297280021563343509871064515632232484240427687755215030384
Short name T241
Test name
Test status
Simulation time 23690054 ps
CPU time 0.59 seconds
Started Nov 22 12:32:05 PM PST 23
Finished Nov 22 12:32:06 PM PST 23
Peak memory 196720 kb
Host smart-5b784e5c-75ca-4f2b-90fd-b8d98318bcfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12532552263618183976297280021563343509871064515632232484240427687755215030384 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.12532552263618183976297280021563343509871064515632232484240427687755215030384
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1769622476040633719796645673642632732702174096252225161549964362045580849159
Short name T192
Test name
Test status
Simulation time 23690054 ps
CPU time 0.58 seconds
Started Nov 22 12:32:11 PM PST 23
Finished Nov 22 12:32:14 PM PST 23
Peak memory 196708 kb
Host smart-e7cb5d80-4847-419d-9a67-a61ab11e73e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769622476040633719796645673642632732702174096252225161549964362045580849159 -assert nopostproc +UV
M_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.1769622476040633719796645673642632732702174096252225161549964362045580849159
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.108779520843534377000637719959535933156628581657695590215018228051523735492211
Short name T211
Test name
Test status
Simulation time 23690054 ps
CPU time 0.59 seconds
Started Nov 22 12:32:11 PM PST 23
Finished Nov 22 12:32:12 PM PST 23
Peak memory 196708 kb
Host smart-d6d5b8d2-bf76-448e-8693-ab5b87d394f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108779520843534377000637719959535933156628581657695590215018228051523735492211 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.108779520843534377000637719959535933156628581657695590215018228051523735492211
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.73982273157631663550678714852347108209704884440273712469265877263244116713047
Short name T227
Test name
Test status
Simulation time 23690054 ps
CPU time 0.62 seconds
Started Nov 22 12:33:16 PM PST 23
Finished Nov 22 12:33:17 PM PST 23
Peak memory 196776 kb
Host smart-ef9d619d-333d-4b56-b612-68e3c5621f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73982273157631663550678714852347108209704884440273712469265877263244116713047 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.73982273157631663550678714852347108209704884440273712469265877263244116713047
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.55787433696625411469214930317824044385513407208806515401836128401780207708097
Short name T57
Test name
Test status
Simulation time 39797068 ps
CPU time 0.69 seconds
Started Nov 22 12:31:40 PM PST 23
Finished Nov 22 12:31:44 PM PST 23
Peak memory 200380 kb
Host smart-a18b460d-0ba5-467b-a3cd-842477244800
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5578743369662541146921493031782404438551340
7208806515401836128401780207708097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.5578743369662541146
9214930317824044385513407208806515401836128401780207708097
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.5709854154528837317566941176742376499868273227066385568665896395698930996600
Short name T206
Test name
Test status
Simulation time 24672189 ps
CPU time 0.61 seconds
Started Nov 22 12:31:35 PM PST 23
Finished Nov 22 12:31:38 PM PST 23
Peak memory 197012 kb
Host smart-16e866fc-4360-42bc-9470-2b668f973ea8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5709854154528837317566941176742376499868273227066385568665896395698930996600 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.5709854154528837317566941176742376499868273227066385568665896395698930996600
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.60101864739556079255357392678560083252441396438842154378765142040972680969979
Short name T218
Test name
Test status
Simulation time 23690054 ps
CPU time 0.59 seconds
Started Nov 22 12:31:48 PM PST 23
Finished Nov 22 12:31:51 PM PST 23
Peak memory 196696 kb
Host smart-dd416988-d201-4004-a3f9-a12ec6596589
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60101864739556079255357392678560083252441396438842154378765142040972680969979 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.60101864739556079255357392678560083252441396438842154378765142040972680969979
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.91965927173514763325089025954180854595315152067769188375345885409420428903163
Short name T76
Test name
Test status
Simulation time 41047058 ps
CPU time 0.68 seconds
Started Nov 22 12:31:34 PM PST 23
Finished Nov 22 12:31:37 PM PST 23
Peak memory 198044 kb
Host smart-153b04c8-ec8b-4e81-928d-cbea71853b71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91965927173514763325089025954180854595315152067769188375345885409420428903163
-assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_same_csr_outstanding.919659271735147633250890259541808545953151520677691883753458
85409420428903163
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.42194228560939909212275596041549269141088871193735563320493153702307677655146
Short name T263
Test name
Test status
Simulation time 103760842 ps
CPU time 1.46 seconds
Started Nov 22 12:31:34 PM PST 23
Finished Nov 22 12:31:39 PM PST 23
Peak memory 200760 kb
Host smart-7413aa39-c621-4600-8aec-4e3b455eb916
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42194228560939909212275596041549269141088871193735563320493153702307677655146 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.42194228560939909212275596041549269141088871193735563320493153702307677655146
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.33870805819441148690335207613418178451353550048158877698112066985607301239778
Short name T245
Test name
Test status
Simulation time 131849903 ps
CPU time 1.09 seconds
Started Nov 22 12:31:34 PM PST 23
Finished Nov 22 12:31:38 PM PST 23
Peak memory 200412 kb
Host smart-de00519a-c630-430a-8fbf-425bbdec126e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33870805819441148690335207613418178451353550048158877698112066985607301239778 -assert n
opostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err.33870805819441148690335207613418178451353550048158877698112066985607301239778
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.113141495876610245522591734780618955901513505873080719573085487623951143713129
Short name T184
Test name
Test status
Simulation time 39797068 ps
CPU time 0.73 seconds
Started Nov 22 12:31:41 PM PST 23
Finished Nov 22 12:31:45 PM PST 23
Peak memory 200412 kb
Host smart-47fcd815-ebe3-4881-9e2d-92d5158ac080
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131414958766102455225917347806189559015135
05873080719573085487623951143713129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.113141495876610245
522591734780618955901513505873080719573085487623951143713129
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.107976609766366479998400199492000160588977256681919301691307309346311126755661
Short name T82
Test name
Test status
Simulation time 24672189 ps
CPU time 0.61 seconds
Started Nov 22 12:31:46 PM PST 23
Finished Nov 22 12:31:47 PM PST 23
Peak memory 196856 kb
Host smart-8069d4d1-1e1d-4752-a300-53b32bbe13ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107976609766366479998400199492000160588977256681919301691307309346311126755661 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_
reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.107976609766366479998400199492000160588977256681919301691307309346311126755661
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.19806285181267319136401370535399220425896242725373200093894826987690781099810
Short name T55
Test name
Test status
Simulation time 23690054 ps
CPU time 0.6 seconds
Started Nov 22 12:31:30 PM PST 23
Finished Nov 22 12:31:32 PM PST 23
Peak memory 196820 kb
Host smart-a88e698d-8153-4c7d-a31c-6cdb3f160eb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19806285181267319136401370535399220425896242725373200093894826987690781099810 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.19806285181267319136401370535399220425896242725373200093894826987690781099810
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.73217222771034087302960884918462178596607550147185550262838656674918109009368
Short name T96
Test name
Test status
Simulation time 41047058 ps
CPU time 0.71 seconds
Started Nov 22 12:31:50 PM PST 23
Finished Nov 22 12:31:52 PM PST 23
Peak memory 197996 kb
Host smart-5b1f5fcb-2146-4e15-b977-a9c689d4470a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73217222771034087302960884918462178596607550147185550262838656674918109009368
-assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_same_csr_outstanding.732172227710340873029608849184621785966075501471855502628386
56674918109009368
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.29068701813148750998041439445131457636630832812261438504997861382115966044571
Short name T70
Test name
Test status
Simulation time 103760842 ps
CPU time 1.42 seconds
Started Nov 22 12:31:37 PM PST 23
Finished Nov 22 12:31:40 PM PST 23
Peak memory 200788 kb
Host smart-1a78ccff-77a1-4107-9e46-7f2ae16c28ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29068701813148750998041439445131457636630832812261438504997861382115966044571 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.29068701813148750998041439445131457636630832812261438504997861382115966044571
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.111599484832562551403500883011381472581868374215583457770820580935923335358051
Short name T182
Test name
Test status
Simulation time 131849903 ps
CPU time 1.09 seconds
Started Nov 22 12:31:31 PM PST 23
Finished Nov 22 12:31:32 PM PST 23
Peak memory 200580 kb
Host smart-e58d61c1-008a-4eb1-af2e-ed22abe28bc6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111599484832562551403500883011381472581868374215583457770820580935923335358051 -assert
nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err.111599484832562551403500883011381472581868374215583457770820580935923335358051
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.73457918268372408218750570628627211632413974323598633302315931640954412004194
Short name T52
Test name
Test status
Simulation time 39797068 ps
CPU time 0.71 seconds
Started Nov 22 12:31:42 PM PST 23
Finished Nov 22 12:31:45 PM PST 23
Peak memory 200400 kb
Host smart-7aa3e995-95c6-413b-8b41-22c9216b3aa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7345791826837240821875057062862721163241397
4323598633302315931640954412004194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.7345791826837240821
8750570628627211632413974323598633302315931640954412004194
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.59349768718982030736590128945123532786658279921231317653779124720616424099460
Short name T79
Test name
Test status
Simulation time 24672189 ps
CPU time 0.63 seconds
Started Nov 22 12:31:41 PM PST 23
Finished Nov 22 12:31:44 PM PST 23
Peak memory 197220 kb
Host smart-2d9522c8-8dc3-4274-b595-c19c728bc3c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59349768718982030736590128945123532786658279921231317653779124720616424099460 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.59349768718982030736590128945123532786658279921231317653779124720616424099460
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.71959787119496501801637972586752710200848323164399085112596553198848981860673
Short name T275
Test name
Test status
Simulation time 23690054 ps
CPU time 0.58 seconds
Started Nov 22 12:31:39 PM PST 23
Finished Nov 22 12:31:41 PM PST 23
Peak memory 196748 kb
Host smart-98ea7ca8-ab52-4ca1-a474-992fc83ad2ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71959787119496501801637972586752710200848323164399085112596553198848981860673 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.71959787119496501801637972586752710200848323164399085112596553198848981860673
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.11390989737993347614940526794465194087822132113340910169820608289386029462163
Short name T251
Test name
Test status
Simulation time 41047058 ps
CPU time 0.68 seconds
Started Nov 22 12:31:37 PM PST 23
Finished Nov 22 12:31:39 PM PST 23
Peak memory 198060 kb
Host smart-e1359dfb-c9ac-40b4-83a1-5edd5eff3614
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11390989737993347614940526794465194087822132113340910169820608289386029462163
-assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_same_csr_outstanding.113909897379933476149405267944651940878221321133409101698206
08289386029462163
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.38879268216154033387307636168302187782559512579324085850299072540305738427593
Short name T274
Test name
Test status
Simulation time 103760842 ps
CPU time 1.37 seconds
Started Nov 22 12:31:38 PM PST 23
Finished Nov 22 12:31:40 PM PST 23
Peak memory 200904 kb
Host smart-0a00458d-0456-4760-a035-377280391ad6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38879268216154033387307636168302187782559512579324085850299072540305738427593 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.38879268216154033387307636168302187782559512579324085850299072540305738427593
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.37739787460528766380291645958303362971864032206447701456210698635765994161732
Short name T59
Test name
Test status
Simulation time 131849903 ps
CPU time 1.1 seconds
Started Nov 22 12:31:50 PM PST 23
Finished Nov 22 12:31:53 PM PST 23
Peak memory 200412 kb
Host smart-b1e73efd-74e8-464e-9360-19521d3d7ed6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37739787460528766380291645958303362971864032206447701456210698635765994161732 -assert n
opostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err.37739787460528766380291645958303362971864032206447701456210698635765994161732
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.23707653630782770771381710840240712443974957594767177183666435756788887838071
Short name T73
Test name
Test status
Simulation time 39797068 ps
CPU time 0.72 seconds
Started Nov 22 12:31:37 PM PST 23
Finished Nov 22 12:31:39 PM PST 23
Peak memory 200436 kb
Host smart-becd7175-d4f3-49c5-a752-242d9a7f4432
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370765363078277077138171084024071244397495
7594767177183666435756788887838071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.2370765363078277077
1381710840240712443974957594767177183666435756788887838071
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.50575481406023193395444987962344613608426998771385194041622878597314879102801
Short name T202
Test name
Test status
Simulation time 24672189 ps
CPU time 0.61 seconds
Started Nov 22 12:31:46 PM PST 23
Finished Nov 22 12:31:47 PM PST 23
Peak memory 196840 kb
Host smart-e7998f93-cb93-42cf-8020-b229b32daeca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50575481406023193395444987962344613608426998771385194041622878597314879102801 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_r
eg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.50575481406023193395444987962344613608426998771385194041622878597314879102801
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.67958487127896756316671863778618146158078096659544891607089737814066937580236
Short name T54
Test name
Test status
Simulation time 23690054 ps
CPU time 0.6 seconds
Started Nov 22 12:31:50 PM PST 23
Finished Nov 22 12:31:52 PM PST 23
Peak memory 196704 kb
Host smart-40adc24a-72bb-40c4-92c9-5dc53b85fb15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67958487127896756316671863778618146158078096659544891607089737814066937580236 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.67958487127896756316671863778618146158078096659544891607089737814066937580236
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.60823251598092210101844032795106289964182004311753951834525205639275273926418
Short name T250
Test name
Test status
Simulation time 41047058 ps
CPU time 0.69 seconds
Started Nov 22 12:31:55 PM PST 23
Finished Nov 22 12:31:57 PM PST 23
Peak memory 198000 kb
Host smart-333119ee-22fc-4e32-94c4-521f7f3f9795
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60823251598092210101844032795106289964182004311753951834525205639275273926418
-assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_same_csr_outstanding.608232515980922101018440327951062899641820043117539518345252
05639275273926418
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.74642413149348348353349274940944529684663405042541658159401872330316059753404
Short name T72
Test name
Test status
Simulation time 103760842 ps
CPU time 1.46 seconds
Started Nov 22 12:31:55 PM PST 23
Finished Nov 22 12:31:57 PM PST 23
Peak memory 200792 kb
Host smart-4ce799ed-df5a-4010-bdb2-845fe4eed0cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74642413149348348353349274940944529684663405042541658159401872330316059753404 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.74642413149348348353349274940944529684663405042541658159401872330316059753404
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.67806966112496765117998326598256134619416666347412070610249467709073641702178
Short name T283
Test name
Test status
Simulation time 131849903 ps
CPU time 1.14 seconds
Started Nov 22 12:31:41 PM PST 23
Finished Nov 22 12:31:45 PM PST 23
Peak memory 200388 kb
Host smart-6dfe5d64-ab41-42a6-b7be-1b4cbc53a086
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67806966112496765117998326598256134619416666347412070610249467709073641702178 -assert n
opostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err.67806966112496765117998326598256134619416666347412070610249467709073641702178
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.58104881140777610295307225699175251657888348567831385008880335577945569169890
Short name T267
Test name
Test status
Simulation time 39797068 ps
CPU time 0.71 seconds
Started Nov 22 12:31:42 PM PST 23
Finished Nov 22 12:31:45 PM PST 23
Peak memory 200392 kb
Host smart-9e9db554-fde4-4cc1-8f80-97888b40e870
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5810488114077761029530722569917525165788834
8567831385008880335577945569169890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.5810488114077761029
5307225699175251657888348567831385008880335577945569169890
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.4441747925632181592330640599430301370843777946317166252522831069866901670980
Short name T88
Test name
Test status
Simulation time 24672189 ps
CPU time 0.6 seconds
Started Nov 22 12:31:41 PM PST 23
Finished Nov 22 12:31:45 PM PST 23
Peak memory 197176 kb
Host smart-8902bbea-4c9c-49d8-9169-1c2a0ea1a39e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4441747925632181592330640599430301370843777946317166252522831069866901670980 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_re
g_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.4441747925632181592330640599430301370843777946317166252522831069866901670980
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.72459078816667065910301097050477345238914810975793415671292468773898400001900
Short name T178
Test name
Test status
Simulation time 23690054 ps
CPU time 0.58 seconds
Started Nov 22 12:31:57 PM PST 23
Finished Nov 22 12:32:02 PM PST 23
Peak memory 196748 kb
Host smart-d58b2df2-3fd6-417e-9bd0-f760ddf8b812
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72459078816667065910301097050477345238914810975793415671292468773898400001900 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.72459078816667065910301097050477345238914810975793415671292468773898400001900
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.17172146510540073892618297446162876396161102987560908613704556488377914767723
Short name T100
Test name
Test status
Simulation time 41047058 ps
CPU time 0.69 seconds
Started Nov 22 12:31:42 PM PST 23
Finished Nov 22 12:31:45 PM PST 23
Peak memory 198012 kb
Host smart-75a48d43-7816-4efd-9c80-1a94624a2e07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17172146510540073892618297446162876396161102987560908613704556488377914767723
-assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_same_csr_outstanding.171721465105400738926182974461628763961611029875609086137045
56488377914767723
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.107078795886949379309542084082882326965037114589661518739741713139656567965463
Short name T249
Test name
Test status
Simulation time 103760842 ps
CPU time 1.41 seconds
Started Nov 22 12:31:38 PM PST 23
Finished Nov 22 12:31:41 PM PST 23
Peak memory 200776 kb
Host smart-4dd5323f-7856-44fe-b6b4-24c21388d411
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107078795886949379309542084082882326965037114589661518739741713139656567965463 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg
_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.107078795886949379309542084082882326965037114589661518739741713139656567965463
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.48312474860731280831769231409025825671941842545867248306964112207010503216257
Short name T226
Test name
Test status
Simulation time 131849903 ps
CPU time 1.12 seconds
Started Nov 22 12:31:57 PM PST 23
Finished Nov 22 12:32:00 PM PST 23
Peak memory 200400 kb
Host smart-81b3d1a7-3f49-460a-8934-97c2c3c066a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48312474860731280831769231409025825671941842545867248306964112207010503216257 -assert n
opostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err.48312474860731280831769231409025825671941842545867248306964112207010503216257
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.38479859393300659877741350809963083963788090428305857386026745367932822017853
Short name T975
Test name
Test status
Simulation time 51975542 ps
CPU time 0.81 seconds
Started Nov 22 01:25:50 PM PST 23
Finished Nov 22 01:25:54 PM PST 23
Peak memory 198972 kb
Host smart-debf3e09-84b4-4da7-8569-beac6c14820e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38479859393300659877741350809963083963788090428305857386026745367932822017853 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 0.pwrmgr_aborted_low_power.38479859393300659877741350809963083963788090428305857386026745367932822017853
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.19087054310132273529421849552358621395965786108149699705742914283274351499125
Short name T795
Test name
Test status
Simulation time 72403950 ps
CPU time 0.76 seconds
Started Nov 22 01:26:00 PM PST 23
Finished Nov 22 01:26:06 PM PST 23
Peak memory 198256 kb
Host smart-1e3f5d3b-b9c5-49ce-9b79-fc0ec4d1bf4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19087054310132273529421849552358621395965786108149699705742914283274351499125 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disable_rom_integrity_check.1908705431013227352942184955235862139596578610814969970
5742914283274351499125
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.114485980670747615153021647708540738555810990984459093141162047535085850565666
Short name T1052
Test name
Test status
Simulation time 30368572 ps
CPU time 0.61 seconds
Started Nov 22 01:26:03 PM PST 23
Finished Nov 22 01:26:09 PM PST 23
Peak memory 195460 kb
Host smart-3a7761ec-28bb-4bb4-8def-0520ddb61061
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114485980670747615153021647708540738555810990984459093141162047535085850565666 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_malfunc.114485980670747615153021647708540738555810990984459093141162047535085850565666
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.56982179569603317195066302650231007074762711194085247438829704735606433439902
Short name T165
Test name
Test status
Simulation time 39672069 ps
CPU time 0.62 seconds
Started Nov 22 01:26:01 PM PST 23
Finished Nov 22 01:26:06 PM PST 23
Peak memory 195508 kb
Host smart-93e29802-4ea7-4c6c-91c1-ff39245948f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56982179569603317195066302650231007074762711194085247438829704735606433439902 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.56982179569603317195066302650231007074762711194085247438829704735606433439902
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.94128972318372929125886648903832742503180878541702944534489581923349925232224
Short name T163
Test name
Test status
Simulation time 33172121 ps
CPU time 0.6 seconds
Started Nov 22 01:26:01 PM PST 23
Finished Nov 22 01:26:06 PM PST 23
Peak memory 196756 kb
Host smart-579f1b54-a237-4b25-8c9e-34cab4901c39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94128972318372929125886648903832742503180878541702944534489581923349925232224 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.94128972318372929125886648903832742503180878541702944534489581923349925232224
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.69695462209213710146038177515616139619695329933927501513585195045652408597563
Short name T639
Test name
Test status
Simulation time 49975558 ps
CPU time 0.68 seconds
Started Nov 22 01:25:46 PM PST 23
Finished Nov 22 01:25:51 PM PST 23
Peak memory 201284 kb
Host smart-d8183b2a-bd9d-477b-bf3d-bd7d001b67aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69695462209213710146038177515616139619695329933927501513585195045652408597563 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invalid.69695462209213710146038177515616139619695329933927501513585195045652408597563
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_wakeup_race.16789591630349345823676756140009809653108438048116175381018584560437992989765
Short name T461
Test name
Test status
Simulation time 296241445 ps
CPU time 1.16 seconds
Started Nov 22 01:25:47 PM PST 23
Finished Nov 22 01:25:52 PM PST 23
Peak memory 200060 kb
Host smart-a0940655-be54-4358-be99-994ccbd04758
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16789591630349345823676756140009809653108438048116175381018584560437992989765 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wakeup_race.16789591630349345823676756140009809653108438048116175381018584560437992989765
Directory /workspace/0.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.21825485559366725431557935686194875361450462729329220358628543563380782105076
Short name T673
Test name
Test status
Simulation time 119707143 ps
CPU time 1.04 seconds
Started Nov 22 01:26:02 PM PST 23
Finished Nov 22 01:26:08 PM PST 23
Peak memory 199332 kb
Host smart-17ca611d-540d-45dd-b09d-d238ab2fb8b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21825485559366725431557935686194875361450462729329220358628543563380782105076 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.21825485559366725431557935686194875361450462729329220358628543563380782105076
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.64294783409521506923076168611427905151785436746580034455465634464573069155950
Short name T27
Test name
Test status
Simulation time 108189378 ps
CPU time 0.84 seconds
Started Nov 22 01:26:02 PM PST 23
Finished Nov 22 01:26:08 PM PST 23
Peak memory 209536 kb
Host smart-cd3d4d9d-e1cc-479a-a0eb-54081ecee4f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64294783409521506923076168611427905151785436746580034455465634464573069155950 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.64294783409521506923076168611427905151785436746580034455465634464573069155950
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.71607109001816706045756857196144590680916402594065084022690872905641666240819
Short name T1046
Test name
Test status
Simulation time 314830582 ps
CPU time 1.42 seconds
Started Nov 22 01:26:01 PM PST 23
Finished Nov 22 01:26:07 PM PST 23
Peak memory 199820 kb
Host smart-31316153-bac2-4537-9271-be927d42cffe
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71607109001816706045756857196144590680916402594065084022690872905641666240819 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_ctrl_config_regwen.7160710900181670604575685719614459068091640259406508402269
0872905641666240819
Directory /workspace/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.97114183517593465688700640014707561461188604728526328321480748812154194675943
Short name T375
Test name
Test status
Simulation time 919450745 ps
CPU time 2.82 seconds
Started Nov 22 01:25:50 PM PST 23
Finished Nov 22 01:25:56 PM PST 23
Peak memory 201244 kb
Host smart-fef3d981-6adf-4dd9-80e3-b6edcc418c8a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971141835175934656887006400147075614611886047285263283214807
48812154194675943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.971141835175934656887006400
14707561461188604728526328321480748812154194675943
Directory /workspace/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.91086397853436115878941549799686686322176357961429298243243223072753864133075
Short name T1053
Test name
Test status
Simulation time 968503924 ps
CPU time 2.9 seconds
Started Nov 22 01:26:06 PM PST 23
Finished Nov 22 01:26:15 PM PST 23
Peak memory 201204 kb
Host smart-1a3e348d-148d-4d5d-8fb6-7e7f97b550b1
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91086397853436115878941549799686686322176357961429298243243
223072753864133075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.9108639785343611587894154
9799686686322176357961429298243243223072753864133075
Directory /workspace/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.100658026834725951129695393510623024207147203577788651044154065113348117031218
Short name T403
Test name
Test status
Simulation time 91600225 ps
CPU time 0.89 seconds
Started Nov 22 01:26:04 PM PST 23
Finished Nov 22 01:26:11 PM PST 23
Peak memory 195528 kb
Host smart-7edd48c5-08c7-49ac-9318-e39a961b3bef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100658026834725951129695393510623024207147203577788651044154065113348117031218 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_mubi.100658026834725951129695393510623024207147203577788651044154065113348117031218
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.8669046308692654389153506125808728270212595179991523412433237664827486701928
Short name T395
Test name
Test status
Simulation time 35743529 ps
CPU time 0.65 seconds
Started Nov 22 01:25:35 PM PST 23
Finished Nov 22 01:25:46 PM PST 23
Peak memory 197792 kb
Host smart-72cc0233-546b-45ee-9728-01806f45037b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8669046308692654389153506125808728270212595179991523412433237664827486701928 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.8669046308692654389153506125808728270212595179991523412433237664827486701928
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/0.pwrmgr_stress_all.36040747886293404662843228358201767686330457888306287892064964052458979515402
Short name T652
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.65 seconds
Started Nov 22 01:25:52 PM PST 23
Finished Nov 22 01:26:04 PM PST 23
Peak memory 201216 kb
Host smart-883bf26b-d773-4da8-b6e3-ba641cbb2d63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36040747886293404662843228358201767686330457888306287892064964052458979515402 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.36040747886293404662843228358201767686330457888306287892064964052458979515402
Directory /workspace/0.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/0.pwrmgr_stress_all_with_rand_reset.78019384957913741112357673176080239193556602409363784225207218001583281517869
Short name T424
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.21 seconds
Started Nov 22 01:26:03 PM PST 23
Finished Nov 22 01:26:19 PM PST 23
Peak memory 201344 kb
Host smart-c8677f6b-a55d-4da2-ad21-2364930280ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780193849579137411123576
73176080239193556602409363784225207218001583281517869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all_with_rand_reset.780193
84957913741112357673176080239193556602409363784225207218001583281517869
Directory /workspace/0.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup.98192326065221385435382234407031465599990996192626790720721732074680790020356
Short name T664
Test name
Test status
Simulation time 283777259 ps
CPU time 1.17 seconds
Started Nov 22 01:25:49 PM PST 23
Finished Nov 22 01:25:54 PM PST 23
Peak memory 200080 kb
Host smart-98baaeed-7bab-46ab-85df-58912f167a1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98192326065221385435382234407031465599990996192626790720721732074680790020356 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.98192326065221385435382234407031465599990996192626790720721732074680790020356
Directory /workspace/0.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup_reset.111076328605995774219449353045472873189030175450838895231929936592464712820239
Short name T377
Test name
Test status
Simulation time 325437640 ps
CPU time 1.44 seconds
Started Nov 22 01:25:30 PM PST 23
Finished Nov 22 01:25:40 PM PST 23
Peak memory 200792 kb
Host smart-10bcee53-48bb-4c50-91a1-aa53903f831c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111076328605995774219449353045472873189030175450838895231929936592464712820239 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.111076328605995774219449353045472873189030175450838895231929936592464712820239
Directory /workspace/0.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.78202115599008602334335619957662025576158981032002046319609908700973906427999
Short name T465
Test name
Test status
Simulation time 51975542 ps
CPU time 0.79 seconds
Started Nov 22 01:25:49 PM PST 23
Finished Nov 22 01:25:53 PM PST 23
Peak memory 198972 kb
Host smart-af23005f-cd1f-4a2d-80a6-841cd3042c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78202115599008602334335619957662025576158981032002046319609908700973906427999 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.pwrmgr_aborted_low_power.78202115599008602334335619957662025576158981032002046319609908700973906427999
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.12213270815940785335777782326221693113686120595924959268086022161991775124272
Short name T1044
Test name
Test status
Simulation time 72403950 ps
CPU time 0.75 seconds
Started Nov 22 01:25:51 PM PST 23
Finished Nov 22 01:25:58 PM PST 23
Peak memory 198080 kb
Host smart-947694bb-cc52-43a7-a755-44f6a707f9ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12213270815940785335777782326221693113686120595924959268086022161991775124272 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disable_rom_integrity_check.1221327081594078533577778232622169311368612059592495926
8086022161991775124272
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.2743500419717421854720224379720125517654845915673397441827361459126340321859
Short name T622
Test name
Test status
Simulation time 30368572 ps
CPU time 0.6 seconds
Started Nov 22 01:26:02 PM PST 23
Finished Nov 22 01:26:08 PM PST 23
Peak memory 195392 kb
Host smart-dc58ba5a-c804-486c-8e9d-3b82b7983c6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743500419717421854720224379720125517654845915673397441827361459126340321859 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_malfunc.2743500419717421854720224379720125517654845915673397441827361459126340321859
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.1225925430556835762131313702124741378842013336323531154434404670027686995920
Short name T764
Test name
Test status
Simulation time 39672069 ps
CPU time 0.67 seconds
Started Nov 22 01:26:07 PM PST 23
Finished Nov 22 01:26:13 PM PST 23
Peak memory 195484 kb
Host smart-0ee64cb7-d48e-47fb-b2db-1ccbc0c4d4d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225925430556835762131313702124741378842013336323531154434404670027686995920 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.1225925430556835762131313702124741378842013336323531154434404670027686995920
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.72237125998995483089446945178746830736992153279325074484438273424736426065697
Short name T588
Test name
Test status
Simulation time 33172121 ps
CPU time 0.59 seconds
Started Nov 22 01:25:51 PM PST 23
Finished Nov 22 01:25:56 PM PST 23
Peak memory 196660 kb
Host smart-394b23db-1ee7-4840-9857-089eeeb89862
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72237125998995483089446945178746830736992153279325074484438273424736426065697 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.72237125998995483089446945178746830736992153279325074484438273424736426065697
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.74537260399294146576001758230805228034559767347710532057584912142357786484365
Short name T855
Test name
Test status
Simulation time 49975558 ps
CPU time 0.71 seconds
Started Nov 22 01:26:07 PM PST 23
Finished Nov 22 01:26:13 PM PST 23
Peak memory 201388 kb
Host smart-72b6e618-b410-4981-96c6-d3755642eb74
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74537260399294146576001758230805228034559767347710532057584912142357786484365 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invalid.74537260399294146576001758230805228034559767347710532057584912142357786484365
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.3677238651758849845534007597896961330194326614322217923096378447768550584025
Short name T698
Test name
Test status
Simulation time 296241445 ps
CPU time 1.25 seconds
Started Nov 22 01:26:00 PM PST 23
Finished Nov 22 01:26:06 PM PST 23
Peak memory 199956 kb
Host smart-e4beb81d-14a3-42df-88ab-e25bd4543f6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677238651758849845534007597896961330194326614322217923096378447768550584025 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wakeup_race.3677238651758849845534007597896961330194326614322217923096378447768550584025
Directory /workspace/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.102710461155532004008917629277287376102614174372543548046970993673787215191530
Short name T1047
Test name
Test status
Simulation time 119707143 ps
CPU time 0.98 seconds
Started Nov 22 01:25:50 PM PST 23
Finished Nov 22 01:25:56 PM PST 23
Peak memory 199304 kb
Host smart-260c659e-36ca-4e81-a14d-e053e6ecbf49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102710461155532004008917629277287376102614174372543548046970993673787215191530 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.102710461155532004008917629277287376102614174372543548046970993673787215191530
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.5077317835112186868199471343980073360476595986667665042076367720728394280188
Short name T402
Test name
Test status
Simulation time 108189378 ps
CPU time 0.85 seconds
Started Nov 22 01:25:55 PM PST 23
Finished Nov 22 01:26:02 PM PST 23
Peak memory 209404 kb
Host smart-b05ddfde-e2d4-465d-a6cc-952671e1cace
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5077317835112186868199471343980073360476595986667665042076367720728394280188 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.5077317835112186868199471343980073360476595986667665042076367720728394280188
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.41192878389798808857742508358224801530540647529646296097222659319248493686858
Short name T16
Test name
Test status
Simulation time 344080348 ps
CPU time 1.26 seconds
Started Nov 22 01:26:10 PM PST 23
Finished Nov 22 01:26:17 PM PST 23
Peak memory 214400 kb
Host smart-02cbe778-682a-4129-88e1-5dee0cc1d183
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41192878389798808857742508358224801530540647529646296097222659319248493686858 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.41192878389798808857742508358224801530540647529646296097222659319248493686858
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.83316247120309163647338116132160336224372446790710651827132614827062199790082
Short name T707
Test name
Test status
Simulation time 314830582 ps
CPU time 1.29 seconds
Started Nov 22 01:25:49 PM PST 23
Finished Nov 22 01:25:54 PM PST 23
Peak memory 199892 kb
Host smart-c5f9877b-6f9d-484e-a7a9-5ba7d4bb2fb5
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83316247120309163647338116132160336224372446790710651827132614827062199790082 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_ctrl_config_regwen.8331624712030916364733811613216033622437244679071065182713
2614827062199790082
Directory /workspace/1.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.64044036291198142969438714337892221922825964314933571631594226758882658361259
Short name T775
Test name
Test status
Simulation time 919450745 ps
CPU time 2.96 seconds
Started Nov 22 01:26:01 PM PST 23
Finished Nov 22 01:26:09 PM PST 23
Peak memory 201260 kb
Host smart-99600b06-8ca1-45b3-9e69-9489023aa680
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640440362911981429694387143378922219228259643149335716315942
26758882658361259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.640440362911981429694387143
37892221922825964314933571631594226758882658361259
Directory /workspace/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.5839834424209318897119546230871895333228403205822700638939613273122597529976
Short name T893
Test name
Test status
Simulation time 968503924 ps
CPU time 2.93 seconds
Started Nov 22 01:25:43 PM PST 23
Finished Nov 22 01:25:51 PM PST 23
Peak memory 201200 kb
Host smart-7b1ade31-1db4-498e-8f76-38e90499c151
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58398344242093188971195462308718953332284032058227006389396
13273122597529976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.58398344242093188971195462
30871895333228403205822700638939613273122597529976
Directory /workspace/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.64735894682444460963748793962295199658403907877358982656818158237316720108969
Short name T498
Test name
Test status
Simulation time 91600225 ps
CPU time 0.91 seconds
Started Nov 22 01:26:12 PM PST 23
Finished Nov 22 01:26:19 PM PST 23
Peak memory 195432 kb
Host smart-8bc3a479-6844-4da4-9661-72ac825899bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64735894682444460963748793962295199658403907877358982656818158237316720108969 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_mubi.64735894682444460963748793962295199658403907877358982656818158237316720108969
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.64263854605960434698488614021827095318669201375874686654879340223885506244889
Short name T131
Test name
Test status
Simulation time 35743529 ps
CPU time 0.64 seconds
Started Nov 22 01:25:44 PM PST 23
Finished Nov 22 01:25:50 PM PST 23
Peak memory 197912 kb
Host smart-6c7112e8-b42a-4c1e-96d7-33e8c70e2516
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64263854605960434698488614021827095318669201375874686654879340223885506244889 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.64263854605960434698488614021827095318669201375874686654879340223885506244889
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_stress_all.113929913286445759044066096454401513977056889787081581858570933439975091797720
Short name T416
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.61 seconds
Started Nov 22 01:26:10 PM PST 23
Finished Nov 22 01:26:22 PM PST 23
Peak memory 201276 kb
Host smart-4e4fd8c4-752f-4051-8af2-14c94b158db0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113929913286445759044066096454401513977056889787081581858570933439975091797720 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.113929913286445759044066096454401513977056889787081581858570933439975091797720
Directory /workspace/1.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/1.pwrmgr_stress_all_with_rand_reset.75845067069334203693232705485843446992552108325491052187414303638803251860235
Short name T836
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.37 seconds
Started Nov 22 01:26:10 PM PST 23
Finished Nov 22 01:26:28 PM PST 23
Peak memory 201460 kb
Host smart-b6950360-3583-41ea-8206-afb7c58d1504
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758450670693342036932327
05485843446992552108325491052187414303638803251860235 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all_with_rand_reset.758450
67069334203693232705485843446992552108325491052187414303638803251860235
Directory /workspace/1.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup.92357046339548157046736037612028061511703352614868128557509478583417793185666
Short name T612
Test name
Test status
Simulation time 283777259 ps
CPU time 1.21 seconds
Started Nov 22 01:25:50 PM PST 23
Finished Nov 22 01:25:54 PM PST 23
Peak memory 200096 kb
Host smart-b7698f34-671c-4ef6-a9cd-94ca4c054058
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92357046339548157046736037612028061511703352614868128557509478583417793185666 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.92357046339548157046736037612028061511703352614868128557509478583417793185666
Directory /workspace/1.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup_reset.13202405895988110059263662007494456133570953664152532753597849572807427263191
Short name T925
Test name
Test status
Simulation time 325437640 ps
CPU time 1.37 seconds
Started Nov 22 01:26:01 PM PST 23
Finished Nov 22 01:26:06 PM PST 23
Peak memory 200712 kb
Host smart-dc371371-2ed3-4ee7-a2a7-c73c7ade905d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13202405895988110059263662007494456133570953664152532753597849572807427263191 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.13202405895988110059263662007494456133570953664152532753597849572807427263191
Directory /workspace/1.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.39262156820341602771416285090795523141389517703695530948116935322819434886282
Short name T7
Test name
Test status
Simulation time 51975542 ps
CPU time 0.8 seconds
Started Nov 22 01:26:03 PM PST 23
Finished Nov 22 01:26:08 PM PST 23
Peak memory 198996 kb
Host smart-420698d4-ec57-4aef-b29b-30e1569428a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39262156820341602771416285090795523141389517703695530948116935322819434886282 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.pwrmgr_aborted_low_power.39262156820341602771416285090795523141389517703695530948116935322819434886282
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.51541066910805151932022772892717524819501779154859919122232755751259896658431
Short name T793
Test name
Test status
Simulation time 72403950 ps
CPU time 0.74 seconds
Started Nov 22 01:26:09 PM PST 23
Finished Nov 22 01:26:16 PM PST 23
Peak memory 198272 kb
Host smart-8bf1b754-6a10-4121-a9a6-fe092fc40386
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51541066910805151932022772892717524819501779154859919122232755751259896658431 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_disable_rom_integrity_check.515410669108051519320227728927175248195017791548599191
22232755751259896658431
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.45773212627570010787637231983070476423055878508095045224474774047228847276546
Short name T472
Test name
Test status
Simulation time 30368572 ps
CPU time 0.6 seconds
Started Nov 22 01:26:09 PM PST 23
Finished Nov 22 01:26:16 PM PST 23
Peak memory 195472 kb
Host smart-66a4b075-666e-4a88-92ca-4a094bb18808
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45773212627570010787637231983070476423055878508095045224474774047228847276546 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst_malfunc.45773212627570010787637231983070476423055878508095045224474774047228847276546
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.7419568706796000880131955439270100201020505472967819975151290140181016206182
Short name T728
Test name
Test status
Simulation time 39672069 ps
CPU time 0.62 seconds
Started Nov 22 01:26:10 PM PST 23
Finished Nov 22 01:26:17 PM PST 23
Peak memory 195532 kb
Host smart-11a1255b-8d4e-4b4b-8341-f7d0519d84da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7419568706796000880131955439270100201020505472967819975151290140181016206182 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.7419568706796000880131955439270100201020505472967819975151290140181016206182
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.86841482811363424711902405930024354286384893768810408198790379728694562830024
Short name T574
Test name
Test status
Simulation time 33172121 ps
CPU time 0.68 seconds
Started Nov 22 01:26:13 PM PST 23
Finished Nov 22 01:26:20 PM PST 23
Peak memory 196108 kb
Host smart-23abbbf1-5332-4a78-a938-5f3256ba1099
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86841482811363424711902405930024354286384893768810408198790379728694562830024 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.86841482811363424711902405930024354286384893768810408198790379728694562830024
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.95630348334449965575742025348043420470733894425221769292966184996555744354919
Short name T515
Test name
Test status
Simulation time 49975558 ps
CPU time 0.74 seconds
Started Nov 22 01:26:13 PM PST 23
Finished Nov 22 01:26:20 PM PST 23
Peak memory 200656 kb
Host smart-3844d03e-e1ad-4e5e-aa33-3a5f3fbd9043
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95630348334449965575742025348043420470733894425221769292966184996555744354919 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_invalid.95630348334449965575742025348043420470733894425221769292966184996555744354919
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_wakeup_race.55149734145868439366413230524584061180763660504173975659867234781222370511486
Short name T121
Test name
Test status
Simulation time 296241445 ps
CPU time 1.27 seconds
Started Nov 22 01:25:58 PM PST 23
Finished Nov 22 01:26:05 PM PST 23
Peak memory 200028 kb
Host smart-f6743ba9-08ea-4e51-b358-de86c93dd8e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55149734145868439366413230524584061180763660504173975659867234781222370511486 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_wakeup_race.55149734145868439366413230524584061180763660504173975659867234781222370511486
Directory /workspace/10.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.55439600954746420203198432492334148843072640435341771830122738915006354162314
Short name T759
Test name
Test status
Simulation time 119707143 ps
CPU time 1.05 seconds
Started Nov 22 01:25:57 PM PST 23
Finished Nov 22 01:26:03 PM PST 23
Peak memory 199256 kb
Host smart-c709ff1b-ae6c-483d-b8dd-228630fceda2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55439600954746420203198432492334148843072640435341771830122738915006354162314 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.55439600954746420203198432492334148843072640435341771830122738915006354162314
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.97803111663095752492694320129939242389304389140997491243324546501875350703921
Short name T339
Test name
Test status
Simulation time 108189378 ps
CPU time 0.93 seconds
Started Nov 22 01:26:13 PM PST 23
Finished Nov 22 01:26:20 PM PST 23
Peak memory 208684 kb
Host smart-f54ea103-170e-4af2-82cc-e694f5f4b046
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97803111663095752492694320129939242389304389140997491243324546501875350703921 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.97803111663095752492694320129939242389304389140997491243324546501875350703921
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.94195918266462711606546653772338500793686488857311463567655205301176918543145
Short name T444
Test name
Test status
Simulation time 314830582 ps
CPU time 1.29 seconds
Started Nov 22 01:26:02 PM PST 23
Finished Nov 22 01:26:07 PM PST 23
Peak memory 199920 kb
Host smart-21e1df5b-4a67-4072-a07d-a543504150ad
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94195918266462711606546653772338500793686488857311463567655205301176918543145 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_ctrl_config_regwen.941959182664627116065466537723385007936864888573114635676
55205301176918543145
Directory /workspace/10.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.80917822342746686913996008390856755516786156050181431863340423061067886284205
Short name T884
Test name
Test status
Simulation time 919450745 ps
CPU time 3.02 seconds
Started Nov 22 01:26:07 PM PST 23
Finished Nov 22 01:26:15 PM PST 23
Peak memory 201248 kb
Host smart-b7c2c25d-af61-4ed6-bc68-c5117bf7e735
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809178223427466869139960083908567555167861560501814318633404
23061067886284205 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.80917822342746686913996008
390856755516786156050181431863340423061067886284205
Directory /workspace/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.51167843789855082851473345486281470069852291623588279202548131040801731649671
Short name T1022
Test name
Test status
Simulation time 968503924 ps
CPU time 3.13 seconds
Started Nov 22 01:25:58 PM PST 23
Finished Nov 22 01:26:06 PM PST 23
Peak memory 201132 kb
Host smart-c2c11ea1-1fec-40fe-b9f8-97a36a633e84
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51167843789855082851473345486281470069852291623588279202548
131040801731649671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.511678437898550828514733
45486281470069852291623588279202548131040801731649671
Directory /workspace/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.46773489861326291712385207721796377782927818611933180090738067703748908466313
Short name T636
Test name
Test status
Simulation time 91600225 ps
CPU time 0.95 seconds
Started Nov 22 01:25:59 PM PST 23
Finished Nov 22 01:26:05 PM PST 23
Peak memory 195540 kb
Host smart-d5fac49c-9421-4b16-aa61-59f231a5c46e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46773489861326291712385207721796377782927818611933180090738067703748908466313 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig_mubi.46773489861326291712385207721796377782927818611933180090738067703748908466313
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.14490437472098808622376763618431597471256810017214429128910718679400777771172
Short name T949
Test name
Test status
Simulation time 35743529 ps
CPU time 0.62 seconds
Started Nov 22 01:26:05 PM PST 23
Finished Nov 22 01:26:11 PM PST 23
Peak memory 197708 kb
Host smart-a3748f7b-ff9d-4547-9352-41e972f919d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14490437472098808622376763618431597471256810017214429128910718679400777771172 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.14490437472098808622376763618431597471256810017214429128910718679400777771172
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_stress_all.4932675655321440840540079353863716989609205888069745112591706689761013217963
Short name T746
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.95 seconds
Started Nov 22 01:26:01 PM PST 23
Finished Nov 22 01:26:11 PM PST 23
Peak memory 201316 kb
Host smart-d48c29fa-3578-40e5-b0bf-06b34b9a6d2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4932675655321440840540079353863716989609205888069745112591706689761013217963 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.4932675655321440840540079353863716989609205888069745112591706689761013217963
Directory /workspace/10.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/10.pwrmgr_stress_all_with_rand_reset.89670745599750410414161165363328015541464468005714935820007565897274674970193
Short name T18
Test name
Test status
Simulation time 4441243999 ps
CPU time 10.81 seconds
Started Nov 22 01:26:10 PM PST 23
Finished Nov 22 01:26:27 PM PST 23
Peak memory 200624 kb
Host smart-b6d9a648-20ca-459d-a703-8fdf00b68193
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896707455997504104141611
65363328015541464468005714935820007565897274674970193 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all_with_rand_reset.89670
745599750410414161165363328015541464468005714935820007565897274674970193
Directory /workspace/10.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup.81459539034761310212315591528300203135768191387045021348167573457783999097717
Short name T497
Test name
Test status
Simulation time 283777259 ps
CPU time 1.26 seconds
Started Nov 22 01:26:09 PM PST 23
Finished Nov 22 01:26:16 PM PST 23
Peak memory 200132 kb
Host smart-2903041d-f5c3-4302-adb9-6b692a671d47
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81459539034761310212315591528300203135768191387045021348167573457783999097717 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.81459539034761310212315591528300203135768191387045021348167573457783999097717
Directory /workspace/10.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup_reset.53924362852210865503121554107384406921284138661521484415757411453392296276879
Short name T711
Test name
Test status
Simulation time 325437640 ps
CPU time 1.38 seconds
Started Nov 22 01:25:57 PM PST 23
Finished Nov 22 01:26:03 PM PST 23
Peak memory 200728 kb
Host smart-a811813c-a5a6-4c52-81f0-37d064fb6771
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53924362852210865503121554107384406921284138661521484415757411453392296276879 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.53924362852210865503121554107384406921284138661521484415757411453392296276879
Directory /workspace/10.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.32716948882277874085881487738692699238261149360662176313039865925864044862049
Short name T958
Test name
Test status
Simulation time 51975542 ps
CPU time 0.79 seconds
Started Nov 22 01:26:08 PM PST 23
Finished Nov 22 01:26:14 PM PST 23
Peak memory 199128 kb
Host smart-1d01054e-b40b-431a-a3a3-6cb452b6a3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32716948882277874085881487738692699238261149360662176313039865925864044862049 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.pwrmgr_aborted_low_power.32716948882277874085881487738692699238261149360662176313039865925864044862049
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.110150525694091881539845171058222246376122730799357842285217949706923082036955
Short name T946
Test name
Test status
Simulation time 72403950 ps
CPU time 0.78 seconds
Started Nov 22 01:26:19 PM PST 23
Finished Nov 22 01:26:23 PM PST 23
Peak memory 198092 kb
Host smart-21a19d4e-0fa8-4dc6-a772-ce2c81fc72df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110150525694091881539845171058222246376122730799357842285217949706923082036955 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_disable_rom_integrity_check.11015052569409188153984517105822224637612273079935784
2285217949706923082036955
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.51539399740772262382816078712975104304385806928132798297256929173882405518118
Short name T437
Test name
Test status
Simulation time 39672069 ps
CPU time 0.67 seconds
Started Nov 22 01:26:59 PM PST 23
Finished Nov 22 01:27:17 PM PST 23
Peak memory 193424 kb
Host smart-3504f21f-f0ca-4700-9f60-386355cd684f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51539399740772262382816078712975104304385806928132798297256929173882405518118 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.51539399740772262382816078712975104304385806928132798297256929173882405518118
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.23162026317487421640150670363926181093584553681820506612030858336967652268143
Short name T594
Test name
Test status
Simulation time 33172121 ps
CPU time 0.57 seconds
Started Nov 22 01:27:07 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 196364 kb
Host smart-3f55fd7a-7428-48ff-90e3-745c5de1b844
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23162026317487421640150670363926181093584553681820506612030858336967652268143 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.23162026317487421640150670363926181093584553681820506612030858336967652268143
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.80034884463880779553778767859856759703568739124909858155654635025496985509417
Short name T841
Test name
Test status
Simulation time 49975558 ps
CPU time 0.81 seconds
Started Nov 22 01:27:18 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 198212 kb
Host smart-cc8f16d0-11ab-4117-9520-5af7ce9d4f7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80034884463880779553778767859856759703568739124909858155654635025496985509417 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_invalid.80034884463880779553778767859856759703568739124909858155654635025496985509417
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_wakeup_race.37763896021553057039795144620127155939450527596709997223656159109567575061932
Short name T160
Test name
Test status
Simulation time 296241445 ps
CPU time 1.23 seconds
Started Nov 22 01:26:12 PM PST 23
Finished Nov 22 01:26:20 PM PST 23
Peak memory 200096 kb
Host smart-279d8d21-c89c-4b45-8cd6-e089dacdb11b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37763896021553057039795144620127155939450527596709997223656159109567575061932 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_wakeup_race.37763896021553057039795144620127155939450527596709997223656159109567575061932
Directory /workspace/11.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.28348373337749263718577959666260058690021649999149044373265574819842447420237
Short name T1060
Test name
Test status
Simulation time 119707143 ps
CPU time 1.06 seconds
Started Nov 22 01:26:01 PM PST 23
Finished Nov 22 01:26:07 PM PST 23
Peak memory 199328 kb
Host smart-42551e7d-a07c-4d30-820e-b129974f89c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28348373337749263718577959666260058690021649999149044373265574819842447420237 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.28348373337749263718577959666260058690021649999149044373265574819842447420237
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.32058704799614920338934753950071524189083287694657940818141867747516004442737
Short name T649
Test name
Test status
Simulation time 108189378 ps
CPU time 0.8 seconds
Started Nov 22 01:27:01 PM PST 23
Finished Nov 22 01:27:18 PM PST 23
Peak memory 209060 kb
Host smart-4e8e6f41-feb3-4dad-a0f8-5ef3ff422e8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32058704799614920338934753950071524189083287694657940818141867747516004442737 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.32058704799614920338934753950071524189083287694657940818141867747516004442737
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.102523087415153510423906774027661683973391759811294535880190465255449203133673
Short name T484
Test name
Test status
Simulation time 314830582 ps
CPU time 1.26 seconds
Started Nov 22 01:27:00 PM PST 23
Finished Nov 22 01:27:18 PM PST 23
Peak memory 199412 kb
Host smart-a5ec16c9-4ad0-47c6-82db-e7a993e0789c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102523087415153510423906774027661683973391759811294535880190465255449203133673 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_ctrl_config_regwen.10252308741515351042390677402766168397339175981129453588
0190465255449203133673
Directory /workspace/11.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.30923532242471703649921576930050496338870519921212153035531758878099767953923
Short name T810
Test name
Test status
Simulation time 919450745 ps
CPU time 3.02 seconds
Started Nov 22 01:26:18 PM PST 23
Finished Nov 22 01:26:25 PM PST 23
Peak memory 201172 kb
Host smart-cd0ff43b-de3b-427c-a641-ccf7bdde6178
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309235322424717036499215769300504963388705199212121530355317
58878099767953923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.30923532242471703649921576
930050496338870519921212153035531758878099767953923
Directory /workspace/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.28715324604088206529420452742639832006612773253710162356202534286319025971363
Short name T344
Test name
Test status
Simulation time 968503924 ps
CPU time 2.98 seconds
Started Nov 22 01:27:01 PM PST 23
Finished Nov 22 01:27:20 PM PST 23
Peak memory 200736 kb
Host smart-cffaf522-d57e-416e-94e5-06262eefac56
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28715324604088206529420452742639832006612773253710162356202
534286319025971363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.287153246040882065294204
52742639832006612773253710162356202534286319025971363
Directory /workspace/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.73035290835919034910451093908067231325503076895421773714473197379060129806567
Short name T144
Test name
Test status
Simulation time 91600225 ps
CPU time 0.9 seconds
Started Nov 22 01:26:06 PM PST 23
Finished Nov 22 01:26:13 PM PST 23
Peak memory 195524 kb
Host smart-4083736c-da74-4287-8b4a-638327a91d7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73035290835919034910451093908067231325503076895421773714473197379060129806567 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig_mubi.73035290835919034910451093908067231325503076895421773714473197379060129806567
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.15205628227936205261807580211866069960253500147964349895022246127837995192883
Short name T867
Test name
Test status
Simulation time 35743529 ps
CPU time 0.65 seconds
Started Nov 22 01:26:10 PM PST 23
Finished Nov 22 01:26:16 PM PST 23
Peak memory 197932 kb
Host smart-07843015-fa7e-448f-aeef-19cf56a90dd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15205628227936205261807580211866069960253500147964349895022246127837995192883 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.15205628227936205261807580211866069960253500147964349895022246127837995192883
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_stress_all.20358187729021633063698783088148733612625222106161517178791467184855971723628
Short name T561
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.51 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:26 PM PST 23
Peak memory 200484 kb
Host smart-e2dc0b8a-c450-4879-9c35-a1e874600404
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20358187729021633063698783088148733612625222106161517178791467184855971723628 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.20358187729021633063698783088148733612625222106161517178791467184855971723628
Directory /workspace/11.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/11.pwrmgr_stress_all_with_rand_reset.98795239749857141768579164322880726344758807548673967736726822160043116466465
Short name T529
Test name
Test status
Simulation time 4441243999 ps
CPU time 10.85 seconds
Started Nov 22 01:27:07 PM PST 23
Finished Nov 22 01:27:32 PM PST 23
Peak memory 200996 kb
Host smart-a7abfb2e-1c07-4abf-a2a1-bdc5e3f06915
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987952397498571417685791
64322880726344758807548673967736726822160043116466465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all_with_rand_reset.98795
239749857141768579164322880726344758807548673967736726822160043116466465
Directory /workspace/11.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup.34067458068558620783572539873534463188982226729316163502356728842155040330741
Short name T419
Test name
Test status
Simulation time 283777259 ps
CPU time 1.18 seconds
Started Nov 22 01:26:04 PM PST 23
Finished Nov 22 01:26:11 PM PST 23
Peak memory 199840 kb
Host smart-f0614154-02cb-4c5b-a80d-7025df41be97
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34067458068558620783572539873534463188982226729316163502356728842155040330741 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.34067458068558620783572539873534463188982226729316163502356728842155040330741
Directory /workspace/11.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup_reset.43451228500106296511811936516151013462234246483448397083398945067996551849068
Short name T391
Test name
Test status
Simulation time 325437640 ps
CPU time 1.33 seconds
Started Nov 22 01:26:06 PM PST 23
Finished Nov 22 01:26:13 PM PST 23
Peak memory 200612 kb
Host smart-aa7c398e-3f09-4f9b-a2f6-5369b6889e9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43451228500106296511811936516151013462234246483448397083398945067996551849068 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.43451228500106296511811936516151013462234246483448397083398945067996551849068
Directory /workspace/11.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.83128720861946845113709448444745122399876956548393092344145712850333416320977
Short name T806
Test name
Test status
Simulation time 51975542 ps
CPU time 0.77 seconds
Started Nov 22 01:27:04 PM PST 23
Finished Nov 22 01:27:20 PM PST 23
Peak memory 199180 kb
Host smart-f0853c5d-ab1e-4d3d-aa44-4e36299208a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83128720861946845113709448444745122399876956548393092344145712850333416320977 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.pwrmgr_aborted_low_power.83128720861946845113709448444745122399876956548393092344145712850333416320977
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.66249434172000517144875901044112847894654221850308368530886792648908215188039
Short name T888
Test name
Test status
Simulation time 72403950 ps
CPU time 0.77 seconds
Started Nov 22 01:27:08 PM PST 23
Finished Nov 22 01:27:24 PM PST 23
Peak memory 197852 kb
Host smart-6d25074b-aab3-45d8-96de-00de395de7a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66249434172000517144875901044112847894654221850308368530886792648908215188039 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_disable_rom_integrity_check.662494341720005171448759010441128478946542218503083685
30886792648908215188039
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.24520611399387131495830418290778094264984388003294858495396230096934461673079
Short name T1009
Test name
Test status
Simulation time 30368572 ps
CPU time 0.61 seconds
Started Nov 22 01:26:28 PM PST 23
Finished Nov 22 01:26:32 PM PST 23
Peak memory 195372 kb
Host smart-a6e91ae4-0fe4-40a7-b8a9-9b47aba77fee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24520611399387131495830418290778094264984388003294858495396230096934461673079 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst_malfunc.24520611399387131495830418290778094264984388003294858495396230096934461673079
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.112042639827625773039560910089991132531311764229614418864324719072614703008232
Short name T304
Test name
Test status
Simulation time 39672069 ps
CPU time 0.6 seconds
Started Nov 22 01:27:07 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 194904 kb
Host smart-f76f7249-da04-4425-a5c4-3426522f0bcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112042639827625773039560910089991132531311764229614418864324719072614703008232 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.112042639827625773039560910089991132531311764229614418864324719072614703008232
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.81996631059841078132669967441091761971029464668535776763033648166743333907853
Short name T501
Test name
Test status
Simulation time 33172121 ps
CPU time 0.59 seconds
Started Nov 22 01:26:32 PM PST 23
Finished Nov 22 01:26:35 PM PST 23
Peak memory 196760 kb
Host smart-93e879c3-2bb9-45dc-a3c8-510acdd155c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81996631059841078132669967441091761971029464668535776763033648166743333907853 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.81996631059841078132669967441091761971029464668535776763033648166743333907853
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.8407962518213571899677496917977216321328222705174170185137785073129849610333
Short name T661
Test name
Test status
Simulation time 49975558 ps
CPU time 0.64 seconds
Started Nov 22 01:26:34 PM PST 23
Finished Nov 22 01:26:37 PM PST 23
Peak memory 201188 kb
Host smart-96d05f90-58c2-4fe9-9f62-8928d6299f34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8407962518213571899677496917977216321328222705174170185137785073129849610333 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_invalid.8407962518213571899677496917977216321328222705174170185137785073129849610333
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_wakeup_race.61804659849659430232879136905807491823263171209126493814957130876383142989595
Short name T709
Test name
Test status
Simulation time 296241445 ps
CPU time 1.21 seconds
Started Nov 22 01:26:25 PM PST 23
Finished Nov 22 01:26:28 PM PST 23
Peak memory 200112 kb
Host smart-9b7608b2-4f51-4bb7-adb1-1daeafe7e852
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61804659849659430232879136905807491823263171209126493814957130876383142989595 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_wakeup_race.61804659849659430232879136905807491823263171209126493814957130876383142989595
Directory /workspace/12.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.86651198651949713571352819137358836861140140105057801909445990059507335135542
Short name T758
Test name
Test status
Simulation time 119707143 ps
CPU time 1 seconds
Started Nov 22 01:26:35 PM PST 23
Finished Nov 22 01:26:38 PM PST 23
Peak memory 199144 kb
Host smart-200fc1ec-dcc6-402f-8f0a-bdee4ba0b8fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86651198651949713571352819137358836861140140105057801909445990059507335135542 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.86651198651949713571352819137358836861140140105057801909445990059507335135542
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.86082192821537290194392599452653186064110000165769127759577068200767792009089
Short name T467
Test name
Test status
Simulation time 108189378 ps
CPU time 0.83 seconds
Started Nov 22 01:26:24 PM PST 23
Finished Nov 22 01:26:27 PM PST 23
Peak memory 209524 kb
Host smart-0ab3bf1a-76ec-4318-9a28-014e1ca8f4ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86082192821537290194392599452653186064110000165769127759577068200767792009089 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.86082192821537290194392599452653186064110000165769127759577068200767792009089
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.50756473353027412198983513057026194626977432466309474933539478869634208626
Short name T552
Test name
Test status
Simulation time 314830582 ps
CPU time 1.28 seconds
Started Nov 22 01:26:25 PM PST 23
Finished Nov 22 01:26:28 PM PST 23
Peak memory 199808 kb
Host smart-afc6933b-f5df-4f07-a8e2-51587514227b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50756473353027412198983513057026194626977432466309474933539478869634208626 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_ctrl_config_regwen.507564733530274121989835130570261946269774324663094749335394
78869634208626
Directory /workspace/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.12105645925364558429889522542179859123227919959775597568339418034591542987022
Short name T628
Test name
Test status
Simulation time 919450745 ps
CPU time 2.9 seconds
Started Nov 22 01:26:25 PM PST 23
Finished Nov 22 01:26:30 PM PST 23
Peak memory 201220 kb
Host smart-82034096-0c36-4807-a3bc-4e8400155afe
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121056459253645584298895225421798591232279199597755975683394
18034591542987022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.12105645925364558429889522
542179859123227919959775597568339418034591542987022
Directory /workspace/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.109517378569784400739662740650663491162266205481148203522068528937422690409815
Short name T802
Test name
Test status
Simulation time 968503924 ps
CPU time 2.79 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:23 PM PST 23
Peak memory 199456 kb
Host smart-45f41f15-0ea3-426d-94dc-3d44e0134bd7
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10951737856978440073966274065066349116226620548114820352206
8528937422690409815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.10951737856978440073966
2740650663491162266205481148203522068528937422690409815
Directory /workspace/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.90211431911110559433642502847171465601884590022808787784011345833804229965107
Short name T620
Test name
Test status
Simulation time 91600225 ps
CPU time 0.88 seconds
Started Nov 22 01:26:26 PM PST 23
Finished Nov 22 01:26:29 PM PST 23
Peak memory 195360 kb
Host smart-3268f951-8466-4175-9fd5-96d6a1fc3728
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90211431911110559433642502847171465601884590022808787784011345833804229965107 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig_mubi.90211431911110559433642502847171465601884590022808787784011345833804229965107
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.39500257720283783599027427958905579809219615091304635206872415909473494118440
Short name T22
Test name
Test status
Simulation time 35743529 ps
CPU time 0.61 seconds
Started Nov 22 01:27:33 PM PST 23
Finished Nov 22 01:27:48 PM PST 23
Peak memory 197556 kb
Host smart-70bc774f-1d14-4736-886b-4d9f942a9459
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39500257720283783599027427958905579809219615091304635206872415909473494118440 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.39500257720283783599027427958905579809219615091304635206872415909473494118440
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_stress_all.48791825781735856880640362526931930420049317745012402478092772596180489493548
Short name T995
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.32 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:25 PM PST 23
Peak memory 199248 kb
Host smart-74f9ad9a-b657-4550-a9f7-01ee5ffc68a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48791825781735856880640362526931930420049317745012402478092772596180489493548 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.48791825781735856880640362526931930420049317745012402478092772596180489493548
Directory /workspace/12.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/12.pwrmgr_stress_all_with_rand_reset.69948595839392119600173700942726354602592206312440481564334741608347549430349
Short name T672
Test name
Test status
Simulation time 4441243999 ps
CPU time 10.92 seconds
Started Nov 22 01:27:18 PM PST 23
Finished Nov 22 01:27:45 PM PST 23
Peak memory 198440 kb
Host smart-c035b987-533d-468a-854b-bcb090a4ee3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699485958393921196001737
00942726354602592206312440481564334741608347549430349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all_with_rand_reset.69948
595839392119600173700942726354602592206312440481564334741608347549430349
Directory /workspace/12.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup.5173829357117242007225697748664816848025835906974311194690102739356844594675
Short name T477
Test name
Test status
Simulation time 283777259 ps
CPU time 1.17 seconds
Started Nov 22 01:26:18 PM PST 23
Finished Nov 22 01:26:23 PM PST 23
Peak memory 200096 kb
Host smart-44566efa-4c01-445d-a66a-e26f92df24f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5173829357117242007225697748664816848025835906974311194690102739356844594675 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.5173829357117242007225697748664816848025835906974311194690102739356844594675
Directory /workspace/12.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup_reset.77138377631752912347840700940012533026213986167718065145526163007221570518801
Short name T159
Test name
Test status
Simulation time 325437640 ps
CPU time 1.33 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 200784 kb
Host smart-baf2621a-e3b9-4783-87bc-53f35dc28cb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77138377631752912347840700940012533026213986167718065145526163007221570518801 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.77138377631752912347840700940012533026213986167718065145526163007221570518801
Directory /workspace/12.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.12889024591324618204400799200622963368444935192781454956777493267462810012650
Short name T745
Test name
Test status
Simulation time 51975542 ps
CPU time 0.97 seconds
Started Nov 22 01:27:18 PM PST 23
Finished Nov 22 01:27:36 PM PST 23
Peak memory 196500 kb
Host smart-aeccdd0f-2e82-4ff1-8d1c-05669abe4a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12889024591324618204400799200622963368444935192781454956777493267462810012650 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 13.pwrmgr_aborted_low_power.12889024591324618204400799200622963368444935192781454956777493267462810012650
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.68188809379683905321903895992229041540132006968119300843636344158042039422373
Short name T920
Test name
Test status
Simulation time 30368572 ps
CPU time 0.59 seconds
Started Nov 22 01:26:36 PM PST 23
Finished Nov 22 01:26:38 PM PST 23
Peak memory 195252 kb
Host smart-d0e8e50b-a573-4f3c-b354-28726a943227
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68188809379683905321903895992229041540132006968119300843636344158042039422373 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst_malfunc.68188809379683905321903895992229041540132006968119300843636344158042039422373
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.926819654939365934609904126201884577757945309318591731845432747115565614142
Short name T1030
Test name
Test status
Simulation time 39672069 ps
CPU time 0.63 seconds
Started Nov 22 01:26:27 PM PST 23
Finished Nov 22 01:26:31 PM PST 23
Peak memory 195456 kb
Host smart-2afb867d-d195-4cd7-8c79-9802326e1c0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926819654939365934609904126201884577757945309318591731845432747115565614142 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.926819654939365934609904126201884577757945309318591731845432747115565614142
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.115171897347918824527909308383189809662520280357729899335680142560934014594679
Short name T295
Test name
Test status
Simulation time 33172121 ps
CPU time 0.67 seconds
Started Nov 22 01:26:31 PM PST 23
Finished Nov 22 01:26:34 PM PST 23
Peak memory 196756 kb
Host smart-b06bffad-159f-410a-ac11-5bdd09f654c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115171897347918824527909308383189809662520280357729899335680142560934014594679 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.115171897347918824527909308383189809662520280357729899335680142560934014594679
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.86359327568838943412738889208903689984027725825119079909212491703493557780375
Short name T619
Test name
Test status
Simulation time 49975558 ps
CPU time 0.68 seconds
Started Nov 22 01:26:23 PM PST 23
Finished Nov 22 01:26:26 PM PST 23
Peak memory 201280 kb
Host smart-f2d9ebdc-5c96-4a63-b07b-194302600b83
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86359327568838943412738889208903689984027725825119079909212491703493557780375 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_invalid.86359327568838943412738889208903689984027725825119079909212491703493557780375
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_wakeup_race.96544080442822635243027190089385550726020472360519495288560927809563535317955
Short name T778
Test name
Test status
Simulation time 296241445 ps
CPU time 1.11 seconds
Started Nov 22 01:27:07 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 199536 kb
Host smart-45147eea-0294-4593-9d32-4ad8a320aa49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96544080442822635243027190089385550726020472360519495288560927809563535317955 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_wakeup_race.96544080442822635243027190089385550726020472360519495288560927809563535317955
Directory /workspace/13.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.102365692208766583786582502987109276775044418382945283208467182610967147123915
Short name T162
Test name
Test status
Simulation time 119707143 ps
CPU time 1.04 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 197140 kb
Host smart-b241506d-c89f-478e-9573-68b34df76cce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102365692208766583786582502987109276775044418382945283208467182610967147123915 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.102365692208766583786582502987109276775044418382945283208467182610967147123915
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.95235160579295995550984055944109586707361683607031763003574379921491613766492
Short name T748
Test name
Test status
Simulation time 108189378 ps
CPU time 0.85 seconds
Started Nov 22 01:26:22 PM PST 23
Finished Nov 22 01:26:25 PM PST 23
Peak memory 209548 kb
Host smart-eb3601b6-3772-49c6-9a45-597abc511138
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95235160579295995550984055944109586707361683607031763003574379921491613766492 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.95235160579295995550984055944109586707361683607031763003574379921491613766492
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.11458589358542415869293694096844597573653823260195954616883675690258430356567
Short name T511
Test name
Test status
Simulation time 919450745 ps
CPU time 2.66 seconds
Started Nov 22 01:27:08 PM PST 23
Finished Nov 22 01:27:24 PM PST 23
Peak memory 200796 kb
Host smart-ef605a54-2540-4723-871c-9692dca0bb4a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114585893585424158692936940968445975736538232601959546168836
75690258430356567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.11458589358542415869293694
096844597573653823260195954616883675690258430356567
Directory /workspace/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.104018105442665824523697119129946735331048626199765690575344348122405102653211
Short name T675
Test name
Test status
Simulation time 968503924 ps
CPU time 3.11 seconds
Started Nov 22 01:26:25 PM PST 23
Finished Nov 22 01:26:31 PM PST 23
Peak memory 201196 kb
Host smart-4d418abe-d9dc-4790-b288-3c6a62cea419
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10401810544266582452369711912994673533104862619976569057534
4348122405102653211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.10401810544266582452369
7119129946735331048626199765690575344348122405102653211
Directory /workspace/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.49700734975012978766908031301397868211847675557307600840115202498772528442572
Short name T648
Test name
Test status
Simulation time 91600225 ps
CPU time 0.85 seconds
Started Nov 22 01:26:25 PM PST 23
Finished Nov 22 01:26:27 PM PST 23
Peak memory 195360 kb
Host smart-fcbd0fe2-7cae-42e3-8bee-c2d29eb06228
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49700734975012978766908031301397868211847675557307600840115202498772528442572 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig_mubi.49700734975012978766908031301397868211847675557307600840115202498772528442572
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.74663100809481090095011626026967031423559511447519077570664539715331236704847
Short name T349
Test name
Test status
Simulation time 35743529 ps
CPU time 0.76 seconds
Started Nov 22 01:27:18 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 194744 kb
Host smart-ee0836f0-cf1b-4118-86c9-19e9d8cba425
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74663100809481090095011626026967031423559511447519077570664539715331236704847 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.74663100809481090095011626026967031423559511447519077570664539715331236704847
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all.39752436036370018359693174578840808215035086947314534755278633792237674997238
Short name T663
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.65 seconds
Started Nov 22 01:26:26 PM PST 23
Finished Nov 22 01:26:36 PM PST 23
Peak memory 201272 kb
Host smart-873e395f-1f88-4d65-9718-6ff0855311f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39752436036370018359693174578840808215035086947314534755278633792237674997238 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.39752436036370018359693174578840808215035086947314534755278633792237674997238
Directory /workspace/13.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all_with_rand_reset.409779034730828510543822940398911112493026681690340495643905164484658347773
Short name T418
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.14 seconds
Started Nov 22 01:26:35 PM PST 23
Finished Nov 22 01:26:48 PM PST 23
Peak memory 201300 kb
Host smart-e566f461-2134-44c0-9cd3-03270c208ccc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409779034730828510543822
940398911112493026681690340495643905164484658347773 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all_with_rand_reset.4097790
34730828510543822940398911112493026681690340495643905164484658347773
Directory /workspace/13.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup.49401509771851633273188155397908176967339996331925471023568107982155532803014
Short name T440
Test name
Test status
Simulation time 283777259 ps
CPU time 1.13 seconds
Started Nov 22 01:27:33 PM PST 23
Finished Nov 22 01:27:48 PM PST 23
Peak memory 199756 kb
Host smart-f74794c0-9864-47b0-b2bd-55f0b419419d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49401509771851633273188155397908176967339996331925471023568107982155532803014 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.49401509771851633273188155397908176967339996331925471023568107982155532803014
Directory /workspace/13.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup_reset.91234955285966315618979257746685861944589685400550022064879916546367515876580
Short name T401
Test name
Test status
Simulation time 325437640 ps
CPU time 1.35 seconds
Started Nov 22 01:27:05 PM PST 23
Finished Nov 22 01:27:22 PM PST 23
Peak memory 200092 kb
Host smart-a6d6cd98-1f48-40c3-9bf4-bcff98c8151d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91234955285966315618979257746685861944589685400550022064879916546367515876580 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.91234955285966315618979257746685861944589685400550022064879916546367515876580
Directory /workspace/13.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.103391483054514045508759368876043162991092260634775752541217554156914191349627
Short name T631
Test name
Test status
Simulation time 51975542 ps
CPU time 0.84 seconds
Started Nov 22 01:26:27 PM PST 23
Finished Nov 22 01:26:32 PM PST 23
Peak memory 199132 kb
Host smart-3c4a9cb8-8553-4656-8133-8d9bb22068d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103391483054514045508759368876043162991092260634775752541217554156914191349627 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.pwrmgr_aborted_low_power.103391483054514045508759368876043162991092260634775752541217554156914191349627
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.70261742388830745877265327382086332634394928558932181010751210355704414882784
Short name T496
Test name
Test status
Simulation time 72403950 ps
CPU time 0.89 seconds
Started Nov 22 01:26:25 PM PST 23
Finished Nov 22 01:26:28 PM PST 23
Peak memory 198224 kb
Host smart-618479f7-d99d-4bc1-a1db-3f93f1443fec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70261742388830745877265327382086332634394928558932181010751210355704414882784 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_disable_rom_integrity_check.702617423888307458772653273820863326343949285589321810
10751210355704414882784
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.98680963253139729488598996463605429963047442144783802185767256012856489150843
Short name T171
Test name
Test status
Simulation time 30368572 ps
CPU time 0.6 seconds
Started Nov 22 01:26:32 PM PST 23
Finished Nov 22 01:26:34 PM PST 23
Peak memory 195372 kb
Host smart-2de7240e-87a7-4fff-8ef4-6f6987a02661
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98680963253139729488598996463605429963047442144783802185767256012856489150843 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst_malfunc.98680963253139729488598996463605429963047442144783802185767256012856489150843
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.98110976104331082706804885092587420222469538858166068329998090690572614094005
Short name T463
Test name
Test status
Simulation time 39672069 ps
CPU time 0.7 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 193104 kb
Host smart-231edef3-bf5a-4bc1-a5ae-6ee085c71bc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98110976104331082706804885092587420222469538858166068329998090690572614094005 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.98110976104331082706804885092587420222469538858166068329998090690572614094005
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.55093980818153004213083370814498519074487141922754184027192662660641895795951
Short name T930
Test name
Test status
Simulation time 33172121 ps
CPU time 0.57 seconds
Started Nov 22 01:26:26 PM PST 23
Finished Nov 22 01:26:29 PM PST 23
Peak memory 196824 kb
Host smart-6167cbe5-06c3-4b23-9f3d-7ece9bfbcb11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55093980818153004213083370814498519074487141922754184027192662660641895795951 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.55093980818153004213083370814498519074487141922754184027192662660641895795951
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.42954370113582644358038102061626010930476905450317709072631192929997191309896
Short name T692
Test name
Test status
Simulation time 49975558 ps
CPU time 0.65 seconds
Started Nov 22 01:27:18 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 200916 kb
Host smart-ead4f97b-1097-47a7-b72a-fd9dc4ba3222
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42954370113582644358038102061626010930476905450317709072631192929997191309896 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_invalid.42954370113582644358038102061626010930476905450317709072631192929997191309896
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_wakeup_race.79095072063517527819924512184365546721724785208534697459470928133660274532009
Short name T792
Test name
Test status
Simulation time 296241445 ps
CPU time 1.16 seconds
Started Nov 22 01:27:08 PM PST 23
Finished Nov 22 01:27:25 PM PST 23
Peak memory 199660 kb
Host smart-f9d3f8ee-f767-4ebb-b4ec-d697b860ec8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79095072063517527819924512184365546721724785208534697459470928133660274532009 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_wakeup_race.79095072063517527819924512184365546721724785208534697459470928133660274532009
Directory /workspace/14.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.104349363856506168828137389474868607892554333270340774616231457326052473570834
Short name T392
Test name
Test status
Simulation time 119707143 ps
CPU time 1.05 seconds
Started Nov 22 01:26:28 PM PST 23
Finished Nov 22 01:26:32 PM PST 23
Peak memory 199364 kb
Host smart-2f72f4e4-8898-43f2-a379-afbca51f1c31
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104349363856506168828137389474868607892554333270340774616231457326052473570834 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.104349363856506168828137389474868607892554333270340774616231457326052473570834
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.89716839729314926356029075702111355344818225527919510936279096737852700014667
Short name T687
Test name
Test status
Simulation time 108189378 ps
CPU time 0.9 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 206544 kb
Host smart-f48ba289-65f5-442e-a92f-280189963bfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89716839729314926356029075702111355344818225527919510936279096737852700014667 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.89716839729314926356029075702111355344818225527919510936279096737852700014667
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.77466270284348864876994084015349875693162901497771842431506208680584339440068
Short name T292
Test name
Test status
Simulation time 314830582 ps
CPU time 1.28 seconds
Started Nov 22 01:26:26 PM PST 23
Finished Nov 22 01:26:30 PM PST 23
Peak memory 199896 kb
Host smart-93454c8b-cb1b-4b4a-bd84-172fbb7e87fa
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77466270284348864876994084015349875693162901497771842431506208680584339440068 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_ctrl_config_regwen.774662702843488648769940840153498756931629014977718424315
06208680584339440068
Directory /workspace/14.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.67668501081699876928268881291424652518463662793697862860175124235586948758092
Short name T926
Test name
Test status
Simulation time 919450745 ps
CPU time 2.78 seconds
Started Nov 22 01:27:11 PM PST 23
Finished Nov 22 01:27:32 PM PST 23
Peak memory 200828 kb
Host smart-67e9d626-b473-4608-8639-3419f2203254
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676685010816998769282688812914246525184636627936978628601751
24235586948758092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.67668501081699876928268881
291424652518463662793697862860175124235586948758092
Directory /workspace/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.53268020541119569250427581639916605478276216119281073937632245544729251486233
Short name T136
Test name
Test status
Simulation time 968503924 ps
CPU time 2.99 seconds
Started Nov 22 01:26:35 PM PST 23
Finished Nov 22 01:26:40 PM PST 23
Peak memory 201020 kb
Host smart-84e54ed0-9d83-41d6-9151-6bfb370f7fce
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53268020541119569250427581639916605478276216119281073937632
245544729251486233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.532680205411195692504275
81639916605478276216119281073937632245544729251486233
Directory /workspace/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.31289315109390397764802427704127836586946262858438153281816019477965978874220
Short name T108
Test name
Test status
Simulation time 91600225 ps
CPU time 0.91 seconds
Started Nov 22 01:26:19 PM PST 23
Finished Nov 22 01:26:23 PM PST 23
Peak memory 195552 kb
Host smart-bf391a92-ac9f-42b3-905d-9fcc734a30f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31289315109390397764802427704127836586946262858438153281816019477965978874220 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig_mubi.31289315109390397764802427704127836586946262858438153281816019477965978874220
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.42167137019406806320909629533687628244711837831044314393537942452875898774574
Short name T1000
Test name
Test status
Simulation time 35743529 ps
CPU time 0.74 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 195084 kb
Host smart-aa0abc47-5215-4ceb-a8b4-1479eef136e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42167137019406806320909629533687628244711837831044314393537942452875898774574 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.42167137019406806320909629533687628244711837831044314393537942452875898774574
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_stress_all.17181384522044288501948729517620556706613471532275475996828315500098319463909
Short name T816
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.81 seconds
Started Nov 22 01:26:26 PM PST 23
Finished Nov 22 01:26:36 PM PST 23
Peak memory 201076 kb
Host smart-b6b0c104-2a54-47bc-a148-eb3ef0273d09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17181384522044288501948729517620556706613471532275475996828315500098319463909 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all.17181384522044288501948729517620556706613471532275475996828315500098319463909
Directory /workspace/14.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/14.pwrmgr_stress_all_with_rand_reset.57519119001173263303641131386086551213586185196551645259843304971756047144864
Short name T290
Test name
Test status
Simulation time 4441243999 ps
CPU time 10.61 seconds
Started Nov 22 01:27:18 PM PST 23
Finished Nov 22 01:27:45 PM PST 23
Peak memory 198644 kb
Host smart-cb76fcb7-68d1-4b62-8d55-9a2f5ef3a58d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575191190011732633036411
31386086551213586185196551645259843304971756047144864 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all_with_rand_reset.57519
119001173263303641131386086551213586185196551645259843304971756047144864
Directory /workspace/14.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup.86632093298075349273340955551691367170845127829097584167923294397296217369266
Short name T400
Test name
Test status
Simulation time 283777259 ps
CPU time 1.12 seconds
Started Nov 22 01:27:21 PM PST 23
Finished Nov 22 01:27:38 PM PST 23
Peak memory 199740 kb
Host smart-63fa78d2-01f1-4c22-9c6e-8a7bf1537a06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86632093298075349273340955551691367170845127829097584167923294397296217369266 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.86632093298075349273340955551691367170845127829097584167923294397296217369266
Directory /workspace/14.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup_reset.13911129218554752199905671799920281385223980355831825780018247587025240240008
Short name T32
Test name
Test status
Simulation time 325437640 ps
CPU time 1.36 seconds
Started Nov 22 01:26:26 PM PST 23
Finished Nov 22 01:26:30 PM PST 23
Peak memory 200772 kb
Host smart-d6e39e6d-0ade-4c0f-834b-21e7076d5184
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13911129218554752199905671799920281385223980355831825780018247587025240240008 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.13911129218554752199905671799920281385223980355831825780018247587025240240008
Directory /workspace/14.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.2227376086133783330823911256734051653595459742177153882401736526496763873738
Short name T702
Test name
Test status
Simulation time 51975542 ps
CPU time 0.78 seconds
Started Nov 22 01:26:26 PM PST 23
Finished Nov 22 01:26:30 PM PST 23
Peak memory 199032 kb
Host smart-ad2325a6-d781-4857-a6f2-cbe1fd81051c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227376086133783330823911256734051653595459742177153882401736526496763873738 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 15.pwrmgr_aborted_low_power.2227376086133783330823911256734051653595459742177153882401736526496763873738
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.17046440718857341303989410162616519844051035252454750212400190000746873767072
Short name T977
Test name
Test status
Simulation time 72403950 ps
CPU time 0.77 seconds
Started Nov 22 01:26:27 PM PST 23
Finished Nov 22 01:26:32 PM PST 23
Peak memory 198168 kb
Host smart-c2b1e734-3a85-47fe-b7d6-a262e55d9352
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17046440718857341303989410162616519844051035252454750212400190000746873767072 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_disable_rom_integrity_check.170464407188573413039894101626165198440510352524547502
12400190000746873767072
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.63586343871550623974654978345689371315664077108321480293815782766861384533217
Short name T643
Test name
Test status
Simulation time 30368572 ps
CPU time 0.62 seconds
Started Nov 22 01:26:24 PM PST 23
Finished Nov 22 01:26:26 PM PST 23
Peak memory 195284 kb
Host smart-ca701e9a-c6c6-407f-ad92-4335da1c5c4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63586343871550623974654978345689371315664077108321480293815782766861384533217 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst_malfunc.63586343871550623974654978345689371315664077108321480293815782766861384533217
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.28313147224325664666462768436391124087861258077037278123981242611270620120957
Short name T493
Test name
Test status
Simulation time 39672069 ps
CPU time 0.61 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 194032 kb
Host smart-3c8fa0a3-6501-45a7-a961-361b4414dd86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28313147224325664666462768436391124087861258077037278123981242611270620120957 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.28313147224325664666462768436391124087861258077037278123981242611270620120957
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.22884872860105663320716609780546375876124031689964549287901886060359241793195
Short name T532
Test name
Test status
Simulation time 33172121 ps
CPU time 0.57 seconds
Started Nov 22 01:26:34 PM PST 23
Finished Nov 22 01:26:37 PM PST 23
Peak memory 196664 kb
Host smart-aa09be45-565e-4dd6-bd70-bfe9cb90c180
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22884872860105663320716609780546375876124031689964549287901886060359241793195 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.22884872860105663320716609780546375876124031689964549287901886060359241793195
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_wakeup_race.109576894109391788441363190662442877222171088415258293590620118960163442878114
Short name T904
Test name
Test status
Simulation time 296241445 ps
CPU time 1.24 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 196804 kb
Host smart-79a12cf9-1f03-4be5-a005-e2c6bb26eb8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109576894109391788441363190662442877222171088415258293590620118960163442878114 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_wakeup_race.109576894109391788441363190662442877222171088415258293590620118960163442878114
Directory /workspace/15.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.50788833754342594264515431198431806707453937438357220377598860963396246672493
Short name T1065
Test name
Test status
Simulation time 119707143 ps
CPU time 1.08 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 196812 kb
Host smart-5751a3f1-a8a4-40a2-afda-f9b63f9699cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50788833754342594264515431198431806707453937438357220377598860963396246672493 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.50788833754342594264515431198431806707453937438357220377598860963396246672493
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.42689190214067882561505612594867540949861375297234294734675401522799704170223
Short name T1050
Test name
Test status
Simulation time 108189378 ps
CPU time 0.91 seconds
Started Nov 22 01:26:41 PM PST 23
Finished Nov 22 01:26:44 PM PST 23
Peak memory 209392 kb
Host smart-c11dba9c-ba84-4346-a272-dc15ec13ae35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42689190214067882561505612594867540949861375297234294734675401522799704170223 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.42689190214067882561505612594867540949861375297234294734675401522799704170223
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.97790873557339293480691395504730214009938216356005146475465245032220027930113
Short name T768
Test name
Test status
Simulation time 314830582 ps
CPU time 1.27 seconds
Started Nov 22 01:26:24 PM PST 23
Finished Nov 22 01:26:27 PM PST 23
Peak memory 199740 kb
Host smart-9d781458-8fbb-4a5f-a6fa-23916a9fa942
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97790873557339293480691395504730214009938216356005146475465245032220027930113 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_ctrl_config_regwen.977908735573392934806913955047302140099382163560051464754
65245032220027930113
Directory /workspace/15.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.64960885708242605022364532792922268387654089859541968127808989606023639976122
Short name T634
Test name
Test status
Simulation time 919450745 ps
CPU time 2.87 seconds
Started Nov 22 01:26:26 PM PST 23
Finished Nov 22 01:26:33 PM PST 23
Peak memory 201008 kb
Host smart-bbf4d27b-3e68-42c6-88c4-351e0378d613
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649608857082426050223645327929222683876540898595419681278089
89606023639976122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.64960885708242605022364532
792922268387654089859541968127808989606023639976122
Directory /workspace/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.45322368926442039691871819399954048022790183863771319676279326350183227815291
Short name T911
Test name
Test status
Simulation time 968503924 ps
CPU time 2.83 seconds
Started Nov 22 01:27:07 PM PST 23
Finished Nov 22 01:27:23 PM PST 23
Peak memory 200628 kb
Host smart-6729e5e8-0c30-477b-a555-dcaf3b78f8e3
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45322368926442039691871819399954048022790183863771319676279
326350183227815291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.453223689264420396918718
19399954048022790183863771319676279326350183227815291
Directory /workspace/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.5369266842517497506646592639960939515731462693702023405715818350798618869013
Short name T737
Test name
Test status
Simulation time 91600225 ps
CPU time 0.9 seconds
Started Nov 22 01:26:26 PM PST 23
Finished Nov 22 01:26:29 PM PST 23
Peak memory 195484 kb
Host smart-d88916b6-2705-441d-bfc4-173639a2a386
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5369266842517497506646592639960939515731462693702023405715818350798618869013 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_mubi.5369266842517497506646592639960939515731462693702023405715818350798618869013
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.56085532187636720068570450667195570519517002304699288539246173907603165093190
Short name T599
Test name
Test status
Simulation time 35743529 ps
CPU time 0.63 seconds
Started Nov 22 01:26:26 PM PST 23
Finished Nov 22 01:26:29 PM PST 23
Peak memory 197896 kb
Host smart-026cd118-460f-4773-8b8b-90933e1b1bb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56085532187636720068570450667195570519517002304699288539246173907603165093190 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.56085532187636720068570450667195570519517002304699288539246173907603165093190
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_stress_all.72229763100232043429601044326579800274714847840542533621495420108412273892033
Short name T838
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.66 seconds
Started Nov 22 01:26:41 PM PST 23
Finished Nov 22 01:26:49 PM PST 23
Peak memory 201268 kb
Host smart-f8548335-2cab-44ed-9a6e-1e71dc288322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72229763100232043429601044326579800274714847840542533621495420108412273892033 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.72229763100232043429601044326579800274714847840542533621495420108412273892033
Directory /workspace/15.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/15.pwrmgr_stress_all_with_rand_reset.60160544005073884003746257806168590992974027635038138509094068749573468592111
Short name T858
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.31 seconds
Started Nov 22 01:26:43 PM PST 23
Finished Nov 22 01:26:55 PM PST 23
Peak memory 201384 kb
Host smart-78a448b2-c333-4bb1-9cfe-61abdfd055e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601605440050738840037462
57806168590992974027635038138509094068749573468592111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all_with_rand_reset.60160
544005073884003746257806168590992974027635038138509094068749573468592111
Directory /workspace/15.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup.97271184724857221128155955683192316036257033061810596399715722271051460866103
Short name T1037
Test name
Test status
Simulation time 283777259 ps
CPU time 1.28 seconds
Started Nov 22 01:26:23 PM PST 23
Finished Nov 22 01:26:27 PM PST 23
Peak memory 199988 kb
Host smart-9310fc26-bccd-42ef-bcf1-51d4221e2db2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97271184724857221128155955683192316036257033061810596399715722271051460866103 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.97271184724857221128155955683192316036257033061810596399715722271051460866103
Directory /workspace/15.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup_reset.76601873634473168828175750545347884382942877716371588119090704138727654707354
Short name T576
Test name
Test status
Simulation time 325437640 ps
CPU time 1.38 seconds
Started Nov 22 01:26:28 PM PST 23
Finished Nov 22 01:26:32 PM PST 23
Peak memory 200764 kb
Host smart-cbca9b4c-c681-404d-b7d7-16eea85a373c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76601873634473168828175750545347884382942877716371588119090704138727654707354 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.76601873634473168828175750545347884382942877716371588119090704138727654707354
Directory /workspace/15.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.39846220435021973897401297030417464920867517834942606480732561784033297314650
Short name T734
Test name
Test status
Simulation time 51975542 ps
CPU time 0.79 seconds
Started Nov 22 01:26:52 PM PST 23
Finished Nov 22 01:27:00 PM PST 23
Peak memory 199060 kb
Host smart-2550db20-be29-43c8-9545-63687e2bf9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39846220435021973897401297030417464920867517834942606480732561784033297314650 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 16.pwrmgr_aborted_low_power.39846220435021973897401297030417464920867517834942606480732561784033297314650
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.106086781742370393783321434499488997069140597232058165837438301448332071900031
Short name T536
Test name
Test status
Simulation time 72403950 ps
CPU time 0.78 seconds
Started Nov 22 01:26:32 PM PST 23
Finished Nov 22 01:26:35 PM PST 23
Peak memory 198272 kb
Host smart-e2f3670e-1bab-4129-adfd-3ee29c9fa79e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106086781742370393783321434499488997069140597232058165837438301448332071900031 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_disable_rom_integrity_check.10608678174237039378332143449948899706914059723205816
5837438301448332071900031
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.21447370126977017506238820590434145489916513932684432347318485150343971367752
Short name T25
Test name
Test status
Simulation time 30368572 ps
CPU time 0.59 seconds
Started Nov 22 01:26:44 PM PST 23
Finished Nov 22 01:26:46 PM PST 23
Peak memory 195412 kb
Host smart-a1c7bb60-601e-41e7-85de-a2057102f4fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21447370126977017506238820590434145489916513932684432347318485150343971367752 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst_malfunc.21447370126977017506238820590434145489916513932684432347318485150343971367752
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.96133071023467935202152528337987831475842963748033765189933944305349565290130
Short name T986
Test name
Test status
Simulation time 39672069 ps
CPU time 0.6 seconds
Started Nov 22 01:26:40 PM PST 23
Finished Nov 22 01:26:42 PM PST 23
Peak memory 195496 kb
Host smart-e4c65e65-47f2-4336-8879-cc2e75a30cc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96133071023467935202152528337987831475842963748033765189933944305349565290130 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.96133071023467935202152528337987831475842963748033765189933944305349565290130
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.84366674407672364557448304224990950452913323389539844215207019475805419276360
Short name T966
Test name
Test status
Simulation time 33172121 ps
CPU time 0.63 seconds
Started Nov 22 01:26:57 PM PST 23
Finished Nov 22 01:27:11 PM PST 23
Peak memory 196832 kb
Host smart-09b46c8b-3df8-41c9-bbb9-a0b48ed98ac0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84366674407672364557448304224990950452913323389539844215207019475805419276360 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.84366674407672364557448304224990950452913323389539844215207019475805419276360
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.98766917772936721933826627145897260206614810193051610400548918042823427362846
Short name T822
Test name
Test status
Simulation time 49975558 ps
CPU time 0.67 seconds
Started Nov 22 01:26:40 PM PST 23
Finished Nov 22 01:26:42 PM PST 23
Peak memory 201408 kb
Host smart-8c28b108-57a9-4fe3-a685-1f96813bd544
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98766917772936721933826627145897260206614810193051610400548918042823427362846 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_invalid.98766917772936721933826627145897260206614810193051610400548918042823427362846
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_wakeup_race.43809444687408280913844510161579579624213890408237652329186829056309119985879
Short name T172
Test name
Test status
Simulation time 296241445 ps
CPU time 1.28 seconds
Started Nov 22 01:26:57 PM PST 23
Finished Nov 22 01:27:12 PM PST 23
Peak memory 200080 kb
Host smart-62b440f4-49da-461c-9337-ed8950645487
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43809444687408280913844510161579579624213890408237652329186829056309119985879 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_wakeup_race.43809444687408280913844510161579579624213890408237652329186829056309119985879
Directory /workspace/16.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.113045604679789038524612152485349610780305341851118167683401852788365864591754
Short name T353
Test name
Test status
Simulation time 119707143 ps
CPU time 1.03 seconds
Started Nov 22 01:26:29 PM PST 23
Finished Nov 22 01:26:33 PM PST 23
Peak memory 199296 kb
Host smart-0e4b1d48-848c-482f-b56b-fcbce8e6c46b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113045604679789038524612152485349610780305341851118167683401852788365864591754 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.113045604679789038524612152485349610780305341851118167683401852788365864591754
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.87028799193553419832470537187162203113856564475826372681834080949995825217058
Short name T500
Test name
Test status
Simulation time 108189378 ps
CPU time 0.8 seconds
Started Nov 22 01:27:07 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 208736 kb
Host smart-d258c0fc-14ed-420a-a729-584babd55e74
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87028799193553419832470537187162203113856564475826372681834080949995825217058 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.87028799193553419832470537187162203113856564475826372681834080949995825217058
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.5003229698569208776391006078889361101228716209910003323597019071826866270238
Short name T1012
Test name
Test status
Simulation time 314830582 ps
CPU time 1.33 seconds
Started Nov 22 01:26:43 PM PST 23
Finished Nov 22 01:26:46 PM PST 23
Peak memory 199876 kb
Host smart-ef6429ac-526a-4b9e-8f3e-58b66e5f48e6
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5003229698569208776391006078889361101228716209910003323597019071826866270238 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_ctrl_config_regwen.5003229698569208776391006078889361101228716209910003323597
019071826866270238
Directory /workspace/16.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.8341578630523256807417812861665641520022233221197622412668613413701635720500
Short name T406
Test name
Test status
Simulation time 919450745 ps
CPU time 2.88 seconds
Started Nov 22 01:26:36 PM PST 23
Finished Nov 22 01:26:41 PM PST 23
Peak memory 201328 kb
Host smart-c1ec90c2-1737-4c17-83d0-341e70c817f5
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834157863052325680741781286166564152002223322119762241266861
3413701635720500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.834157863052325680741781286
1665641520022233221197622412668613413701635720500
Directory /workspace/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.81911066643254503347287398774922932917524383916812981040397700328667522401714
Short name T309
Test name
Test status
Simulation time 968503924 ps
CPU time 2.98 seconds
Started Nov 22 01:26:57 PM PST 23
Finished Nov 22 01:27:14 PM PST 23
Peak memory 201188 kb
Host smart-fd83ddbd-d2f0-4514-8206-5df48e083d0f
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81911066643254503347287398774922932917524383916812981040397
700328667522401714 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.819110666432545033472873
98774922932917524383916812981040397700328667522401714
Directory /workspace/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.51373975067067857197003239290714372321350468006987144789291136916053758027838
Short name T902
Test name
Test status
Simulation time 91600225 ps
CPU time 0.89 seconds
Started Nov 22 01:26:30 PM PST 23
Finished Nov 22 01:26:34 PM PST 23
Peak memory 195532 kb
Host smart-26a0e969-197e-4eec-8c3b-59c3770614e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51373975067067857197003239290714372321350468006987144789291136916053758027838 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig_mubi.51373975067067857197003239290714372321350468006987144789291136916053758027838
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.81695531836843863691592764081331118537888368742842166419502239125589268494244
Short name T901
Test name
Test status
Simulation time 35743529 ps
CPU time 0.68 seconds
Started Nov 22 01:26:39 PM PST 23
Finished Nov 22 01:26:41 PM PST 23
Peak memory 197884 kb
Host smart-d5f46ab4-ff32-40fb-802a-f7676231b264
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81695531836843863691592764081331118537888368742842166419502239125589268494244 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.81695531836843863691592764081331118537888368742842166419502239125589268494244
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_stress_all.92045425671692969873521866951606075435294066195766921605121631528012967783634
Short name T669
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.67 seconds
Started Nov 22 01:26:39 PM PST 23
Finished Nov 22 01:26:46 PM PST 23
Peak memory 201096 kb
Host smart-aa502e78-1f0b-4f02-8ea1-abe7bd8d45b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92045425671692969873521866951606075435294066195766921605121631528012967783634 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.92045425671692969873521866951606075435294066195766921605121631528012967783634
Directory /workspace/16.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/16.pwrmgr_stress_all_with_rand_reset.4519376893108120473201573661149129686252732489778453040212704743138058216331
Short name T512
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.69 seconds
Started Nov 22 01:26:39 PM PST 23
Finished Nov 22 01:26:52 PM PST 23
Peak memory 201412 kb
Host smart-c108c38c-1950-4969-acfd-66c4b4ab01ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451937689310812047320157
3661149129686252732489778453040212704743138058216331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all_with_rand_reset.451937
6893108120473201573661149129686252732489778453040212704743138058216331
Directory /workspace/16.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup.78385945471594810861755888818098790954982460071365886331773873448923510312590
Short name T438
Test name
Test status
Simulation time 283777259 ps
CPU time 1.17 seconds
Started Nov 22 01:26:29 PM PST 23
Finished Nov 22 01:26:33 PM PST 23
Peak memory 200028 kb
Host smart-4e77ddfb-f1b7-4c1b-8903-9f8d4cad9889
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78385945471594810861755888818098790954982460071365886331773873448923510312590 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup.78385945471594810861755888818098790954982460071365886331773873448923510312590
Directory /workspace/16.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup_reset.43399574643203821233455694307461936320910314468982651304339766854583572400707
Short name T168
Test name
Test status
Simulation time 325437640 ps
CPU time 1.36 seconds
Started Nov 22 01:26:40 PM PST 23
Finished Nov 22 01:26:43 PM PST 23
Peak memory 200804 kb
Host smart-5f651963-733e-4b19-b802-e954a9342293
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43399574643203821233455694307461936320910314468982651304339766854583572400707 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.43399574643203821233455694307461936320910314468982651304339766854583572400707
Directory /workspace/16.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.67529886939962673242087736614282813329190436024478091011075489603717968408277
Short name T703
Test name
Test status
Simulation time 51975542 ps
CPU time 0.74 seconds
Started Nov 22 01:26:36 PM PST 23
Finished Nov 22 01:26:38 PM PST 23
Peak memory 198892 kb
Host smart-dc2fdee3-549c-489d-b54c-f6efd4793eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67529886939962673242087736614282813329190436024478091011075489603717968408277 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.pwrmgr_aborted_low_power.67529886939962673242087736614282813329190436024478091011075489603717968408277
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.41749980616012084898699854984403752945102281416936414191560665068046523491148
Short name T115
Test name
Test status
Simulation time 72403950 ps
CPU time 0.77 seconds
Started Nov 22 01:26:57 PM PST 23
Finished Nov 22 01:27:10 PM PST 23
Peak memory 198252 kb
Host smart-7ecd994f-c980-42c5-86e2-33f460da1441
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41749980616012084898699854984403752945102281416936414191560665068046523491148 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_disable_rom_integrity_check.417499806160120848986998549844037529451022814169364141
91560665068046523491148
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.87081384343977620639935741152657322044385713651033032896758372582988685821165
Short name T963
Test name
Test status
Simulation time 30368572 ps
CPU time 0.64 seconds
Started Nov 22 01:26:40 PM PST 23
Finished Nov 22 01:26:43 PM PST 23
Peak memory 195448 kb
Host smart-75f54039-9004-4273-b3d5-b4658d5189a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87081384343977620639935741152657322044385713651033032896758372582988685821165 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst_malfunc.87081384343977620639935741152657322044385713651033032896758372582988685821165
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.69093941281661219514543839982013214315197748090973109869509150817631224286552
Short name T415
Test name
Test status
Simulation time 39672069 ps
CPU time 0.6 seconds
Started Nov 22 01:26:38 PM PST 23
Finished Nov 22 01:26:40 PM PST 23
Peak memory 195408 kb
Host smart-158e5ca7-7312-49d4-b85f-278b055c2d3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69093941281661219514543839982013214315197748090973109869509150817631224286552 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.69093941281661219514543839982013214315197748090973109869509150817631224286552
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.50722256560270777934168456082412080868444482549914921412721035869933681812022
Short name T776
Test name
Test status
Simulation time 33172121 ps
CPU time 0.63 seconds
Started Nov 22 01:27:05 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 196752 kb
Host smart-82c088c9-cc86-42b2-a1ba-bbd7f433276e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50722256560270777934168456082412080868444482549914921412721035869933681812022 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.50722256560270777934168456082412080868444482549914921412721035869933681812022
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.81753310691071335391938562744006359895024844550122770492220266427279093536607
Short name T1008
Test name
Test status
Simulation time 49975558 ps
CPU time 0.69 seconds
Started Nov 22 01:26:48 PM PST 23
Finished Nov 22 01:26:52 PM PST 23
Peak memory 201288 kb
Host smart-90c81311-8905-4b49-8821-0665515f6e1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81753310691071335391938562744006359895024844550122770492220266427279093536607 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_invalid.81753310691071335391938562744006359895024844550122770492220266427279093536607
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_wakeup_race.240974209772840228807124500402797770442897572888969927768151565193859371684
Short name T834
Test name
Test status
Simulation time 296241445 ps
CPU time 1.19 seconds
Started Nov 22 01:26:39 PM PST 23
Finished Nov 22 01:26:42 PM PST 23
Peak memory 200100 kb
Host smart-3b370fcd-0382-4ed6-96fc-08185477c912
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240974209772840228807124500402797770442897572888969927768151565193859371684 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_wakeup_race.240974209772840228807124500402797770442897572888969927768151565193859371684
Directory /workspace/17.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.28112179984677117562038158311628402157186838626304500188552855963835492250397
Short name T347
Test name
Test status
Simulation time 119707143 ps
CPU time 1.04 seconds
Started Nov 22 01:26:56 PM PST 23
Finished Nov 22 01:27:09 PM PST 23
Peak memory 199320 kb
Host smart-211578bd-caf9-4fb9-992f-48846916e596
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28112179984677117562038158311628402157186838626304500188552855963835492250397 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.28112179984677117562038158311628402157186838626304500188552855963835492250397
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.101872130345897074546092688250876369712924992660839524757715404411784067715319
Short name T1014
Test name
Test status
Simulation time 108189378 ps
CPU time 0.82 seconds
Started Nov 22 01:26:33 PM PST 23
Finished Nov 22 01:26:35 PM PST 23
Peak memory 209424 kb
Host smart-8d3faa28-4035-4efd-aaf1-8e949d6bb59b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101872130345897074546092688250876369712924992660839524757715404411784067715319 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.101872130345897074546092688250876369712924992660839524757715404411784067715319
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.89059051525600326411870924293666895465611564800385439422177084500722719026816
Short name T464
Test name
Test status
Simulation time 314830582 ps
CPU time 1.27 seconds
Started Nov 22 01:26:50 PM PST 23
Finished Nov 22 01:26:56 PM PST 23
Peak memory 199660 kb
Host smart-fd649fa6-8513-4071-9f26-dfc168d51659
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89059051525600326411870924293666895465611564800385439422177084500722719026816 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_ctrl_config_regwen.890590515256003264118709242936668954656115648003854394221
77084500722719026816
Directory /workspace/17.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.44964293616749169289687298404466461602156167499463545122141878942043034444348
Short name T587
Test name
Test status
Simulation time 919450745 ps
CPU time 2.74 seconds
Started Nov 22 01:27:01 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 201284 kb
Host smart-f298105a-53df-45e0-a4ee-fe6b0b6510f3
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449642936167491692896872984044664616021561674994635451221418
78942043034444348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.44964293616749169289687298
404466461602156167499463545122141878942043034444348
Directory /workspace/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.63034423149066224702166302776845656737971096528546587481027289652384533556438
Short name T473
Test name
Test status
Simulation time 968503924 ps
CPU time 3.1 seconds
Started Nov 22 01:26:38 PM PST 23
Finished Nov 22 01:26:43 PM PST 23
Peak memory 201204 kb
Host smart-8395e45e-f0cc-4942-8e60-a500411909b6
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63034423149066224702166302776845656737971096528546587481027
289652384533556438 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.630344231490662247021663
02776845656737971096528546587481027289652384533556438
Directory /workspace/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.13835171799133903726058701799721229499049662634765048084071777590141247109977
Short name T489
Test name
Test status
Simulation time 91600225 ps
CPU time 0.9 seconds
Started Nov 22 01:26:41 PM PST 23
Finished Nov 22 01:26:44 PM PST 23
Peak memory 195560 kb
Host smart-d39b5da9-41df-428b-9a9f-4bde8850d4da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13835171799133903726058701799721229499049662634765048084071777590141247109977 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig_mubi.13835171799133903726058701799721229499049662634765048084071777590141247109977
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.62788749905313128894490747295391239400786260462162463031078609748109884929755
Short name T448
Test name
Test status
Simulation time 35743529 ps
CPU time 0.63 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:12 PM PST 23
Peak memory 197880 kb
Host smart-038e2e71-87d9-43c5-bbfc-aa8d7a827931
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62788749905313128894490747295391239400786260462162463031078609748109884929755 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.62788749905313128894490747295391239400786260462162463031078609748109884929755
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_stress_all.68221091750057525001750562442436660472245681757384178261848168785604229831805
Short name T640
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.81 seconds
Started Nov 22 01:26:56 PM PST 23
Finished Nov 22 01:27:14 PM PST 23
Peak memory 201264 kb
Host smart-b2c4e131-7cb0-4a32-9ee3-dffba0933d5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68221091750057525001750562442436660472245681757384178261848168785604229831805 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.68221091750057525001750562442436660472245681757384178261848168785604229831805
Directory /workspace/17.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/17.pwrmgr_stress_all_with_rand_reset.47102105631825646913502011680493778525747263135181101173351045882322414242557
Short name T479
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.69 seconds
Started Nov 22 01:26:46 PM PST 23
Finished Nov 22 01:27:00 PM PST 23
Peak memory 201452 kb
Host smart-5b032dae-e95c-4755-b221-5bd0c47aa957
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471021056318256469135020
11680493778525747263135181101173351045882322414242557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all_with_rand_reset.47102
105631825646913502011680493778525747263135181101173351045882322414242557
Directory /workspace/17.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup.77094247993829385559042349254877684382461131361991596629672959246583319931523
Short name T523
Test name
Test status
Simulation time 283777259 ps
CPU time 1.23 seconds
Started Nov 22 01:26:45 PM PST 23
Finished Nov 22 01:26:48 PM PST 23
Peak memory 199992 kb
Host smart-9c811f42-a69f-486c-9533-1c31a3048d8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77094247993829385559042349254877684382461131361991596629672959246583319931523 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.77094247993829385559042349254877684382461131361991596629672959246583319931523
Directory /workspace/17.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup_reset.69206928306910203498491730059380386989511331917141326054408561462845585760899
Short name T646
Test name
Test status
Simulation time 325437640 ps
CPU time 1.41 seconds
Started Nov 22 01:26:40 PM PST 23
Finished Nov 22 01:26:44 PM PST 23
Peak memory 200748 kb
Host smart-b6a99b5b-ff47-4fe5-ba0b-18ab0cbc12f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69206928306910203498491730059380386989511331917141326054408561462845585760899 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.69206928306910203498491730059380386989511331917141326054408561462845585760899
Directory /workspace/17.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.114788625006726006915744040286301475555808787424056917047854942031119894529764
Short name T1021
Test name
Test status
Simulation time 51975542 ps
CPU time 0.81 seconds
Started Nov 22 01:26:41 PM PST 23
Finished Nov 22 01:26:43 PM PST 23
Peak memory 198996 kb
Host smart-42a72a7c-eabb-46a6-9934-1182a15dfe0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114788625006726006915744040286301475555808787424056917047854942031119894529764 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.pwrmgr_aborted_low_power.114788625006726006915744040286301475555808787424056917047854942031119894529764
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.66436493468022564275327071098287469039249487891970166103421211339531742941788
Short name T676
Test name
Test status
Simulation time 72403950 ps
CPU time 0.72 seconds
Started Nov 22 01:26:50 PM PST 23
Finished Nov 22 01:26:54 PM PST 23
Peak memory 198072 kb
Host smart-78473ed1-2884-48cd-a242-8abc0b00367b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66436493468022564275327071098287469039249487891970166103421211339531742941788 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_disable_rom_integrity_check.664364934680225642753270710982874690392494878919701661
03421211339531742941788
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.24705135913800945026885402922350296197700521134354143009320053674356403097470
Short name T388
Test name
Test status
Simulation time 30368572 ps
CPU time 0.6 seconds
Started Nov 22 01:26:42 PM PST 23
Finished Nov 22 01:26:44 PM PST 23
Peak memory 195492 kb
Host smart-1ab56e06-4fab-422c-a3d7-1e067f6c4ec9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24705135913800945026885402922350296197700521134354143009320053674356403097470 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst_malfunc.24705135913800945026885402922350296197700521134354143009320053674356403097470
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.19284432568352103533842812652348947115320425555407325662222531351542431040154
Short name T1023
Test name
Test status
Simulation time 39672069 ps
CPU time 0.61 seconds
Started Nov 22 01:26:40 PM PST 23
Finished Nov 22 01:26:43 PM PST 23
Peak memory 195456 kb
Host smart-98d0b948-d5c9-4b6c-b5f3-ca2dc24317d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19284432568352103533842812652348947115320425555407325662222531351542431040154 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.19284432568352103533842812652348947115320425555407325662222531351542431040154
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.29256001934518971606687808184344934338451068641042191116866178067212996572349
Short name T978
Test name
Test status
Simulation time 33172121 ps
CPU time 0.6 seconds
Started Nov 22 01:26:38 PM PST 23
Finished Nov 22 01:26:41 PM PST 23
Peak memory 196736 kb
Host smart-8230a09e-1a8a-4a8d-965b-ff0edae5f1e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29256001934518971606687808184344934338451068641042191116866178067212996572349 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.29256001934518971606687808184344934338451068641042191116866178067212996572349
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.85994136626993710414031126874555355038983644999678856611338948794766199207707
Short name T433
Test name
Test status
Simulation time 49975558 ps
CPU time 0.65 seconds
Started Nov 22 01:26:49 PM PST 23
Finished Nov 22 01:26:54 PM PST 23
Peak memory 201216 kb
Host smart-d0627c70-259a-48ef-bfbe-51b330b037fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85994136626993710414031126874555355038983644999678856611338948794766199207707 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_invalid.85994136626993710414031126874555355038983644999678856611338948794766199207707
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_wakeup_race.58141111513102282988930530145200025413224344819773883100138863878155770563702
Short name T1063
Test name
Test status
Simulation time 296241445 ps
CPU time 1.2 seconds
Started Nov 22 01:26:33 PM PST 23
Finished Nov 22 01:26:36 PM PST 23
Peak memory 200004 kb
Host smart-10061010-6cf9-4d59-8bec-5e5c2fbc4155
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58141111513102282988930530145200025413224344819773883100138863878155770563702 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_wakeup_race.58141111513102282988930530145200025413224344819773883100138863878155770563702
Directory /workspace/18.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.43018542620608149713408238980752168103762042431427355011233727937625041396737
Short name T821
Test name
Test status
Simulation time 119707143 ps
CPU time 0.99 seconds
Started Nov 22 01:26:38 PM PST 23
Finished Nov 22 01:26:41 PM PST 23
Peak memory 199368 kb
Host smart-f633cc2a-b316-4dc0-8159-2838b55456d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43018542620608149713408238980752168103762042431427355011233727937625041396737 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.43018542620608149713408238980752168103762042431427355011233727937625041396737
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.72724142340068595330732756617241185098329169584779503134420953222932107687496
Short name T962
Test name
Test status
Simulation time 108189378 ps
CPU time 0.84 seconds
Started Nov 22 01:26:49 PM PST 23
Finished Nov 22 01:26:54 PM PST 23
Peak memory 209536 kb
Host smart-7bde7612-8555-42c2-9582-e2339b074115
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72724142340068595330732756617241185098329169584779503134420953222932107687496 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.72724142340068595330732756617241185098329169584779503134420953222932107687496
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.104035860414508860415380521074649650869114934548777929901599188257787768689181
Short name T311
Test name
Test status
Simulation time 314830582 ps
CPU time 1.32 seconds
Started Nov 22 01:26:42 PM PST 23
Finished Nov 22 01:26:45 PM PST 23
Peak memory 199912 kb
Host smart-a7b6603b-a2ff-4251-ba0f-3370cbfba508
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104035860414508860415380521074649650869114934548777929901599188257787768689181 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_ctrl_config_regwen.10403586041450886041538052107464965086911493454877792990
1599188257787768689181
Directory /workspace/18.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.57211049977203109236980378230918522812361388519969546869300519265142943769436
Short name T654
Test name
Test status
Simulation time 919450745 ps
CPU time 2.82 seconds
Started Nov 22 01:26:40 PM PST 23
Finished Nov 22 01:26:45 PM PST 23
Peak memory 201064 kb
Host smart-1c9d43fc-cf6d-4c20-a239-f1161dae690d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572110499772031092369803782309185228123613885199695468693005
19265142943769436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.57211049977203109236980378
230918522812361388519969546869300519265142943769436
Directory /workspace/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.9280933043110651045002036374819234750306830761080859261566978253208283372636
Short name T999
Test name
Test status
Simulation time 968503924 ps
CPU time 3 seconds
Started Nov 22 01:26:37 PM PST 23
Finished Nov 22 01:26:41 PM PST 23
Peak memory 201136 kb
Host smart-f12e4f65-bd5a-48e8-b2d9-9e0fbe25cb64
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92809330431106510450020363748192347503068307610808592615669
78253208283372636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.9280933043110651045002036
374819234750306830761080859261566978253208283372636
Directory /workspace/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.13099297344401451484271290814367111338650171347292509165148607528056413537611
Short name T398
Test name
Test status
Simulation time 91600225 ps
CPU time 0.91 seconds
Started Nov 22 01:26:40 PM PST 23
Finished Nov 22 01:26:43 PM PST 23
Peak memory 195436 kb
Host smart-3840568f-d3d2-4347-ade8-2f7ffed8e86d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13099297344401451484271290814367111338650171347292509165148607528056413537611 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig_mubi.13099297344401451484271290814367111338650171347292509165148607528056413537611
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.27268188923491799239478083659588623145918448673081323201905575998408619416966
Short name T848
Test name
Test status
Simulation time 35743529 ps
CPU time 0.64 seconds
Started Nov 22 01:26:39 PM PST 23
Finished Nov 22 01:26:42 PM PST 23
Peak memory 197896 kb
Host smart-f89b6be1-6c4b-413b-9877-5232d4368f07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27268188923491799239478083659588623145918448673081323201905575998408619416966 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.27268188923491799239478083659588623145918448673081323201905575998408619416966
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_stress_all.7846573293762168740888076481569116237973620609721586824706829054425477442158
Short name T736
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.87 seconds
Started Nov 22 01:26:52 PM PST 23
Finished Nov 22 01:27:04 PM PST 23
Peak memory 201264 kb
Host smart-4a635763-c57e-470c-befd-749dd809937c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7846573293762168740888076481569116237973620609721586824706829054425477442158 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all.7846573293762168740888076481569116237973620609721586824706829054425477442158
Directory /workspace/18.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/18.pwrmgr_stress_all_with_rand_reset.13137311739688170696543569733272117725159954468723471593414400370950621109436
Short name T695
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.68 seconds
Started Nov 22 01:26:43 PM PST 23
Finished Nov 22 01:26:56 PM PST 23
Peak memory 201432 kb
Host smart-dc705349-1d40-4300-9352-0e81051c6626
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131373117396881706965435
69733272117725159954468723471593414400370950621109436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all_with_rand_reset.13137
311739688170696543569733272117725159954468723471593414400370950621109436
Directory /workspace/18.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup.17068368175123391683204217732995850362195659202748464636829683089397719352009
Short name T883
Test name
Test status
Simulation time 283777259 ps
CPU time 1.23 seconds
Started Nov 22 01:26:39 PM PST 23
Finished Nov 22 01:26:43 PM PST 23
Peak memory 200104 kb
Host smart-a642f9d5-659e-4375-8bd8-62678437c731
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17068368175123391683204217732995850362195659202748464636829683089397719352009 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.17068368175123391683204217732995850362195659202748464636829683089397719352009
Directory /workspace/18.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup_reset.34138807787418585915507584336866122549854420608126908986412975924701316510687
Short name T469
Test name
Test status
Simulation time 325437640 ps
CPU time 1.42 seconds
Started Nov 22 01:27:00 PM PST 23
Finished Nov 22 01:27:17 PM PST 23
Peak memory 200756 kb
Host smart-764800d1-3243-4368-beda-095212f4cabf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34138807787418585915507584336866122549854420608126908986412975924701316510687 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.34138807787418585915507584336866122549854420608126908986412975924701316510687
Directory /workspace/18.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.64675263011548031177668758467519634898553039132509550410720275394181919730196
Short name T545
Test name
Test status
Simulation time 51975542 ps
CPU time 0.81 seconds
Started Nov 22 01:26:51 PM PST 23
Finished Nov 22 01:26:59 PM PST 23
Peak memory 199160 kb
Host smart-21602824-f0f1-4198-b846-5d9420ca120d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64675263011548031177668758467519634898553039132509550410720275394181919730196 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.pwrmgr_aborted_low_power.64675263011548031177668758467519634898553039132509550410720275394181919730196
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.79110915085232029136205626551451837618355013303900914969403279981550061385587
Short name T372
Test name
Test status
Simulation time 72403950 ps
CPU time 0.75 seconds
Started Nov 22 01:26:46 PM PST 23
Finished Nov 22 01:26:49 PM PST 23
Peak memory 198168 kb
Host smart-8c20bd2f-3313-4825-9dc5-ef86f989864e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79110915085232029136205626551451837618355013303900914969403279981550061385587 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_disable_rom_integrity_check.791109150852320291362056265514518376183550133039009149
69403279981550061385587
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.90871533450292789463704281639366189062944427090103537483256017849922511783516
Short name T28
Test name
Test status
Simulation time 30368572 ps
CPU time 0.61 seconds
Started Nov 22 01:26:54 PM PST 23
Finished Nov 22 01:27:06 PM PST 23
Peak memory 195380 kb
Host smart-75bf0bf1-883a-4ca9-b463-f6817f3646e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90871533450292789463704281639366189062944427090103537483256017849922511783516 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst_malfunc.90871533450292789463704281639366189062944427090103537483256017849922511783516
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.67677883288339932576552517978066098551903335094838359284468537037152645587819
Short name T328
Test name
Test status
Simulation time 39672069 ps
CPU time 0.62 seconds
Started Nov 22 01:26:44 PM PST 23
Finished Nov 22 01:26:45 PM PST 23
Peak memory 195308 kb
Host smart-52884a65-0c0a-464e-80b8-a3bd0a744948
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67677883288339932576552517978066098551903335094838359284468537037152645587819 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.67677883288339932576552517978066098551903335094838359284468537037152645587819
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.49787766509579527806027840977191479099890682964042264083397844334770006912595
Short name T335
Test name
Test status
Simulation time 33172121 ps
CPU time 0.61 seconds
Started Nov 22 01:26:52 PM PST 23
Finished Nov 22 01:27:00 PM PST 23
Peak memory 196828 kb
Host smart-fa10221e-babf-43f5-9a2a-68847378b100
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49787766509579527806027840977191479099890682964042264083397844334770006912595 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.49787766509579527806027840977191479099890682964042264083397844334770006912595
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.23548350543035606118002079650675271957796324650227550962058982979401130893665
Short name T910
Test name
Test status
Simulation time 49975558 ps
CPU time 0.68 seconds
Started Nov 22 01:26:50 PM PST 23
Finished Nov 22 01:26:57 PM PST 23
Peak memory 201176 kb
Host smart-c63189ea-49a7-4e4e-a43c-77ea2c932b93
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23548350543035606118002079650675271957796324650227550962058982979401130893665 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_invalid.23548350543035606118002079650675271957796324650227550962058982979401130893665
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_wakeup_race.33436189616007197245075952815812758203070769357871948453509038359726456313500
Short name T332
Test name
Test status
Simulation time 296241445 ps
CPU time 1.23 seconds
Started Nov 22 01:26:41 PM PST 23
Finished Nov 22 01:26:44 PM PST 23
Peak memory 200108 kb
Host smart-4621001d-178f-41ad-80dd-6eceae0c1458
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33436189616007197245075952815812758203070769357871948453509038359726456313500 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_wakeup_race.33436189616007197245075952815812758203070769357871948453509038359726456313500
Directory /workspace/19.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.96188789204836534588462177208708167045039327779558230908042467028310675159401
Short name T1020
Test name
Test status
Simulation time 119707143 ps
CPU time 1.08 seconds
Started Nov 22 01:26:51 PM PST 23
Finished Nov 22 01:26:59 PM PST 23
Peak memory 199336 kb
Host smart-a4f1cb9d-144a-4d7e-a6cf-f3552f4d1fdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96188789204836534588462177208708167045039327779558230908042467028310675159401 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.96188789204836534588462177208708167045039327779558230908042467028310675159401
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.113265733581939256292577576996981741352362570854061069902554340450722055474342
Short name T674
Test name
Test status
Simulation time 108189378 ps
CPU time 0.84 seconds
Started Nov 22 01:26:49 PM PST 23
Finished Nov 22 01:26:53 PM PST 23
Peak memory 209464 kb
Host smart-2d6a29bc-5872-4eac-879d-388a2d08204c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113265733581939256292577576996981741352362570854061069902554340450722055474342 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.113265733581939256292577576996981741352362570854061069902554340450722055474342
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.58986064030109360959108101380269082789820844977565291382204539761977970717318
Short name T651
Test name
Test status
Simulation time 314830582 ps
CPU time 1.32 seconds
Started Nov 22 01:26:44 PM PST 23
Finished Nov 22 01:26:47 PM PST 23
Peak memory 199736 kb
Host smart-a702ffa1-8a9f-45d6-8744-8d574aa4355e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58986064030109360959108101380269082789820844977565291382204539761977970717318 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_ctrl_config_regwen.589860640301093609591081013802690827898208449775652913822
04539761977970717318
Directory /workspace/19.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.48064497067768430672822882074148857132938395231212666978467453005823635911185
Short name T618
Test name
Test status
Simulation time 919450745 ps
CPU time 2.83 seconds
Started Nov 22 01:26:51 PM PST 23
Finished Nov 22 01:27:00 PM PST 23
Peak memory 201252 kb
Host smart-c9bc7f60-6dfe-4eeb-87bf-0d65a1a507e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480644970677684306728228820741488571329383952312126669784674
53005823635911185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.48064497067768430672822882
074148857132938395231212666978467453005823635911185
Directory /workspace/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3372790507009222831884771081230310225772957153236425246144836254499741593657
Short name T934
Test name
Test status
Simulation time 968503924 ps
CPU time 2.98 seconds
Started Nov 22 01:26:50 PM PST 23
Finished Nov 22 01:26:58 PM PST 23
Peak memory 201220 kb
Host smart-e5c7132f-fcf0-41e7-8623-d4a497942b73
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33727905070092228318847710812303102257729571532364252461448
36254499741593657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3372790507009222831884771
081230310225772957153236425246144836254499741593657
Directory /workspace/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.69653251739278936562882985739367910105576660939630082214414051290208198671467
Short name T903
Test name
Test status
Simulation time 91600225 ps
CPU time 0.87 seconds
Started Nov 22 01:26:50 PM PST 23
Finished Nov 22 01:26:57 PM PST 23
Peak memory 195316 kb
Host smart-74264a45-69e1-4d68-89fb-f5c12098adf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69653251739278936562882985739367910105576660939630082214414051290208198671467 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig_mubi.69653251739278936562882985739367910105576660939630082214414051290208198671467
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.30471221425042852854713488592502789716689890480980964712139570546842153511703
Short name T812
Test name
Test status
Simulation time 35743529 ps
CPU time 0.64 seconds
Started Nov 22 01:26:44 PM PST 23
Finished Nov 22 01:26:45 PM PST 23
Peak memory 197860 kb
Host smart-19a790a7-12f0-4678-a79a-781c712c7ec0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30471221425042852854713488592502789716689890480980964712139570546842153511703 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.30471221425042852854713488592502789716689890480980964712139570546842153511703
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_stress_all.102230515474167380608960185182255990585277930660023630140741315537482393317557
Short name T445
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.53 seconds
Started Nov 22 01:26:45 PM PST 23
Finished Nov 22 01:26:52 PM PST 23
Peak memory 201264 kb
Host smart-46773bee-a0b9-4f3d-ac17-12a88f0b7867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102230515474167380608960185182255990585277930660023630140741315537482393317557 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all.102230515474167380608960185182255990585277930660023630140741315537482393317557
Directory /workspace/19.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/19.pwrmgr_stress_all_with_rand_reset.103269518356237052575193056382920661242030540129830486687014747866886797323081
Short name T457
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.06 seconds
Started Nov 22 01:26:49 PM PST 23
Finished Nov 22 01:27:04 PM PST 23
Peak memory 201452 kb
Host smart-0304ca21-5b49-4d9f-8986-9fe9f6ae9e97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103269518356237052575193
056382920661242030540129830486687014747866886797323081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all_with_rand_reset.1032
69518356237052575193056382920661242030540129830486687014747866886797323081
Directory /workspace/19.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup.34814396530752125953951792469184034613793117358773971148391730672281080740772
Short name T570
Test name
Test status
Simulation time 283777259 ps
CPU time 1.15 seconds
Started Nov 22 01:26:50 PM PST 23
Finished Nov 22 01:26:57 PM PST 23
Peak memory 199832 kb
Host smart-0fd091b0-1858-467a-82d2-c8fc6a224db0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34814396530752125953951792469184034613793117358773971148391730672281080740772 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.34814396530752125953951792469184034613793117358773971148391730672281080740772
Directory /workspace/19.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup_reset.30492402082034419101642337464725221749058999313461676639656471757026123118118
Short name T611
Test name
Test status
Simulation time 325437640 ps
CPU time 1.34 seconds
Started Nov 22 01:26:50 PM PST 23
Finished Nov 22 01:26:57 PM PST 23
Peak memory 200596 kb
Host smart-3cc9958c-e19b-4e89-bd8f-61bdc68b5f65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30492402082034419101642337464725221749058999313461676639656471757026123118118 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.30492402082034419101642337464725221749058999313461676639656471757026123118118
Directory /workspace/19.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.68986499421061436129408354110399840015825517171482526214474014302035640061480
Short name T459
Test name
Test status
Simulation time 51975542 ps
CPU time 0.77 seconds
Started Nov 22 01:26:13 PM PST 23
Finished Nov 22 01:26:20 PM PST 23
Peak memory 199128 kb
Host smart-9a190166-d761-45cd-a24d-c79725a5c8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68986499421061436129408354110399840015825517171482526214474014302035640061480 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.pwrmgr_aborted_low_power.68986499421061436129408354110399840015825517171482526214474014302035640061480
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.16958519943402153674888687086847792703076228812118799153800758107988310752943
Short name T110
Test name
Test status
Simulation time 72403950 ps
CPU time 0.73 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 197672 kb
Host smart-93de9f14-b76a-495a-b487-24aa33de05b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16958519943402153674888687086847792703076228812118799153800758107988310752943 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disable_rom_integrity_check.1695851994340215367488868708684779270307622881211879915
3800758107988310752943
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.63640115064616135143199489438264071879510773353566205349474179251183709494091
Short name T726
Test name
Test status
Simulation time 30368572 ps
CPU time 0.61 seconds
Started Nov 22 01:26:08 PM PST 23
Finished Nov 22 01:26:14 PM PST 23
Peak memory 195436 kb
Host smart-67fbbe85-35ae-4228-88e0-01340590c22c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63640115064616135143199489438264071879510773353566205349474179251183709494091 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_malfunc.63640115064616135143199489438264071879510773353566205349474179251183709494091
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.71342609467383798891494063899928390804209906487920612530313075035713658425509
Short name T132
Test name
Test status
Simulation time 39672069 ps
CPU time 0.79 seconds
Started Nov 22 01:27:18 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 192484 kb
Host smart-8ee6641c-3954-4ed5-802d-a572ba270949
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71342609467383798891494063899928390804209906487920612530313075035713658425509 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.71342609467383798891494063899928390804209906487920612530313075035713658425509
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.10393902108527508286073545514722076078527161498505477362426822974967174800264
Short name T861
Test name
Test status
Simulation time 33172121 ps
CPU time 0.59 seconds
Started Nov 22 01:26:09 PM PST 23
Finished Nov 22 01:26:16 PM PST 23
Peak memory 196784 kb
Host smart-dd024c39-b5ef-44f4-abc5-594df65d0a11
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10393902108527508286073545514722076078527161498505477362426822974967174800264 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.10393902108527508286073545514722076078527161498505477362426822974967174800264
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.81094351078891146719489116933008501150940785204358038928719121844881035599469
Short name T744
Test name
Test status
Simulation time 49975558 ps
CPU time 0.74 seconds
Started Nov 22 01:26:06 PM PST 23
Finished Nov 22 01:26:13 PM PST 23
Peak memory 201344 kb
Host smart-82787213-4f1d-4ccb-8258-afa73280acab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81094351078891146719489116933008501150940785204358038928719121844881035599469 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invalid.81094351078891146719489116933008501150940785204358038928719121844881035599469
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_wakeup_race.98623868012275867004122245131174690342056892577862406162295203999330516813516
Short name T916
Test name
Test status
Simulation time 296241445 ps
CPU time 1.21 seconds
Started Nov 22 01:26:05 PM PST 23
Finished Nov 22 01:26:12 PM PST 23
Peak memory 200060 kb
Host smart-e4992537-594f-40f6-8c4e-983b31c761b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98623868012275867004122245131174690342056892577862406162295203999330516813516 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wakeup_race.98623868012275867004122245131174690342056892577862406162295203999330516813516
Directory /workspace/2.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.96970184015132955128857300497538318798437106006456856539860559724561793466850
Short name T641
Test name
Test status
Simulation time 119707143 ps
CPU time 1.01 seconds
Started Nov 22 01:26:12 PM PST 23
Finished Nov 22 01:26:19 PM PST 23
Peak memory 199344 kb
Host smart-91315d09-79fc-44e3-a7f7-5e7655220b3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96970184015132955128857300497538318798437106006456856539860559724561793466850 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.96970184015132955128857300497538318798437106006456856539860559724561793466850
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.84245661286779717782621564724146950490708108978422961181726666710956480841655
Short name T772
Test name
Test status
Simulation time 108189378 ps
CPU time 0.8 seconds
Started Nov 22 01:27:07 PM PST 23
Finished Nov 22 01:27:22 PM PST 23
Peak memory 209080 kb
Host smart-ba099901-6590-4075-82a9-1f280a166243
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84245661286779717782621564724146950490708108978422961181726666710956480841655 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.84245661286779717782621564724146950490708108978422961181726666710956480841655
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.83530956607526205568125912174568803542023125882031454689641885892393839392379
Short name T17
Test name
Test status
Simulation time 344080348 ps
CPU time 1.2 seconds
Started Nov 22 01:26:25 PM PST 23
Finished Nov 22 01:26:27 PM PST 23
Peak memory 214376 kb
Host smart-3c801abe-9aa9-4081-a123-4a2eace337b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83530956607526205568125912174568803542023125882031454689641885892393839392379 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.83530956607526205568125912174568803542023125882031454689641885892393839392379
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.109972505489831331336680746838357103348407357466689250273456799225832121115127
Short name T134
Test name
Test status
Simulation time 314830582 ps
CPU time 1.34 seconds
Started Nov 22 01:26:14 PM PST 23
Finished Nov 22 01:26:21 PM PST 23
Peak memory 199912 kb
Host smart-c5494e7d-456d-4138-84a9-da0aeb11711a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109972505489831331336680746838357103348407357466689250273456799225832121115127 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_ctrl_config_regwen.109972505489831331336680746838357103348407357466689250273
456799225832121115127
Directory /workspace/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.34079592738324869167150038482785038925892543362621183438866272546334263439082
Short name T580
Test name
Test status
Simulation time 919450745 ps
CPU time 2.86 seconds
Started Nov 22 01:26:13 PM PST 23
Finished Nov 22 01:26:22 PM PST 23
Peak memory 201232 kb
Host smart-bdd898ad-b9af-4c27-8e93-6dbff0b0c8d5
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340795927383248691671500384827850389258925433626211834388662
72546334263439082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.340795927383248691671500384
82785038925892543362621183438866272546334263439082
Directory /workspace/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.84401360032566409234956475223955375009349825427985193742973162589936799315191
Short name T126
Test name
Test status
Simulation time 968503924 ps
CPU time 3.05 seconds
Started Nov 22 01:26:13 PM PST 23
Finished Nov 22 01:26:22 PM PST 23
Peak memory 201184 kb
Host smart-4f87a0ce-e69f-467d-999d-a6f667fdd30e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84401360032566409234956475223955375009349825427985193742973
162589936799315191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.8440136003256640923495647
5223955375009349825427985193742973162589936799315191
Directory /workspace/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.48166699363029657746722161646813761754502801166204000513921660975476670836259
Short name T878
Test name
Test status
Simulation time 91600225 ps
CPU time 0.91 seconds
Started Nov 22 01:26:15 PM PST 23
Finished Nov 22 01:26:21 PM PST 23
Peak memory 195520 kb
Host smart-eee560e1-2f45-4a98-af51-52b93543b4e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48166699363029657746722161646813761754502801166204000513921660975476670836259 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_mubi.48166699363029657746722161646813761754502801166204000513921660975476670836259
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.96542315508113477062755544022227533493209878747487388303811450811521208714006
Short name T534
Test name
Test status
Simulation time 35743529 ps
CPU time 0.69 seconds
Started Nov 22 01:26:03 PM PST 23
Finished Nov 22 01:26:08 PM PST 23
Peak memory 197940 kb
Host smart-399929a8-ae67-4e08-bc47-01ac02633a2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96542315508113477062755544022227533493209878747487388303811450811521208714006 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.96542315508113477062755544022227533493209878747487388303811450811521208714006
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_stress_all.111632043977256913781795712512514938068988853163044470548425335208180848714311
Short name T341
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.54 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:26 PM PST 23
Peak memory 198908 kb
Host smart-0ab746c8-7c8e-4dc1-8aca-71185451f894
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111632043977256913781795712512514938068988853163044470548425335208180848714311 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.111632043977256913781795712512514938068988853163044470548425335208180848714311
Directory /workspace/2.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/2.pwrmgr_stress_all_with_rand_reset.104235138818704561060792478965066316291211594094392096270980259978446101027904
Short name T359
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.06 seconds
Started Nov 22 01:27:08 PM PST 23
Finished Nov 22 01:27:36 PM PST 23
Peak memory 201084 kb
Host smart-5b8e1c44-2f74-4ed5-9dde-d984edd0f564
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104235138818704561060792
478965066316291211594094392096270980259978446101027904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all_with_rand_reset.10423
5138818704561060792478965066316291211594094392096270980259978446101027904
Directory /workspace/2.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup.93127692379571832767720286597012034146744966040475374087396060105044133689619
Short name T754
Test name
Test status
Simulation time 283777259 ps
CPU time 1.22 seconds
Started Nov 22 01:26:08 PM PST 23
Finished Nov 22 01:26:14 PM PST 23
Peak memory 199532 kb
Host smart-3c0ffb10-03b6-42f2-a513-f3a036ad3aeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93127692379571832767720286597012034146744966040475374087396060105044133689619 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.93127692379571832767720286597012034146744966040475374087396060105044133689619
Directory /workspace/2.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup_reset.88019264780356914591566806062768450060718741770513523821899866071796272669814
Short name T364
Test name
Test status
Simulation time 325437640 ps
CPU time 1.42 seconds
Started Nov 22 01:26:04 PM PST 23
Finished Nov 22 01:26:11 PM PST 23
Peak memory 200732 kb
Host smart-1b91f36c-2212-4088-b632-c8adb5ba63e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88019264780356914591566806062768450060718741770513523821899866071796272669814 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.88019264780356914591566806062768450060718741770513523821899866071796272669814
Directory /workspace/2.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.86399272023554903940682432096073732873382767729512983250030150979327005380034
Short name T322
Test name
Test status
Simulation time 51975542 ps
CPU time 0.79 seconds
Started Nov 22 01:26:46 PM PST 23
Finished Nov 22 01:26:49 PM PST 23
Peak memory 199104 kb
Host smart-72fa57db-1aa1-4cbc-8b0b-0604214dd9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86399272023554903940682432096073732873382767729512983250030150979327005380034 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 20.pwrmgr_aborted_low_power.86399272023554903940682432096073732873382767729512983250030150979327005380034
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.65764785306165505204089669227518943077498945612872929128298861185597352387824
Short name T644
Test name
Test status
Simulation time 72403950 ps
CPU time 0.77 seconds
Started Nov 22 01:26:46 PM PST 23
Finished Nov 22 01:26:48 PM PST 23
Peak memory 198240 kb
Host smart-dbe3504e-5662-4be7-88b9-18456e28bc7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65764785306165505204089669227518943077498945612872929128298861185597352387824 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_disable_rom_integrity_check.657647853061655052040896692275189430774989456128729291
28298861185597352387824
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.65757912428236667347860484310281759264174565481910341706194788051586393859126
Short name T953
Test name
Test status
Simulation time 30368572 ps
CPU time 0.61 seconds
Started Nov 22 01:26:51 PM PST 23
Finished Nov 22 01:26:58 PM PST 23
Peak memory 195464 kb
Host smart-b42264fa-b83a-4327-a776-cc1ca7543592
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65757912428236667347860484310281759264174565481910341706194788051586393859126 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst_malfunc.65757912428236667347860484310281759264174565481910341706194788051586393859126
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.90194635782737721704807926969887163924055619229271191707533353741523511967947
Short name T537
Test name
Test status
Simulation time 39672069 ps
CPU time 0.64 seconds
Started Nov 22 01:26:50 PM PST 23
Finished Nov 22 01:26:56 PM PST 23
Peak memory 195488 kb
Host smart-87692083-8366-483a-8a30-02e7eed9ad75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90194635782737721704807926969887163924055619229271191707533353741523511967947 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.90194635782737721704807926969887163924055619229271191707533353741523511967947
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.93538351350371630777897051496800239062543931134016410698692891905036093985031
Short name T456
Test name
Test status
Simulation time 33172121 ps
CPU time 0.57 seconds
Started Nov 22 01:26:50 PM PST 23
Finished Nov 22 01:26:55 PM PST 23
Peak memory 196584 kb
Host smart-9c10ae29-3a38-4a1b-9e28-a9413767ebef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93538351350371630777897051496800239062543931134016410698692891905036093985031 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.93538351350371630777897051496800239062543931134016410698692891905036093985031
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.106182711465589563399038096828817422010095543236721480440502578210735015569615
Short name T856
Test name
Test status
Simulation time 49975558 ps
CPU time 0.69 seconds
Started Nov 22 01:26:49 PM PST 23
Finished Nov 22 01:26:53 PM PST 23
Peak memory 201408 kb
Host smart-5a6c73bc-9f25-4d80-b2c2-dfde157ab232
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106182711465589563399038096828817422010095543236721480440502578210735015569615 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_invalid.106182711465589563399038096828817422010095543236721480440502578210735015569615
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_wakeup_race.89548843942204282217707327540105325016101908128069727465526694430931548396546
Short name T919
Test name
Test status
Simulation time 296241445 ps
CPU time 1.21 seconds
Started Nov 22 01:26:46 PM PST 23
Finished Nov 22 01:26:49 PM PST 23
Peak memory 200080 kb
Host smart-c5aa2cda-b01e-4559-901f-ed90a57667f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89548843942204282217707327540105325016101908128069727465526694430931548396546 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_wakeup_race.89548843942204282217707327540105325016101908128069727465526694430931548396546
Directory /workspace/20.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.39072311931006871968608447409314762306698252071906198033474795029361356700783
Short name T368
Test name
Test status
Simulation time 119707143 ps
CPU time 1.03 seconds
Started Nov 22 01:26:51 PM PST 23
Finished Nov 22 01:26:57 PM PST 23
Peak memory 199100 kb
Host smart-01772a67-2e95-4af4-83b7-e506979db445
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39072311931006871968608447409314762306698252071906198033474795029361356700783 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.39072311931006871968608447409314762306698252071906198033474795029361356700783
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.24379534859631815791769244344050929539832656018294526595266706233443002970689
Short name T343
Test name
Test status
Simulation time 108189378 ps
CPU time 0.88 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:13 PM PST 23
Peak memory 209500 kb
Host smart-c32c7474-c979-4df1-bae9-f0efa26f95a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24379534859631815791769244344050929539832656018294526595266706233443002970689 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.24379534859631815791769244344050929539832656018294526595266706233443002970689
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.33608430463676678768749453355317844618482197091909659845857065322830753389543
Short name T135
Test name
Test status
Simulation time 314830582 ps
CPU time 1.35 seconds
Started Nov 22 01:26:46 PM PST 23
Finished Nov 22 01:26:50 PM PST 23
Peak memory 199740 kb
Host smart-ac177b47-047d-4c4a-a2b0-94bc2729c115
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33608430463676678768749453355317844618482197091909659845857065322830753389543 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_ctrl_config_regwen.336084304636766787687494533553178446184821970919096598458
57065322830753389543
Directory /workspace/20.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.25002074024038154514018265913061830865063025455123018522342000309477762792843
Short name T430
Test name
Test status
Simulation time 919450745 ps
CPU time 2.87 seconds
Started Nov 22 01:26:56 PM PST 23
Finished Nov 22 01:27:11 PM PST 23
Peak memory 201216 kb
Host smart-4533a00f-a40b-4c02-9dc4-ffd8a84c739d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250020740240381545140182659130618308650630254551230185223420
00309477762792843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.25002074024038154514018265
913061830865063025455123018522342000309477762792843
Directory /workspace/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.66009459395503984350145607434863331635121816373093536490649270668068942465443
Short name T633
Test name
Test status
Simulation time 968503924 ps
CPU time 3.11 seconds
Started Nov 22 01:26:45 PM PST 23
Finished Nov 22 01:26:50 PM PST 23
Peak memory 201144 kb
Host smart-0fcb7988-a872-4d05-9c47-7e4b139d38a6
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66009459395503984350145607434863331635121816373093536490649
270668068942465443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.660094593955039843501456
07434863331635121816373093536490649270668068942465443
Directory /workspace/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.110835013036953314624995538060128802042455626165414875364655097383335194107507
Short name T721
Test name
Test status
Simulation time 91600225 ps
CPU time 0.89 seconds
Started Nov 22 01:27:10 PM PST 23
Finished Nov 22 01:27:28 PM PST 23
Peak memory 195524 kb
Host smart-df35d6a2-f2eb-4f04-a4dc-89495d57fc34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110835013036953314624995538060128802042455626165414875364655097383335194107507 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig_mubi.110835013036953314624995538060128802042455626165414875364655097383335194107507
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.108147566017029945511425179341277476261861594478642243979584075501217196782381
Short name T842
Test name
Test status
Simulation time 35743529 ps
CPU time 0.67 seconds
Started Nov 22 01:26:54 PM PST 23
Finished Nov 22 01:27:07 PM PST 23
Peak memory 197844 kb
Host smart-55168e2c-b12d-4b9c-8fd7-d1403618605e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108147566017029945511425179341277476261861594478642243979584075501217196782381 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.108147566017029945511425179341277476261861594478642243979584075501217196782381
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_stress_all.78026916077650379503719719065353798744603040015864084700910960237716211961642
Short name T1025
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.45 seconds
Started Nov 22 01:26:50 PM PST 23
Finished Nov 22 01:27:00 PM PST 23
Peak memory 201056 kb
Host smart-fba28d2a-8a1c-4f21-b785-9baf3169850d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78026916077650379503719719065353798744603040015864084700910960237716211961642 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.78026916077650379503719719065353798744603040015864084700910960237716211961642
Directory /workspace/20.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/20.pwrmgr_stress_all_with_rand_reset.12863383224481879623509960827875071325050301997350683303182911224286398491473
Short name T381
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.01 seconds
Started Nov 22 01:26:46 PM PST 23
Finished Nov 22 01:26:59 PM PST 23
Peak memory 201300 kb
Host smart-fe1ad6c9-5c76-4a8b-a053-10d32f86ef25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128633832244818796235099
60827875071325050301997350683303182911224286398491473 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all_with_rand_reset.12863
383224481879623509960827875071325050301997350683303182911224286398491473
Directory /workspace/20.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup.68285468579478949979373916031004646822698729796456493382405081739298828923924
Short name T938
Test name
Test status
Simulation time 283777259 ps
CPU time 1.13 seconds
Started Nov 22 01:26:46 PM PST 23
Finished Nov 22 01:26:49 PM PST 23
Peak memory 200096 kb
Host smart-7bd1529e-c695-4fd4-bc9c-df248dc63a68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68285468579478949979373916031004646822698729796456493382405081739298828923924 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.68285468579478949979373916031004646822698729796456493382405081739298828923924
Directory /workspace/20.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup_reset.1190621045598332292751233730172768696809073003943175725721140302543664668172
Short name T701
Test name
Test status
Simulation time 325437640 ps
CPU time 1.46 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:14 PM PST 23
Peak memory 200740 kb
Host smart-fb13cc9d-7a5d-4f1f-b86e-613772e20a70
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190621045598332292751233730172768696809073003943175725721140302543664668172 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.1190621045598332292751233730172768696809073003943175725721140302543664668172
Directory /workspace/20.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.33975052852503957239287453625900097246103605940523805059957774965945378490970
Short name T971
Test name
Test status
Simulation time 51975542 ps
CPU time 0.84 seconds
Started Nov 22 01:26:48 PM PST 23
Finished Nov 22 01:26:53 PM PST 23
Peak memory 199128 kb
Host smart-08cfc61b-3c56-4f8f-bc2e-ae2c5c61f348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33975052852503957239287453625900097246103605940523805059957774965945378490970 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 21.pwrmgr_aborted_low_power.33975052852503957239287453625900097246103605940523805059957774965945378490970
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.19556822095354093227678388993145059454051307656405721021100698775966206666469
Short name T924
Test name
Test status
Simulation time 72403950 ps
CPU time 0.78 seconds
Started Nov 22 01:26:47 PM PST 23
Finished Nov 22 01:26:50 PM PST 23
Peak memory 198252 kb
Host smart-136badd7-b5e4-4df9-8771-38b8ac909679
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19556822095354093227678388993145059454051307656405721021100698775966206666469 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_disable_rom_integrity_check.195568220953540932276783889931450594540513076564057210
21100698775966206666469
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.11329547683535600159453455769480021180871277131614958739431452055048245771578
Short name T11
Test name
Test status
Simulation time 30368572 ps
CPU time 0.58 seconds
Started Nov 22 01:26:54 PM PST 23
Finished Nov 22 01:27:06 PM PST 23
Peak memory 195472 kb
Host smart-c5fde547-5806-420e-91fc-ec03616c8a47
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11329547683535600159453455769480021180871277131614958739431452055048245771578 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst_malfunc.11329547683535600159453455769480021180871277131614958739431452055048245771578
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.30051215629236276177850694878784745743289967410003852291184944185855184457730
Short name T510
Test name
Test status
Simulation time 39672069 ps
CPU time 0.61 seconds
Started Nov 22 01:26:52 PM PST 23
Finished Nov 22 01:27:00 PM PST 23
Peak memory 195432 kb
Host smart-b72e9be3-dca0-4883-bd5d-5000ac61ec07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30051215629236276177850694878784745743289967410003852291184944185855184457730 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.30051215629236276177850694878784745743289967410003852291184944185855184457730
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.86767085590412072256065295521369075415765433428474393691581485216457188666840
Short name T942
Test name
Test status
Simulation time 33172121 ps
CPU time 0.6 seconds
Started Nov 22 01:26:44 PM PST 23
Finished Nov 22 01:26:47 PM PST 23
Peak memory 196820 kb
Host smart-b7adc1b4-658c-4204-9318-046ab8874586
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86767085590412072256065295521369075415765433428474393691581485216457188666840 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.86767085590412072256065295521369075415765433428474393691581485216457188666840
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.63501897025485951186947994175070512756161870167758657495601909812193783964197
Short name T36
Test name
Test status
Simulation time 49975558 ps
CPU time 0.73 seconds
Started Nov 22 01:26:46 PM PST 23
Finished Nov 22 01:26:48 PM PST 23
Peak memory 201256 kb
Host smart-ab5cb2fb-9d2a-47ad-84d4-da637abbabe2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63501897025485951186947994175070512756161870167758657495601909812193783964197 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_invalid.63501897025485951186947994175070512756161870167758657495601909812193783964197
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_wakeup_race.94280169059604021974358933157735038831835749932538174631622327994598929599781
Short name T833
Test name
Test status
Simulation time 296241445 ps
CPU time 1.21 seconds
Started Nov 22 01:27:00 PM PST 23
Finished Nov 22 01:27:17 PM PST 23
Peak memory 199980 kb
Host smart-64108398-3c6a-4f89-a84c-6bc8c869dfd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94280169059604021974358933157735038831835749932538174631622327994598929599781 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_wakeup_race.94280169059604021974358933157735038831835749932538174631622327994598929599781
Directory /workspace/21.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.68495219304854981016315004118043544096129048892901989635094767981292991570804
Short name T605
Test name
Test status
Simulation time 119707143 ps
CPU time 0.98 seconds
Started Nov 22 01:26:46 PM PST 23
Finished Nov 22 01:26:49 PM PST 23
Peak memory 199268 kb
Host smart-d970064e-7d6c-4cc5-88c9-1d8d53be93de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68495219304854981016315004118043544096129048892901989635094767981292991570804 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.68495219304854981016315004118043544096129048892901989635094767981292991570804
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.18999493811671373926992386261358706179798747072041763904479223099649849582579
Short name T380
Test name
Test status
Simulation time 108189378 ps
CPU time 0.81 seconds
Started Nov 22 01:26:59 PM PST 23
Finished Nov 22 01:27:15 PM PST 23
Peak memory 209432 kb
Host smart-6f137fab-fc8f-4b8f-b72b-30b5b9ca8a7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18999493811671373926992386261358706179798747072041763904479223099649849582579 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.18999493811671373926992386261358706179798747072041763904479223099649849582579
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.1172646950661956176000727058320333287335941534084380707494177837777891947333
Short name T845
Test name
Test status
Simulation time 314830582 ps
CPU time 1.33 seconds
Started Nov 22 01:26:47 PM PST 23
Finished Nov 22 01:26:50 PM PST 23
Peak memory 199864 kb
Host smart-7a0712fc-5555-48e7-ad8a-896e7229d9a3
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172646950661956176000727058320333287335941534084380707494177837777891947333 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_ctrl_config_regwen.1172646950661956176000727058320333287335941534084380707494
177837777891947333
Directory /workspace/21.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.7368654684287510045921123031819036835828840288568561485803621686007874880564
Short name T837
Test name
Test status
Simulation time 919450745 ps
CPU time 2.83 seconds
Started Nov 22 01:26:46 PM PST 23
Finished Nov 22 01:26:51 PM PST 23
Peak memory 201212 kb
Host smart-e3010772-62bc-4034-b635-50d18bec9545
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736865468428751004592112303181903683582884028856856148580362
1686007874880564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.736865468428751004592112303
1819036835828840288568561485803621686007874880564
Directory /workspace/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.92076890387699836862100122408150227685670679745814123947175953132176145601983
Short name T325
Test name
Test status
Simulation time 968503924 ps
CPU time 2.98 seconds
Started Nov 22 01:26:47 PM PST 23
Finished Nov 22 01:26:52 PM PST 23
Peak memory 201156 kb
Host smart-62f590f6-1861-49d7-9d03-e50fc9a1db34
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92076890387699836862100122408150227685670679745814123947175
953132176145601983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.920768903876998368621001
22408150227685670679745814123947175953132176145601983
Directory /workspace/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.76414899216499091704112762853919422855996200445480963189248359595900487816966
Short name T305
Test name
Test status
Simulation time 91600225 ps
CPU time 0.88 seconds
Started Nov 22 01:26:46 PM PST 23
Finished Nov 22 01:26:49 PM PST 23
Peak memory 195480 kb
Host smart-d6f30a58-ad7a-41b1-baa2-2f3e0a7a8b5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76414899216499091704112762853919422855996200445480963189248359595900487816966 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig_mubi.76414899216499091704112762853919422855996200445480963189248359595900487816966
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.113118343541050863444418868379448705238229069325686417650234335820257633085184
Short name T789
Test name
Test status
Simulation time 35743529 ps
CPU time 0.64 seconds
Started Nov 22 01:26:42 PM PST 23
Finished Nov 22 01:26:44 PM PST 23
Peak memory 197876 kb
Host smart-7962bd3e-c1ff-4acd-94e4-6ed6dd6341d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113118343541050863444418868379448705238229069325686417650234335820257633085184 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.113118343541050863444418868379448705238229069325686417650234335820257633085184
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_stress_all.109517225425497206323464531704104294304671173038207708610947348426787488365522
Short name T354
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.77 seconds
Started Nov 22 01:26:57 PM PST 23
Finished Nov 22 01:27:16 PM PST 23
Peak memory 201280 kb
Host smart-583e3343-ee3c-4ebf-8622-00d8773d2f24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109517225425497206323464531704104294304671173038207708610947348426787488365522 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.109517225425497206323464531704104294304671173038207708610947348426787488365522
Directory /workspace/21.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/21.pwrmgr_stress_all_with_rand_reset.1706305459739142325810294716643629221170278787841736067728941054554699362949
Short name T14
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.27 seconds
Started Nov 22 01:26:54 PM PST 23
Finished Nov 22 01:27:17 PM PST 23
Peak memory 201412 kb
Host smart-54ec480b-30b3-490f-93f1-c57275b7e654
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170630545973914232581029
4716643629221170278787841736067728941054554699362949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all_with_rand_reset.170630
5459739142325810294716643629221170278787841736067728941054554699362949
Directory /workspace/21.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup.48665780668206389029484511005027450127772366389175065088057065482717312948144
Short name T694
Test name
Test status
Simulation time 283777259 ps
CPU time 1.2 seconds
Started Nov 22 01:26:46 PM PST 23
Finished Nov 22 01:26:49 PM PST 23
Peak memory 200032 kb
Host smart-2a41ee73-912b-4aa6-88ef-f6e7e77f7a92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48665780668206389029484511005027450127772366389175065088057065482717312948144 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.48665780668206389029484511005027450127772366389175065088057065482717312948144
Directory /workspace/21.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup_reset.17397035800000390322827967539925961495868366442499038708274556770830288829966
Short name T308
Test name
Test status
Simulation time 325437640 ps
CPU time 1.48 seconds
Started Nov 22 01:26:47 PM PST 23
Finished Nov 22 01:26:52 PM PST 23
Peak memory 200796 kb
Host smart-bf8fbc67-5892-4489-930b-01f00e92eb67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17397035800000390322827967539925961495868366442499038708274556770830288829966 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.17397035800000390322827967539925961495868366442499038708274556770830288829966
Directory /workspace/21.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.91768655641243353270123459403208195519408768031727286277859194867325459327411
Short name T681
Test name
Test status
Simulation time 51975542 ps
CPU time 0.79 seconds
Started Nov 22 01:26:46 PM PST 23
Finished Nov 22 01:26:50 PM PST 23
Peak memory 199076 kb
Host smart-0c3019ef-bc21-4ddd-b6f9-3e4d820af1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91768655641243353270123459403208195519408768031727286277859194867325459327411 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.pwrmgr_aborted_low_power.91768655641243353270123459403208195519408768031727286277859194867325459327411
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.113080414380878279294826376668446685077739006749165829718144085120037741562480
Short name T638
Test name
Test status
Simulation time 72403950 ps
CPU time 0.75 seconds
Started Nov 22 01:26:49 PM PST 23
Finished Nov 22 01:26:53 PM PST 23
Peak memory 198256 kb
Host smart-93ca4c49-0da7-444c-a46f-bd58565a2517
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113080414380878279294826376668446685077739006749165829718144085120037741562480 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_disable_rom_integrity_check.11308041438087827929482637666844668507773900674916582
9718144085120037741562480
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.12326993913655440873173454045979933553493242801855809398775221721887521546699
Short name T1026
Test name
Test status
Simulation time 30368572 ps
CPU time 0.61 seconds
Started Nov 22 01:26:55 PM PST 23
Finished Nov 22 01:27:08 PM PST 23
Peak memory 195300 kb
Host smart-042938d7-1135-40fe-a3ff-184a20d24fab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12326993913655440873173454045979933553493242801855809398775221721887521546699 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst_malfunc.12326993913655440873173454045979933553493242801855809398775221721887521546699
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.41964691705470842800001196954336256562611828538318710990341505427986001928854
Short name T514
Test name
Test status
Simulation time 39672069 ps
CPU time 0.61 seconds
Started Nov 22 01:26:44 PM PST 23
Finished Nov 22 01:26:46 PM PST 23
Peak memory 195520 kb
Host smart-497bb964-8c31-4977-8f6b-6307b0ad7641
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41964691705470842800001196954336256562611828538318710990341505427986001928854 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.41964691705470842800001196954336256562611828538318710990341505427986001928854
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.2366853187968369513507641322738130323336332298654258929822264746360002383176
Short name T39
Test name
Test status
Simulation time 33172121 ps
CPU time 0.6 seconds
Started Nov 22 01:26:47 PM PST 23
Finished Nov 22 01:26:51 PM PST 23
Peak memory 196700 kb
Host smart-5fd46ff4-30b4-415c-ae79-8ca3a1914353
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366853187968369513507641322738130323336332298654258929822264746360002383176 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.2366853187968369513507641322738130323336332298654258929822264746360002383176
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.49508995263616230428004520408878951857838838334197292060616121581619282468202
Short name T976
Test name
Test status
Simulation time 49975558 ps
CPU time 0.67 seconds
Started Nov 22 01:26:50 PM PST 23
Finished Nov 22 01:26:57 PM PST 23
Peak memory 201140 kb
Host smart-8d1665f2-8881-4021-a2fe-b617f0fcf16d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49508995263616230428004520408878951857838838334197292060616121581619282468202 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_invalid.49508995263616230428004520408878951857838838334197292060616121581619282468202
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_wakeup_race.47087096738964233010952335535927759658765952844745955174776588691430283929662
Short name T299
Test name
Test status
Simulation time 296241445 ps
CPU time 1.2 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:13 PM PST 23
Peak memory 200068 kb
Host smart-16813189-fcaa-45fc-bd67-cf4d13950249
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47087096738964233010952335535927759658765952844745955174776588691430283929662 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_wakeup_race.47087096738964233010952335535927759658765952844745955174776588691430283929662
Directory /workspace/22.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.45710311859146421715474472952670780407676701104244828650232825202122052725912
Short name T715
Test name
Test status
Simulation time 119707143 ps
CPU time 1 seconds
Started Nov 22 01:26:43 PM PST 23
Finished Nov 22 01:26:45 PM PST 23
Peak memory 199144 kb
Host smart-31172a2d-1f0d-45f9-895a-37a9e5bc580e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45710311859146421715474472952670780407676701104244828650232825202122052725912 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.45710311859146421715474472952670780407676701104244828650232825202122052725912
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.102903104782108884771696773204390130826938194995965095109473094532822993525006
Short name T301
Test name
Test status
Simulation time 108189378 ps
CPU time 0.84 seconds
Started Nov 22 01:26:47 PM PST 23
Finished Nov 22 01:26:51 PM PST 23
Peak memory 209540 kb
Host smart-ed5c0157-0560-42e7-9b3d-521b5062de9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102903104782108884771696773204390130826938194995965095109473094532822993525006 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.102903104782108884771696773204390130826938194995965095109473094532822993525006
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.22620697790584315926404785895004183655720034891510746197718359795745422955358
Short name T948
Test name
Test status
Simulation time 314830582 ps
CPU time 1.37 seconds
Started Nov 22 01:26:52 PM PST 23
Finished Nov 22 01:27:01 PM PST 23
Peak memory 199844 kb
Host smart-c10f5e48-919d-406f-8b19-49d0fa4a446b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22620697790584315926404785895004183655720034891510746197718359795745422955358 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_ctrl_config_regwen.226206977905843159264047858950041836557200348915107461977
18359795745422955358
Directory /workspace/22.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.5439109905944629747030017447051826721784891257731087279469465937167664238148
Short name T362
Test name
Test status
Simulation time 919450745 ps
CPU time 2.97 seconds
Started Nov 22 01:26:44 PM PST 23
Finished Nov 22 01:26:49 PM PST 23
Peak memory 201280 kb
Host smart-7d1d2502-f6e1-47c8-b032-745e43f3ccf7
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543910990594462974703001744705182672178489125773108727946946
5937167664238148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.543910990594462974703001744
7051826721784891257731087279469465937167664238148
Directory /workspace/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.112541333574354717664389409222931088364037114891313374664938474077665549591155
Short name T137
Test name
Test status
Simulation time 968503924 ps
CPU time 2.99 seconds
Started Nov 22 01:26:44 PM PST 23
Finished Nov 22 01:26:48 PM PST 23
Peak memory 201052 kb
Host smart-8f360ba2-2513-4ddd-8b8a-99283389294e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11254133357435471766438940922293108836403711489131337466493
8474077665549591155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.11254133357435471766438
9409222931088364037114891313374664938474077665549591155
Directory /workspace/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.45685270476819336788558838539590353488250644914269213083070490088467938671860
Short name T969
Test name
Test status
Simulation time 91600225 ps
CPU time 0.88 seconds
Started Nov 22 01:26:50 PM PST 23
Finished Nov 22 01:26:54 PM PST 23
Peak memory 195528 kb
Host smart-e6acab62-51d8-45a2-aae1-11da361e69c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45685270476819336788558838539590353488250644914269213083070490088467938671860 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig_mubi.45685270476819336788558838539590353488250644914269213083070490088467938671860
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.50149545190586399995997465919198668042925475611731387622972107130093362677849
Short name T521
Test name
Test status
Simulation time 35743529 ps
CPU time 0.63 seconds
Started Nov 22 01:26:42 PM PST 23
Finished Nov 22 01:26:44 PM PST 23
Peak memory 197712 kb
Host smart-ed5b4ba7-73db-43eb-8be1-924ae39807a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50149545190586399995997465919198668042925475611731387622972107130093362677849 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.50149545190586399995997465919198668042925475611731387622972107130093362677849
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_stress_all.7766271465585822128003159045889026172022683725351536180700363574416422788360
Short name T607
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.43 seconds
Started Nov 22 01:26:51 PM PST 23
Finished Nov 22 01:27:02 PM PST 23
Peak memory 201052 kb
Host smart-de095163-bdaa-40b0-8861-6198a4435c06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7766271465585822128003159045889026172022683725351536180700363574416422788360 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.7766271465585822128003159045889026172022683725351536180700363574416422788360
Directory /workspace/22.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/22.pwrmgr_stress_all_with_rand_reset.9008133781910144085811175486072901757545032613193066833490564004158610414296
Short name T553
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.02 seconds
Started Nov 22 01:26:52 PM PST 23
Finished Nov 22 01:27:10 PM PST 23
Peak memory 201268 kb
Host smart-9d92b209-2d37-4343-b028-440e0f3b93d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900813378191014408581117
5486072901757545032613193066833490564004158610414296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all_with_rand_reset.900813
3781910144085811175486072901757545032613193066833490564004158610414296
Directory /workspace/22.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_wakeup.66974908403071585594629895090071662412402344836048014760901994264972410655037
Short name T161
Test name
Test status
Simulation time 283777259 ps
CPU time 1.21 seconds
Started Nov 22 01:26:52 PM PST 23
Finished Nov 22 01:27:00 PM PST 23
Peak memory 200032 kb
Host smart-be4523b7-9773-40d2-ba47-848a9946b9cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66974908403071585594629895090071662412402344836048014760901994264972410655037 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup.66974908403071585594629895090071662412402344836048014760901994264972410655037
Directory /workspace/22.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/22.pwrmgr_wakeup_reset.87839936455990863834862920306540049530247786985839944437188434893475117537794
Short name T149
Test name
Test status
Simulation time 325437640 ps
CPU time 1.42 seconds
Started Nov 22 01:26:47 PM PST 23
Finished Nov 22 01:26:51 PM PST 23
Peak memory 200780 kb
Host smart-7f5668d3-3ce5-4c91-bbb3-b23de51f3268
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87839936455990863834862920306540049530247786985839944437188434893475117537794 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup_reset.87839936455990863834862920306540049530247786985839944437188434893475117537794
Directory /workspace/22.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.101611959312727272963476043079268710633106314147816249071264953182342847745066
Short name T506
Test name
Test status
Simulation time 51975542 ps
CPU time 0.8 seconds
Started Nov 22 01:27:04 PM PST 23
Finished Nov 22 01:27:20 PM PST 23
Peak memory 199160 kb
Host smart-10e26c34-8422-40f4-acc6-5293bc6fb5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101611959312727272963476043079268710633106314147816249071264953182342847745066 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.pwrmgr_aborted_low_power.101611959312727272963476043079268710633106314147816249071264953182342847745066
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.9351764506666557977901966164879483065319471145202985898353414257863188747843
Short name T38
Test name
Test status
Simulation time 72403950 ps
CPU time 0.74 seconds
Started Nov 22 01:26:45 PM PST 23
Finished Nov 22 01:26:48 PM PST 23
Peak memory 198264 kb
Host smart-a1c77656-1ca0-4f9e-a86c-81361bbb37f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9351764506666557977901966164879483065319471145202985898353414257863188747843 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_disable_rom_integrity_check.9351764506666557977901966164879483065319471145202985898
353414257863188747843
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.41875540748995173256597250917040684092078646301054955717647949582272069268170
Short name T474
Test name
Test status
Simulation time 30368572 ps
CPU time 0.6 seconds
Started Nov 22 01:27:04 PM PST 23
Finished Nov 22 01:27:19 PM PST 23
Peak memory 195472 kb
Host smart-1a7af475-f684-42c6-aebc-c390b217b1fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41875540748995173256597250917040684092078646301054955717647949582272069268170 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst_malfunc.41875540748995173256597250917040684092078646301054955717647949582272069268170
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.40238397863973158094216908733421126090723239998401595807876279441755490179469
Short name T981
Test name
Test status
Simulation time 39672069 ps
CPU time 0.61 seconds
Started Nov 22 01:26:52 PM PST 23
Finished Nov 22 01:27:00 PM PST 23
Peak memory 195432 kb
Host smart-59ad4cb8-6509-4182-88fa-d13ea421b774
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40238397863973158094216908733421126090723239998401595807876279441755490179469 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.40238397863973158094216908733421126090723239998401595807876279441755490179469
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.57199855075489807962835136400851172633927690415961121934521439468674315011549
Short name T520
Test name
Test status
Simulation time 33172121 ps
CPU time 0.58 seconds
Started Nov 22 01:27:09 PM PST 23
Finished Nov 22 01:27:27 PM PST 23
Peak memory 196820 kb
Host smart-0a5b3abd-07f6-4dc8-bcf5-80fa08ea6983
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57199855075489807962835136400851172633927690415961121934521439468674315011549 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.57199855075489807962835136400851172633927690415961121934521439468674315011549
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.72038264114626365543672027692155506249416042828103352608231545236565456642019
Short name T767
Test name
Test status
Simulation time 49975558 ps
CPU time 0.71 seconds
Started Nov 22 01:26:47 PM PST 23
Finished Nov 22 01:26:51 PM PST 23
Peak memory 201408 kb
Host smart-30f3f098-ac01-4526-8678-07e7a2ebc204
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72038264114626365543672027692155506249416042828103352608231545236565456642019 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_invalid.72038264114626365543672027692155506249416042828103352608231545236565456642019
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_wakeup_race.16036450698278844780280257071499532576952520093091415168498908258652148613882
Short name T912
Test name
Test status
Simulation time 296241445 ps
CPU time 1.19 seconds
Started Nov 22 01:26:47 PM PST 23
Finished Nov 22 01:26:50 PM PST 23
Peak memory 200076 kb
Host smart-f2070772-53af-4f90-a786-d400e03287b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16036450698278844780280257071499532576952520093091415168498908258652148613882 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_wakeup_race.16036450698278844780280257071499532576952520093091415168498908258652148613882
Directory /workspace/23.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.110173905878874913269950396362105728609059286202545567619260115766028497682313
Short name T321
Test name
Test status
Simulation time 119707143 ps
CPU time 1 seconds
Started Nov 22 01:26:45 PM PST 23
Finished Nov 22 01:26:47 PM PST 23
Peak memory 199156 kb
Host smart-d8f2da39-0f34-40e6-bb44-f2a9e791359f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110173905878874913269950396362105728609059286202545567619260115766028497682313 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.110173905878874913269950396362105728609059286202545567619260115766028497682313
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.2147641374337571038453342795495949486250142123318357112045570662700949358280
Short name T968
Test name
Test status
Simulation time 108189378 ps
CPU time 0.87 seconds
Started Nov 22 01:26:57 PM PST 23
Finished Nov 22 01:27:11 PM PST 23
Peak memory 209532 kb
Host smart-9156bb8b-8970-4bdc-a723-d7506aec6d01
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147641374337571038453342795495949486250142123318357112045570662700949358280 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.2147641374337571038453342795495949486250142123318357112045570662700949358280
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.8316798506060951534217557698763260640279518727827968136565175050782677780870
Short name T741
Test name
Test status
Simulation time 314830582 ps
CPU time 1.38 seconds
Started Nov 22 01:26:49 PM PST 23
Finished Nov 22 01:26:55 PM PST 23
Peak memory 200008 kb
Host smart-45ef84fd-a200-450e-8fe6-df0a5b95489d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8316798506060951534217557698763260640279518727827968136565175050782677780870 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_ctrl_config_regwen.8316798506060951534217557698763260640279518727827968136565
175050782677780870
Directory /workspace/23.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.32536408547318737748847527710599655196811987012268202267477477223500631769492
Short name T483
Test name
Test status
Simulation time 968503924 ps
CPU time 2.76 seconds
Started Nov 22 01:26:41 PM PST 23
Finished Nov 22 01:26:45 PM PST 23
Peak memory 200976 kb
Host smart-548161df-3a4a-4dd8-9954-015e10a4b4e8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32536408547318737748847527710599655196811987012268202267477
477223500631769492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.325364085473187377488475
27710599655196811987012268202267477477223500631769492
Directory /workspace/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.93807768603234130754625243583997308956993063536248609876895007527692939817950
Short name T125
Test name
Test status
Simulation time 91600225 ps
CPU time 0.86 seconds
Started Nov 22 01:27:10 PM PST 23
Finished Nov 22 01:27:29 PM PST 23
Peak memory 195520 kb
Host smart-fed213ac-9cb7-40d7-ba25-d4c0b6e2f4d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93807768603234130754625243583997308956993063536248609876895007527692939817950 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig_mubi.93807768603234130754625243583997308956993063536248609876895007527692939817950
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.29207970569740903539102081484601627605399841742935174581141784141686441461367
Short name T637
Test name
Test status
Simulation time 35743529 ps
CPU time 0.66 seconds
Started Nov 22 01:26:47 PM PST 23
Finished Nov 22 01:26:50 PM PST 23
Peak memory 197716 kb
Host smart-365fe808-6d5f-46ee-b2ee-3ebec3ebb9c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29207970569740903539102081484601627605399841742935174581141784141686441461367 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.29207970569740903539102081484601627605399841742935174581141784141686441461367
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_stress_all.40098609019473051498961765657962346361715128259009188548094899974037838757936
Short name T527
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.43 seconds
Started Nov 22 01:26:51 PM PST 23
Finished Nov 22 01:27:02 PM PST 23
Peak memory 201088 kb
Host smart-cab9d4da-35fe-4ebd-8901-526bee08dc1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40098609019473051498961765657962346361715128259009188548094899974037838757936 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.40098609019473051498961765657962346361715128259009188548094899974037838757936
Directory /workspace/23.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/23.pwrmgr_stress_all_with_rand_reset.96557736073579431766314063866776116070527690139027834284676813705511356514122
Short name T777
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.2 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:24 PM PST 23
Peak memory 201412 kb
Host smart-63259102-2691-442d-a393-a0f72fd815d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965577360735794317663140
63866776116070527690139027834284676813705511356514122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all_with_rand_reset.96557
736073579431766314063866776116070527690139027834284676813705511356514122
Directory /workspace/23.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup.11873415082047807786195732909723911061345426377777669535684714038765274684562
Short name T870
Test name
Test status
Simulation time 283777259 ps
CPU time 1.17 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 200004 kb
Host smart-19f1d064-ef87-4c99-a8f5-0b49f3f74516
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11873415082047807786195732909723911061345426377777669535684714038765274684562 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.11873415082047807786195732909723911061345426377777669535684714038765274684562
Directory /workspace/23.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup_reset.68435096973795333365290801978476205619494206762031185686049348285140703051260
Short name T397
Test name
Test status
Simulation time 325437640 ps
CPU time 1.37 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 200784 kb
Host smart-3048ae03-089f-4eee-b67b-85666dd1e293
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68435096973795333365290801978476205619494206762031185686049348285140703051260 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.68435096973795333365290801978476205619494206762031185686049348285140703051260
Directory /workspace/23.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.97655421506105199303765970762662572453447073921687644985585162446911713832375
Short name T542
Test name
Test status
Simulation time 51975542 ps
CPU time 0.79 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:12 PM PST 23
Peak memory 199016 kb
Host smart-4bc4f6e7-6161-4ce1-bfb9-1a522cd31508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97655421506105199303765970762662572453447073921687644985585162446911713832375 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 24.pwrmgr_aborted_low_power.97655421506105199303765970762662572453447073921687644985585162446911713832375
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.7145310489246438153742292885814086766390216635497791668152670452633355651927
Short name T566
Test name
Test status
Simulation time 72403950 ps
CPU time 0.75 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:13 PM PST 23
Peak memory 198256 kb
Host smart-74aba330-554b-4dac-a65b-648dfabd6d7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7145310489246438153742292885814086766390216635497791668152670452633355651927 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_disable_rom_integrity_check.7145310489246438153742292885814086766390216635497791668
152670452633355651927
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.65234337814095025482334747510086587388965591108180864802175679216689620866599
Short name T564
Test name
Test status
Simulation time 30368572 ps
CPU time 0.6 seconds
Started Nov 22 01:27:00 PM PST 23
Finished Nov 22 01:27:16 PM PST 23
Peak memory 195472 kb
Host smart-d5972fe7-550b-4841-b2ea-2b3451f74dc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65234337814095025482334747510086587388965591108180864802175679216689620866599 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst_malfunc.65234337814095025482334747510086587388965591108180864802175679216689620866599
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.59136942098917120856262290985512803449549076895891141031950175621103762789490
Short name T541
Test name
Test status
Simulation time 39672069 ps
CPU time 0.6 seconds
Started Nov 22 01:26:49 PM PST 23
Finished Nov 22 01:26:53 PM PST 23
Peak memory 195476 kb
Host smart-0d75f753-aff6-4b91-a55f-5b875b54340b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59136942098917120856262290985512803449549076895891141031950175621103762789490 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.59136942098917120856262290985512803449549076895891141031950175621103762789490
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.39781789934292929390195667858941176095876649650265689525315955175667714817656
Short name T548
Test name
Test status
Simulation time 33172121 ps
CPU time 0.6 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:13 PM PST 23
Peak memory 196848 kb
Host smart-581822f4-6c53-4ac3-9074-a30c5511fe2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39781789934292929390195667858941176095876649650265689525315955175667714817656 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.39781789934292929390195667858941176095876649650265689525315955175667714817656
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.65169371954114727076820522955655468288436358269406202084067061940450630706745
Short name T146
Test name
Test status
Simulation time 49975558 ps
CPU time 0.72 seconds
Started Nov 22 01:26:59 PM PST 23
Finished Nov 22 01:27:14 PM PST 23
Peak memory 201380 kb
Host smart-14986faa-eb37-4322-bd8c-26fbaf512764
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65169371954114727076820522955655468288436358269406202084067061940450630706745 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_invalid.65169371954114727076820522955655468288436358269406202084067061940450630706745
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_wakeup_race.56902489647548717912577485356496095005305397073272493129875824182759988813420
Short name T103
Test name
Test status
Simulation time 296241445 ps
CPU time 1.21 seconds
Started Nov 22 01:26:45 PM PST 23
Finished Nov 22 01:26:48 PM PST 23
Peak memory 200084 kb
Host smart-2350072d-67ec-4717-80cb-01562fcf630f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56902489647548717912577485356496095005305397073272493129875824182759988813420 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_wakeup_race.56902489647548717912577485356496095005305397073272493129875824182759988813420
Directory /workspace/24.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.29478487627522288074270029668934424338578944362642724431730651305346348934535
Short name T423
Test name
Test status
Simulation time 119707143 ps
CPU time 1.01 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:14 PM PST 23
Peak memory 199336 kb
Host smart-81074f96-33bf-49a6-89cc-3f27527fd4c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29478487627522288074270029668934424338578944362642724431730651305346348934535 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.29478487627522288074270029668934424338578944362642724431730651305346348934535
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.67530907878955827071852021389273502323831783438727032629534244828489813987945
Short name T356
Test name
Test status
Simulation time 108189378 ps
CPU time 0.85 seconds
Started Nov 22 01:26:56 PM PST 23
Finished Nov 22 01:27:09 PM PST 23
Peak memory 209544 kb
Host smart-5c0a8ac5-2cab-4c62-990e-3ae8b115cb76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67530907878955827071852021389273502323831783438727032629534244828489813987945 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.67530907878955827071852021389273502323831783438727032629534244828489813987945
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.25096141199004262825532940002271653748007065961808765114193444069697528213790
Short name T49
Test name
Test status
Simulation time 314830582 ps
CPU time 1.32 seconds
Started Nov 22 01:26:47 PM PST 23
Finished Nov 22 01:26:52 PM PST 23
Peak memory 199920 kb
Host smart-9c504f29-f5e9-436d-b801-5d10eeffb6a2
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25096141199004262825532940002271653748007065961808765114193444069697528213790 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_ctrl_config_regwen.250961411990042628255329400022716537480070659618087651141
93444069697528213790
Directory /workspace/24.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.50464985357714738276933619894913732525595849116032786985860431919811865295378
Short name T118
Test name
Test status
Simulation time 919450745 ps
CPU time 3.05 seconds
Started Nov 22 01:26:59 PM PST 23
Finished Nov 22 01:27:16 PM PST 23
Peak memory 201236 kb
Host smart-c6b7ca96-221e-464d-b870-472d33ca5b3b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504649853577147382769336198949137325255958491160327869858604
31919811865295378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.50464985357714738276933619
894913732525595849116032786985860431919811865295378
Directory /workspace/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.110977563942622492981780405125743383917628379844689573221160209941489037319606
Short name T345
Test name
Test status
Simulation time 968503924 ps
CPU time 2.91 seconds
Started Nov 22 01:26:51 PM PST 23
Finished Nov 22 01:27:01 PM PST 23
Peak memory 201028 kb
Host smart-db5b64b5-c657-4a88-936b-7258ba150b5b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11097756394262249298178040512574338391762837984468957322116
0209941489037319606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.11097756394262249298178
0405125743383917628379844689573221160209941489037319606
Directory /workspace/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.100804158233114897532279681702384373059242157052129579451779775575818832122868
Short name T502
Test name
Test status
Simulation time 91600225 ps
CPU time 0.88 seconds
Started Nov 22 01:27:04 PM PST 23
Finished Nov 22 01:27:20 PM PST 23
Peak memory 195436 kb
Host smart-1c6c41c5-f1be-45ae-999c-2aaedc36e995
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100804158233114897532279681702384373059242157052129579451779775575818832122868 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig_mubi.100804158233114897532279681702384373059242157052129579451779775575818832122868
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.65943932082395352241470774381497041309019376975536029058279850300612660747584
Short name T898
Test name
Test status
Simulation time 35743529 ps
CPU time 0.66 seconds
Started Nov 22 01:26:48 PM PST 23
Finished Nov 22 01:26:53 PM PST 23
Peak memory 197888 kb
Host smart-940df0e9-5676-4058-b0ff-b8fef2f982e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65943932082395352241470774381497041309019376975536029058279850300612660747584 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.65943932082395352241470774381497041309019376975536029058279850300612660747584
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_stress_all.29063875705076321109179911035764420713199223410865481345506474880675180286397
Short name T577
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.79 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:17 PM PST 23
Peak memory 201164 kb
Host smart-b5117f89-9835-46c9-9124-9496a11ea09f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29063875705076321109179911035764420713199223410865481345506474880675180286397 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.29063875705076321109179911035764420713199223410865481345506474880675180286397
Directory /workspace/24.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/24.pwrmgr_stress_all_with_rand_reset.114043765058303293606359809515025163262719232226420629802500569533676497666200
Short name T346
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.57 seconds
Started Nov 22 01:27:00 PM PST 23
Finished Nov 22 01:27:27 PM PST 23
Peak memory 201440 kb
Host smart-88ff598e-a3dc-4d19-87f5-5738c3a0ffe3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114043765058303293606359
809515025163262719232226420629802500569533676497666200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all_with_rand_reset.1140
43765058303293606359809515025163262719232226420629802500569533676497666200
Directory /workspace/24.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup.105000119565198983901746596790290103136444575546646844676831934274149189915025
Short name T480
Test name
Test status
Simulation time 283777259 ps
CPU time 1.19 seconds
Started Nov 22 01:26:46 PM PST 23
Finished Nov 22 01:26:50 PM PST 23
Peak memory 200096 kb
Host smart-3ed9bedd-732a-4e4d-996c-ee90baf5add7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105000119565198983901746596790290103136444575546646844676831934274149189915025 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.105000119565198983901746596790290103136444575546646844676831934274149189915025
Directory /workspace/24.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup_reset.43913918273176177044984269754652810077727179769413726939308234586624068448252
Short name T774
Test name
Test status
Simulation time 325437640 ps
CPU time 1.37 seconds
Started Nov 22 01:26:51 PM PST 23
Finished Nov 22 01:26:59 PM PST 23
Peak memory 200588 kb
Host smart-dbb3d219-86f2-40e6-bc85-3db6112967d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43913918273176177044984269754652810077727179769413726939308234586624068448252 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.43913918273176177044984269754652810077727179769413726939308234586624068448252
Directory /workspace/24.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.8710325023952710180742740640937675696147602652496081417908437555968379857172
Short name T752
Test name
Test status
Simulation time 51975542 ps
CPU time 0.8 seconds
Started Nov 22 01:26:57 PM PST 23
Finished Nov 22 01:27:10 PM PST 23
Peak memory 199140 kb
Host smart-eb6bd40c-9e49-4447-a141-5f2509581da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8710325023952710180742740640937675696147602652496081417908437555968379857172 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 25.pwrmgr_aborted_low_power.8710325023952710180742740640937675696147602652496081417908437555968379857172
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.34612064112310925612100976263271957748626277633464160672773899142276449099731
Short name T784
Test name
Test status
Simulation time 72403950 ps
CPU time 0.74 seconds
Started Nov 22 01:26:59 PM PST 23
Finished Nov 22 01:27:14 PM PST 23
Peak memory 198244 kb
Host smart-1a5c695c-e4f7-4831-a046-e97462e6d9e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34612064112310925612100976263271957748626277633464160672773899142276449099731 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_disable_rom_integrity_check.346120641123109256121009762632719577486262776334641606
72773899142276449099731
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.5837935782561960767579882321493582687135127793102156017758179599687271013990
Short name T928
Test name
Test status
Simulation time 30368572 ps
CPU time 0.61 seconds
Started Nov 22 01:26:57 PM PST 23
Finished Nov 22 01:27:11 PM PST 23
Peak memory 195420 kb
Host smart-cc6f81c3-8c7d-4d7b-a0eb-d0bb81acef11
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5837935782561960767579882321493582687135127793102156017758179599687271013990 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst_malfunc.5837935782561960767579882321493582687135127793102156017758179599687271013990
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.49175126322303578620642853227496002622932246025243953926768994711916673581635
Short name T725
Test name
Test status
Simulation time 39672069 ps
CPU time 0.61 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:13 PM PST 23
Peak memory 195460 kb
Host smart-5dd9aa01-fb4e-4e65-8000-e19a198b5e4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49175126322303578620642853227496002622932246025243953926768994711916673581635 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.49175126322303578620642853227496002622932246025243953926768994711916673581635
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.53152419723023993365482897089989392195681091349861554996099406703815426325581
Short name T630
Test name
Test status
Simulation time 33172121 ps
CPU time 0.59 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:13 PM PST 23
Peak memory 196736 kb
Host smart-4a997cbb-2979-424c-9680-3003a3f2c4cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53152419723023993365482897089989392195681091349861554996099406703815426325581 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.53152419723023993365482897089989392195681091349861554996099406703815426325581
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.95718162930185808439095745905918162409472445313951898392137593721166575500820
Short name T621
Test name
Test status
Simulation time 49975558 ps
CPU time 0.69 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:13 PM PST 23
Peak memory 201356 kb
Host smart-9bedb6ac-c1ba-4473-a00c-f3460360574b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95718162930185808439095745905918162409472445313951898392137593721166575500820 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_invalid.95718162930185808439095745905918162409472445313951898392137593721166575500820
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_wakeup_race.110571862218980024841974255457165678243775625973932235342970966272019426963239
Short name T1019
Test name
Test status
Simulation time 296241445 ps
CPU time 1.2 seconds
Started Nov 22 01:26:57 PM PST 23
Finished Nov 22 01:27:12 PM PST 23
Peak memory 200048 kb
Host smart-73faeb93-0e0f-4988-b075-614169dd7f24
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110571862218980024841974255457165678243775625973932235342970966272019426963239 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_wakeup_race.110571862218980024841974255457165678243775625973932235342970966272019426963239
Directory /workspace/25.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.101033077180122290319671875772864815044805827206755594203248315849997980903940
Short name T965
Test name
Test status
Simulation time 119707143 ps
CPU time 1.06 seconds
Started Nov 22 01:27:11 PM PST 23
Finished Nov 22 01:27:30 PM PST 23
Peak memory 199320 kb
Host smart-5765ac77-bf78-4de9-ae72-a0d10bfb19f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101033077180122290319671875772864815044805827206755594203248315849997980903940 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.101033077180122290319671875772864815044805827206755594203248315849997980903940
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.39559751122744233908738641341560602002461581932413124077627215311748245004317
Short name T559
Test name
Test status
Simulation time 108189378 ps
CPU time 0.89 seconds
Started Nov 22 01:27:07 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 209524 kb
Host smart-1c6446f7-06a0-48cc-a01e-1e9d87f87dd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39559751122744233908738641341560602002461581932413124077627215311748245004317 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.39559751122744233908738641341560602002461581932413124077627215311748245004317
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.107753798417463675113570044814906082926852946267551741330161853001315951555966
Short name T595
Test name
Test status
Simulation time 314830582 ps
CPU time 1.35 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:14 PM PST 23
Peak memory 199896 kb
Host smart-63fe89cc-0658-4129-8c7a-bd08c11c59f2
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107753798417463675113570044814906082926852946267551741330161853001315951555966 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_ctrl_config_regwen.10775379841746367511357004481490608292685294626755174133
0161853001315951555966
Directory /workspace/25.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.28827179125601379427070597592550093402069278361530009843107809304100720771014
Short name T608
Test name
Test status
Simulation time 919450745 ps
CPU time 3 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:15 PM PST 23
Peak memory 201236 kb
Host smart-0c4e6fe6-39f5-46c9-bc6c-eb3e3116d577
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288271791256013794270705975925500934020692783615300098431078
09304100720771014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.28827179125601379427070597
592550093402069278361530009843107809304100720771014
Directory /workspace/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.94356889686800948714926195447805076693067001191536638395569332430991853861398
Short name T471
Test name
Test status
Simulation time 968503924 ps
CPU time 2.81 seconds
Started Nov 22 01:27:02 PM PST 23
Finished Nov 22 01:27:22 PM PST 23
Peak memory 201144 kb
Host smart-73c8745e-0d38-42b5-b3d4-f63e8e701074
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94356889686800948714926195447805076693067001191536638395569
332430991853861398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.943568896868009487149261
95447805076693067001191536638395569332430991853861398
Directory /workspace/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.76009876137317959395757986738592385612275074479108870204187245472421381521227
Short name T873
Test name
Test status
Simulation time 91600225 ps
CPU time 0.9 seconds
Started Nov 22 01:26:59 PM PST 23
Finished Nov 22 01:27:15 PM PST 23
Peak memory 195516 kb
Host smart-d7215825-378c-45d7-a0b2-da09a74d9c40
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76009876137317959395757986738592385612275074479108870204187245472421381521227 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig_mubi.76009876137317959395757986738592385612275074479108870204187245472421381521227
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.69545576968774275677022108597031374550170799510707470972173187352055230566187
Short name T923
Test name
Test status
Simulation time 35743529 ps
CPU time 0.64 seconds
Started Nov 22 01:27:02 PM PST 23
Finished Nov 22 01:27:20 PM PST 23
Peak memory 197912 kb
Host smart-b4093fc4-ef22-4355-b040-493b77e93a1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69545576968774275677022108597031374550170799510707470972173187352055230566187 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.69545576968774275677022108597031374550170799510707470972173187352055230566187
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_stress_all.68520937026384223463252584775836349540842126071357139120473314668089704724083
Short name T951
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.65 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:18 PM PST 23
Peak memory 201196 kb
Host smart-6925f661-cae6-478b-a148-4634cb8a00c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68520937026384223463252584775836349540842126071357139120473314668089704724083 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.68520937026384223463252584775836349540842126071357139120473314668089704724083
Directory /workspace/25.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/25.pwrmgr_stress_all_with_rand_reset.60251020233891571040940890780198823881366290147303337068106044234448461626031
Short name T656
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.73 seconds
Started Nov 22 01:26:59 PM PST 23
Finished Nov 22 01:27:26 PM PST 23
Peak memory 201392 kb
Host smart-9da256c7-b2e0-47c4-8415-d88a20d47c3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602510202338915710409408
90780198823881366290147303337068106044234448461626031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all_with_rand_reset.60251
020233891571040940890780198823881366290147303337068106044234448461626031
Directory /workspace/25.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup.43998287593546183868588113987619109124297724571443984476433321274676362312970
Short name T169
Test name
Test status
Simulation time 283777259 ps
CPU time 1.2 seconds
Started Nov 22 01:27:01 PM PST 23
Finished Nov 22 01:27:19 PM PST 23
Peak memory 199992 kb
Host smart-54374601-9530-4147-8aa4-13c3e6084c60
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43998287593546183868588113987619109124297724571443984476433321274676362312970 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.43998287593546183868588113987619109124297724571443984476433321274676362312970
Directory /workspace/25.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup_reset.23714573378228084343519626921384891287125846716614906088855791087804341507091
Short name T871
Test name
Test status
Simulation time 325437640 ps
CPU time 1.4 seconds
Started Nov 22 01:26:57 PM PST 23
Finished Nov 22 01:27:12 PM PST 23
Peak memory 200792 kb
Host smart-04cc3f7d-f6b5-4174-bfa5-237efc877d17
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23714573378228084343519626921384891287125846716614906088855791087804341507091 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.23714573378228084343519626921384891287125846716614906088855791087804341507091
Directory /workspace/25.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.93512006416069396800058700291130784655061180761082050208714597912241818322820
Short name T24
Test name
Test status
Simulation time 51975542 ps
CPU time 0.77 seconds
Started Nov 22 01:27:01 PM PST 23
Finished Nov 22 01:27:19 PM PST 23
Peak memory 199160 kb
Host smart-beda1088-fe00-4a97-9980-197ef7af85ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93512006416069396800058700291130784655061180761082050208714597912241818322820 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.pwrmgr_aborted_low_power.93512006416069396800058700291130784655061180761082050208714597912241818322820
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.65473918921950498935360109210940023369628538630792703527550341224780479712819
Short name T670
Test name
Test status
Simulation time 72403950 ps
CPU time 0.77 seconds
Started Nov 22 01:26:57 PM PST 23
Finished Nov 22 01:27:10 PM PST 23
Peak memory 198164 kb
Host smart-c83adbdc-2d7e-4aa4-bc3a-ca857476265f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65473918921950498935360109210940023369628538630792703527550341224780479712819 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_disable_rom_integrity_check.654739189219504989353601092109400233696285386307927035
27550341224780479712819
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.107684154505756927827996321832860579850797762437828633912608507128942711120091
Short name T683
Test name
Test status
Simulation time 30368572 ps
CPU time 0.57 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 195280 kb
Host smart-30d3c45d-ee2b-44b8-a660-71ab83477236
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107684154505756927827996321832860579850797762437828633912608507128942711120091 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst_malfunc.107684154505756927827996321832860579850797762437828633912608507128942711120091
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.54515766972359684054257820700774190246645002326710054273077918826887540761452
Short name T872
Test name
Test status
Simulation time 39672069 ps
CPU time 0.61 seconds
Started Nov 22 01:27:04 PM PST 23
Finished Nov 22 01:27:19 PM PST 23
Peak memory 195404 kb
Host smart-f5b6d346-ca09-4b77-a3b5-f0190f6dabec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54515766972359684054257820700774190246645002326710054273077918826887540761452 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.54515766972359684054257820700774190246645002326710054273077918826887540761452
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.25767353843493192219321030358473777588609516059141080438094685695089770598747
Short name T882
Test name
Test status
Simulation time 33172121 ps
CPU time 0.64 seconds
Started Nov 22 01:26:59 PM PST 23
Finished Nov 22 01:27:15 PM PST 23
Peak memory 196884 kb
Host smart-1d2c1889-6ddd-46f2-9d5d-2a5ed94e3e2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25767353843493192219321030358473777588609516059141080438094685695089770598747 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.25767353843493192219321030358473777588609516059141080438094685695089770598747
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.78665868180968405733339161778573083430489673008648104377004565033193273798099
Short name T753
Test name
Test status
Simulation time 49975558 ps
CPU time 0.72 seconds
Started Nov 22 01:26:59 PM PST 23
Finished Nov 22 01:27:15 PM PST 23
Peak memory 201424 kb
Host smart-f43fd288-e3ad-471c-ab64-498a9fbddf0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78665868180968405733339161778573083430489673008648104377004565033193273798099 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_invalid.78665868180968405733339161778573083430489673008648104377004565033193273798099
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_wakeup_race.72395066177131560808553012528975562163462837161213215397481533220659693175678
Short name T379
Test name
Test status
Simulation time 296241445 ps
CPU time 1.2 seconds
Started Nov 22 01:27:01 PM PST 23
Finished Nov 22 01:27:18 PM PST 23
Peak memory 200100 kb
Host smart-7ead4461-8c68-4e4b-8a67-9bff38003623
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72395066177131560808553012528975562163462837161213215397481533220659693175678 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_wakeup_race.72395066177131560808553012528975562163462837161213215397481533220659693175678
Directory /workspace/26.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.79864050113378758201172850330880686336287326388398996602019120296153291552700
Short name T407
Test name
Test status
Simulation time 119707143 ps
CPU time 1.02 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:14 PM PST 23
Peak memory 199304 kb
Host smart-e2b6c09b-89d8-4534-aa00-6a6555b631de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79864050113378758201172850330880686336287326388398996602019120296153291552700 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.79864050113378758201172850330880686336287326388398996602019120296153291552700
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.72683995547532789525587710008233390380167171364973098510520570877322404962397
Short name T667
Test name
Test status
Simulation time 314830582 ps
CPU time 1.31 seconds
Started Nov 22 01:26:57 PM PST 23
Finished Nov 22 01:27:12 PM PST 23
Peak memory 199916 kb
Host smart-9e76098e-1667-4b96-a8ff-e4f345ea1446
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72683995547532789525587710008233390380167171364973098510520570877322404962397 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_ctrl_config_regwen.726839955475327895255877100082333903801671713649730985105
20570877322404962397
Directory /workspace/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.92874795354408533408720625519419351744700827963809051021353707499322494378880
Short name T763
Test name
Test status
Simulation time 919450745 ps
CPU time 2.99 seconds
Started Nov 22 01:26:57 PM PST 23
Finished Nov 22 01:27:13 PM PST 23
Peak memory 201236 kb
Host smart-e291b8a2-aa14-4327-abaa-6b86e7e28cee
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928747953544085334087206255194193517447008279638090510213537
07499322494378880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.92874795354408533408720625
519419351744700827963809051021353707499322494378880
Directory /workspace/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.106632723262688782748401029933152302561124324973277796637621917737350968804489
Short name T435
Test name
Test status
Simulation time 968503924 ps
CPU time 3.09 seconds
Started Nov 22 01:27:00 PM PST 23
Finished Nov 22 01:27:19 PM PST 23
Peak memory 201104 kb
Host smart-4faa1092-72be-43a1-badf-51fe40783bce
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10663272326268878274840102993315230256112432497327779663762
1917737350968804489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.10663272326268878274840
1029933152302561124324973277796637621917737350968804489
Directory /workspace/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.23923752704966633093694188610772006934315553541015694115015125261945543605458
Short name T1027
Test name
Test status
Simulation time 91600225 ps
CPU time 0.92 seconds
Started Nov 22 01:27:09 PM PST 23
Finished Nov 22 01:27:27 PM PST 23
Peak memory 195520 kb
Host smart-b1233cd5-e802-4efc-a27e-f041f0c0679e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23923752704966633093694188610772006934315553541015694115015125261945543605458 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig_mubi.23923752704966633093694188610772006934315553541015694115015125261945543605458
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.78908818867402529666740571201060139001412218652086192213781634569445288991979
Short name T294
Test name
Test status
Simulation time 35743529 ps
CPU time 0.64 seconds
Started Nov 22 01:27:05 PM PST 23
Finished Nov 22 01:27:20 PM PST 23
Peak memory 197804 kb
Host smart-64582dde-98b7-4107-a2a5-02fd7e909545
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78908818867402529666740571201060139001412218652086192213781634569445288991979 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.78908818867402529666740571201060139001412218652086192213781634569445288991979
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_stress_all.106504996021291456409532003631301187226184269160562038306793870071818387177746
Short name T23
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.46 seconds
Started Nov 22 01:27:01 PM PST 23
Finished Nov 22 01:27:23 PM PST 23
Peak memory 201296 kb
Host smart-f7b0526e-6d15-4d2a-b8b6-82a684ddb72f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106504996021291456409532003631301187226184269160562038306793870071818387177746 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all.106504996021291456409532003631301187226184269160562038306793870071818387177746
Directory /workspace/26.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/26.pwrmgr_stress_all_with_rand_reset.40872730240784565921612669303108705360129427927899331831975741846405021890893
Short name T623
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.73 seconds
Started Nov 22 01:26:55 PM PST 23
Finished Nov 22 01:27:20 PM PST 23
Peak memory 201416 kb
Host smart-841135b3-e652-4991-8bea-4cb0c096d955
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408727302407845659216126
69303108705360129427927899331831975741846405021890893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all_with_rand_reset.40872
730240784565921612669303108705360129427927899331831975741846405021890893
Directory /workspace/26.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup.31968642810262653093259990451595013146446167447953483050183157070730149670192
Short name T491
Test name
Test status
Simulation time 283777259 ps
CPU time 1.21 seconds
Started Nov 22 01:26:57 PM PST 23
Finished Nov 22 01:27:12 PM PST 23
Peak memory 200092 kb
Host smart-44396c8d-a73d-4b51-967c-634d2effc984
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31968642810262653093259990451595013146446167447953483050183157070730149670192 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.31968642810262653093259990451595013146446167447953483050183157070730149670192
Directory /workspace/26.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup_reset.93617020457728559482438940643732261130853359122150859175517959061495049359747
Short name T298
Test name
Test status
Simulation time 325437640 ps
CPU time 1.43 seconds
Started Nov 22 01:26:57 PM PST 23
Finished Nov 22 01:27:12 PM PST 23
Peak memory 200728 kb
Host smart-27e3e3b1-cbe5-4e16-ba8a-58bb9badfc3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93617020457728559482438940643732261130853359122150859175517959061495049359747 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup_reset.93617020457728559482438940643732261130853359122150859175517959061495049359747
Directory /workspace/26.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.67389899792448258250610790550150498858523167650348205397264748389488988536978
Short name T769
Test name
Test status
Simulation time 51975542 ps
CPU time 0.73 seconds
Started Nov 22 01:27:07 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 198968 kb
Host smart-537eeab3-4e29-407a-9d0a-e26267b3c78b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67389899792448258250610790550150498858523167650348205397264748389488988536978 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.pwrmgr_aborted_low_power.67389899792448258250610790550150498858523167650348205397264748389488988536978
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.30221722663696273629767368231010105203943888228890736418395916930765162526935
Short name T629
Test name
Test status
Simulation time 72403950 ps
CPU time 0.74 seconds
Started Nov 22 01:27:02 PM PST 23
Finished Nov 22 01:27:19 PM PST 23
Peak memory 198152 kb
Host smart-5177954b-f9b1-43d5-9eaa-a2b635b22468
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30221722663696273629767368231010105203943888228890736418395916930765162526935 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_disable_rom_integrity_check.302217226636962736297673682310101052039438882288907364
18395916930765162526935
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.74123904717579484562827503487465534876765204104381604181201587811325997605530
Short name T895
Test name
Test status
Simulation time 30368572 ps
CPU time 0.59 seconds
Started Nov 22 01:27:07 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 195372 kb
Host smart-c2cc4309-a0cb-441f-8d64-2f7c5ec5782a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74123904717579484562827503487465534876765204104381604181201587811325997605530 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst_malfunc.74123904717579484562827503487465534876765204104381604181201587811325997605530
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.92566334143323199692307576702185001672328183430729669873231410632448354011460
Short name T988
Test name
Test status
Simulation time 39672069 ps
CPU time 0.6 seconds
Started Nov 22 01:27:02 PM PST 23
Finished Nov 22 01:27:19 PM PST 23
Peak memory 195532 kb
Host smart-f37a746c-9467-4919-a0e4-8053b4e13b9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92566334143323199692307576702185001672328183430729669873231410632448354011460 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.92566334143323199692307576702185001672328183430729669873231410632448354011460
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.25634853309219096943241002446272571345762728192022246424873256621698919470192
Short name T665
Test name
Test status
Simulation time 33172121 ps
CPU time 0.6 seconds
Started Nov 22 01:27:10 PM PST 23
Finished Nov 22 01:27:27 PM PST 23
Peak memory 196848 kb
Host smart-e2219abb-a519-4715-9e2e-79eac2c5771c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25634853309219096943241002446272571345762728192022246424873256621698919470192 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.25634853309219096943241002446272571345762728192022246424873256621698919470192
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.63289581294082743886170415432932139741329191956162623498752698091721918144629
Short name T679
Test name
Test status
Simulation time 49975558 ps
CPU time 0.68 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:13 PM PST 23
Peak memory 201400 kb
Host smart-aafa55ac-86c7-40c6-a0b0-0e029ec12df6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63289581294082743886170415432932139741329191956162623498752698091721918144629 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_invalid.63289581294082743886170415432932139741329191956162623498752698091721918144629
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_wakeup_race.44533887036071358990326232189029806538544478099381637256957683570420150369731
Short name T124
Test name
Test status
Simulation time 296241445 ps
CPU time 1.18 seconds
Started Nov 22 01:27:01 PM PST 23
Finished Nov 22 01:27:18 PM PST 23
Peak memory 200100 kb
Host smart-1bc5e94c-9365-46f3-868c-ca20527928b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44533887036071358990326232189029806538544478099381637256957683570420150369731 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_wakeup_race.44533887036071358990326232189029806538544478099381637256957683570420150369731
Directory /workspace/27.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.9151820247775127874551989431914077666125766248033405700271220146882162401174
Short name T147
Test name
Test status
Simulation time 119707143 ps
CPU time 1.01 seconds
Started Nov 22 01:26:57 PM PST 23
Finished Nov 22 01:27:12 PM PST 23
Peak memory 199292 kb
Host smart-5493d4b7-62a0-403f-a551-0929fd90edef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9151820247775127874551989431914077666125766248033405700271220146882162401174 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.9151820247775127874551989431914077666125766248033405700271220146882162401174
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.6460359286580509903814477668903676001339418625291066185105421622738644891069
Short name T680
Test name
Test status
Simulation time 108189378 ps
CPU time 0.82 seconds
Started Nov 22 01:27:00 PM PST 23
Finished Nov 22 01:27:16 PM PST 23
Peak memory 209516 kb
Host smart-1b448a9b-a772-4f22-817e-c021947028e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6460359286580509903814477668903676001339418625291066185105421622738644891069 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.6460359286580509903814477668903676001339418625291066185105421622738644891069
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.99450391672820179811039617031922263713999595966560125869715263830457147269653
Short name T1034
Test name
Test status
Simulation time 314830582 ps
CPU time 1.29 seconds
Started Nov 22 01:26:57 PM PST 23
Finished Nov 22 01:27:11 PM PST 23
Peak memory 199928 kb
Host smart-dd1fea20-5f5b-4982-9aa4-157729f2064b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99450391672820179811039617031922263713999595966560125869715263830457147269653 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_ctrl_config_regwen.994503916728201798110396170319222637139995959665601258697
15263830457147269653
Directory /workspace/27.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.60965202215192864122282478646080602837281944130255439324766256392198767092058
Short name T994
Test name
Test status
Simulation time 919450745 ps
CPU time 2.92 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:16 PM PST 23
Peak memory 201236 kb
Host smart-83500b86-5935-41a5-ac9f-62d218c21b33
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609652022151928641222824786460806028372819441302554393247662
56392198767092058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.60965202215192864122282478
646080602837281944130255439324766256392198767092058
Directory /workspace/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.88628252625281562727763716941698788302234706763188377099202330041355237974828
Short name T817
Test name
Test status
Simulation time 968503924 ps
CPU time 3.09 seconds
Started Nov 22 01:26:59 PM PST 23
Finished Nov 22 01:27:16 PM PST 23
Peak memory 201076 kb
Host smart-12570004-ef39-47de-8d77-02388813adf8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88628252625281562727763716941698788302234706763188377099202
330041355237974828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.886282526252815627277637
16941698788302234706763188377099202330041355237974828
Directory /workspace/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.49655659420039283951109935828790077365105904324900192583759562574622700997130
Short name T425
Test name
Test status
Simulation time 91600225 ps
CPU time 0.92 seconds
Started Nov 22 01:27:00 PM PST 23
Finished Nov 22 01:27:16 PM PST 23
Peak memory 195516 kb
Host smart-dee12b93-47f1-4c92-8c9e-dde764ad3340
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49655659420039283951109935828790077365105904324900192583759562574622700997130 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig_mubi.49655659420039283951109935828790077365105904324900192583759562574622700997130
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.102451501778626985303076870368677024644359448538347160006504885959283812903505
Short name T606
Test name
Test status
Simulation time 35743529 ps
CPU time 0.68 seconds
Started Nov 22 01:27:01 PM PST 23
Finished Nov 22 01:27:18 PM PST 23
Peak memory 197796 kb
Host smart-12267f79-f733-4b76-b70b-c057118a1862
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102451501778626985303076870368677024644359448538347160006504885959283812903505 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.102451501778626985303076870368677024644359448538347160006504885959283812903505
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_stress_all.32890836435952649095115269012923134076003701735725752866787211974898435450081
Short name T944
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.54 seconds
Started Nov 22 01:26:56 PM PST 23
Finished Nov 22 01:27:14 PM PST 23
Peak memory 201224 kb
Host smart-a10d7e8a-3d69-4af1-8370-a255faf0a1b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32890836435952649095115269012923134076003701735725752866787211974898435450081 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.32890836435952649095115269012923134076003701735725752866787211974898435450081
Directory /workspace/27.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/27.pwrmgr_stress_all_with_rand_reset.44775423816523510887089154200491386092511224686546848600741874789887969797883
Short name T773
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.5 seconds
Started Nov 22 01:26:56 PM PST 23
Finished Nov 22 01:27:20 PM PST 23
Peak memory 201484 kb
Host smart-2e2e5481-c389-40cd-a521-4caeef119da5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447754238165235108870891
54200491386092511224686546848600741874789887969797883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all_with_rand_reset.44775
423816523510887089154200491386092511224686546848600741874789887969797883
Directory /workspace/27.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup.33731600019046058390321506496259857663728167425544920307922647027340479129095
Short name T800
Test name
Test status
Simulation time 283777259 ps
CPU time 1.16 seconds
Started Nov 22 01:27:01 PM PST 23
Finished Nov 22 01:27:19 PM PST 23
Peak memory 200116 kb
Host smart-d9a1be54-2f20-49d9-94d4-2422a9eb19cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33731600019046058390321506496259857663728167425544920307922647027340479129095 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.33731600019046058390321506496259857663728167425544920307922647027340479129095
Directory /workspace/27.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup_reset.73480848848216756985023620217540723474938921429435830366557477997631384781332
Short name T173
Test name
Test status
Simulation time 325437640 ps
CPU time 1.33 seconds
Started Nov 22 01:26:57 PM PST 23
Finished Nov 22 01:27:12 PM PST 23
Peak memory 200776 kb
Host smart-c6afdb1f-3243-4d2d-bc0d-612177df6d9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73480848848216756985023620217540723474938921429435830366557477997631384781332 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.73480848848216756985023620217540723474938921429435830366557477997631384781332
Directory /workspace/27.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.93473010030592487538076682445800242863006389951154248239220459852251416280845
Short name T549
Test name
Test status
Simulation time 51975542 ps
CPU time 0.81 seconds
Started Nov 22 01:27:11 PM PST 23
Finished Nov 22 01:27:30 PM PST 23
Peak memory 199108 kb
Host smart-daf50652-b9e4-4378-a55b-2c0f10778df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93473010030592487538076682445800242863006389951154248239220459852251416280845 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.pwrmgr_aborted_low_power.93473010030592487538076682445800242863006389951154248239220459852251416280845
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.75182887976444192317170230580601726135490985755360311383439263343407029052309
Short name T835
Test name
Test status
Simulation time 72403950 ps
CPU time 0.76 seconds
Started Nov 22 01:27:03 PM PST 23
Finished Nov 22 01:27:20 PM PST 23
Peak memory 198216 kb
Host smart-318eaac6-8d8d-43de-8b8c-fc353e932b36
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75182887976444192317170230580601726135490985755360311383439263343407029052309 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_disable_rom_integrity_check.751828879764441923171702305806017261354909857553603113
83439263343407029052309
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.14419790460733854714569930685402901953930519490277483388058983446342199814193
Short name T307
Test name
Test status
Simulation time 30368572 ps
CPU time 0.61 seconds
Started Nov 22 01:27:00 PM PST 23
Finished Nov 22 01:27:17 PM PST 23
Peak memory 195564 kb
Host smart-427f2184-4e5d-4119-866b-7a0c19ab00bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14419790460733854714569930685402901953930519490277483388058983446342199814193 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst_malfunc.14419790460733854714569930685402901953930519490277483388058983446342199814193
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.109855703530641988338611767778234883262184371866615656205083240081878032710633
Short name T313
Test name
Test status
Simulation time 39672069 ps
CPU time 0.6 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 195504 kb
Host smart-42f809fc-b078-45c3-b4e8-6ef31949766d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109855703530641988338611767778234883262184371866615656205083240081878032710633 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.109855703530641988338611767778234883262184371866615656205083240081878032710633
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.108395355053317560530436106025339147557063309745826627720569608074258668000565
Short name T756
Test name
Test status
Simulation time 33172121 ps
CPU time 0.6 seconds
Started Nov 22 01:27:03 PM PST 23
Finished Nov 22 01:27:19 PM PST 23
Peak memory 196676 kb
Host smart-46e874e6-5f0d-41e3-84e9-720c2a6a7474
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108395355053317560530436106025339147557063309745826627720569608074258668000565 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.108395355053317560530436106025339147557063309745826627720569608074258668000565
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.87867285832557474339735072558244550805887517225753370935020436228146163776669
Short name T593
Test name
Test status
Simulation time 49975558 ps
CPU time 0.66 seconds
Started Nov 22 01:27:07 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 201404 kb
Host smart-af8eacd6-fc69-4375-a37f-5bbc97b49aec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87867285832557474339735072558244550805887517225753370935020436228146163776669 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_invalid.87867285832557474339735072558244550805887517225753370935020436228146163776669
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_wakeup_race.99549451818338793708747442413604503949004688689046322186071267875521645507594
Short name T892
Test name
Test status
Simulation time 296241445 ps
CPU time 1.18 seconds
Started Nov 22 01:26:58 PM PST 23
Finished Nov 22 01:27:14 PM PST 23
Peak memory 200056 kb
Host smart-97df7abd-a686-44e6-9d59-029590339c52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99549451818338793708747442413604503949004688689046322186071267875521645507594 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_wakeup_race.99549451818338793708747442413604503949004688689046322186071267875521645507594
Directory /workspace/28.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.46102094857821539886490227525174096167586980898270222159744198387890795107887
Short name T431
Test name
Test status
Simulation time 119707143 ps
CPU time 1.02 seconds
Started Nov 22 01:27:01 PM PST 23
Finished Nov 22 01:27:19 PM PST 23
Peak memory 199228 kb
Host smart-042f1c43-1c35-4e75-9851-474b7d4ce11c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46102094857821539886490227525174096167586980898270222159744198387890795107887 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.46102094857821539886490227525174096167586980898270222159744198387890795107887
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.89227123336810742778962322005769859368747453341673778387957443222076053418757
Short name T685
Test name
Test status
Simulation time 108189378 ps
CPU time 0.83 seconds
Started Nov 22 01:27:03 PM PST 23
Finished Nov 22 01:27:20 PM PST 23
Peak memory 209508 kb
Host smart-602c4fda-001f-4c5a-af14-0149e3c3902f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89227123336810742778962322005769859368747453341673778387957443222076053418757 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.89227123336810742778962322005769859368747453341673778387957443222076053418757
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.18831865689227448997429639878448708249944008771572702379994643131396472374920
Short name T716
Test name
Test status
Simulation time 314830582 ps
CPU time 1.34 seconds
Started Nov 22 01:27:01 PM PST 23
Finished Nov 22 01:27:20 PM PST 23
Peak memory 199888 kb
Host smart-56b2dfd8-5c75-4a0c-9bf5-e7537f34aae5
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18831865689227448997429639878448708249944008771572702379994643131396472374920 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_ctrl_config_regwen.188318656892274489974296398784487082499440087715727023799
94643131396472374920
Directory /workspace/28.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.115432753436361073464059613914070869143110539625252785135380329342122928756737
Short name T596
Test name
Test status
Simulation time 919450745 ps
CPU time 2.89 seconds
Started Nov 22 01:27:02 PM PST 23
Finished Nov 22 01:27:22 PM PST 23
Peak memory 201192 kb
Host smart-c89f1b17-f76a-437c-8368-92d38642b95f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115432753436361073464059613914070869143110539625252785135380
329342122928756737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1154327534363610734640596
13914070869143110539625252785135380329342122928756737
Directory /workspace/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.105786793293005266981442875381094916907955642650365739870935889588611281492540
Short name T850
Test name
Test status
Simulation time 968503924 ps
CPU time 3.08 seconds
Started Nov 22 01:26:59 PM PST 23
Finished Nov 22 01:27:17 PM PST 23
Peak memory 201128 kb
Host smart-4b08b710-d81d-49fa-8fd1-aaf4018400e7
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10578679329300526698144287538109491690795564265036573987093
5889588611281492540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.10578679329300526698144
2875381094916907955642650365739870935889588611281492540
Directory /workspace/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.90063741695506062926098630795901265069920500688241911076893224446450963881222
Short name T899
Test name
Test status
Simulation time 91600225 ps
CPU time 0.88 seconds
Started Nov 22 01:27:01 PM PST 23
Finished Nov 22 01:27:19 PM PST 23
Peak memory 195372 kb
Host smart-de5d2c36-9939-4b10-a534-489f4c49e21d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90063741695506062926098630795901265069920500688241911076893224446450963881222 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig_mubi.90063741695506062926098630795901265069920500688241911076893224446450963881222
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.80608987449965965478946236211474064902460714068823863649026696690482277321206
Short name T603
Test name
Test status
Simulation time 35743529 ps
CPU time 0.64 seconds
Started Nov 22 01:26:59 PM PST 23
Finished Nov 22 01:27:15 PM PST 23
Peak memory 197832 kb
Host smart-a3800550-315e-440d-99bf-3fbaff6987aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80608987449965965478946236211474064902460714068823863649026696690482277321206 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.80608987449965965478946236211474064902460714068823863649026696690482277321206
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_stress_all.30750176866749346140506851269024646366609078866483223168327236558141366238023
Short name T984
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.43 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:25 PM PST 23
Peak memory 201276 kb
Host smart-547aae09-fe88-4241-8943-a5496f92acd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30750176866749346140506851269024646366609078866483223168327236558141366238023 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all.30750176866749346140506851269024646366609078866483223168327236558141366238023
Directory /workspace/28.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/28.pwrmgr_stress_all_with_rand_reset.109238756867229387858371321645180378375908519510806959383564657453805144855789
Short name T105
Test name
Test status
Simulation time 4441243999 ps
CPU time 10.54 seconds
Started Nov 22 01:27:10 PM PST 23
Finished Nov 22 01:27:39 PM PST 23
Peak memory 201292 kb
Host smart-98f005d3-a868-4b84-9305-5cd9e1adce6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109238756867229387858371
321645180378375908519510806959383564657453805144855789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all_with_rand_reset.1092
38756867229387858371321645180378375908519510806959383564657453805144855789
Directory /workspace/28.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup.76898107175066411659385037200259685797971364677288436941408376211317924649893
Short name T319
Test name
Test status
Simulation time 283777259 ps
CPU time 1.22 seconds
Started Nov 22 01:27:02 PM PST 23
Finished Nov 22 01:27:20 PM PST 23
Peak memory 200032 kb
Host smart-2623fb97-6017-4797-9d5c-730794b04751
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76898107175066411659385037200259685797971364677288436941408376211317924649893 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.76898107175066411659385037200259685797971364677288436941408376211317924649893
Directory /workspace/28.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup_reset.28012352280859098296636550368011671003108338639884377804800620547728903364813
Short name T819
Test name
Test status
Simulation time 325437640 ps
CPU time 1.38 seconds
Started Nov 22 01:27:00 PM PST 23
Finished Nov 22 01:27:17 PM PST 23
Peak memory 200756 kb
Host smart-f25a0730-7849-4822-98b3-8a296e5224b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28012352280859098296636550368011671003108338639884377804800620547728903364813 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.28012352280859098296636550368011671003108338639884377804800620547728903364813
Directory /workspace/28.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.25523033156183157474487839561595924463047111231348007251665156915729365220388
Short name T941
Test name
Test status
Simulation time 51975542 ps
CPU time 0.78 seconds
Started Nov 22 01:27:15 PM PST 23
Finished Nov 22 01:27:32 PM PST 23
Peak memory 199144 kb
Host smart-5b9904a1-a73a-47c4-b0a2-7ce13af73b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25523033156183157474487839561595924463047111231348007251665156915729365220388 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.pwrmgr_aborted_low_power.25523033156183157474487839561595924463047111231348007251665156915729365220388
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.75440621045060290842225206470659149753426300647124729085755748260646755257067
Short name T723
Test name
Test status
Simulation time 72403950 ps
CPU time 0.75 seconds
Started Nov 22 01:27:17 PM PST 23
Finished Nov 22 01:27:34 PM PST 23
Peak memory 198064 kb
Host smart-8d0dcb41-e095-491e-89c8-1d70c12af545
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75440621045060290842225206470659149753426300647124729085755748260646755257067 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_disable_rom_integrity_check.754406210450602908422252064706591497534263006471247290
85755748260646755257067
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.17524323305051619464129746995719222335925820032704847279898264590337866147053
Short name T1001
Test name
Test status
Simulation time 30368572 ps
CPU time 0.64 seconds
Started Nov 22 01:27:18 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 195452 kb
Host smart-ca5d40e2-0cfd-48c8-8ebe-0ac673469873
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17524323305051619464129746995719222335925820032704847279898264590337866147053 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst_malfunc.17524323305051619464129746995719222335925820032704847279898264590337866147053
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.109957961556360214787526454069529801289255302819718070873586463824693362405310
Short name T766
Test name
Test status
Simulation time 39672069 ps
CPU time 0.61 seconds
Started Nov 22 01:27:20 PM PST 23
Finished Nov 22 01:27:36 PM PST 23
Peak memory 195504 kb
Host smart-9cd35511-444d-4395-ae5b-411f38c8c84a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109957961556360214787526454069529801289255302819718070873586463824693362405310 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.109957961556360214787526454069529801289255302819718070873586463824693362405310
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.90513374764178893201990166729130045472297381733902928872144660946519474213060
Short name T468
Test name
Test status
Simulation time 33172121 ps
CPU time 0.6 seconds
Started Nov 22 01:27:20 PM PST 23
Finished Nov 22 01:27:37 PM PST 23
Peak memory 196132 kb
Host smart-3cc87a73-2025-4236-b3ff-d01fab52b73f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90513374764178893201990166729130045472297381733902928872144660946519474213060 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.90513374764178893201990166729130045472297381733902928872144660946519474213060
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.58659806833135248296835523747832435708189929294932739195189067639058470958309
Short name T868
Test name
Test status
Simulation time 49975558 ps
CPU time 0.67 seconds
Started Nov 22 01:27:14 PM PST 23
Finished Nov 22 01:27:32 PM PST 23
Peak memory 201376 kb
Host smart-ac690839-55f2-4c41-a4d3-d19099ef6770
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58659806833135248296835523747832435708189929294932739195189067639058470958309 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_invalid.58659806833135248296835523747832435708189929294932739195189067639058470958309
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_wakeup_race.20382145417835473584042098245178715560340027128856085387387752843539757513290
Short name T9
Test name
Test status
Simulation time 296241445 ps
CPU time 1.22 seconds
Started Nov 22 01:27:02 PM PST 23
Finished Nov 22 01:27:20 PM PST 23
Peak memory 199912 kb
Host smart-c7f83930-10e8-4458-9f63-61236cb8d209
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20382145417835473584042098245178715560340027128856085387387752843539757513290 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_wakeup_race.20382145417835473584042098245178715560340027128856085387387752843539757513290
Directory /workspace/29.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.102388253172006417340133725770961383964816891598891491151965955609376412446358
Short name T857
Test name
Test status
Simulation time 119707143 ps
CPU time 0.96 seconds
Started Nov 22 01:27:09 PM PST 23
Finished Nov 22 01:27:26 PM PST 23
Peak memory 199132 kb
Host smart-224e1db8-5764-4fa9-8f54-f68b0e6eaa15
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102388253172006417340133725770961383964816891598891491151965955609376412446358 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.102388253172006417340133725770961383964816891598891491151965955609376412446358
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.94521212109258640800636250170494903327515949601074877340288285118083873266336
Short name T592
Test name
Test status
Simulation time 108189378 ps
CPU time 0.81 seconds
Started Nov 22 01:27:32 PM PST 23
Finished Nov 22 01:27:47 PM PST 23
Peak memory 209320 kb
Host smart-afc5146d-dc10-4d6f-821c-481d8dfc90bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94521212109258640800636250170494903327515949601074877340288285118083873266336 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.94521212109258640800636250170494903327515949601074877340288285118083873266336
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.77610530803641901352891924651806021059432480334796096900598563617009187422971
Short name T662
Test name
Test status
Simulation time 314830582 ps
CPU time 1.32 seconds
Started Nov 22 01:27:24 PM PST 23
Finished Nov 22 01:27:40 PM PST 23
Peak memory 199892 kb
Host smart-f0dcc2af-f037-4a24-9cd3-275802726dda
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77610530803641901352891924651806021059432480334796096900598563617009187422971 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_ctrl_config_regwen.776105308036419013528919246518060210594324803347960969005
98563617009187422971
Directory /workspace/29.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.54019690979566332191957294750283152286745723786550155166137966202419060558798
Short name T119
Test name
Test status
Simulation time 919450745 ps
CPU time 2.94 seconds
Started Nov 22 01:27:14 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 201176 kb
Host smart-8689344a-5de8-4967-be5c-40558a1d4504
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540196909795663321919572947502831522867457237865501551661379
66202419060558798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.54019690979566332191957294
750283152286745723786550155166137966202419060558798
Directory /workspace/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.70140087049694545750012902802138749085783919622302834915542851959512698269026
Short name T30
Test name
Test status
Simulation time 968503924 ps
CPU time 3 seconds
Started Nov 22 01:27:17 PM PST 23
Finished Nov 22 01:27:37 PM PST 23
Peak memory 201168 kb
Host smart-e1ce224f-9dbe-4ccc-bffc-f31e9bda1434
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70140087049694545750012902802138749085783919622302834915542
851959512698269026 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.701400870496945457500129
02802138749085783919622302834915542851959512698269026
Directory /workspace/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.12890115796056967560834016720631153291802452499525014187155078786451377954620
Short name T539
Test name
Test status
Simulation time 91600225 ps
CPU time 0.92 seconds
Started Nov 22 01:27:21 PM PST 23
Finished Nov 22 01:27:38 PM PST 23
Peak memory 195412 kb
Host smart-a1a3a64d-8bd7-44aa-b63b-cd77630fc0d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12890115796056967560834016720631153291802452499525014187155078786451377954620 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig_mubi.12890115796056967560834016720631153291802452499525014187155078786451377954620
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.1521189421285065000789586930104741459810560409198797122975308134128839307108
Short name T869
Test name
Test status
Simulation time 35743529 ps
CPU time 0.62 seconds
Started Nov 22 01:27:08 PM PST 23
Finished Nov 22 01:27:25 PM PST 23
Peak memory 197700 kb
Host smart-0bb94690-68b3-437d-a9d3-9037144fdfb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521189421285065000789586930104741459810560409198797122975308134128839307108 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.1521189421285065000789586930104741459810560409198797122975308134128839307108
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_stress_all.13894829603416669460537390287219324043615673180916075115297402449052056976890
Short name T1029
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.6 seconds
Started Nov 22 01:27:13 PM PST 23
Finished Nov 22 01:27:36 PM PST 23
Peak memory 201264 kb
Host smart-4dd3b97c-dd15-40f0-b793-8737b5e22f1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13894829603416669460537390287219324043615673180916075115297402449052056976890 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.13894829603416669460537390287219324043615673180916075115297402449052056976890
Directory /workspace/29.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/29.pwrmgr_stress_all_with_rand_reset.54349026908973162580275995049305548590184535948669015014971936670562543694519
Short name T106
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.47 seconds
Started Nov 22 01:27:15 PM PST 23
Finished Nov 22 01:27:43 PM PST 23
Peak memory 201432 kb
Host smart-cf4b24ac-61d1-42b2-9b16-5042bd7022df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543490269089731625802759
95049305548590184535948669015014971936670562543694519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all_with_rand_reset.54349
026908973162580275995049305548590184535948669015014971936670562543694519
Directory /workspace/29.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup.77740052518652908196332817653415556226803718750740455501169446117421854797623
Short name T102
Test name
Test status
Simulation time 283777259 ps
CPU time 1.18 seconds
Started Nov 22 01:27:12 PM PST 23
Finished Nov 22 01:27:32 PM PST 23
Peak memory 200028 kb
Host smart-281d6fca-cd6c-400f-aec8-75a162d481f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77740052518652908196332817653415556226803718750740455501169446117421854797623 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.77740052518652908196332817653415556226803718750740455501169446117421854797623
Directory /workspace/29.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup_reset.9150724704295955399828993114428066465459618149027846016275755374259402177754
Short name T601
Test name
Test status
Simulation time 325437640 ps
CPU time 1.38 seconds
Started Nov 22 01:27:13 PM PST 23
Finished Nov 22 01:27:32 PM PST 23
Peak memory 200696 kb
Host smart-76d002e8-7d3a-401c-8717-5ebf66dd9de3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9150724704295955399828993114428066465459618149027846016275755374259402177754 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.9150724704295955399828993114428066465459618149027846016275755374259402177754
Directory /workspace/29.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.30635739234125168291066528309413316077980008313135781395600065739743606712091
Short name T130
Test name
Test status
Simulation time 51975542 ps
CPU time 0.74 seconds
Started Nov 22 01:27:08 PM PST 23
Finished Nov 22 01:27:24 PM PST 23
Peak memory 198740 kb
Host smart-30393304-4e57-4768-90ad-761b14344326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30635739234125168291066528309413316077980008313135781395600065739743606712091 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.pwrmgr_aborted_low_power.30635739234125168291066528309413316077980008313135781395600065739743606712091
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.37145133684100435355581343005696514935158613233924205389697895284895573572322
Short name T797
Test name
Test status
Simulation time 72403950 ps
CPU time 0.76 seconds
Started Nov 22 01:26:05 PM PST 23
Finished Nov 22 01:26:11 PM PST 23
Peak memory 198136 kb
Host smart-dc7f6cfb-4e07-4112-b8e6-9885ae9a071f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37145133684100435355581343005696514935158613233924205389697895284895573572322 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disable_rom_integrity_check.3714513368410043535558134300569651493515861323392420538
9697895284895573572322
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.16691238810913547324102148136821967522466082339355407105352400158637715809405
Short name T394
Test name
Test status
Simulation time 30368572 ps
CPU time 0.61 seconds
Started Nov 22 01:26:27 PM PST 23
Finished Nov 22 01:26:31 PM PST 23
Peak memory 195464 kb
Host smart-2e9995c7-012a-4200-97b6-f82a4e4d31f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16691238810913547324102148136821967522466082339355407105352400158637715809405 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_malfunc.16691238810913547324102148136821967522466082339355407105352400158637715809405
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.33897694218880963830925707539611315742311182510025904687490125924494698780288
Short name T625
Test name
Test status
Simulation time 39672069 ps
CPU time 0.6 seconds
Started Nov 22 01:25:48 PM PST 23
Finished Nov 22 01:25:53 PM PST 23
Peak memory 195520 kb
Host smart-524830cb-9e5d-4a0e-940d-659032c1ff7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33897694218880963830925707539611315742311182510025904687490125924494698780288 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.33897694218880963830925707539611315742311182510025904687490125924494698780288
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.39759366122688543131516287754399699211750303082637869300510652334896348233685
Short name T823
Test name
Test status
Simulation time 33172121 ps
CPU time 0.6 seconds
Started Nov 22 01:25:49 PM PST 23
Finished Nov 22 01:25:53 PM PST 23
Peak memory 196836 kb
Host smart-262d26e5-ba9c-4992-83f4-bd44dbe07c97
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39759366122688543131516287754399699211750303082637869300510652334896348233685 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.39759366122688543131516287754399699211750303082637869300510652334896348233685
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.9215419865110129599017162745983118670063294480977129503036043867942605431269
Short name T980
Test name
Test status
Simulation time 49975558 ps
CPU time 0.67 seconds
Started Nov 22 01:25:52 PM PST 23
Finished Nov 22 01:25:59 PM PST 23
Peak memory 201336 kb
Host smart-49aadc1e-0825-4450-92af-460f87d24772
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9215419865110129599017162745983118670063294480977129503036043867942605431269 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invalid.9215419865110129599017162745983118670063294480977129503036043867942605431269
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_wakeup_race.45247798945946648903762399628094154328283854939391703092479808531214144359469
Short name T955
Test name
Test status
Simulation time 296241445 ps
CPU time 1.21 seconds
Started Nov 22 01:26:26 PM PST 23
Finished Nov 22 01:26:31 PM PST 23
Peak memory 200036 kb
Host smart-2a7dd267-df24-44d8-a025-0311172dc5a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45247798945946648903762399628094154328283854939391703092479808531214144359469 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wakeup_race.45247798945946648903762399628094154328283854939391703092479808531214144359469
Directory /workspace/3.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.66408966081043995705818862644702168137589839290675577235718786671340916020879
Short name T363
Test name
Test status
Simulation time 119707143 ps
CPU time 1.13 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 196840 kb
Host smart-a25aa028-08c5-41d4-909e-fff5c6ea4bc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66408966081043995705818862644702168137589839290675577235718786671340916020879 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.66408966081043995705818862644702168137589839290675577235718786671340916020879
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.30842831647652088519783029260859853424670548050192112172885164060523885330397
Short name T645
Test name
Test status
Simulation time 108189378 ps
CPU time 0.86 seconds
Started Nov 22 01:26:05 PM PST 23
Finished Nov 22 01:26:11 PM PST 23
Peak memory 209552 kb
Host smart-24bc7feb-978e-4842-976c-c96ea7d584de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30842831647652088519783029260859853424670548050192112172885164060523885330397 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.30842831647652088519783029260859853424670548050192112172885164060523885330397
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.110193769445871678156422669677324385416325970306643830211900487157988035211626
Short name T20
Test name
Test status
Simulation time 344080348 ps
CPU time 1.27 seconds
Started Nov 22 01:26:02 PM PST 23
Finished Nov 22 01:26:09 PM PST 23
Peak memory 214452 kb
Host smart-e665f1c3-1e4f-40a6-8cbe-09800c737cec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110193769445871678156422669677324385416325970306643830211900487157988035211626 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.110193769445871678156422669677324385416325970306643830211900487157988035211626
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.78447814266118675670521268514898616953128691789110137733979501841958572571675
Short name T866
Test name
Test status
Simulation time 314830582 ps
CPU time 1.3 seconds
Started Nov 22 01:25:50 PM PST 23
Finished Nov 22 01:25:55 PM PST 23
Peak memory 199936 kb
Host smart-beb35e72-0fa5-4f61-a84f-0b75672f322c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78447814266118675670521268514898616953128691789110137733979501841958572571675 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_ctrl_config_regwen.7844781426611867567052126851489861695312869178911013773397
9501841958572571675
Directory /workspace/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.108946656570629678936700072319617544268886949484983482267837678653284840135404
Short name T820
Test name
Test status
Simulation time 919450745 ps
CPU time 2.93 seconds
Started Nov 22 01:26:29 PM PST 23
Finished Nov 22 01:26:35 PM PST 23
Peak memory 201264 kb
Host smart-5b6f7521-0168-4d3c-aa22-bcf0305d99fe
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108946656570629678936700072319617544268886949484983482267837
678653284840135404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.10894665657062967893670007
2319617544268886949484983482267837678653284840135404
Directory /workspace/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.67362110067359299598578479590776155374655077620550071095230531717079923258994
Short name T765
Test name
Test status
Simulation time 968503924 ps
CPU time 2.98 seconds
Started Nov 22 01:26:28 PM PST 23
Finished Nov 22 01:26:34 PM PST 23
Peak memory 201212 kb
Host smart-0e04ff03-6033-459a-9521-2a5a6c1ef60e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67362110067359299598578479590776155374655077620550071095230
531717079923258994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.6736211006735929959857847
9590776155374655077620550071095230531717079923258994
Directory /workspace/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.17808915895885131833252585841325362876807398127524634205979836235599397128382
Short name T973
Test name
Test status
Simulation time 91600225 ps
CPU time 0.97 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 193068 kb
Host smart-2c06c64d-6639-4d7d-898d-2d178b0e27a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17808915895885131833252585841325362876807398127524634205979836235599397128382 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_mubi.17808915895885131833252585841325362876807398127524634205979836235599397128382
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.75098118062937650792957154963659532435966291059289888245676971493806965796162
Short name T880
Test name
Test status
Simulation time 35743529 ps
CPU time 0.78 seconds
Started Nov 22 01:27:18 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 194988 kb
Host smart-b813a9f3-bae1-4f4f-bcd4-c95a8b06e2ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75098118062937650792957154963659532435966291059289888245676971493806965796162 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.75098118062937650792957154963659532435966291059289888245676971493806965796162
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_stress_all.98858308344257253920853808967517832009773125250285214115273300359526690676856
Short name T361
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.69 seconds
Started Nov 22 01:26:05 PM PST 23
Finished Nov 22 01:26:17 PM PST 23
Peak memory 201284 kb
Host smart-a61cf9c4-f8c3-456f-b4b8-f56f6da266ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98858308344257253920853808967517832009773125250285214115273300359526690676856 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all.98858308344257253920853808967517832009773125250285214115273300359526690676856
Directory /workspace/3.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/3.pwrmgr_stress_all_with_rand_reset.49217836576494012445844891157875483064631124278594046666800579662086597803118
Short name T785
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.59 seconds
Started Nov 22 01:26:03 PM PST 23
Finished Nov 22 01:26:19 PM PST 23
Peak memory 201540 kb
Host smart-dc15e949-e09d-40ff-a9db-3bb57b807237
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492178365764940124458448
91157875483064631124278594046666800579662086597803118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all_with_rand_reset.492178
36576494012445844891157875483064631124278594046666800579662086597803118
Directory /workspace/3.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup.14825244777181156264828904916154988956166053192303660104171453395686965142829
Short name T157
Test name
Test status
Simulation time 283777259 ps
CPU time 1.2 seconds
Started Nov 22 01:26:59 PM PST 23
Finished Nov 22 01:27:17 PM PST 23
Peak memory 197956 kb
Host smart-beb30178-ff8f-40be-9a60-5ae5e420e070
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14825244777181156264828904916154988956166053192303660104171453395686965142829 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.14825244777181156264828904916154988956166053192303660104171453395686965142829
Directory /workspace/3.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup_reset.105474404743976476537232902523158849608174903146689846353222398431456209764678
Short name T369
Test name
Test status
Simulation time 325437640 ps
CPU time 1.39 seconds
Started Nov 22 01:26:25 PM PST 23
Finished Nov 22 01:26:28 PM PST 23
Peak memory 200700 kb
Host smart-72215f8f-a594-4dd5-892e-1c4ca92d47b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105474404743976476537232902523158849608174903146689846353222398431456209764678 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.105474404743976476537232902523158849608174903146689846353222398431456209764678
Directory /workspace/3.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.83357316596856220667661193093994329478651731779887715313704271966072237007946
Short name T175
Test name
Test status
Simulation time 51975542 ps
CPU time 0.8 seconds
Started Nov 22 01:27:16 PM PST 23
Finished Nov 22 01:27:34 PM PST 23
Peak memory 199040 kb
Host smart-0b3ee510-2278-46a8-9651-6b227c40d2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83357316596856220667661193093994329478651731779887715313704271966072237007946 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.pwrmgr_aborted_low_power.83357316596856220667661193093994329478651731779887715313704271966072237007946
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.52825781017168988490344164089467325085601815893505548558902467637340183256759
Short name T1033
Test name
Test status
Simulation time 72403950 ps
CPU time 0.76 seconds
Started Nov 22 01:27:22 PM PST 23
Finished Nov 22 01:27:38 PM PST 23
Peak memory 198080 kb
Host smart-fd197495-51d9-4440-84bf-31477edbe829
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52825781017168988490344164089467325085601815893505548558902467637340183256759 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disable_rom_integrity_check.528257810171689884903441640894673250856018158935055485
58902467637340183256759
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.28484572835107493338870449968149530395239954347478847071240548882965449313499
Short name T544
Test name
Test status
Simulation time 30368572 ps
CPU time 0.58 seconds
Started Nov 22 01:27:24 PM PST 23
Finished Nov 22 01:27:39 PM PST 23
Peak memory 195456 kb
Host smart-c8d66089-6740-4959-83bf-64382ee16da8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28484572835107493338870449968149530395239954347478847071240548882965449313499 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst_malfunc.28484572835107493338870449968149530395239954347478847071240548882965449313499
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.13386049787749838935932741064857868142945415106236626195143048347012144790001
Short name T370
Test name
Test status
Simulation time 39672069 ps
CPU time 0.61 seconds
Started Nov 22 01:27:17 PM PST 23
Finished Nov 22 01:27:34 PM PST 23
Peak memory 195408 kb
Host smart-0b437faf-f392-4772-8cb8-39827209068f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13386049787749838935932741064857868142945415106236626195143048347012144790001 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.13386049787749838935932741064857868142945415106236626195143048347012144790001
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.52639808121738235238539196909384945441445062002616696752325776569296551990461
Short name T300
Test name
Test status
Simulation time 33172121 ps
CPU time 0.57 seconds
Started Nov 22 01:27:17 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 196880 kb
Host smart-4eb13320-ccdd-4ea7-b2dc-07bbc4c8c490
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52639808121738235238539196909384945441445062002616696752325776569296551990461 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.52639808121738235238539196909384945441445062002616696752325776569296551990461
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.74802072804136808995058649046421121526284241772322241511250402011024742205413
Short name T291
Test name
Test status
Simulation time 49975558 ps
CPU time 0.67 seconds
Started Nov 22 01:27:14 PM PST 23
Finished Nov 22 01:27:32 PM PST 23
Peak memory 201404 kb
Host smart-273a4232-c24f-495f-9e0f-ca7968715856
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74802072804136808995058649046421121526284241772322241511250402011024742205413 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_invalid.74802072804136808995058649046421121526284241772322241511250402011024742205413
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_wakeup_race.86716680525692593089473638061331388504683934631448376105513426644516290427784
Short name T123
Test name
Test status
Simulation time 296241445 ps
CPU time 1.19 seconds
Started Nov 22 01:27:22 PM PST 23
Finished Nov 22 01:27:39 PM PST 23
Peak memory 199924 kb
Host smart-3f90501d-d68a-4d1c-a3b4-e58f089e64c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86716680525692593089473638061331388504683934631448376105513426644516290427784 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_wakeup_race.86716680525692593089473638061331388504683934631448376105513426644516290427784
Directory /workspace/30.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.64947742676812699374185550301037505690098273738145034596349109860279968940613
Short name T964
Test name
Test status
Simulation time 119707143 ps
CPU time 1.02 seconds
Started Nov 22 01:27:15 PM PST 23
Finished Nov 22 01:27:33 PM PST 23
Peak memory 199328 kb
Host smart-e5a1afbb-5bdb-4c77-ae3b-f8dfd7d49618
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64947742676812699374185550301037505690098273738145034596349109860279968940613 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.64947742676812699374185550301037505690098273738145034596349109860279968940613
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.54481212652191870969857751388557821713591557393710035604947592226522727540964
Short name T476
Test name
Test status
Simulation time 108189378 ps
CPU time 0.85 seconds
Started Nov 22 01:27:15 PM PST 23
Finished Nov 22 01:27:33 PM PST 23
Peak memory 209440 kb
Host smart-5b5bd750-b2d3-4221-b5f2-3ba814a513cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54481212652191870969857751388557821713591557393710035604947592226522727540964 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.54481212652191870969857751388557821713591557393710035604947592226522727540964
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.105724751618463497597858352578644268604212351161832133241316319436582395422313
Short name T847
Test name
Test status
Simulation time 314830582 ps
CPU time 1.3 seconds
Started Nov 22 01:27:19 PM PST 23
Finished Nov 22 01:27:36 PM PST 23
Peak memory 199908 kb
Host smart-6ff9d444-1532-46d1-8b99-163788caedda
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105724751618463497597858352578644268604212351161832133241316319436582395422313 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_ctrl_config_regwen.10572475161846349759785835257864426860421235116183213324
1316319436582395422313
Directory /workspace/30.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.83383817753869417391652768745494345115989552808523820492184314322206712933605
Short name T783
Test name
Test status
Simulation time 919450745 ps
CPU time 3.03 seconds
Started Nov 22 01:27:20 PM PST 23
Finished Nov 22 01:27:40 PM PST 23
Peak memory 201120 kb
Host smart-68b6ef27-068c-41ff-a9c8-5457912b6d17
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833838177538694173916527687454943451159895528085238204921843
14322206712933605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.83383817753869417391652768
745494345115989552808523820492184314322206712933605
Directory /workspace/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.55563756348368581896420837870443599170406337315873408762011530568410771519106
Short name T29
Test name
Test status
Simulation time 968503924 ps
CPU time 3.19 seconds
Started Nov 22 01:27:15 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 201124 kb
Host smart-28dcf28b-49f6-44a9-947a-847b3e54f8d8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55563756348368581896420837870443599170406337315873408762011
530568410771519106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.555637563483685818964208
37870443599170406337315873408762011530568410771519106
Directory /workspace/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.102642356384441643767315866972252542157475321389202321813801206884259024185568
Short name T513
Test name
Test status
Simulation time 91600225 ps
CPU time 0.88 seconds
Started Nov 22 01:27:20 PM PST 23
Finished Nov 22 01:27:37 PM PST 23
Peak memory 195436 kb
Host smart-a68c0823-e6c7-4875-bfed-6743326270d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102642356384441643767315866972252542157475321389202321813801206884259024185568 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig_mubi.102642356384441643767315866972252542157475321389202321813801206884259024185568
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.47555284034403301050085440124081049234970809042110638674098317298554458360381
Short name T366
Test name
Test status
Simulation time 35743529 ps
CPU time 0.61 seconds
Started Nov 22 01:27:05 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 197836 kb
Host smart-fca6ac4b-02cc-43a3-879f-e6c0257523d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47555284034403301050085440124081049234970809042110638674098317298554458360381 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.47555284034403301050085440124081049234970809042110638674098317298554458360381
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_stress_all.54696088527055143084815165091851994829547319229116966597502902662869852818064
Short name T572
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.49 seconds
Started Nov 22 01:27:13 PM PST 23
Finished Nov 22 01:27:37 PM PST 23
Peak memory 201276 kb
Host smart-e06a02cc-f1ae-4a28-9259-fb00d9226f54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54696088527055143084815165091851994829547319229116966597502902662869852818064 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all.54696088527055143084815165091851994829547319229116966597502902662869852818064
Directory /workspace/30.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/30.pwrmgr_stress_all_with_rand_reset.42838714068795781407200084642145345398669890516009694024637838483630494697055
Short name T330
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.8 seconds
Started Nov 22 01:27:17 PM PST 23
Finished Nov 22 01:27:45 PM PST 23
Peak memory 201472 kb
Host smart-c7014361-fc23-4c70-ac10-295c857e4255
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428387140687957814072000
84642145345398669890516009694024637838483630494697055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all_with_rand_reset.42838
714068795781407200084642145345398669890516009694024637838483630494697055
Directory /workspace/30.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup.12546891009100328724695908924423960867385833468018384663973773859698905288614
Short name T487
Test name
Test status
Simulation time 283777259 ps
CPU time 1.2 seconds
Started Nov 22 01:27:16 PM PST 23
Finished Nov 22 01:27:34 PM PST 23
Peak memory 199968 kb
Host smart-ae26aac5-7132-4fd2-9bfe-a89f4ee90ea8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12546891009100328724695908924423960867385833468018384663973773859698905288614 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup.12546891009100328724695908924423960867385833468018384663973773859698905288614
Directory /workspace/30.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup_reset.101025677229226674271960947723179857437953435557485825835235181702485326572748
Short name T117
Test name
Test status
Simulation time 325437640 ps
CPU time 1.36 seconds
Started Nov 22 01:27:24 PM PST 23
Finished Nov 22 01:27:40 PM PST 23
Peak memory 200764 kb
Host smart-2c6cf335-9eaa-4e23-a5f9-f4f7b8bec759
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101025677229226674271960947723179857437953435557485825835235181702485326572748 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.101025677229226674271960947723179857437953435557485825835235181702485326572748
Directory /workspace/30.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.48535062738801678240049890178636532062209591218320398679923721940174167705998
Short name T441
Test name
Test status
Simulation time 51975542 ps
CPU time 0.79 seconds
Started Nov 22 01:27:16 PM PST 23
Finished Nov 22 01:27:34 PM PST 23
Peak memory 199164 kb
Host smart-c287c3ac-da88-4bf9-b3fc-8640b233f2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48535062738801678240049890178636532062209591218320398679923721940174167705998 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 31.pwrmgr_aborted_low_power.48535062738801678240049890178636532062209591218320398679923721940174167705998
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.36500328074385205527932572199467648613718953840151472237132387511890837304099
Short name T600
Test name
Test status
Simulation time 72403950 ps
CPU time 0.82 seconds
Started Nov 22 01:27:13 PM PST 23
Finished Nov 22 01:27:32 PM PST 23
Peak memory 198148 kb
Host smart-3e3b3ef9-a950-466f-a053-fa9cd7166a0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36500328074385205527932572199467648613718953840151472237132387511890837304099 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_disable_rom_integrity_check.365003280743852055279325721994676486137189538401514722
37132387511890837304099
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.51757993625647262465621619832603147813870084378945889630151327206715625519360
Short name T956
Test name
Test status
Simulation time 30368572 ps
CPU time 0.63 seconds
Started Nov 22 01:27:12 PM PST 23
Finished Nov 22 01:27:31 PM PST 23
Peak memory 195440 kb
Host smart-c29ed51e-84f1-4fe5-96ca-de5304e908c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51757993625647262465621619832603147813870084378945889630151327206715625519360 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst_malfunc.51757993625647262465621619832603147813870084378945889630151327206715625519360
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.22759592585306444447541271617880935626073708277919164183897492969991792755197
Short name T569
Test name
Test status
Simulation time 39672069 ps
CPU time 0.62 seconds
Started Nov 22 01:27:16 PM PST 23
Finished Nov 22 01:27:34 PM PST 23
Peak memory 195472 kb
Host smart-7b1589fc-2c3d-4146-9384-cda417b1a4a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22759592585306444447541271617880935626073708277919164183897492969991792755197 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.22759592585306444447541271617880935626073708277919164183897492969991792755197
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.2425992119892538499513837495962460213774033360162242282179168034069571974489
Short name T386
Test name
Test status
Simulation time 33172121 ps
CPU time 0.59 seconds
Started Nov 22 01:27:20 PM PST 23
Finished Nov 22 01:27:37 PM PST 23
Peak memory 196664 kb
Host smart-bc8437f6-dfb0-4a5a-b6d9-427b0a572a83
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425992119892538499513837495962460213774033360162242282179168034069571974489 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.2425992119892538499513837495962460213774033360162242282179168034069571974489
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.112512428724124330838994414185715659646666063132409405874812469328250317737700
Short name T454
Test name
Test status
Simulation time 49975558 ps
CPU time 0.68 seconds
Started Nov 22 01:27:03 PM PST 23
Finished Nov 22 01:27:20 PM PST 23
Peak memory 201216 kb
Host smart-c7c92d40-7659-4d89-9bbd-e4ad48716643
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112512428724124330838994414185715659646666063132409405874812469328250317737700 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_invalid.112512428724124330838994414185715659646666063132409405874812469328250317737700
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_wakeup_race.105591402680714655095881513894794702617420186914974215704615187365455349165862
Short name T6
Test name
Test status
Simulation time 296241445 ps
CPU time 1.27 seconds
Started Nov 22 01:27:17 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 200116 kb
Host smart-e4eb5321-2cc8-4fec-b6cc-0e2f06562589
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105591402680714655095881513894794702617420186914974215704615187365455349165862 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_wakeup_race.105591402680714655095881513894794702617420186914974215704615187365455349165862
Directory /workspace/31.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.33123511024147952081600285930094532331104275796914320617365178235434418424544
Short name T1054
Test name
Test status
Simulation time 119707143 ps
CPU time 1.02 seconds
Started Nov 22 01:27:15 PM PST 23
Finished Nov 22 01:27:33 PM PST 23
Peak memory 199280 kb
Host smart-99dcddbd-9ac5-43b6-9f3b-ebd2be249d7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33123511024147952081600285930094532331104275796914320617365178235434418424544 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.33123511024147952081600285930094532331104275796914320617365178235434418424544
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.22546200763322953196084101066002455480352447350358208617692732519215855913162
Short name T972
Test name
Test status
Simulation time 108189378 ps
CPU time 0.83 seconds
Started Nov 22 01:27:19 PM PST 23
Finished Nov 22 01:27:36 PM PST 23
Peak memory 209544 kb
Host smart-c36c5663-5742-49c2-acac-5c77697c516e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22546200763322953196084101066002455480352447350358208617692732519215855913162 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.22546200763322953196084101066002455480352447350358208617692732519215855913162
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.42707248093527500523698717754533233274297838852784870021017923642215152653020
Short name T518
Test name
Test status
Simulation time 314830582 ps
CPU time 1.38 seconds
Started Nov 22 01:27:17 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 199740 kb
Host smart-899dd02f-01cd-4da1-bd64-7807707ab759
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42707248093527500523698717754533233274297838852784870021017923642215152653020 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_ctrl_config_regwen.427072480935275005236987177545332332742978388527848700210
17923642215152653020
Directory /workspace/31.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.66619562027499291034143515246331002986656048441291990962383403016729646844769
Short name T591
Test name
Test status
Simulation time 919450745 ps
CPU time 2.91 seconds
Started Nov 22 01:27:15 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 201240 kb
Host smart-3e161b73-1a01-4954-860a-c5a3401120e6
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666195620274992910341435152463310029866560484412919909623834
03016729646844769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.66619562027499291034143515
246331002986656048441291990962383403016729646844769
Directory /workspace/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.8289279799072161188377121494405456139349497846562886684600017270638578013187
Short name T373
Test name
Test status
Simulation time 968503924 ps
CPU time 3.19 seconds
Started Nov 22 01:27:17 PM PST 23
Finished Nov 22 01:27:37 PM PST 23
Peak memory 201156 kb
Host smart-b5d325e2-3a68-4824-9b70-6d47749e0fd3
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82892797990721611883771214944054561393494978465628866846000
17270638578013187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.8289279799072161188377121
494405456139349497846562886684600017270638578013187
Directory /workspace/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.76533488473730126913947336483707857374080336496090504088824974959217670323010
Short name T411
Test name
Test status
Simulation time 91600225 ps
CPU time 0.93 seconds
Started Nov 22 01:27:20 PM PST 23
Finished Nov 22 01:27:37 PM PST 23
Peak memory 195412 kb
Host smart-f5bddaa2-b316-4c1b-a0af-20f338f3eb72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76533488473730126913947336483707857374080336496090504088824974959217670323010 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig_mubi.76533488473730126913947336483707857374080336496090504088824974959217670323010
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.91258493226880400849949677526314401733397922040964414691525769983461894139162
Short name T1018
Test name
Test status
Simulation time 35743529 ps
CPU time 0.67 seconds
Started Nov 22 01:27:36 PM PST 23
Finished Nov 22 01:27:49 PM PST 23
Peak memory 197812 kb
Host smart-a8cb2ef1-7981-4338-9553-c6884bc5b403
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91258493226880400849949677526314401733397922040964414691525769983461894139162 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.91258493226880400849949677526314401733397922040964414691525769983461894139162
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_stress_all.67852320827342636666428318797968868817503305955805969110216072436092753139315
Short name T358
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.78 seconds
Started Nov 22 01:27:18 PM PST 23
Finished Nov 22 01:27:40 PM PST 23
Peak memory 201292 kb
Host smart-1d2b83f7-d552-49da-b16c-e00a919af902
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67852320827342636666428318797968868817503305955805969110216072436092753139315 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.67852320827342636666428318797968868817503305955805969110216072436092753139315
Directory /workspace/31.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/31.pwrmgr_stress_all_with_rand_reset.78226879308222760893809573468738168891819349879435994731233616400450182269928
Short name T950
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.3 seconds
Started Nov 22 01:27:27 PM PST 23
Finished Nov 22 01:27:52 PM PST 23
Peak memory 201460 kb
Host smart-95eaeb71-72c7-4a0d-9646-2ac594663264
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782268793082227608938095
73468738168891819349879435994731233616400450182269928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all_with_rand_reset.78226
879308222760893809573468738168891819349879435994731233616400450182269928
Directory /workspace/31.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup.82073862354631163805713914011781648958337145467052457412183491893107725888584
Short name T743
Test name
Test status
Simulation time 283777259 ps
CPU time 1.19 seconds
Started Nov 22 01:27:14 PM PST 23
Finished Nov 22 01:27:33 PM PST 23
Peak memory 200020 kb
Host smart-727afc27-9a3d-4599-9566-0882278fe747
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82073862354631163805713914011781648958337145467052457412183491893107725888584 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.82073862354631163805713914011781648958337145467052457412183491893107725888584
Directory /workspace/31.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup_reset.110360702278243351059676516425872127992052064969070287907783301650504099390650
Short name T809
Test name
Test status
Simulation time 325437640 ps
CPU time 1.31 seconds
Started Nov 22 01:27:17 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 200724 kb
Host smart-b4b1d0a2-d391-4314-b82b-acdc99625357
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110360702278243351059676516425872127992052064969070287907783301650504099390650 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.110360702278243351059676516425872127992052064969070287907783301650504099390650
Directory /workspace/31.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.100543274739616814988805269893505704533615942727633474636573627695288592544788
Short name T727
Test name
Test status
Simulation time 51975542 ps
CPU time 0.81 seconds
Started Nov 22 01:27:19 PM PST 23
Finished Nov 22 01:27:36 PM PST 23
Peak memory 199168 kb
Host smart-099b1834-ccf6-4f24-9a58-382784cff254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100543274739616814988805269893505704533615942727633474636573627695288592544788 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.pwrmgr_aborted_low_power.100543274739616814988805269893505704533615942727633474636573627695288592544788
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.65158296742019362439422630302421415588148690417594524089281547250885494040328
Short name T933
Test name
Test status
Simulation time 72403950 ps
CPU time 0.79 seconds
Started Nov 22 01:27:30 PM PST 23
Finished Nov 22 01:27:44 PM PST 23
Peak memory 198104 kb
Host smart-08648e39-6b72-49d9-b383-c15a873d740c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65158296742019362439422630302421415588148690417594524089281547250885494040328 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_disable_rom_integrity_check.651582967420193624394226303024214155881486904175945240
89281547250885494040328
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.73956732664301979061168595750765274208576380799469661193095543911625390868763
Short name T540
Test name
Test status
Simulation time 30368572 ps
CPU time 0.6 seconds
Started Nov 22 01:27:14 PM PST 23
Finished Nov 22 01:27:32 PM PST 23
Peak memory 195380 kb
Host smart-ed71701b-bb25-4a37-a2c2-42fe3e6d2cc9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73956732664301979061168595750765274208576380799469661193095543911625390868763 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst_malfunc.73956732664301979061168595750765274208576380799469661193095543911625390868763
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.76962292322757700522845064763765631112983292904130961712311558730314114691854
Short name T504
Test name
Test status
Simulation time 39672069 ps
CPU time 0.6 seconds
Started Nov 22 01:27:19 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 195500 kb
Host smart-600d34d1-f4ac-456d-9589-00d7a5bdff9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76962292322757700522845064763765631112983292904130961712311558730314114691854 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.76962292322757700522845064763765631112983292904130961712311558730314114691854
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.85061818667287394359799332920859899668180141981374982954426137812782965608919
Short name T376
Test name
Test status
Simulation time 33172121 ps
CPU time 0.6 seconds
Started Nov 22 01:27:11 PM PST 23
Finished Nov 22 01:27:30 PM PST 23
Peak memory 196836 kb
Host smart-54d6c0d9-d87f-45df-814d-997aeaea85e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85061818667287394359799332920859899668180141981374982954426137812782965608919 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.85061818667287394359799332920859899668180141981374982954426137812782965608919
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.98646780979783342475431121291339099697984784687362949835404367685621775567212
Short name T597
Test name
Test status
Simulation time 49975558 ps
CPU time 0.72 seconds
Started Nov 22 01:27:58 PM PST 23
Finished Nov 22 01:28:05 PM PST 23
Peak memory 201304 kb
Host smart-6dce0150-72e5-4259-a304-b471a575ed51
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98646780979783342475431121291339099697984784687362949835404367685621775567212 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_invalid.98646780979783342475431121291339099697984784687362949835404367685621775567212
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_wakeup_race.13863048768399643772374616118290532287558607893290739555081658426370766857305
Short name T840
Test name
Test status
Simulation time 296241445 ps
CPU time 1.21 seconds
Started Nov 22 01:27:11 PM PST 23
Finished Nov 22 01:27:31 PM PST 23
Peak memory 200048 kb
Host smart-f28ccefb-d6df-4797-9f4b-46848de1c68a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13863048768399643772374616118290532287558607893290739555081658426370766857305 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_wakeup_race.13863048768399643772374616118290532287558607893290739555081658426370766857305
Directory /workspace/32.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.57240518321755763149475769923112685487521093800811706842639264146502882517435
Short name T1058
Test name
Test status
Simulation time 119707143 ps
CPU time 1.11 seconds
Started Nov 22 01:27:19 PM PST 23
Finished Nov 22 01:27:36 PM PST 23
Peak memory 199264 kb
Host smart-31899564-12f7-4ded-8441-9d7687374118
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57240518321755763149475769923112685487521093800811706842639264146502882517435 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.57240518321755763149475769923112685487521093800811706842639264146502882517435
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.58440022602997313790678801323173300164741984968463001096117100844870668532319
Short name T4
Test name
Test status
Simulation time 108189378 ps
CPU time 0.82 seconds
Started Nov 22 01:27:20 PM PST 23
Finished Nov 22 01:27:37 PM PST 23
Peak memory 208892 kb
Host smart-19ea3637-d8d3-48c0-a922-248eb9b1b011
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58440022602997313790678801323173300164741984968463001096117100844870668532319 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.58440022602997313790678801323173300164741984968463001096117100844870668532319
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.102880866312594890427103560717849467319769381379481336730985623824290177055912
Short name T887
Test name
Test status
Simulation time 314830582 ps
CPU time 1.33 seconds
Started Nov 22 01:27:17 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 199912 kb
Host smart-a0eb4259-0a33-4e01-9f72-ae00cd92d5c2
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102880866312594890427103560717849467319769381379481336730985623824290177055912 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_ctrl_config_regwen.10288086631259489042710356071784946731976938137948133673
0985623824290177055912
Directory /workspace/32.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.108355805451582725196963170317107349538327197176496150079588123420246590510362
Short name T1045
Test name
Test status
Simulation time 919450745 ps
CPU time 2.87 seconds
Started Nov 22 01:27:30 PM PST 23
Finished Nov 22 01:27:46 PM PST 23
Peak memory 200988 kb
Host smart-f6636448-59c6-4d8f-b7bf-e8b5f3337737
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108355805451582725196963170317107349538327197176496150079588
123420246590510362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1083558054515827251969631
70317107349538327197176496150079588123420246590510362
Directory /workspace/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.48189125144690973671976902511194112199126879062640762963630672155135262252712
Short name T1043
Test name
Test status
Simulation time 968503924 ps
CPU time 3.11 seconds
Started Nov 22 01:27:23 PM PST 23
Finished Nov 22 01:27:42 PM PST 23
Peak memory 201180 kb
Host smart-7cac9749-0597-47f2-b76b-dbc06cde8be1
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48189125144690973671976902511194112199126879062640762963630
672155135262252712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.481891251446909736719769
02511194112199126879062640762963630672155135262252712
Directory /workspace/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.26863199930320703228812950363447027893871357721651189645254116181638132595097
Short name T535
Test name
Test status
Simulation time 91600225 ps
CPU time 0.88 seconds
Started Nov 22 01:27:22 PM PST 23
Finished Nov 22 01:27:38 PM PST 23
Peak memory 195372 kb
Host smart-d60a1e00-4de9-4973-a656-302a71945066
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26863199930320703228812950363447027893871357721651189645254116181638132595097 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig_mubi.26863199930320703228812950363447027893871357721651189645254116181638132595097
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.23725207951098821133202918262878484076273000070945975565407790391523518427273
Short name T525
Test name
Test status
Simulation time 35743529 ps
CPU time 0.65 seconds
Started Nov 22 01:27:12 PM PST 23
Finished Nov 22 01:27:31 PM PST 23
Peak memory 197808 kb
Host smart-18116a46-0963-4d1e-86d5-89c028274701
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23725207951098821133202918262878484076273000070945975565407790391523518427273 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.23725207951098821133202918262878484076273000070945975565407790391523518427273
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_stress_all.44449722434517924615290691455431675987540282054006985806548606719463951955583
Short name T598
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.79 seconds
Started Nov 22 01:28:03 PM PST 23
Finished Nov 22 01:28:14 PM PST 23
Peak memory 201272 kb
Host smart-eee5a69f-b9be-4981-a9ea-de9b825c9adf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44449722434517924615290691455431675987540282054006985806548606719463951955583 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.44449722434517924615290691455431675987540282054006985806548606719463951955583
Directory /workspace/32.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/32.pwrmgr_stress_all_with_rand_reset.113945242461118933174622205418570582022717769330213693822265844027464719386670
Short name T555
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.67 seconds
Started Nov 22 01:27:58 PM PST 23
Finished Nov 22 01:28:17 PM PST 23
Peak memory 201468 kb
Host smart-23e41eec-a2ec-47d3-a70b-11f010a75765
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113945242461118933174622
205418570582022717769330213693822265844027464719386670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all_with_rand_reset.1139
45242461118933174622205418570582022717769330213693822265844027464719386670
Directory /workspace/32.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup.72780256305809456828834654457130397436140268322084383627161152417395857865279
Short name T921
Test name
Test status
Simulation time 283777259 ps
CPU time 1.21 seconds
Started Nov 22 01:27:18 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 200112 kb
Host smart-a5e2166c-38e4-41f2-9f58-c4510a8368c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72780256305809456828834654457130397436140268322084383627161152417395857865279 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.72780256305809456828834654457130397436140268322084383627161152417395857865279
Directory /workspace/32.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup_reset.57039823243907882951635378091312853147254851471504888832033879493427689491109
Short name T732
Test name
Test status
Simulation time 325437640 ps
CPU time 1.37 seconds
Started Nov 22 01:27:21 PM PST 23
Finished Nov 22 01:27:39 PM PST 23
Peak memory 200668 kb
Host smart-809f4e53-ade2-4f28-811e-9c57b89587f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57039823243907882951635378091312853147254851471504888832033879493427689491109 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.57039823243907882951635378091312853147254851471504888832033879493427689491109
Directory /workspace/32.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.69663763132576549085677262874335164911632397324882162306832789871657157004476
Short name T655
Test name
Test status
Simulation time 51975542 ps
CPU time 0.78 seconds
Started Nov 22 01:27:32 PM PST 23
Finished Nov 22 01:27:47 PM PST 23
Peak memory 199052 kb
Host smart-66d174c6-6887-4899-bd52-0b6eb1ac3892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69663763132576549085677262874335164911632397324882162306832789871657157004476 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.pwrmgr_aborted_low_power.69663763132576549085677262874335164911632397324882162306832789871657157004476
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.34980432021797778070024169172417552698745335136511707794942178206175245940312
Short name T706
Test name
Test status
Simulation time 72403950 ps
CPU time 0.77 seconds
Started Nov 22 01:27:50 PM PST 23
Finished Nov 22 01:28:01 PM PST 23
Peak memory 198180 kb
Host smart-f3a2db80-050b-4ef0-ba88-9bc79fd5bc48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34980432021797778070024169172417552698745335136511707794942178206175245940312 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_disable_rom_integrity_check.349804320217977780700241691724175526987453351365117077
94942178206175245940312
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.23815100464609691719608744030293669309960943734946235192911043414503954920805
Short name T824
Test name
Test status
Simulation time 30368572 ps
CPU time 0.59 seconds
Started Nov 22 01:27:37 PM PST 23
Finished Nov 22 01:27:50 PM PST 23
Peak memory 195204 kb
Host smart-372112aa-3518-4f14-b81c-bc1d6fab1b44
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23815100464609691719608744030293669309960943734946235192911043414503954920805 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst_malfunc.23815100464609691719608744030293669309960943734946235192911043414503954920805
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.106897167820342572114370535120660613754836085495781107755213903426727387584567
Short name T355
Test name
Test status
Simulation time 39672069 ps
CPU time 0.61 seconds
Started Nov 22 01:27:30 PM PST 23
Finished Nov 22 01:27:44 PM PST 23
Peak memory 195352 kb
Host smart-d65ee2ab-4c33-4ff3-81f1-0fe01ebbef34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106897167820342572114370535120660613754836085495781107755213903426727387584567 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.106897167820342572114370535120660613754836085495781107755213903426727387584567
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.25340410612970504934258694422115296462041072379177204725186971935277647515858
Short name T490
Test name
Test status
Simulation time 33172121 ps
CPU time 0.64 seconds
Started Nov 22 01:27:25 PM PST 23
Finished Nov 22 01:27:40 PM PST 23
Peak memory 196800 kb
Host smart-78fce826-e988-4bd7-a4a5-4a8698ec0345
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25340410612970504934258694422115296462041072379177204725186971935277647515858 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.25340410612970504934258694422115296462041072379177204725186971935277647515858
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.27327775016976478972360786698294798220913065323663870001611089267759363935417
Short name T689
Test name
Test status
Simulation time 49975558 ps
CPU time 0.69 seconds
Started Nov 22 01:27:35 PM PST 23
Finished Nov 22 01:27:49 PM PST 23
Peak memory 201392 kb
Host smart-6714da78-3a9e-474b-ade1-eb37a299b6af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27327775016976478972360786698294798220913065323663870001611089267759363935417 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_invalid.27327775016976478972360786698294798220913065323663870001611089267759363935417
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_wakeup_race.56460429130324070955648951169499147383820830444286576978599423544379392974389
Short name T907
Test name
Test status
Simulation time 296241445 ps
CPU time 1.15 seconds
Started Nov 22 01:27:29 PM PST 23
Finished Nov 22 01:27:44 PM PST 23
Peak memory 199896 kb
Host smart-518e1731-b15a-4c4b-8787-e6103a406671
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56460429130324070955648951169499147383820830444286576978599423544379392974389 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_wakeup_race.56460429130324070955648951169499147383820830444286576978599423544379392974389
Directory /workspace/33.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.109598646290321622631554625537687694407664535809220565813033812151787071632077
Short name T427
Test name
Test status
Simulation time 119707143 ps
CPU time 0.95 seconds
Started Nov 22 01:27:29 PM PST 23
Finished Nov 22 01:27:43 PM PST 23
Peak memory 199128 kb
Host smart-9a1425c1-0005-4260-acf3-bd65c8093f3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109598646290321622631554625537687694407664535809220565813033812151787071632077 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.109598646290321622631554625537687694407664535809220565813033812151787071632077
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.60855943008592496122287508527497125313730784570984355782946757615930237600118
Short name T481
Test name
Test status
Simulation time 108189378 ps
CPU time 0.83 seconds
Started Nov 22 01:27:23 PM PST 23
Finished Nov 22 01:27:39 PM PST 23
Peak memory 209536 kb
Host smart-58e27056-3a9b-471d-8dd9-f148296673d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60855943008592496122287508527497125313730784570984355782946757615930237600118 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.60855943008592496122287508527497125313730784570984355782946757615930237600118
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.82893349721917542470461190200279250539222407270662943950238560868682119724768
Short name T739
Test name
Test status
Simulation time 314830582 ps
CPU time 1.34 seconds
Started Nov 22 01:27:27 PM PST 23
Finished Nov 22 01:27:42 PM PST 23
Peak memory 199816 kb
Host smart-6dfe12ed-cb0b-40e7-aa88-bd42cb022fc4
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82893349721917542470461190200279250539222407270662943950238560868682119724768 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_ctrl_config_regwen.828933497219175424704611902002792505392224072706629439502
38560868682119724768
Directory /workspace/33.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.103760494974828952791355714770342385604212523723454026024002504321646655345044
Short name T530
Test name
Test status
Simulation time 919450745 ps
CPU time 2.86 seconds
Started Nov 22 01:27:36 PM PST 23
Finished Nov 22 01:27:52 PM PST 23
Peak memory 201016 kb
Host smart-c9248efa-e0cd-4989-b82e-9bd989322275
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103760494974828952791355714770342385604212523723454026024002
504321646655345044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1037604949748289527913557
14770342385604212523723454026024002504321646655345044
Directory /workspace/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3585550249510764006953518667432065380646986228474840213385133360674575306450
Short name T466
Test name
Test status
Simulation time 968503924 ps
CPU time 3.08 seconds
Started Nov 22 01:27:39 PM PST 23
Finished Nov 22 01:27:54 PM PST 23
Peak memory 201196 kb
Host smart-5d9c2488-9dcb-4adc-9440-5e9f0cac1b67
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35855502495107640069535186674320653806469862284748402133851
33360674575306450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3585550249510764006953518
667432065380646986228474840213385133360674575306450
Directory /workspace/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.75018751040099682571453977195819769484072000632876415022850948516714019822150
Short name T450
Test name
Test status
Simulation time 91600225 ps
CPU time 0.87 seconds
Started Nov 22 01:27:36 PM PST 23
Finished Nov 22 01:27:50 PM PST 23
Peak memory 195272 kb
Host smart-efa1126c-be5d-4c33-95fe-cc53c25b747c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75018751040099682571453977195819769484072000632876415022850948516714019822150 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig_mubi.75018751040099682571453977195819769484072000632876415022850948516714019822150
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.102349994365315662282439963060956776657845226818194813432589163322007451787500
Short name T455
Test name
Test status
Simulation time 35743529 ps
CPU time 0.63 seconds
Started Nov 22 01:27:57 PM PST 23
Finished Nov 22 01:28:05 PM PST 23
Peak memory 197868 kb
Host smart-e30492aa-a957-40a8-ad15-945bb9010561
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102349994365315662282439963060956776657845226818194813432589163322007451787500 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.102349994365315662282439963060956776657845226818194813432589163322007451787500
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_stress_all.45542893847554699900555296102365646541603229494437411525975353517530401894721
Short name T876
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.69 seconds
Started Nov 22 01:27:36 PM PST 23
Finished Nov 22 01:27:55 PM PST 23
Peak memory 201204 kb
Host smart-4f29627a-66d5-424e-bb3f-b6a7b2812d95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45542893847554699900555296102365646541603229494437411525975353517530401894721 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all.45542893847554699900555296102365646541603229494437411525975353517530401894721
Directory /workspace/33.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/33.pwrmgr_stress_all_with_rand_reset.106658077476752741054809883369744569854546281655911931400023982205306293159609
Short name T609
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.28 seconds
Started Nov 22 01:27:33 PM PST 23
Finished Nov 22 01:27:58 PM PST 23
Peak memory 201448 kb
Host smart-6bf18f45-5c43-46bf-ab8e-17e65be6cb4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106658077476752741054809
883369744569854546281655911931400023982205306293159609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all_with_rand_reset.1066
58077476752741054809883369744569854546281655911931400023982205306293159609
Directory /workspace/33.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_wakeup.41372731673003428475505152970146288868964339693520638702397636685085355259544
Short name T786
Test name
Test status
Simulation time 283777259 ps
CPU time 1.2 seconds
Started Nov 22 01:27:52 PM PST 23
Finished Nov 22 01:28:02 PM PST 23
Peak memory 200096 kb
Host smart-661ebab7-2a97-4857-bad8-0ab387a5c073
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41372731673003428475505152970146288868964339693520638702397636685085355259544 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.41372731673003428475505152970146288868964339693520638702397636685085355259544
Directory /workspace/33.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/33.pwrmgr_wakeup_reset.6306036414207798018307351273053957278834164954034179750497632232422481010088
Short name T575
Test name
Test status
Simulation time 325437640 ps
CPU time 1.25 seconds
Started Nov 22 01:27:29 PM PST 23
Finished Nov 22 01:27:44 PM PST 23
Peak memory 200584 kb
Host smart-8e73faff-773f-4a29-8a47-fa33f5ccd04c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6306036414207798018307351273053957278834164954034179750497632232422481010088 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.6306036414207798018307351273053957278834164954034179750497632232422481010088
Directory /workspace/33.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.106239187861928489184862137332813666606797018882790660329316413107945302024199
Short name T1057
Test name
Test status
Simulation time 51975542 ps
CPU time 0.78 seconds
Started Nov 22 01:27:30 PM PST 23
Finished Nov 22 01:27:45 PM PST 23
Peak memory 199076 kb
Host smart-228be13c-6e62-4b3e-9558-6c80193ff177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106239187861928489184862137332813666606797018882790660329316413107945302024199 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.pwrmgr_aborted_low_power.106239187861928489184862137332813666606797018882790660329316413107945302024199
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.50774395274848077027102337875744722673957293843863847314929766236751575436666
Short name T34
Test name
Test status
Simulation time 72403950 ps
CPU time 0.75 seconds
Started Nov 22 01:27:48 PM PST 23
Finished Nov 22 01:27:59 PM PST 23
Peak memory 198064 kb
Host smart-836db093-99d6-48d8-a9ce-6d337fb1d1f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50774395274848077027102337875744722673957293843863847314929766236751575436666 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_disable_rom_integrity_check.507743952748480770271023378757447226739572938438638473
14929766236751575436666
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.109022409940340797586776469340976407749456026061232620393083843095161621604825
Short name T399
Test name
Test status
Simulation time 30368572 ps
CPU time 0.67 seconds
Started Nov 22 01:27:32 PM PST 23
Finished Nov 22 01:27:46 PM PST 23
Peak memory 195472 kb
Host smart-b57bbe80-151a-4a27-b848-b5811810aa96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109022409940340797586776469340976407749456026061232620393083843095161621604825 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst_malfunc.109022409940340797586776469340976407749456026061232620393083843095161621604825
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.39215466451971444182537648531828796275837695549308921905575163234816986832597
Short name T329
Test name
Test status
Simulation time 39672069 ps
CPU time 0.61 seconds
Started Nov 22 01:27:40 PM PST 23
Finished Nov 22 01:27:52 PM PST 23
Peak memory 195480 kb
Host smart-9786b43e-da74-432e-b5ab-4467029702d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39215466451971444182537648531828796275837695549308921905575163234816986832597 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.39215466451971444182537648531828796275837695549308921905575163234816986832597
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.113366694904849445902949993641829688920018364658304091728963587380590228749260
Short name T682
Test name
Test status
Simulation time 33172121 ps
CPU time 0.64 seconds
Started Nov 22 01:27:34 PM PST 23
Finished Nov 22 01:27:48 PM PST 23
Peak memory 196776 kb
Host smart-c8840eae-aab4-4af9-907f-4f87627b8fb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113366694904849445902949993641829688920018364658304091728963587380590228749260 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.113366694904849445902949993641829688920018364658304091728963587380590228749260
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.20539092837505852808587269542997117406675575932910889529503602886732757466295
Short name T488
Test name
Test status
Simulation time 49975558 ps
CPU time 0.7 seconds
Started Nov 22 01:27:48 PM PST 23
Finished Nov 22 01:27:59 PM PST 23
Peak memory 201224 kb
Host smart-f99f0210-e572-4f44-a9a3-3f1bd2cfcd58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20539092837505852808587269542997117406675575932910889529503602886732757466295 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_invalid.20539092837505852808587269542997117406675575932910889529503602886732757466295
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_wakeup_race.58096238802025134240862070619777004470558051781370793874803281414357958389785
Short name T747
Test name
Test status
Simulation time 296241445 ps
CPU time 1.13 seconds
Started Nov 22 01:27:37 PM PST 23
Finished Nov 22 01:27:51 PM PST 23
Peak memory 199860 kb
Host smart-136324b0-b28d-4f85-8c57-0bc60785f01d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58096238802025134240862070619777004470558051781370793874803281414357958389785 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_wakeup_race.58096238802025134240862070619777004470558051781370793874803281414357958389785
Directory /workspace/34.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.42584425546299156281861336533947653805558021724213744468545615553712189857044
Short name T954
Test name
Test status
Simulation time 119707143 ps
CPU time 1.02 seconds
Started Nov 22 01:27:32 PM PST 23
Finished Nov 22 01:27:47 PM PST 23
Peak memory 199300 kb
Host smart-24cda4cf-d4d6-492f-a540-feb9940c10cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42584425546299156281861336533947653805558021724213744468545615553712189857044 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.42584425546299156281861336533947653805558021724213744468545615553712189857044
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.26932179266229553878257221147939376164357709220472994784661050252163625150355
Short name T293
Test name
Test status
Simulation time 108189378 ps
CPU time 0.86 seconds
Started Nov 22 01:27:43 PM PST 23
Finished Nov 22 01:27:54 PM PST 23
Peak memory 209412 kb
Host smart-df15f168-f34d-498c-b19d-1da374453bc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26932179266229553878257221147939376164357709220472994784661050252163625150355 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.26932179266229553878257221147939376164357709220472994784661050252163625150355
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.10690892521839503109864080788689163883010710039022359737094819827706364007134
Short name T546
Test name
Test status
Simulation time 314830582 ps
CPU time 1.33 seconds
Started Nov 22 01:27:35 PM PST 23
Finished Nov 22 01:27:49 PM PST 23
Peak memory 199908 kb
Host smart-a37a7d53-56f6-4a3c-8917-a5f76ab14b6c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10690892521839503109864080788689163883010710039022359737094819827706364007134 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_ctrl_config_regwen.106908925218395031098640807886891638830107100390223597370
94819827706364007134
Directory /workspace/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.44428098163040457495649250399290239491406857812342895108212103587204147550354
Short name T389
Test name
Test status
Simulation time 919450745 ps
CPU time 2.85 seconds
Started Nov 22 01:27:33 PM PST 23
Finished Nov 22 01:27:50 PM PST 23
Peak memory 201232 kb
Host smart-c1d0632d-a44b-482e-b96b-819315ab046f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444280981630404574956492503992902394914068578123428951082121
03587204147550354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.44428098163040457495649250
399290239491406857812342895108212103587204147550354
Directory /workspace/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.59597635452786797204998192802836282129916649398910110710381370577360383301908
Short name T170
Test name
Test status
Simulation time 968503924 ps
CPU time 3.06 seconds
Started Nov 22 01:27:34 PM PST 23
Finished Nov 22 01:27:51 PM PST 23
Peak memory 201204 kb
Host smart-1e1d0944-0820-4f71-a181-3572b2d9d61b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59597635452786797204998192802836282129916649398910110710381
370577360383301908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.595976354527867972049981
92802836282129916649398910110710381370577360383301908
Directory /workspace/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.104793714647066067641054095207500791483922467220660563113402287309310025723554
Short name T458
Test name
Test status
Simulation time 91600225 ps
CPU time 0.98 seconds
Started Nov 22 01:28:22 PM PST 23
Finished Nov 22 01:28:26 PM PST 23
Peak memory 192852 kb
Host smart-e813264b-03ed-4866-94c6-a9ff29aff810
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104793714647066067641054095207500791483922467220660563113402287309310025723554 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig_mubi.104793714647066067641054095207500791483922467220660563113402287309310025723554
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.68886949626677264601774514757181839735220142619903738389654304880814001329735
Short name T602
Test name
Test status
Simulation time 35743529 ps
CPU time 0.64 seconds
Started Nov 22 01:27:31 PM PST 23
Finished Nov 22 01:27:45 PM PST 23
Peak memory 197868 kb
Host smart-8f16c96a-6642-4911-b055-7a9e50bd8d0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68886949626677264601774514757181839735220142619903738389654304880814001329735 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.68886949626677264601774514757181839735220142619903738389654304880814001329735
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_stress_all.94723202888631633964926809896532401111107471479592475127449326502486290944496
Short name T320
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.56 seconds
Started Nov 22 01:27:15 PM PST 23
Finished Nov 22 01:27:37 PM PST 23
Peak memory 201252 kb
Host smart-b9181fbe-38c1-4133-b689-bfae7b05c081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94723202888631633964926809896532401111107471479592475127449326502486290944496 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all.94723202888631633964926809896532401111107471479592475127449326502486290944496
Directory /workspace/34.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/34.pwrmgr_stress_all_with_rand_reset.85871224639776803562372601737454197166798736177513635226080281952163067986679
Short name T526
Test name
Test status
Simulation time 4441243999 ps
CPU time 10.97 seconds
Started Nov 22 01:27:30 PM PST 23
Finished Nov 22 01:27:54 PM PST 23
Peak memory 201312 kb
Host smart-cece0138-1109-477a-af9c-30b35467c060
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858712246397768035623726
01737454197166798736177513635226080281952163067986679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all_with_rand_reset.85871
224639776803562372601737454197166798736177513635226080281952163067986679
Directory /workspace/34.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup.1270176279593481594232297947413469138100513585133423603932084951902208906235
Short name T1051
Test name
Test status
Simulation time 283777259 ps
CPU time 1.15 seconds
Started Nov 22 01:27:34 PM PST 23
Finished Nov 22 01:27:48 PM PST 23
Peak memory 199908 kb
Host smart-954817a5-42be-46f0-8635-c91e1b8d5ba0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270176279593481594232297947413469138100513585133423603932084951902208906235 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.1270176279593481594232297947413469138100513585133423603932084951902208906235
Directory /workspace/34.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup_reset.19642486738513797346213364755978653844377053596733852398836314330914373731980
Short name T331
Test name
Test status
Simulation time 325437640 ps
CPU time 1.38 seconds
Started Nov 22 01:27:30 PM PST 23
Finished Nov 22 01:27:44 PM PST 23
Peak memory 200772 kb
Host smart-a72a37a4-e5a7-4fbd-842d-0e44663a4130
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19642486738513797346213364755978653844377053596733852398836314330914373731980 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.19642486738513797346213364755978653844377053596733852398836314330914373731980
Directory /workspace/34.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.46790404130313532649980397284993816448144086041168611328942046086601869555886
Short name T1003
Test name
Test status
Simulation time 51975542 ps
CPU time 0.79 seconds
Started Nov 22 01:27:20 PM PST 23
Finished Nov 22 01:27:37 PM PST 23
Peak memory 199192 kb
Host smart-e79b5f2d-5970-4ea7-a9d6-6145afe2ef52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46790404130313532649980397284993816448144086041168611328942046086601869555886 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.pwrmgr_aborted_low_power.46790404130313532649980397284993816448144086041168611328942046086601869555886
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.90936085139292693968992403824898238565596265918867667645016734590102043602108
Short name T26
Test name
Test status
Simulation time 72403950 ps
CPU time 0.76 seconds
Started Nov 22 01:27:20 PM PST 23
Finished Nov 22 01:27:37 PM PST 23
Peak memory 198164 kb
Host smart-9dfbf051-2f78-4a97-b463-c5f6290cb5b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90936085139292693968992403824898238565596265918867667645016734590102043602108 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_disable_rom_integrity_check.909360851392926939689924038248982385655962659188676676
45016734590102043602108
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.17528219112646472910990091769477995461793330304734967982197033432029539589289
Short name T913
Test name
Test status
Simulation time 30368572 ps
CPU time 0.59 seconds
Started Nov 22 01:27:34 PM PST 23
Finished Nov 22 01:27:48 PM PST 23
Peak memory 195276 kb
Host smart-be4366d2-f241-4d9a-82b4-9664f8631e58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17528219112646472910990091769477995461793330304734967982197033432029539589289 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_malfunc.17528219112646472910990091769477995461793330304734967982197033432029539589289
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.2559416644690850644209395493824146258339127898369251377876129667034562504095
Short name T897
Test name
Test status
Simulation time 39672069 ps
CPU time 0.62 seconds
Started Nov 22 01:27:58 PM PST 23
Finished Nov 22 01:28:06 PM PST 23
Peak memory 195492 kb
Host smart-a14e3102-5ddc-4b9e-98d8-9da34d006abb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559416644690850644209395493824146258339127898369251377876129667034562504095 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.2559416644690850644209395493824146258339127898369251377876129667034562504095
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.56354174873036742257822141487910563526108493967003666357393914762371361763268
Short name T385
Test name
Test status
Simulation time 33172121 ps
CPU time 0.56 seconds
Started Nov 22 01:27:30 PM PST 23
Finished Nov 22 01:27:44 PM PST 23
Peak memory 196648 kb
Host smart-c88f1aac-7ce4-497b-b6c9-18d10de90daf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56354174873036742257822141487910563526108493967003666357393914762371361763268 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.56354174873036742257822141487910563526108493967003666357393914762371361763268
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.40460148339920542834871042981277161015534298025737593882960248909611747376211
Short name T1
Test name
Test status
Simulation time 49975558 ps
CPU time 0.64 seconds
Started Nov 22 01:27:30 PM PST 23
Finished Nov 22 01:27:44 PM PST 23
Peak memory 201208 kb
Host smart-7ffcd4d8-b88f-4468-9ea2-46b5348fd6f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40460148339920542834871042981277161015534298025737593882960248909611747376211 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_invalid.40460148339920542834871042981277161015534298025737593882960248909611747376211
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_wakeup_race.4206402886844850452054823786527388879492263879236427753706230521499011192884
Short name T979
Test name
Test status
Simulation time 296241445 ps
CPU time 1.22 seconds
Started Nov 22 01:27:20 PM PST 23
Finished Nov 22 01:27:37 PM PST 23
Peak memory 199912 kb
Host smart-82f8d61f-5fa8-425a-9534-9093ba028479
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206402886844850452054823786527388879492263879236427753706230521499011192884 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_wakeup_race.4206402886844850452054823786527388879492263879236427753706230521499011192884
Directory /workspace/35.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.13209682742671184899468179461165014529304683982187930573275164923279558795729
Short name T989
Test name
Test status
Simulation time 119707143 ps
CPU time 0.96 seconds
Started Nov 22 01:27:29 PM PST 23
Finished Nov 22 01:27:44 PM PST 23
Peak memory 199140 kb
Host smart-6a0c5992-13b4-491d-9fc6-48e184134bcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13209682742671184899468179461165014529304683982187930573275164923279558795729 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.13209682742671184899468179461165014529304683982187930573275164923279558795729
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.27938062244392221771358311375750820600148769900470098688403809201348340796719
Short name T859
Test name
Test status
Simulation time 108189378 ps
CPU time 0.8 seconds
Started Nov 22 01:27:29 PM PST 23
Finished Nov 22 01:27:43 PM PST 23
Peak memory 209328 kb
Host smart-6243e628-f311-4c0d-bc77-a173ec41e582
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27938062244392221771358311375750820600148769900470098688403809201348340796719 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.27938062244392221771358311375750820600148769900470098688403809201348340796719
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.18854029086125801269194181132924661749613140355123963178604573869637155762275
Short name T409
Test name
Test status
Simulation time 314830582 ps
CPU time 1.33 seconds
Started Nov 22 01:27:26 PM PST 23
Finished Nov 22 01:27:41 PM PST 23
Peak memory 199888 kb
Host smart-e8e21a62-b0b9-42ad-8113-4372315c9010
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18854029086125801269194181132924661749613140355123963178604573869637155762275 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_ctrl_config_regwen.188540290861258012691941811329246617496131403551239631786
04573869637155762275
Directory /workspace/35.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.22268301713445763230571614879453466529003880389506816506724305294928607037596
Short name T554
Test name
Test status
Simulation time 919450745 ps
CPU time 2.94 seconds
Started Nov 22 01:27:14 PM PST 23
Finished Nov 22 01:27:34 PM PST 23
Peak memory 201200 kb
Host smart-b4f1d780-8a44-4e03-a498-4932e1813d56
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222683017134457632305716148794534665290038803895068165067243
05294928607037596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.22268301713445763230571614
879453466529003880389506816506724305294928607037596
Directory /workspace/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.104447055375664789876511370936980474323076460514791103455117459265525830536355
Short name T1049
Test name
Test status
Simulation time 968503924 ps
CPU time 3.19 seconds
Started Nov 22 01:27:37 PM PST 23
Finished Nov 22 01:27:53 PM PST 23
Peak memory 201104 kb
Host smart-69e2e367-b5be-4d87-950d-91e8ad4f1ac2
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10444705537566478987651137093698047432307646051479110345511
7459265525830536355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.10444705537566478987651
1370936980474323076460514791103455117459265525830536355
Directory /workspace/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.112264444227512857078351644134385207781320241092977609723090387587970091755249
Short name T854
Test name
Test status
Simulation time 91600225 ps
CPU time 0.89 seconds
Started Nov 22 01:27:16 PM PST 23
Finished Nov 22 01:27:33 PM PST 23
Peak memory 195528 kb
Host smart-edb80660-3508-4f8e-bbd8-073b6f1bc9f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112264444227512857078351644134385207781320241092977609723090387587970091755249 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig_mubi.112264444227512857078351644134385207781320241092977609723090387587970091755249
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.53420869731742563160917207561403857172138232916947394869293081822886207240501
Short name T413
Test name
Test status
Simulation time 35743529 ps
CPU time 0.66 seconds
Started Nov 22 01:27:14 PM PST 23
Finished Nov 22 01:27:32 PM PST 23
Peak memory 197804 kb
Host smart-2ef77c2c-3981-4c93-95c7-7c733b1f7e3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53420869731742563160917207561403857172138232916947394869293081822886207240501 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.53420869731742563160917207561403857172138232916947394869293081822886207240501
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_stress_all.108263238695982700854220389633599417060821171312686427014777595779499688214875
Short name T731
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.39 seconds
Started Nov 22 01:27:36 PM PST 23
Finished Nov 22 01:27:54 PM PST 23
Peak memory 201048 kb
Host smart-01859bf9-6652-4a36-a5d1-11d3cde857c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108263238695982700854220389633599417060821171312686427014777595779499688214875 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.108263238695982700854220389633599417060821171312686427014777595779499688214875
Directory /workspace/35.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/35.pwrmgr_stress_all_with_rand_reset.93368061006123956608507761044406064456553931824709792279339140424859150935863
Short name T987
Test name
Test status
Simulation time 4441243999 ps
CPU time 10.72 seconds
Started Nov 22 01:27:28 PM PST 23
Finished Nov 22 01:27:52 PM PST 23
Peak memory 201264 kb
Host smart-77adac85-69ad-4840-9d78-9f96222d578b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933680610061239566085077
61044406064456553931824709792279339140424859150935863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all_with_rand_reset.93368
061006123956608507761044406064456553931824709792279339140424859150935863
Directory /workspace/35.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup.8664003268206644334410392224618505788450707267559459232836079632374829741914
Short name T1016
Test name
Test status
Simulation time 283777259 ps
CPU time 1.26 seconds
Started Nov 22 01:27:17 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 200084 kb
Host smart-6c65a3bc-ec00-4883-ba16-50a2215fbafa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8664003268206644334410392224618505788450707267559459232836079632374829741914 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.8664003268206644334410392224618505788450707267559459232836079632374829741914
Directory /workspace/35.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup_reset.1188530625057918794345746361246347877358500138624559398073631787104468421901
Short name T617
Test name
Test status
Simulation time 325437640 ps
CPU time 1.31 seconds
Started Nov 22 01:27:16 PM PST 23
Finished Nov 22 01:27:34 PM PST 23
Peak memory 200592 kb
Host smart-3174ddab-bd49-4a5c-9c40-beac5af6cec2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188530625057918794345746361246347877358500138624559398073631787104468421901 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.1188530625057918794345746361246347877358500138624559398073631787104468421901
Directory /workspace/35.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.26614528109915587179342803118874118576000160766138735148671085312370654281962
Short name T166
Test name
Test status
Simulation time 51975542 ps
CPU time 0.81 seconds
Started Nov 22 01:27:30 PM PST 23
Finished Nov 22 01:27:44 PM PST 23
Peak memory 198848 kb
Host smart-7ef93e52-cab7-4522-9593-7e6febb17a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26614528109915587179342803118874118576000160766138735148671085312370654281962 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.pwrmgr_aborted_low_power.26614528109915587179342803118874118576000160766138735148671085312370654281962
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.75504451764787404250492269329996742902230900104224216308647219173419431714878
Short name T814
Test name
Test status
Simulation time 72403950 ps
CPU time 0.74 seconds
Started Nov 22 01:27:24 PM PST 23
Finished Nov 22 01:27:39 PM PST 23
Peak memory 198236 kb
Host smart-59e882e2-f0ea-4e50-bf1e-369b202d7e72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75504451764787404250492269329996742902230900104224216308647219173419431714878 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_disable_rom_integrity_check.755044517647874042504922693299967429022309001042242163
08647219173419431714878
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.18185391849324239196581096190881835719013259145824332925831568202022895305261
Short name T826
Test name
Test status
Simulation time 30368572 ps
CPU time 0.65 seconds
Started Nov 22 01:27:21 PM PST 23
Finished Nov 22 01:27:37 PM PST 23
Peak memory 195548 kb
Host smart-4fb59596-4ed6-48e8-8c97-c4002baa854c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18185391849324239196581096190881835719013259145824332925831568202022895305261 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst_malfunc.18185391849324239196581096190881835719013259145824332925831568202022895305261
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.25977420020242018478179565535231155249652222614042497214367258955878204196998
Short name T794
Test name
Test status
Simulation time 39672069 ps
CPU time 0.61 seconds
Started Nov 22 01:27:32 PM PST 23
Finished Nov 22 01:27:46 PM PST 23
Peak memory 195268 kb
Host smart-b2b3ae72-4898-474d-a316-5d89a55e075b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25977420020242018478179565535231155249652222614042497214367258955878204196998 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.25977420020242018478179565535231155249652222614042497214367258955878204196998
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.4181131528243699051974211759080107495155848614917883405830612918401149706494
Short name T582
Test name
Test status
Simulation time 33172121 ps
CPU time 0.6 seconds
Started Nov 22 01:27:26 PM PST 23
Finished Nov 22 01:27:40 PM PST 23
Peak memory 196772 kb
Host smart-a3c05a7a-c3bc-4a02-994c-b7385021c676
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181131528243699051974211759080107495155848614917883405830612918401149706494 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.4181131528243699051974211759080107495155848614917883405830612918401149706494
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.11137549508394323260867874778078152889822208621565926903335168594985007830710
Short name T342
Test name
Test status
Simulation time 49975558 ps
CPU time 0.66 seconds
Started Nov 22 01:27:29 PM PST 23
Finished Nov 22 01:27:43 PM PST 23
Peak memory 201184 kb
Host smart-723ac3bd-c9da-41c6-8e83-fea6e9c350e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11137549508394323260867874778078152889822208621565926903335168594985007830710 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_invalid.11137549508394323260867874778078152889822208621565926903335168594985007830710
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_wakeup_race.7368138521209184038813549436676108423449949218895488468281876412480786207471
Short name T1004
Test name
Test status
Simulation time 296241445 ps
CPU time 1.23 seconds
Started Nov 22 01:27:40 PM PST 23
Finished Nov 22 01:27:53 PM PST 23
Peak memory 200116 kb
Host smart-82884869-5484-467a-b9fb-82fe8e88125a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7368138521209184038813549436676108423449949218895488468281876412480786207471 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_wakeup_race.7368138521209184038813549436676108423449949218895488468281876412480786207471
Directory /workspace/36.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.115687929133767375506585326105516275911473328750800888607605959535487007582584
Short name T750
Test name
Test status
Simulation time 119707143 ps
CPU time 0.98 seconds
Started Nov 22 01:27:36 PM PST 23
Finished Nov 22 01:27:50 PM PST 23
Peak memory 199092 kb
Host smart-08755018-398d-4686-970d-37ac65107a43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115687929133767375506585326105516275911473328750800888607605959535487007582584 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.115687929133767375506585326105516275911473328750800888607605959535487007582584
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.40952768438158390864597439904228909901429853885263928480690928147813287416383
Short name T475
Test name
Test status
Simulation time 108189378 ps
CPU time 0.85 seconds
Started Nov 22 01:27:20 PM PST 23
Finished Nov 22 01:27:37 PM PST 23
Peak memory 209548 kb
Host smart-e13dad20-da1e-426a-9091-6893fb1fb7e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40952768438158390864597439904228909901429853885263928480690928147813287416383 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.40952768438158390864597439904228909901429853885263928480690928147813287416383
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.56723173233699073505762415802847291526157529403543421334642989428080030515444
Short name T288
Test name
Test status
Simulation time 314830582 ps
CPU time 1.31 seconds
Started Nov 22 01:27:17 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 199740 kb
Host smart-0eb75ac7-cfd0-44e2-98ad-852f04f62c41
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56723173233699073505762415802847291526157529403543421334642989428080030515444 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_ctrl_config_regwen.567231732336990735057624158028472915261575294035434213346
42989428080030515444
Directory /workspace/36.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.51755344661337929913199717136925584546985810306039358338344184392973533071370
Short name T860
Test name
Test status
Simulation time 919450745 ps
CPU time 2.88 seconds
Started Nov 22 01:27:27 PM PST 23
Finished Nov 22 01:27:43 PM PST 23
Peak memory 201228 kb
Host smart-328e89a0-1d15-4cc6-b09f-b20bf8886c51
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517553446613379299131997171369255845469858103060393583383441
84392973533071370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.51755344661337929913199717
136925584546985810306039358338344184392973533071370
Directory /workspace/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.975115348261780900361201388489076370763455913649520478997045113023559918286
Short name T155
Test name
Test status
Simulation time 968503924 ps
CPU time 2.9 seconds
Started Nov 22 01:27:48 PM PST 23
Finished Nov 22 01:28:00 PM PST 23
Peak memory 201100 kb
Host smart-d6c66c4f-f631-42cb-893f-8e78c61ab4e5
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97511534826178090036120138848907637076345591364952047899704
5113023559918286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.97511534826178090036120138
8489076370763455913649520478997045113023559918286
Directory /workspace/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.104906228654572450047092424205154993988923829513225641034301322801983266905725
Short name T770
Test name
Test status
Simulation time 91600225 ps
CPU time 0.88 seconds
Started Nov 22 01:27:48 PM PST 23
Finished Nov 22 01:27:59 PM PST 23
Peak memory 195448 kb
Host smart-1dad6a0e-9e4d-4e3a-8895-8539a5a3e149
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104906228654572450047092424205154993988923829513225641034301322801983266905725 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig_mubi.104906228654572450047092424205154993988923829513225641034301322801983266905725
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.73087150360241896852474754002894665187723277391089713586792530669942845572483
Short name T705
Test name
Test status
Simulation time 35743529 ps
CPU time 0.64 seconds
Started Nov 22 01:27:31 PM PST 23
Finished Nov 22 01:27:45 PM PST 23
Peak memory 197696 kb
Host smart-10bf9e9c-f960-49cc-94ff-54d04fd8edcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73087150360241896852474754002894665187723277391089713586792530669942845572483 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.73087150360241896852474754002894665187723277391089713586792530669942845572483
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_stress_all.34409798991594460806608737988649921570021877902590595780441017350941084745271
Short name T1061
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.49 seconds
Started Nov 22 01:27:32 PM PST 23
Finished Nov 22 01:27:51 PM PST 23
Peak memory 201056 kb
Host smart-7553df90-1575-4987-8e0b-10691635473c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34409798991594460806608737988649921570021877902590595780441017350941084745271 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.34409798991594460806608737988649921570021877902590595780441017350941084745271
Directory /workspace/36.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/36.pwrmgr_stress_all_with_rand_reset.90555110538770744036072676237494230817999419163102229425069724384893619596799
Short name T729
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.72 seconds
Started Nov 22 01:27:35 PM PST 23
Finished Nov 22 01:28:00 PM PST 23
Peak memory 201440 kb
Host smart-023eebf0-3ad6-43ab-84d2-565dad49e7de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905551105387707440360726
76237494230817999419163102229425069724384893619596799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all_with_rand_reset.90555
110538770744036072676237494230817999419163102229425069724384893619596799
Directory /workspace/36.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup.59078371551349213287142803508619513031780761830210175865496709711560401745685
Short name T451
Test name
Test status
Simulation time 283777259 ps
CPU time 1.23 seconds
Started Nov 22 01:27:57 PM PST 23
Finished Nov 22 01:28:06 PM PST 23
Peak memory 199992 kb
Host smart-42bb1439-cfb0-44e8-8951-e830c28fba11
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59078371551349213287142803508619513031780761830210175865496709711560401745685 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.59078371551349213287142803508619513031780761830210175865496709711560401745685
Directory /workspace/36.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup_reset.56873551257971564494196447405918801117100511900525035909202415296220177056425
Short name T959
Test name
Test status
Simulation time 325437640 ps
CPU time 1.42 seconds
Started Nov 22 01:27:30 PM PST 23
Finished Nov 22 01:27:44 PM PST 23
Peak memory 200692 kb
Host smart-40c03b29-fafb-4fc7-b7d2-e09cb0acc26a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56873551257971564494196447405918801117100511900525035909202415296220177056425 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.56873551257971564494196447405918801117100511900525035909202415296220177056425
Directory /workspace/36.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.107668784687499607846290218265700637685305174303965736926564687581907442753267
Short name T494
Test name
Test status
Simulation time 51975542 ps
CPU time 0.77 seconds
Started Nov 22 01:27:35 PM PST 23
Finished Nov 22 01:27:49 PM PST 23
Peak memory 199080 kb
Host smart-6a9569d1-f48a-436a-9ad9-dbdc27de9892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107668784687499607846290218265700637685305174303965736926564687581907442753267 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.pwrmgr_aborted_low_power.107668784687499607846290218265700637685305174303965736926564687581907442753267
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.33189607218525083904425783764944593231061822155786947862196320835866577660910
Short name T699
Test name
Test status
Simulation time 72403950 ps
CPU time 0.76 seconds
Started Nov 22 01:27:52 PM PST 23
Finished Nov 22 01:28:01 PM PST 23
Peak memory 198256 kb
Host smart-db795379-bfd7-4307-a705-630cb51bd1ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33189607218525083904425783764944593231061822155786947862196320835866577660910 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_disable_rom_integrity_check.331896072185250839044257837649445932310618221557869478
62196320835866577660910
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.84329526334754700591415669111084891076242852468394382587184740629417614515449
Short name T881
Test name
Test status
Simulation time 30368572 ps
CPU time 0.59 seconds
Started Nov 22 01:27:32 PM PST 23
Finished Nov 22 01:27:46 PM PST 23
Peak memory 195244 kb
Host smart-99a031ab-e16d-4738-880d-9d96a92c6592
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84329526334754700591415669111084891076242852468394382587184740629417614515449 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst_malfunc.84329526334754700591415669111084891076242852468394382587184740629417614515449
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.38798975371120475923190343865917609221429768286897953425116962607528819163318
Short name T1005
Test name
Test status
Simulation time 39672069 ps
CPU time 0.64 seconds
Started Nov 22 01:27:30 PM PST 23
Finished Nov 22 01:27:44 PM PST 23
Peak memory 195096 kb
Host smart-1c54e97a-5259-4872-b920-9e588b35a239
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38798975371120475923190343865917609221429768286897953425116962607528819163318 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.38798975371120475923190343865917609221429768286897953425116962607528819163318
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.92964275052629598062467185047036776316228682685796216824729222996999866302353
Short name T143
Test name
Test status
Simulation time 33172121 ps
CPU time 0.59 seconds
Started Nov 22 01:27:47 PM PST 23
Finished Nov 22 01:27:58 PM PST 23
Peak memory 196784 kb
Host smart-3acbc3da-d209-4be7-9ca4-4ab842bc68b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92964275052629598062467185047036776316228682685796216824729222996999866302353 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.92964275052629598062467185047036776316228682685796216824729222996999866302353
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.56205757854893719592647411700453751623322786736580880996848717727973236004182
Short name T762
Test name
Test status
Simulation time 49975558 ps
CPU time 0.67 seconds
Started Nov 22 01:27:58 PM PST 23
Finished Nov 22 01:28:06 PM PST 23
Peak memory 201356 kb
Host smart-73e0e7d5-07bd-49c5-88e3-033edc99f4f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56205757854893719592647411700453751623322786736580880996848717727973236004182 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_invalid.56205757854893719592647411700453751623322786736580880996848717727973236004182
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_wakeup_race.72986950341937198121345218206494217199381261064063540811050264244093425036721
Short name T678
Test name
Test status
Simulation time 296241445 ps
CPU time 1.2 seconds
Started Nov 22 01:27:30 PM PST 23
Finished Nov 22 01:27:45 PM PST 23
Peak memory 199944 kb
Host smart-65124192-4726-44d7-ac92-761abe7139a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72986950341937198121345218206494217199381261064063540811050264244093425036721 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_wakeup_race.72986950341937198121345218206494217199381261064063540811050264244093425036721
Directory /workspace/37.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.61326091991186190859220280216663917931757440951846206828972088165148884744613
Short name T563
Test name
Test status
Simulation time 119707143 ps
CPU time 1.01 seconds
Started Nov 22 01:27:58 PM PST 23
Finished Nov 22 01:28:06 PM PST 23
Peak memory 199228 kb
Host smart-bb3e67c0-2798-4eea-bae3-11a7065d7599
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61326091991186190859220280216663917931757440951846206828972088165148884744613 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.61326091991186190859220280216663917931757440951846206828972088165148884744613
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.69546701083685895278969044959697095795070008900602573106500232687399644639410
Short name T805
Test name
Test status
Simulation time 108189378 ps
CPU time 0.86 seconds
Started Nov 22 01:27:58 PM PST 23
Finished Nov 22 01:28:05 PM PST 23
Peak memory 209432 kb
Host smart-a0471d63-715f-440f-8e65-1570738dea77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69546701083685895278969044959697095795070008900602573106500232687399644639410 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.69546701083685895278969044959697095795070008900602573106500232687399644639410
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.91552003957355995781334631270783511178851609744718382975667657937036233519637
Short name T909
Test name
Test status
Simulation time 314830582 ps
CPU time 1.23 seconds
Started Nov 22 01:27:30 PM PST 23
Finished Nov 22 01:27:44 PM PST 23
Peak memory 199724 kb
Host smart-221005bd-3e14-4d4f-816f-c9328c19064b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91552003957355995781334631270783511178851609744718382975667657937036233519637 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_ctrl_config_regwen.915520039573559957813346312707835111788516097447183829756
67657937036233519637
Directory /workspace/37.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.65939066761224384881155690856932284751396441735352381341024880084736176700006
Short name T428
Test name
Test status
Simulation time 919450745 ps
CPU time 2.89 seconds
Started Nov 22 01:27:38 PM PST 23
Finished Nov 22 01:27:54 PM PST 23
Peak memory 201216 kb
Host smart-07a7cc22-b95d-4568-bf45-adc7b867994e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659390667612243848811556908569322847513964417353523813410248
80084736176700006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.65939066761224384881155690
856932284751396441735352381341024880084736176700006
Directory /workspace/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.67920500940144916316025961213757529443795342653724102820367846683829124003079
Short name T624
Test name
Test status
Simulation time 968503924 ps
CPU time 2.89 seconds
Started Nov 22 01:27:30 PM PST 23
Finished Nov 22 01:27:46 PM PST 23
Peak memory 201004 kb
Host smart-48712fa4-c867-4278-a0f3-cf5bb12d5fcf
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67920500940144916316025961213757529443795342653724102820367
846683829124003079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.679205009401449163160259
61213757529443795342653724102820367846683829124003079
Directory /workspace/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.71939145725644847641392544084889424007690696678483699409183274921059016916220
Short name T668
Test name
Test status
Simulation time 91600225 ps
CPU time 0.85 seconds
Started Nov 22 01:27:30 PM PST 23
Finished Nov 22 01:27:44 PM PST 23
Peak memory 195356 kb
Host smart-83cc7ff6-a6aa-41e1-b818-10eecfd36320
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71939145725644847641392544084889424007690696678483699409183274921059016916220 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig_mubi.71939145725644847641392544084889424007690696678483699409183274921059016916220
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.64426021114483793164509184172349443155949998843308262300599647943784884339923
Short name T410
Test name
Test status
Simulation time 35743529 ps
CPU time 0.65 seconds
Started Nov 22 01:27:45 PM PST 23
Finished Nov 22 01:27:55 PM PST 23
Peak memory 197908 kb
Host smart-922e275d-c754-41a4-87ee-422924a6622c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64426021114483793164509184172349443155949998843308262300599647943784884339923 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.64426021114483793164509184172349443155949998843308262300599647943784884339923
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_stress_all.87681707353310204563138245850334389395413861898939879820388630200556718574100
Short name T164
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.53 seconds
Started Nov 22 01:27:30 PM PST 23
Finished Nov 22 01:27:49 PM PST 23
Peak memory 201096 kb
Host smart-fbfa66e3-90ec-426c-9959-fffc735de43c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87681707353310204563138245850334389395413861898939879820388630200556718574100 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all.87681707353310204563138245850334389395413861898939879820388630200556718574100
Directory /workspace/37.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/37.pwrmgr_stress_all_with_rand_reset.82534710289947562189360404876544797752783197532502315060181085503027588596742
Short name T712
Test name
Test status
Simulation time 4441243999 ps
CPU time 10.97 seconds
Started Nov 22 01:27:29 PM PST 23
Finished Nov 22 01:27:54 PM PST 23
Peak memory 201296 kb
Host smart-75afb5be-abbb-48a5-87de-34e90989c74e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825347102899475621893604
04876544797752783197532502315060181085503027588596742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all_with_rand_reset.82534
710289947562189360404876544797752783197532502315060181085503027588596742
Directory /workspace/37.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup.63309873349059163975446658572439841529121736973804741139305817884468621699144
Short name T931
Test name
Test status
Simulation time 283777259 ps
CPU time 1.2 seconds
Started Nov 22 01:27:32 PM PST 23
Finished Nov 22 01:27:47 PM PST 23
Peak memory 199868 kb
Host smart-b40ebd18-2cfd-41b4-9d40-db87cf2d1719
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63309873349059163975446658572439841529121736973804741139305817884468621699144 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.63309873349059163975446658572439841529121736973804741139305817884468621699144
Directory /workspace/37.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup_reset.70306602663020597343612551846880618831930283715916967816249502074311527501
Short name T714
Test name
Test status
Simulation time 325437640 ps
CPU time 1.35 seconds
Started Nov 22 01:27:49 PM PST 23
Finished Nov 22 01:28:00 PM PST 23
Peak memory 200704 kb
Host smart-0058e195-211f-47e7-adb6-0bd42dc96879
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70306602663020597343612551846880618831930283715916967816249502074311527501 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.70306602663020597343612551846880618831930283715916967816249502074311527501
Directory /workspace/37.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.9096118051275232449015478502691055521477860993004932323056299256155923511500
Short name T528
Test name
Test status
Simulation time 51975542 ps
CPU time 0.79 seconds
Started Nov 22 01:27:49 PM PST 23
Finished Nov 22 01:27:59 PM PST 23
Peak memory 199132 kb
Host smart-21b3a6ae-feb2-4492-a6e1-1cbd2f1efadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9096118051275232449015478502691055521477860993004932323056299256155923511500 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 38.pwrmgr_aborted_low_power.9096118051275232449015478502691055521477860993004932323056299256155923511500
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.84373146066595865073455036911552003959171997667741180955010751977829378873833
Short name T352
Test name
Test status
Simulation time 72403950 ps
CPU time 0.76 seconds
Started Nov 22 01:27:29 PM PST 23
Finished Nov 22 01:27:43 PM PST 23
Peak memory 198188 kb
Host smart-6d3ceed7-1d6c-4bd4-8914-fd0c57d401ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84373146066595865073455036911552003959171997667741180955010751977829378873833 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_disable_rom_integrity_check.843731460665958650734550369115520039591719976677411809
55010751977829378873833
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.102501778435646054995056234116872686939305824664634528295795931408206733090613
Short name T10
Test name
Test status
Simulation time 30368572 ps
CPU time 0.6 seconds
Started Nov 22 01:27:32 PM PST 23
Finished Nov 22 01:27:47 PM PST 23
Peak memory 195480 kb
Host smart-676f8192-6190-43b6-8eea-08ac34387d7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102501778435646054995056234116872686939305824664634528295795931408206733090613 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst_malfunc.102501778435646054995056234116872686939305824664634528295795931408206733090613
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.14863860275822379983535315550279944063419531613268973964232524965728313474128
Short name T616
Test name
Test status
Simulation time 39672069 ps
CPU time 0.61 seconds
Started Nov 22 01:27:34 PM PST 23
Finished Nov 22 01:27:48 PM PST 23
Peak memory 195496 kb
Host smart-610acf6c-0169-49f0-a0a2-08c75cdd8b6b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14863860275822379983535315550279944063419531613268973964232524965728313474128 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.14863860275822379983535315550279944063419531613268973964232524965728313474128
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.74636722457405620883833795886747652707864459983885744657498348194106566313566
Short name T813
Test name
Test status
Simulation time 33172121 ps
CPU time 0.79 seconds
Started Nov 22 01:28:22 PM PST 23
Finished Nov 22 01:28:26 PM PST 23
Peak memory 194632 kb
Host smart-fd2b5aad-3fa9-443e-b304-6f78f60b4b40
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74636722457405620883833795886747652707864459983885744657498348194106566313566 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.74636722457405620883833795886747652707864459983885744657498348194106566313566
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.75399197820271697323641865694373417624141005860517852874118877885612211099873
Short name T657
Test name
Test status
Simulation time 49975558 ps
CPU time 0.7 seconds
Started Nov 22 01:27:31 PM PST 23
Finished Nov 22 01:27:45 PM PST 23
Peak memory 201408 kb
Host smart-68a6c87a-8260-4c28-b75c-454cb6c35ed3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75399197820271697323641865694373417624141005860517852874118877885612211099873 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_invalid.75399197820271697323641865694373417624141005860517852874118877885612211099873
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_wakeup_race.37235598912440189746720258234763171878110864613751237435255498753783027121244
Short name T781
Test name
Test status
Simulation time 296241445 ps
CPU time 1.15 seconds
Started Nov 22 01:27:36 PM PST 23
Finished Nov 22 01:27:50 PM PST 23
Peak memory 199828 kb
Host smart-6ccac8f9-92d6-4472-9cbb-27076c297fa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37235598912440189746720258234763171878110864613751237435255498753783027121244 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_wakeup_race.37235598912440189746720258234763171878110864613751237435255498753783027121244
Directory /workspace/38.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.3208707198804251049740596118715847018990203665487607630060656990658143011428
Short name T148
Test name
Test status
Simulation time 119707143 ps
CPU time 1 seconds
Started Nov 22 01:27:32 PM PST 23
Finished Nov 22 01:27:47 PM PST 23
Peak memory 199100 kb
Host smart-56c1f6ab-cb9b-4039-b079-42dba0caeb8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208707198804251049740596118715847018990203665487607630060656990658143011428 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.3208707198804251049740596118715847018990203665487607630060656990658143011428
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.70871734219358432968514976303010000326625404348598722215325841289538123266470
Short name T337
Test name
Test status
Simulation time 108189378 ps
CPU time 0.85 seconds
Started Nov 22 01:27:39 PM PST 23
Finished Nov 22 01:27:52 PM PST 23
Peak memory 209552 kb
Host smart-c8405d35-b277-41d7-a798-cf662869ee7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70871734219358432968514976303010000326625404348598722215325841289538123266470 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.70871734219358432968514976303010000326625404348598722215325841289538123266470
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.6092217158168105348222141714427147699841615588860948775697137465185014960999
Short name T316
Test name
Test status
Simulation time 314830582 ps
CPU time 1.38 seconds
Started Nov 22 01:27:32 PM PST 23
Finished Nov 22 01:27:48 PM PST 23
Peak memory 199804 kb
Host smart-71ee733f-4b3c-4c3a-88fb-11a326f09f3b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6092217158168105348222141714427147699841615588860948775697137465185014960999 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_ctrl_config_regwen.6092217158168105348222141714427147699841615588860948775697
137465185014960999
Directory /workspace/38.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.62191976338189696893615982622552863804453978653946384120376961867868385679529
Short name T684
Test name
Test status
Simulation time 919450745 ps
CPU time 2.9 seconds
Started Nov 22 01:27:29 PM PST 23
Finished Nov 22 01:27:45 PM PST 23
Peak memory 201216 kb
Host smart-e15f7391-4d5e-45e9-adac-130bffe50c97
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621919763381896968936159826225528638044539786539463841203769
61867868385679529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.62191976338189696893615982
622552863804453978653946384120376961867868385679529
Directory /workspace/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.45412341044948287953754798285517931608111589204024105711941788307262243742258
Short name T318
Test name
Test status
Simulation time 968503924 ps
CPU time 2.88 seconds
Started Nov 22 01:27:37 PM PST 23
Finished Nov 22 01:27:52 PM PST 23
Peak memory 200968 kb
Host smart-7bce2b46-22ce-438b-b16a-4fd08ed989ec
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45412341044948287953754798285517931608111589204024105711941
788307262243742258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.454123410449482879537547
98285517931608111589204024105711941788307262243742258
Directory /workspace/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.39969141833531114984672852237436837463602314880517104865747060472914377572367
Short name T396
Test name
Test status
Simulation time 91600225 ps
CPU time 0.95 seconds
Started Nov 22 01:27:20 PM PST 23
Finished Nov 22 01:27:37 PM PST 23
Peak memory 195468 kb
Host smart-18dee3df-f6c1-4f48-93a4-96baf923d972
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39969141833531114984672852237436837463602314880517104865747060472914377572367 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig_mubi.39969141833531114984672852237436837463602314880517104865747060472914377572367
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.86746536140113807172529677456198810957042989289504217980385408108461695441965
Short name T1017
Test name
Test status
Simulation time 35743529 ps
CPU time 0.66 seconds
Started Nov 22 01:27:30 PM PST 23
Finished Nov 22 01:27:44 PM PST 23
Peak memory 197972 kb
Host smart-9043a078-35e9-4ebf-9d33-8fd41020e5e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86746536140113807172529677456198810957042989289504217980385408108461695441965 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.86746536140113807172529677456198810957042989289504217980385408108461695441965
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_stress_all.69036836546107729898608036516180303226815214765823629935506498323590507022914
Short name T990
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.65 seconds
Started Nov 22 01:27:35 PM PST 23
Finished Nov 22 01:27:54 PM PST 23
Peak memory 201252 kb
Host smart-2843e93e-a54f-47a5-97aa-0801a0e5119e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69036836546107729898608036516180303226815214765823629935506498323590507022914 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all.69036836546107729898608036516180303226815214765823629935506498323590507022914
Directory /workspace/38.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/38.pwrmgr_stress_all_with_rand_reset.91184123764931965062635543953678962818783024299293557766699392678674095368635
Short name T1036
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.34 seconds
Started Nov 22 01:27:36 PM PST 23
Finished Nov 22 01:28:00 PM PST 23
Peak memory 201372 kb
Host smart-021ab1d8-51d8-404b-b68c-107e60526d07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911841237649319650626355
43953678962818783024299293557766699392678674095368635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all_with_rand_reset.91184
123764931965062635543953678962818783024299293557766699392678674095368635
Directory /workspace/38.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup.21206261416791416663801386411714090512072608407989754964993373188069760122686
Short name T730
Test name
Test status
Simulation time 283777259 ps
CPU time 1.24 seconds
Started Nov 22 01:27:19 PM PST 23
Finished Nov 22 01:27:37 PM PST 23
Peak memory 200144 kb
Host smart-1a93b109-e10e-4766-96e2-97d4440625c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21206261416791416663801386411714090512072608407989754964993373188069760122686 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.21206261416791416663801386411714090512072608407989754964993373188069760122686
Directory /workspace/38.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup_reset.29050538721130541354546302168103235564568074108480321713110608507300591298645
Short name T993
Test name
Test status
Simulation time 325437640 ps
CPU time 1.37 seconds
Started Nov 22 01:27:49 PM PST 23
Finished Nov 22 01:28:00 PM PST 23
Peak memory 200768 kb
Host smart-e1bf4ef6-4b70-4f1d-a719-d061b51b7082
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29050538721130541354546302168103235564568074108480321713110608507300591298645 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.29050538721130541354546302168103235564568074108480321713110608507300591298645
Directory /workspace/38.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.82717737937532554369316489523121192024422945034164745780222009036302370447159
Short name T360
Test name
Test status
Simulation time 51975542 ps
CPU time 0.78 seconds
Started Nov 22 01:27:35 PM PST 23
Finished Nov 22 01:27:49 PM PST 23
Peak memory 199120 kb
Host smart-3ff16edc-6641-4b0c-b51d-6315fab4114c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82717737937532554369316489523121192024422945034164745780222009036302370447159 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 39.pwrmgr_aborted_low_power.82717737937532554369316489523121192024422945034164745780222009036302370447159
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.4737032712575718377647710883634106177766346969562423024568337726931850946225
Short name T755
Test name
Test status
Simulation time 72403950 ps
CPU time 0.76 seconds
Started Nov 22 01:27:41 PM PST 23
Finished Nov 22 01:27:53 PM PST 23
Peak memory 198256 kb
Host smart-e501e238-3a02-4a0d-b03d-2c5c712a7194
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4737032712575718377647710883634106177766346969562423024568337726931850946225 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_disable_rom_integrity_check.4737032712575718377647710883634106177766346969562423024
568337726931850946225
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.3486782325111367168332369082232256742985046041078161608418909295317002844943
Short name T420
Test name
Test status
Simulation time 30368572 ps
CPU time 0.61 seconds
Started Nov 22 01:27:46 PM PST 23
Finished Nov 22 01:27:56 PM PST 23
Peak memory 195488 kb
Host smart-1d0ce7ef-1615-4f7e-acde-b6168436e84a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486782325111367168332369082232256742985046041078161608418909295317002844943 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst_malfunc.3486782325111367168332369082232256742985046041078161608418909295317002844943
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.5214154664570246668252254956773819870754293660556930431956789914620930387209
Short name T957
Test name
Test status
Simulation time 39672069 ps
CPU time 0.62 seconds
Started Nov 22 01:27:50 PM PST 23
Finished Nov 22 01:28:00 PM PST 23
Peak memory 195508 kb
Host smart-d9202f8e-3c14-4531-ac39-85d4a6110a24
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5214154664570246668252254956773819870754293660556930431956789914620930387209 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.5214154664570246668252254956773819870754293660556930431956789914620930387209
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.60476576198363349873291211706136909332653362936308277743698498780608736588396
Short name T350
Test name
Test status
Simulation time 33172121 ps
CPU time 0.61 seconds
Started Nov 22 01:27:50 PM PST 23
Finished Nov 22 01:28:00 PM PST 23
Peak memory 196848 kb
Host smart-9fbfcbcf-660f-4478-aa7d-f2c28637609e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60476576198363349873291211706136909332653362936308277743698498780608736588396 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.60476576198363349873291211706136909332653362936308277743698498780608736588396
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.76554633846402602224012468376177041957756058722866017710231535867033388845146
Short name T788
Test name
Test status
Simulation time 49975558 ps
CPU time 0.68 seconds
Started Nov 22 01:28:01 PM PST 23
Finished Nov 22 01:28:08 PM PST 23
Peak memory 201380 kb
Host smart-f364c9c9-f0ac-410d-bd1c-a16ff3a1ae48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76554633846402602224012468376177041957756058722866017710231535867033388845146 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_invalid.76554633846402602224012468376177041957756058722866017710231535867033388845146
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_wakeup_race.105231725905156106894119592946015872000710366503097152823351397515568155565474
Short name T914
Test name
Test status
Simulation time 296241445 ps
CPU time 1.19 seconds
Started Nov 22 01:27:43 PM PST 23
Finished Nov 22 01:27:54 PM PST 23
Peak memory 200100 kb
Host smart-9fa8ea97-4202-4bef-9016-9a3bc27aff7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105231725905156106894119592946015872000710366503097152823351397515568155565474 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_wakeup_race.105231725905156106894119592946015872000710366503097152823351397515568155565474
Directory /workspace/39.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.61501123883494753181776276856632652319782952532827024551346204577049649897877
Short name T414
Test name
Test status
Simulation time 119707143 ps
CPU time 1.07 seconds
Started Nov 22 01:27:40 PM PST 23
Finished Nov 22 01:27:53 PM PST 23
Peak memory 199296 kb
Host smart-4e593ece-e6f9-4d47-bba3-87ac120a4bb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61501123883494753181776276856632652319782952532827024551346204577049649897877 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.61501123883494753181776276856632652319782952532827024551346204577049649897877
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.8144611864972742909894326130207947096383672295400078768374681893083340610244
Short name T1070
Test name
Test status
Simulation time 108189378 ps
CPU time 0.89 seconds
Started Nov 22 01:27:35 PM PST 23
Finished Nov 22 01:27:49 PM PST 23
Peak memory 209492 kb
Host smart-7ef73d63-7be5-4c93-959a-db1793c4c7f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8144611864972742909894326130207947096383672295400078768374681893083340610244 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.8144611864972742909894326130207947096383672295400078768374681893083340610244
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.52138142730806406043491624245725993822469871602637498939791534224715971804392
Short name T154
Test name
Test status
Simulation time 314830582 ps
CPU time 1.35 seconds
Started Nov 22 01:27:46 PM PST 23
Finished Nov 22 01:27:57 PM PST 23
Peak memory 199884 kb
Host smart-8f87722b-7bad-428c-8294-fcf3909a3109
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52138142730806406043491624245725993822469871602637498939791534224715971804392 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_ctrl_config_regwen.521381427308064060434916242457259938224698716026374989397
91534224715971804392
Directory /workspace/39.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.82070189660340761426524578692564889936370708293475994639911075313965764604666
Short name T1032
Test name
Test status
Simulation time 919450745 ps
CPU time 2.82 seconds
Started Nov 22 01:27:34 PM PST 23
Finished Nov 22 01:27:51 PM PST 23
Peak memory 201056 kb
Host smart-73651cf6-29ad-4b82-87a3-c9b8cb0122ba
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820701896603407614265245786925648899363707082934759946399110
75313965764604666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.82070189660340761426524578
692564889936370708293475994639911075313965764604666
Directory /workspace/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.108104703742176507728927547337381463963671753090314384142931995608670063768483
Short name T879
Test name
Test status
Simulation time 968503924 ps
CPU time 2.89 seconds
Started Nov 22 01:27:33 PM PST 23
Finished Nov 22 01:27:50 PM PST 23
Peak memory 201100 kb
Host smart-d4c33ac2-c1cb-4689-8f9c-a6fd11208876
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10810470374217650772892754733738146396367175309031438414293
1995608670063768483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.10810470374217650772892
7547337381463963671753090314384142931995608670063768483
Directory /workspace/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.26454160890244007615632978034329433098291053126770635241825828060897196232685
Short name T917
Test name
Test status
Simulation time 91600225 ps
CPU time 0.9 seconds
Started Nov 22 01:27:48 PM PST 23
Finished Nov 22 01:27:59 PM PST 23
Peak memory 195548 kb
Host smart-42b8aa77-f71c-41fb-848b-01955a9b26e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26454160890244007615632978034329433098291053126770635241825828060897196232685 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig_mubi.26454160890244007615632978034329433098291053126770635241825828060897196232685
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.6802825486974133486773786496892354136114902079701794832228617792993081407779
Short name T735
Test name
Test status
Simulation time 35743529 ps
CPU time 0.64 seconds
Started Nov 22 01:27:37 PM PST 23
Finished Nov 22 01:27:50 PM PST 23
Peak memory 197888 kb
Host smart-c38ec1b6-45ce-4400-bb7d-324f37aa2400
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6802825486974133486773786496892354136114902079701794832228617792993081407779 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.6802825486974133486773786496892354136114902079701794832228617792993081407779
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_stress_all.109883417713133740037613828055499965139094046118700316834042119481837102010483
Short name T558
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.85 seconds
Started Nov 22 01:27:59 PM PST 23
Finished Nov 22 01:28:12 PM PST 23
Peak memory 201368 kb
Host smart-c5d4a2fc-ed4f-404c-8305-d256a33ef7a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109883417713133740037613828055499965139094046118700316834042119481837102010483 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all.109883417713133740037613828055499965139094046118700316834042119481837102010483
Directory /workspace/39.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/39.pwrmgr_stress_all_with_rand_reset.24231817026419714512376835105069317262967832965380312459888413137523345626820
Short name T387
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.01 seconds
Started Nov 22 01:27:57 PM PST 23
Finished Nov 22 01:28:15 PM PST 23
Peak memory 201464 kb
Host smart-1fb01f0e-dc8a-4f89-b235-cc8c5fe3dbe1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242318170264197145123768
35105069317262967832965380312459888413137523345626820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all_with_rand_reset.24231
817026419714512376835105069317262967832965380312459888413137523345626820
Directory /workspace/39.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup.12459277649174783106386430809037133590770781327512211924404110143906869721225
Short name T961
Test name
Test status
Simulation time 283777259 ps
CPU time 1.33 seconds
Started Nov 22 01:28:22 PM PST 23
Finished Nov 22 01:28:26 PM PST 23
Peak memory 197488 kb
Host smart-518bc94d-4b72-4f0e-b25d-de03777c09d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12459277649174783106386430809037133590770781327512211924404110143906869721225 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.12459277649174783106386430809037133590770781327512211924404110143906869721225
Directory /workspace/39.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup_reset.59574846671118682860354665162169482404643984649101436589407816259156971186772
Short name T133
Test name
Test status
Simulation time 325437640 ps
CPU time 1.38 seconds
Started Nov 22 01:27:30 PM PST 23
Finished Nov 22 01:27:44 PM PST 23
Peak memory 200776 kb
Host smart-2f39b166-e4e4-44d5-888c-8988abfd3366
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59574846671118682860354665162169482404643984649101436589407816259156971186772 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.59574846671118682860354665162169482404643984649101436589407816259156971186772
Directory /workspace/39.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.86154839426162128407503719835822469659214250533116689348180812277806327418376
Short name T439
Test name
Test status
Simulation time 51975542 ps
CPU time 0.83 seconds
Started Nov 22 01:26:06 PM PST 23
Finished Nov 22 01:26:12 PM PST 23
Peak memory 199148 kb
Host smart-d5c70a24-145a-4c36-a9e8-b7d288972070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86154839426162128407503719835822469659214250533116689348180812277806327418376 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.pwrmgr_aborted_low_power.86154839426162128407503719835822469659214250533116689348180812277806327418376
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.56684723478251573068934342896801466759405793719480834266282195444766183288110
Short name T936
Test name
Test status
Simulation time 72403950 ps
CPU time 0.72 seconds
Started Nov 22 01:26:12 PM PST 23
Finished Nov 22 01:26:19 PM PST 23
Peak memory 198264 kb
Host smart-7246b395-01a4-419d-9e67-7a8636d28c58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56684723478251573068934342896801466759405793719480834266282195444766183288110 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disable_rom_integrity_check.5668472347825157306893434289680146675940579371948083426
6282195444766183288110
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.15895543691975124113342095331408575520445324767766892930915317065796459247332
Short name T12
Test name
Test status
Simulation time 30368572 ps
CPU time 0.62 seconds
Started Nov 22 01:26:05 PM PST 23
Finished Nov 22 01:26:11 PM PST 23
Peak memory 195320 kb
Host smart-9392fdd0-1ce3-418f-917c-7cc71b102e8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15895543691975124113342095331408575520445324767766892930915317065796459247332 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_malfunc.15895543691975124113342095331408575520445324767766892930915317065796459247332
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.71219282922811270410580338088598015614023765312053008024936329427660216049454
Short name T505
Test name
Test status
Simulation time 39672069 ps
CPU time 0.6 seconds
Started Nov 22 01:26:07 PM PST 23
Finished Nov 22 01:26:13 PM PST 23
Peak memory 195452 kb
Host smart-791fd207-dae6-44fe-95c5-b88a3677c189
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71219282922811270410580338088598015614023765312053008024936329427660216049454 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.71219282922811270410580338088598015614023765312053008024936329427660216049454
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.73153219971587086661962701102337642746728356747583279248577863133515689204051
Short name T442
Test name
Test status
Simulation time 33172121 ps
CPU time 0.6 seconds
Started Nov 22 01:26:07 PM PST 23
Finished Nov 22 01:26:13 PM PST 23
Peak memory 196836 kb
Host smart-1e52eb35-a9df-4837-ac44-30750f5d7616
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73153219971587086661962701102337642746728356747583279248577863133515689204051 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.73153219971587086661962701102337642746728356747583279248577863133515689204051
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.46131606526294936818597396371075745603228248018374449506948545706355876668667
Short name T323
Test name
Test status
Simulation time 49975558 ps
CPU time 0.67 seconds
Started Nov 22 01:27:01 PM PST 23
Finished Nov 22 01:27:19 PM PST 23
Peak memory 200964 kb
Host smart-d7e30e91-f3b4-4248-819b-b088d726a200
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46131606526294936818597396371075745603228248018374449506948545706355876668667 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invalid.46131606526294936818597396371075745603228248018374449506948545706355876668667
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_wakeup_race.108457591307273682874986790716696826626358056558529064571268685417999327179684
Short name T686
Test name
Test status
Simulation time 296241445 ps
CPU time 1.2 seconds
Started Nov 22 01:26:06 PM PST 23
Finished Nov 22 01:26:13 PM PST 23
Peak memory 200048 kb
Host smart-6354707a-0512-43a9-a721-69603450ee1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108457591307273682874986790716696826626358056558529064571268685417999327179684 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wakeup_race.108457591307273682874986790716696826626358056558529064571268685417999327179684
Directory /workspace/4.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.78562797934148535797843657975889098618494800105441393842050068014842798391815
Short name T383
Test name
Test status
Simulation time 119707143 ps
CPU time 1.02 seconds
Started Nov 22 01:25:52 PM PST 23
Finished Nov 22 01:25:59 PM PST 23
Peak memory 199292 kb
Host smart-e22038f6-b28d-4ea8-9c26-262dfb4585ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78562797934148535797843657975889098618494800105441393842050068014842798391815 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.78562797934148535797843657975889098618494800105441393842050068014842798391815
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.29633728414248139039000303704659654926089907253430082883005396381797962262880
Short name T853
Test name
Test status
Simulation time 108189378 ps
CPU time 0.88 seconds
Started Nov 22 01:26:04 PM PST 23
Finished Nov 22 01:26:11 PM PST 23
Peak memory 209400 kb
Host smart-ac05be36-610f-4470-9e9e-31a187bb1623
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29633728414248139039000303704659654926089907253430082883005396381797962262880 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.29633728414248139039000303704659654926089907253430082883005396381797962262880
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.90192392825842744458168088906808232114876758179748088054227707181028871319041
Short name T15
Test name
Test status
Simulation time 344080348 ps
CPU time 1.28 seconds
Started Nov 22 01:26:05 PM PST 23
Finished Nov 22 01:26:12 PM PST 23
Peak memory 214260 kb
Host smart-119dc87a-702d-4b2f-8e4e-fb74d21c7600
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90192392825842744458168088906808232114876758179748088054227707181028871319041 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.90192392825842744458168088906808232114876758179748088054227707181028871319041
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.100871010492349166758726105727069158236171929272246078058660292136082270411939
Short name T327
Test name
Test status
Simulation time 314830582 ps
CPU time 1.29 seconds
Started Nov 22 01:26:07 PM PST 23
Finished Nov 22 01:26:14 PM PST 23
Peak memory 199892 kb
Host smart-049b3002-f888-4fd3-b0b3-d557d507d2fc
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100871010492349166758726105727069158236171929272246078058660292136082270411939 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_ctrl_config_regwen.100871010492349166758726105727069158236171929272246078058
660292136082270411939
Directory /workspace/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.22816950115602648593112540438278213295625375110567257363976828234906549633132
Short name T382
Test name
Test status
Simulation time 919450745 ps
CPU time 2.85 seconds
Started Nov 22 01:25:52 PM PST 23
Finished Nov 22 01:26:02 PM PST 23
Peak memory 201056 kb
Host smart-dd25cdfe-69ed-4b5a-a5fe-bde695d185dd
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228169501156026485931125404382782132956253751105672573639768
28234906549633132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.228169501156026485931125404
38278213295625375110567257363976828234906549633132
Directory /workspace/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.98363063534349694445186246841183582342677541053082594802542056584807028637121
Short name T2
Test name
Test status
Simulation time 968503924 ps
CPU time 2.9 seconds
Started Nov 22 01:26:05 PM PST 23
Finished Nov 22 01:26:13 PM PST 23
Peak memory 201012 kb
Host smart-aeaa3833-9787-4bb9-bf1b-6887b6c20501
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98363063534349694445186246841183582342677541053082594802542
056584807028637121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.9836306353434969444518624
6841183582342677541053082594802542056584807028637121
Directory /workspace/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.104388363767101445869989406872970887096504389039548475814828606340341030084156
Short name T751
Test name
Test status
Simulation time 91600225 ps
CPU time 0.87 seconds
Started Nov 22 01:25:51 PM PST 23
Finished Nov 22 01:25:58 PM PST 23
Peak memory 195412 kb
Host smart-01a22652-4299-438c-a025-9e290a2b999a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104388363767101445869989406872970887096504389039548475814828606340341030084156 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_mubi.104388363767101445869989406872970887096504389039548475814828606340341030084156
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.54715511718714502715333950639237839696786764972143354460361533603526865126612
Short name T348
Test name
Test status
Simulation time 35743529 ps
CPU time 0.63 seconds
Started Nov 22 01:26:05 PM PST 23
Finished Nov 22 01:26:11 PM PST 23
Peak memory 197900 kb
Host smart-8bd81b51-2a0e-47a6-83ac-595c42d31f87
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54715511718714502715333950639237839696786764972143354460361533603526865126612 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.54715511718714502715333950639237839696786764972143354460361533603526865126612
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_stress_all.98155274591595939403155415745276175035216060737029259251008473143045836867171
Short name T927
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.46 seconds
Started Nov 22 01:26:05 PM PST 23
Finished Nov 22 01:26:16 PM PST 23
Peak memory 201096 kb
Host smart-190ad57c-c2d0-4d7b-a1ca-07a691ba9906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98155274591595939403155415745276175035216060737029259251008473143045836867171 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.98155274591595939403155415745276175035216060737029259251008473143045836867171
Directory /workspace/4.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/4.pwrmgr_stress_all_with_rand_reset.49933362285106916736020333999180943325509824994977008423324340629553138286917
Short name T610
Test name
Test status
Simulation time 4441243999 ps
CPU time 11 seconds
Started Nov 22 01:26:19 PM PST 23
Finished Nov 22 01:26:33 PM PST 23
Peak memory 201324 kb
Host smart-fb658197-d723-487f-833f-5460fc4d5036
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499333622851069167360203
33999180943325509824994977008423324340629553138286917 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all_with_rand_reset.499333
62285106916736020333999180943325509824994977008423324340629553138286917
Directory /workspace/4.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup.103245719168692777215789095584536677322698991827115159111245240166521728145144
Short name T738
Test name
Test status
Simulation time 283777259 ps
CPU time 1.19 seconds
Started Nov 22 01:26:03 PM PST 23
Finished Nov 22 01:26:09 PM PST 23
Peak memory 200020 kb
Host smart-e60752d0-8984-423a-b6d3-7bdf376074ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103245719168692777215789095584536677322698991827115159111245240166521728145144 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.103245719168692777215789095584536677322698991827115159111245240166521728145144
Directory /workspace/4.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup_reset.97629494459946006684750620113213189895169125203604311860870393083902045720367
Short name T704
Test name
Test status
Simulation time 325437640 ps
CPU time 1.37 seconds
Started Nov 22 01:26:03 PM PST 23
Finished Nov 22 01:26:09 PM PST 23
Peak memory 200764 kb
Host smart-2703e3fb-3dd2-4be1-ac5b-c257cfa3d154
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97629494459946006684750620113213189895169125203604311860870393083902045720367 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.97629494459946006684750620113213189895169125203604311860870393083902045720367
Directory /workspace/4.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.29678474062775321706784003599618708881521296574711414474071454257611286828707
Short name T289
Test name
Test status
Simulation time 51975542 ps
CPU time 0.75 seconds
Started Nov 22 01:27:31 PM PST 23
Finished Nov 22 01:27:45 PM PST 23
Peak memory 198964 kb
Host smart-75188337-c867-47de-a536-fd3e3c63f747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29678474062775321706784003599618708881521296574711414474071454257611286828707 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.pwrmgr_aborted_low_power.29678474062775321706784003599618708881521296574711414474071454257611286828707
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.29510237589327267744532523548275867471071364021782610418050366447288073982782
Short name T112
Test name
Test status
Simulation time 72403950 ps
CPU time 0.79 seconds
Started Nov 22 01:27:46 PM PST 23
Finished Nov 22 01:27:57 PM PST 23
Peak memory 198064 kb
Host smart-206bd2c2-ee6a-4439-a378-22c79ea3b4f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29510237589327267744532523548275867471071364021782610418050366447288073982782 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_disable_rom_integrity_check.295102375893272677445325235482758674710713640217826104
18050366447288073982782
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.47038729415618222079807912535673141450308902745994110135052191752157529937350
Short name T894
Test name
Test status
Simulation time 30368572 ps
CPU time 0.61 seconds
Started Nov 22 01:27:48 PM PST 23
Finished Nov 22 01:27:58 PM PST 23
Peak memory 195484 kb
Host smart-ce21e436-888b-42a1-b469-67325de267ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47038729415618222079807912535673141450308902745994110135052191752157529937350 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst_malfunc.47038729415618222079807912535673141450308902745994110135052191752157529937350
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.3378160259974532555908429603162958239172397217266683827820612048562063037184
Short name T740
Test name
Test status
Simulation time 39672069 ps
CPU time 0.6 seconds
Started Nov 22 01:27:46 PM PST 23
Finished Nov 22 01:27:56 PM PST 23
Peak memory 195536 kb
Host smart-22fe88e6-a73f-48d2-8029-32028a621536
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378160259974532555908429603162958239172397217266683827820612048562063037184 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.3378160259974532555908429603162958239172397217266683827820612048562063037184
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.66109803452221580831634503287770829958441001142926772080507531049302628909813
Short name T908
Test name
Test status
Simulation time 33172121 ps
CPU time 0.58 seconds
Started Nov 22 01:27:46 PM PST 23
Finished Nov 22 01:27:56 PM PST 23
Peak memory 196856 kb
Host smart-636cb3f5-da5d-4796-8759-becdb4294298
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66109803452221580831634503287770829958441001142926772080507531049302628909813 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.66109803452221580831634503287770829958441001142926772080507531049302628909813
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.51172641268688309061991573149586667528748551269967360470519530655773261534607
Short name T557
Test name
Test status
Simulation time 49975558 ps
CPU time 0.83 seconds
Started Nov 22 01:28:22 PM PST 23
Finished Nov 22 01:28:26 PM PST 23
Peak memory 198704 kb
Host smart-9177d1a1-0345-4f5d-a5f8-524ebb78f601
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51172641268688309061991573149586667528748551269967360470519530655773261534607 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_invalid.51172641268688309061991573149586667528748551269967360470519530655773261534607
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_wakeup_race.83316764403596826239207178876528548440510081745414338009002698011905929480304
Short name T543
Test name
Test status
Simulation time 296241445 ps
CPU time 1.16 seconds
Started Nov 22 01:27:51 PM PST 23
Finished Nov 22 01:28:01 PM PST 23
Peak memory 200048 kb
Host smart-40934523-22fe-4b09-a687-d08310288be6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83316764403596826239207178876528548440510081745414338009002698011905929480304 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_wakeup_race.83316764403596826239207178876528548440510081745414338009002698011905929480304
Directory /workspace/40.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.76361725864923430507190390055710486244015475001507621422656611327098800594721
Short name T696
Test name
Test status
Simulation time 119707143 ps
CPU time 1.06 seconds
Started Nov 22 01:27:54 PM PST 23
Finished Nov 22 01:28:04 PM PST 23
Peak memory 199328 kb
Host smart-77bd80cb-391c-4953-b2a2-4f50f1b8bfa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76361725864923430507190390055710486244015475001507621422656611327098800594721 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.76361725864923430507190390055710486244015475001507621422656611327098800594721
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.34758587098228683728711863694213352009827633895607157463587830169103981644029
Short name T1038
Test name
Test status
Simulation time 108189378 ps
CPU time 0.86 seconds
Started Nov 22 01:27:52 PM PST 23
Finished Nov 22 01:28:02 PM PST 23
Peak memory 209552 kb
Host smart-88d58383-25ac-4b3f-a3c2-620f77923260
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34758587098228683728711863694213352009827633895607157463587830169103981644029 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.34758587098228683728711863694213352009827633895607157463587830169103981644029
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.85624267778713434976711426723883434138664736709711252415143368911766625459887
Short name T583
Test name
Test status
Simulation time 314830582 ps
CPU time 1.32 seconds
Started Nov 22 01:27:20 PM PST 23
Finished Nov 22 01:27:37 PM PST 23
Peak memory 199800 kb
Host smart-810812f1-d3a3-4f54-858e-1788c2a9f073
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85624267778713434976711426723883434138664736709711252415143368911766625459887 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_ctrl_config_regwen.856242677787134349767114267238834341386647367097112524151
43368911766625459887
Directory /workspace/40.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.67022141928876596333373558718582717426427011752539519875131597426632232904004
Short name T852
Test name
Test status
Simulation time 919450745 ps
CPU time 2.9 seconds
Started Nov 22 01:27:48 PM PST 23
Finished Nov 22 01:28:00 PM PST 23
Peak memory 201244 kb
Host smart-8ec49d0f-dd7e-494c-952d-d006894e983c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670221419288765963333735587185827174264270117525395198751315
97426632232904004 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.67022141928876596333373558
718582717426427011752539519875131597426632232904004
Directory /workspace/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.104365078925082671923048785717334713858570256081595762109394560515398855825153
Short name T578
Test name
Test status
Simulation time 968503924 ps
CPU time 3.05 seconds
Started Nov 22 01:27:25 PM PST 23
Finished Nov 22 01:27:42 PM PST 23
Peak memory 201196 kb
Host smart-0201a9b9-492b-47f5-a0cd-bac23a990933
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10436507892508267192304878571733471385857025608159576210939
4560515398855825153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.10436507892508267192304
8785717334713858570256081595762109394560515398855825153
Directory /workspace/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.83172688641738113162407319145251897344072202810290241664589099642567982924644
Short name T584
Test name
Test status
Simulation time 91600225 ps
CPU time 0.87 seconds
Started Nov 22 01:27:32 PM PST 23
Finished Nov 22 01:27:47 PM PST 23
Peak memory 195316 kb
Host smart-01d0152e-0ca6-4120-bc09-d802e28a5452
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83172688641738113162407319145251897344072202810290241664589099642567982924644 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig_mubi.83172688641738113162407319145251897344072202810290241664589099642567982924644
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.71567614317106170969591121983556848414273102804652896496698510910226371368087
Short name T462
Test name
Test status
Simulation time 35743529 ps
CPU time 0.63 seconds
Started Nov 22 01:27:54 PM PST 23
Finished Nov 22 01:28:03 PM PST 23
Peak memory 197880 kb
Host smart-eab04c18-9e87-4e54-85a6-3612c446d73d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71567614317106170969591121983556848414273102804652896496698510910226371368087 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.71567614317106170969591121983556848414273102804652896496698510910226371368087
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_stress_all.14423008843507992736377770571179637444782629449872401870648246980390428546653
Short name T1028
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.52 seconds
Started Nov 22 01:27:49 PM PST 23
Finished Nov 22 01:28:04 PM PST 23
Peak memory 201096 kb
Host smart-971f80a4-e0fa-4bff-855d-1c645ab53d99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14423008843507992736377770571179637444782629449872401870648246980390428546653 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.14423008843507992736377770571179637444782629449872401870648246980390428546653
Directory /workspace/40.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/40.pwrmgr_stress_all_with_rand_reset.115000169868303554569511764207201340029677244974988905453916328881911210133344
Short name T846
Test name
Test status
Simulation time 4441243999 ps
CPU time 10.98 seconds
Started Nov 22 01:28:22 PM PST 23
Finished Nov 22 01:28:36 PM PST 23
Peak memory 198852 kb
Host smart-7abad46a-435a-4be2-9882-c07e309bed8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115000169868303554569511
764207201340029677244974988905453916328881911210133344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all_with_rand_reset.1150
00169868303554569511764207201340029677244974988905453916328881911210133344
Directory /workspace/40.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup.20312423926709089133506970795882912598187487723921701634319457891534881836529
Short name T338
Test name
Test status
Simulation time 283777259 ps
CPU time 1.16 seconds
Started Nov 22 01:27:40 PM PST 23
Finished Nov 22 01:27:53 PM PST 23
Peak memory 200108 kb
Host smart-2d8271db-d6af-49f8-9433-183c8ce28209
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20312423926709089133506970795882912598187487723921701634319457891534881836529 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.20312423926709089133506970795882912598187487723921701634319457891534881836529
Directory /workspace/40.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup_reset.68610131431741956703193126430319064442025043044065897511088520846878746121763
Short name T156
Test name
Test status
Simulation time 325437640 ps
CPU time 1.34 seconds
Started Nov 22 01:27:37 PM PST 23
Finished Nov 22 01:27:50 PM PST 23
Peak memory 200548 kb
Host smart-044d52cf-972a-4672-9756-8e2aec8e1a44
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68610131431741956703193126430319064442025043044065897511088520846878746121763 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.68610131431741956703193126430319064442025043044065897511088520846878746121763
Directory /workspace/40.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.28127527323087273325039648771452698067679159478399747915409390635175103984494
Short name T801
Test name
Test status
Simulation time 51975542 ps
CPU time 0.8 seconds
Started Nov 22 01:27:45 PM PST 23
Finished Nov 22 01:27:56 PM PST 23
Peak memory 199200 kb
Host smart-2b6f0b3f-f09b-4010-9d72-81285d10f188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28127527323087273325039648771452698067679159478399747915409390635175103984494 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.pwrmgr_aborted_low_power.28127527323087273325039648771452698067679159478399747915409390635175103984494
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.110397906811443958852899742150556741478377976520584862337594308031948155005829
Short name T111
Test name
Test status
Simulation time 72403950 ps
CPU time 0.78 seconds
Started Nov 22 01:27:45 PM PST 23
Finished Nov 22 01:27:56 PM PST 23
Peak memory 198296 kb
Host smart-b7d0e104-10fe-409d-9a19-d909accf8ae4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110397906811443958852899742150556741478377976520584862337594308031948155005829 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_disable_rom_integrity_check.11039790681144395885289974215055674147837797652058486
2337594308031948155005829
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.77391217443532179484128785956379882873476951719597625402567910705796217043816
Short name T485
Test name
Test status
Simulation time 30368572 ps
CPU time 0.59 seconds
Started Nov 22 01:27:49 PM PST 23
Finished Nov 22 01:27:59 PM PST 23
Peak memory 195300 kb
Host smart-16c97b59-2d86-481e-b50c-df06d55c9724
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77391217443532179484128785956379882873476951719597625402567910705796217043816 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst_malfunc.77391217443532179484128785956379882873476951719597625402567910705796217043816
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.10236719787134458092534636446665967245391055788391169895613873553620787673557
Short name T434
Test name
Test status
Simulation time 39672069 ps
CPU time 0.59 seconds
Started Nov 22 01:28:39 PM PST 23
Finished Nov 22 01:28:46 PM PST 23
Peak memory 195332 kb
Host smart-dec70bd1-c9c3-4db0-8d26-75792fcee6cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10236719787134458092534636446665967245391055788391169895613873553620787673557 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.10236719787134458092534636446665967245391055788391169895613873553620787673557
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.107460440495512796775634724151542524383966540664494956618007483625142570170805
Short name T905
Test name
Test status
Simulation time 33172121 ps
CPU time 0.75 seconds
Started Nov 22 01:28:22 PM PST 23
Finished Nov 22 01:28:26 PM PST 23
Peak memory 194140 kb
Host smart-1f23d3ec-048a-4e53-b22f-6be6c6942364
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107460440495512796775634724151542524383966540664494956618007483625142570170805 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.107460440495512796775634724151542524383966540664494956618007483625142570170805
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.59353315114923721686456668290994508569832154668014298596406726932461556349744
Short name T974
Test name
Test status
Simulation time 49975558 ps
CPU time 0.68 seconds
Started Nov 22 01:27:45 PM PST 23
Finished Nov 22 01:27:56 PM PST 23
Peak memory 201388 kb
Host smart-39c62a4b-d2fa-4d85-b867-62d629ec16eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59353315114923721686456668290994508569832154668014298596406726932461556349744 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_invalid.59353315114923721686456668290994508569832154668014298596406726932461556349744
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_wakeup_race.59811783536632464869507067130890196575311111918759584860984762208562046063946
Short name T749
Test name
Test status
Simulation time 296241445 ps
CPU time 1.15 seconds
Started Nov 22 01:27:40 PM PST 23
Finished Nov 22 01:27:53 PM PST 23
Peak memory 200064 kb
Host smart-76d1d03c-beba-4610-83e5-8f9b3e321d28
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59811783536632464869507067130890196575311111918759584860984762208562046063946 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_wakeup_race.59811783536632464869507067130890196575311111918759584860984762208562046063946
Directory /workspace/41.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.52009956843420676744178642117743837443448204245124291149393175242180902245728
Short name T547
Test name
Test status
Simulation time 119707143 ps
CPU time 0.96 seconds
Started Nov 22 01:28:39 PM PST 23
Finished Nov 22 01:28:46 PM PST 23
Peak memory 199168 kb
Host smart-fab8ab78-ffef-4289-9e9f-75977e640215
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52009956843420676744178642117743837443448204245124291149393175242180902245728 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.52009956843420676744178642117743837443448204245124291149393175242180902245728
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.49709199492028768327626872104845015975076898256066748685920589407300271126493
Short name T708
Test name
Test status
Simulation time 108189378 ps
CPU time 0.84 seconds
Started Nov 22 01:27:54 PM PST 23
Finished Nov 22 01:28:03 PM PST 23
Peak memory 209500 kb
Host smart-c91a885a-2e51-457e-8426-1a4844ccc902
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49709199492028768327626872104845015975076898256066748685920589407300271126493 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.49709199492028768327626872104845015975076898256066748685920589407300271126493
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.28295579098685549359633968485793293225829356443996193977883667418306450301612
Short name T128
Test name
Test status
Simulation time 314830582 ps
CPU time 1.33 seconds
Started Nov 22 01:27:44 PM PST 23
Finished Nov 22 01:27:56 PM PST 23
Peak memory 199920 kb
Host smart-9ecef722-0a71-484e-aa2a-120b4cc3f091
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28295579098685549359633968485793293225829356443996193977883667418306450301612 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_ctrl_config_regwen.282955790986855493596339684857932932258293564439961939778
83667418306450301612
Directory /workspace/41.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.21233817690276304732691177170878961688841529658084017223308791027553278129330
Short name T991
Test name
Test status
Simulation time 919450745 ps
CPU time 2.91 seconds
Started Nov 22 01:27:48 PM PST 23
Finished Nov 22 01:28:00 PM PST 23
Peak memory 201256 kb
Host smart-1ef00b3c-d40e-44b5-bfc1-8e3777e69564
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212338176902763047326911771708789616888415296580840172233087
91027553278129330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.21233817690276304732691177
170878961688841529658084017223308791027553278129330
Directory /workspace/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2772500353257196064988732906717884909313382215828276664252205764252376889857
Short name T864
Test name
Test status
Simulation time 968503924 ps
CPU time 2.8 seconds
Started Nov 22 01:28:39 PM PST 23
Finished Nov 22 01:28:49 PM PST 23
Peak memory 201040 kb
Host smart-c0b09cba-0490-46f4-baec-bba270f4ed76
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27725003532571960649887329067178849093133822158282766642522
05764252376889857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2772500353257196064988732
906717884909313382215828276664252205764252376889857
Directory /workspace/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.66412159726734133082563574248206940676443909250652541744361135708586515794241
Short name T1024
Test name
Test status
Simulation time 91600225 ps
CPU time 1.06 seconds
Started Nov 22 01:28:22 PM PST 23
Finished Nov 22 01:28:26 PM PST 23
Peak memory 192704 kb
Host smart-2f08f8a9-27ab-4aa2-bf0b-448640025439
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66412159726734133082563574248206940676443909250652541744361135708586515794241 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig_mubi.66412159726734133082563574248206940676443909250652541744361135708586515794241
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.62239194001858662814678992749469693952253821896480702425815167689927227817122
Short name T565
Test name
Test status
Simulation time 35743529 ps
CPU time 0.66 seconds
Started Nov 22 01:27:48 PM PST 23
Finished Nov 22 01:27:58 PM PST 23
Peak memory 197884 kb
Host smart-82fb1d08-4c86-4b80-b6fe-e370814c1fa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62239194001858662814678992749469693952253821896480702425815167689927227817122 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.62239194001858662814678992749469693952253821896480702425815167689927227817122
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_stress_all.24528652705696220291377627751795156537019624340637048631740524820430958187424
Short name T585
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.63 seconds
Started Nov 22 01:27:43 PM PST 23
Finished Nov 22 01:27:59 PM PST 23
Peak memory 201268 kb
Host smart-54118beb-7d32-4415-8398-6fdb477a5aa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24528652705696220291377627751795156537019624340637048631740524820430958187424 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.24528652705696220291377627751795156537019624340637048631740524820430958187424
Directory /workspace/41.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/41.pwrmgr_stress_all_with_rand_reset.102548433750507574401178399939106903556797923060334567342109727806295305308639
Short name T849
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.19 seconds
Started Nov 22 01:27:34 PM PST 23
Finished Nov 22 01:27:59 PM PST 23
Peak memory 201452 kb
Host smart-67bb1c78-8dad-4a20-838b-d93776186eb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102548433750507574401178
399939106903556797923060334567342109727806295305308639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all_with_rand_reset.1025
48433750507574401178399939106903556797923060334567342109727806295305308639
Directory /workspace/41.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup.37288540961402499742638059221509850473217183593544828814116978509833099074063
Short name T803
Test name
Test status
Simulation time 283777259 ps
CPU time 1.32 seconds
Started Nov 22 01:28:22 PM PST 23
Finished Nov 22 01:28:26 PM PST 23
Peak memory 197472 kb
Host smart-812a10b0-acd1-401b-864b-a9cc86c48f4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37288540961402499742638059221509850473217183593544828814116978509833099074063 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.37288540961402499742638059221509850473217183593544828814116978509833099074063
Directory /workspace/41.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup_reset.55482272026035350016121808927437343045082238185141239511779920835232006606246
Short name T885
Test name
Test status
Simulation time 325437640 ps
CPU time 1.42 seconds
Started Nov 22 01:27:33 PM PST 23
Finished Nov 22 01:27:48 PM PST 23
Peak memory 200760 kb
Host smart-7c942af3-1992-4dac-94b0-ed9d8de29364
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55482272026035350016121808927437343045082238185141239511779920835232006606246 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.55482272026035350016121808927437343045082238185141239511779920835232006606246
Directory /workspace/41.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.88920757305592945874863746725856895585266548820717748835694857085174830434859
Short name T839
Test name
Test status
Simulation time 51975542 ps
CPU time 0.8 seconds
Started Nov 22 01:27:34 PM PST 23
Finished Nov 22 01:27:48 PM PST 23
Peak memory 199156 kb
Host smart-81c82ab0-67d0-4e3a-997d-dca9226fa7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88920757305592945874863746725856895585266548820717748835694857085174830434859 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.pwrmgr_aborted_low_power.88920757305592945874863746725856895585266548820717748835694857085174830434859
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.26457587460232645833149323899689375517705816323541969277970937610574530711296
Short name T828
Test name
Test status
Simulation time 72403950 ps
CPU time 0.77 seconds
Started Nov 22 01:27:46 PM PST 23
Finished Nov 22 01:27:57 PM PST 23
Peak memory 198128 kb
Host smart-a161b101-d1f3-45d0-ac54-32fbea640f30
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26457587460232645833149323899689375517705816323541969277970937610574530711296 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_disable_rom_integrity_check.264575874602326458331493238996893755177058163235419692
77970937610574530711296
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.25458594439821933558116904460421620813206165232700118269521908580871876554158
Short name T831
Test name
Test status
Simulation time 30368572 ps
CPU time 0.59 seconds
Started Nov 22 01:27:54 PM PST 23
Finished Nov 22 01:28:03 PM PST 23
Peak memory 195468 kb
Host smart-cf304ed3-7fc8-4d5c-a812-967a0f4806e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25458594439821933558116904460421620813206165232700118269521908580871876554158 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst_malfunc.25458594439821933558116904460421620813206165232700118269521908580871876554158
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.16452084550067615654848375483437130020633532258104763621732543809960825189757
Short name T733
Test name
Test status
Simulation time 39672069 ps
CPU time 0.6 seconds
Started Nov 22 01:27:32 PM PST 23
Finished Nov 22 01:27:47 PM PST 23
Peak memory 195444 kb
Host smart-5ade6469-42be-4e5a-8892-5689a190f504
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16452084550067615654848375483437130020633532258104763621732543809960825189757 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.16452084550067615654848375483437130020633532258104763621732543809960825189757
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.69260867566515585673499475571430731239348551663638821013910987146901833069187
Short name T960
Test name
Test status
Simulation time 33172121 ps
CPU time 0.58 seconds
Started Nov 22 01:27:36 PM PST 23
Finished Nov 22 01:27:49 PM PST 23
Peak memory 196840 kb
Host smart-8598a865-dae8-4ad0-a08c-0b5643f6d67e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69260867566515585673499475571430731239348551663638821013910987146901833069187 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.69260867566515585673499475571430731239348551663638821013910987146901833069187
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.59723423324737856530774099592412710480684054871931706570800847093042127830016
Short name T556
Test name
Test status
Simulation time 49975558 ps
CPU time 0.67 seconds
Started Nov 22 01:27:45 PM PST 23
Finished Nov 22 01:27:56 PM PST 23
Peak memory 201424 kb
Host smart-a01e39f9-8f20-4098-96f0-cd4ac05179ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59723423324737856530774099592412710480684054871931706570800847093042127830016 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_invalid.59723423324737856530774099592412710480684054871931706570800847093042127830016
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_wakeup_race.111135190689499227752058855143935663460367674388427291773001112862538797893909
Short name T851
Test name
Test status
Simulation time 296241445 ps
CPU time 1.19 seconds
Started Nov 22 01:27:46 PM PST 23
Finished Nov 22 01:27:57 PM PST 23
Peak memory 200100 kb
Host smart-bd165e4e-a1e8-424b-88d5-53d404d9ca28
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111135190689499227752058855143935663460367674388427291773001112862538797893909 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_wakeup_race.111135190689499227752058855143935663460367674388427291773001112862538797893909
Directory /workspace/42.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.8035552390027429550329434707562774820127759405075473375677329182041364907708
Short name T417
Test name
Test status
Simulation time 119707143 ps
CPU time 1.02 seconds
Started Nov 22 01:27:50 PM PST 23
Finished Nov 22 01:28:01 PM PST 23
Peak memory 199312 kb
Host smart-cbc78bf0-e145-4e63-83bd-e2c2fffb2ded
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8035552390027429550329434707562774820127759405075473375677329182041364907708 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.8035552390027429550329434707562774820127759405075473375677329182041364907708
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.111326145949485576112182677473938506131143398396036001977608387215320144385293
Short name T35
Test name
Test status
Simulation time 108189378 ps
CPU time 0.86 seconds
Started Nov 22 01:27:48 PM PST 23
Finished Nov 22 01:27:58 PM PST 23
Peak memory 209468 kb
Host smart-90b54327-3e98-4796-bb29-1e21123905cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111326145949485576112182677473938506131143398396036001977608387215320144385293 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.111326145949485576112182677473938506131143398396036001977608387215320144385293
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.53032097341586593317119391100798703892182458873459888480748477421907251066732
Short name T1013
Test name
Test status
Simulation time 314830582 ps
CPU time 1.36 seconds
Started Nov 22 01:27:38 PM PST 23
Finished Nov 22 01:27:52 PM PST 23
Peak memory 199996 kb
Host smart-a46fffde-66f7-4092-8f77-bdd530c59daa
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53032097341586593317119391100798703892182458873459888480748477421907251066732 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_ctrl_config_regwen.530320973415865933171193911007987038921824588734598884807
48477421907251066732
Directory /workspace/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.26043178988378218991611449812995425979025658686439125721727575421244347984617
Short name T1011
Test name
Test status
Simulation time 919450745 ps
CPU time 2.86 seconds
Started Nov 22 01:27:46 PM PST 23
Finished Nov 22 01:27:59 PM PST 23
Peak memory 201064 kb
Host smart-1556d57d-a32a-455f-90d0-d9e4f4191905
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260431789883782189916114498129954259790256586864391257217275
75421244347984617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.26043178988378218991611449
812995425979025658686439125721727575421244347984617
Directory /workspace/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.88154660690743198126089680552163666292226129215592990369649235791924133743803
Short name T722
Test name
Test status
Simulation time 968503924 ps
CPU time 2.81 seconds
Started Nov 22 01:27:56 PM PST 23
Finished Nov 22 01:28:06 PM PST 23
Peak memory 200968 kb
Host smart-76ebd67b-11da-4e69-ba7d-6df6416a9ec9
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88154660690743198126089680552163666292226129215592990369649
235791924133743803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.881546606907431981260896
80552163666292226129215592990369649235791924133743803
Directory /workspace/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.79502525145475169199768253918409832875805954709387882276549810886978092776984
Short name T1055
Test name
Test status
Simulation time 91600225 ps
CPU time 0.9 seconds
Started Nov 22 01:27:51 PM PST 23
Finished Nov 22 01:28:01 PM PST 23
Peak memory 195524 kb
Host smart-94e6d57e-f336-4f19-a4ce-62f02ad19de6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79502525145475169199768253918409832875805954709387882276549810886978092776984 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig_mubi.79502525145475169199768253918409832875805954709387882276549810886978092776984
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.87098162638952446618719853211443249356475381080474559171215778217330947717356
Short name T635
Test name
Test status
Simulation time 35743529 ps
CPU time 0.65 seconds
Started Nov 22 01:27:34 PM PST 23
Finished Nov 22 01:27:48 PM PST 23
Peak memory 197892 kb
Host smart-c0808391-254c-4a49-ac10-80c101e26772
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87098162638952446618719853211443249356475381080474559171215778217330947717356 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.87098162638952446618719853211443249356475381080474559171215778217330947717356
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all.58951574571210786242135155662719078332429296522445698392408366761720089500512
Short name T862
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.67 seconds
Started Nov 22 01:27:37 PM PST 23
Finished Nov 22 01:27:55 PM PST 23
Peak memory 201260 kb
Host smart-e6e06abb-04d3-40d9-b22b-bc4a8af6da89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58951574571210786242135155662719078332429296522445698392408366761720089500512 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.58951574571210786242135155662719078332429296522445698392408366761720089500512
Directory /workspace/42.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all_with_rand_reset.33952473480283807297703999556503837702303210604138993705760550668449091479655
Short name T615
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.18 seconds
Started Nov 22 01:27:38 PM PST 23
Finished Nov 22 01:28:01 PM PST 23
Peak memory 201448 kb
Host smart-f7197659-8ac7-47a5-b522-65fd9c94b78d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339524734802838072977039
99556503837702303210604138993705760550668449091479655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all_with_rand_reset.33952
473480283807297703999556503837702303210604138993705760550668449091479655
Directory /workspace/42.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup.35641259858570961195756385795765225396822399661556457253876741672189006568474
Short name T404
Test name
Test status
Simulation time 283777259 ps
CPU time 1.2 seconds
Started Nov 22 01:27:47 PM PST 23
Finished Nov 22 01:27:58 PM PST 23
Peak memory 199912 kb
Host smart-c8a08f2e-5946-45ba-b25c-a4d0a00838d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35641259858570961195756385795765225396822399661556457253876741672189006568474 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.35641259858570961195756385795765225396822399661556457253876741672189006568474
Directory /workspace/42.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup_reset.20327299283938301600677013851853150876675881947158550759371471831820241991160
Short name T967
Test name
Test status
Simulation time 325437640 ps
CPU time 1.36 seconds
Started Nov 22 01:27:39 PM PST 23
Finished Nov 22 01:27:52 PM PST 23
Peak memory 200768 kb
Host smart-2205f30d-470a-4b54-b1f3-6d5a179b157a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20327299283938301600677013851853150876675881947158550759371471831820241991160 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.20327299283938301600677013851853150876675881947158550759371471831820241991160
Directory /workspace/42.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.33562967386673873115879328655110796974501791863770173069289482530308533869650
Short name T787
Test name
Test status
Simulation time 51975542 ps
CPU time 0.79 seconds
Started Nov 22 01:27:37 PM PST 23
Finished Nov 22 01:27:50 PM PST 23
Peak memory 199144 kb
Host smart-882111da-15a8-4168-9200-6223fea5062c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33562967386673873115879328655110796974501791863770173069289482530308533869650 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.pwrmgr_aborted_low_power.33562967386673873115879328655110796974501791863770173069289482530308533869650
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.48672649754328114557607527121538076077261415702493622214248110108969376288661
Short name T405
Test name
Test status
Simulation time 72403950 ps
CPU time 0.76 seconds
Started Nov 22 01:27:47 PM PST 23
Finished Nov 22 01:27:58 PM PST 23
Peak memory 198128 kb
Host smart-9a2031bf-afc5-41a1-a059-c5864d257061
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48672649754328114557607527121538076077261415702493622214248110108969376288661 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_disable_rom_integrity_check.486726497543281145576075271215380760772614157024936222
14248110108969376288661
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.26299789990886945916622294853399589375810005093832673416247081435027520948957
Short name T818
Test name
Test status
Simulation time 30368572 ps
CPU time 0.59 seconds
Started Nov 22 01:27:45 PM PST 23
Finished Nov 22 01:27:55 PM PST 23
Peak memory 195460 kb
Host smart-07c184f8-64bf-4805-a9d4-fd4825b61a99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26299789990886945916622294853399589375810005093832673416247081435027520948957 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst_malfunc.26299789990886945916622294853399589375810005093832673416247081435027520948957
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.16431012213846748878064700198866074301258023849144874288664148426702168253657
Short name T700
Test name
Test status
Simulation time 39672069 ps
CPU time 0.61 seconds
Started Nov 22 01:27:49 PM PST 23
Finished Nov 22 01:27:59 PM PST 23
Peak memory 195504 kb
Host smart-b074a343-e3e6-4038-beb6-bc96998f8316
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16431012213846748878064700198866074301258023849144874288664148426702168253657 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.16431012213846748878064700198866074301258023849144874288664148426702168253657
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.115328298236430016417417649309761149489676718020858415399188996713276583493079
Short name T677
Test name
Test status
Simulation time 33172121 ps
CPU time 0.6 seconds
Started Nov 22 01:27:47 PM PST 23
Finished Nov 22 01:27:58 PM PST 23
Peak memory 196820 kb
Host smart-18240f7e-28dd-4448-8e8b-fda4c4b41163
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115328298236430016417417649309761149489676718020858415399188996713276583493079 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.115328298236430016417417649309761149489676718020858415399188996713276583493079
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.36286822842859082942911534374364366593985086508930103343061298832417596359660
Short name T41
Test name
Test status
Simulation time 49975558 ps
CPU time 0.66 seconds
Started Nov 22 01:27:35 PM PST 23
Finished Nov 22 01:27:49 PM PST 23
Peak memory 201404 kb
Host smart-2482d18f-e479-4f81-8f23-ccef47edc5a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36286822842859082942911534374364366593985086508930103343061298832417596359660 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_invalid.36286822842859082942911534374364366593985086508930103343061298832417596359660
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_wakeup_race.35371486706833097490603310404731436787246133976363462612607397295582390890515
Short name T720
Test name
Test status
Simulation time 296241445 ps
CPU time 1.2 seconds
Started Nov 22 01:27:35 PM PST 23
Finished Nov 22 01:27:50 PM PST 23
Peak memory 200176 kb
Host smart-810acf54-2c08-42c8-9e03-f7d454869971
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35371486706833097490603310404731436787246133976363462612607397295582390890515 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_wakeup_race.35371486706833097490603310404731436787246133976363462612607397295582390890515
Directory /workspace/43.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.73424351968701564110953247279471349652537047640886752676975661287665078617771
Short name T334
Test name
Test status
Simulation time 119707143 ps
CPU time 1.02 seconds
Started Nov 22 01:27:49 PM PST 23
Finished Nov 22 01:28:00 PM PST 23
Peak memory 199292 kb
Host smart-4d6b7274-7f7d-471f-8fd4-cdf00301728c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73424351968701564110953247279471349652537047640886752676975661287665078617771 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.73424351968701564110953247279471349652537047640886752676975661287665078617771
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.45291538999672649988378375568222186134654217812581380894014187204950271309087
Short name T446
Test name
Test status
Simulation time 108189378 ps
CPU time 0.87 seconds
Started Nov 22 01:27:46 PM PST 23
Finished Nov 22 01:27:56 PM PST 23
Peak memory 209516 kb
Host smart-578946e6-2f3a-415f-b76e-7684d41e9ebe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45291538999672649988378375568222186134654217812581380894014187204950271309087 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.45291538999672649988378375568222186134654217812581380894014187204950271309087
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.80053526842767994897095987111080202648923072114526248056480907719776115489953
Short name T1066
Test name
Test status
Simulation time 314830582 ps
CPU time 1.36 seconds
Started Nov 22 01:27:39 PM PST 23
Finished Nov 22 01:27:52 PM PST 23
Peak memory 199836 kb
Host smart-ecba3fc9-327d-4e8a-a1c9-2d1775467081
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80053526842767994897095987111080202648923072114526248056480907719776115489953 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_ctrl_config_regwen.800535268427679948970959871110802026489230721145262480564
80907719776115489953
Directory /workspace/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.87914327484443672812778151688785538770354426355747803928156326812570707910397
Short name T567
Test name
Test status
Simulation time 919450745 ps
CPU time 3.01 seconds
Started Nov 22 01:27:47 PM PST 23
Finished Nov 22 01:28:00 PM PST 23
Peak memory 201068 kb
Host smart-ff48a6fd-40f4-45a5-8979-799cc557aa38
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879143274844436728127781516887855387703544263557478039281563
26812570707910397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.87914327484443672812778151
688785538770354426355747803928156326812570707910397
Directory /workspace/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.58661578359316708594652750143545635675212447495360893382231248210034257648633
Short name T889
Test name
Test status
Simulation time 968503924 ps
CPU time 3.06 seconds
Started Nov 22 01:27:46 PM PST 23
Finished Nov 22 01:27:58 PM PST 23
Peak memory 201224 kb
Host smart-ee99c125-ee58-4dfb-8d8a-2b3c5ff5d25f
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58661578359316708594652750143545635675212447495360893382231
248210034257648633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.586615783593167085946527
50143545635675212447495360893382231248210034257648633
Directory /workspace/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.90423642019324762288046705286008870340808812447951369608583867798655386654166
Short name T138
Test name
Test status
Simulation time 91600225 ps
CPU time 0.89 seconds
Started Nov 22 01:27:54 PM PST 23
Finished Nov 22 01:28:03 PM PST 23
Peak memory 195340 kb
Host smart-e7cb2fc5-3a71-438d-b1c3-d84f0dc3b574
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90423642019324762288046705286008870340808812447951369608583867798655386654166 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig_mubi.90423642019324762288046705286008870340808812447951369608583867798655386654166
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.114981242641709463418818515872877922853358511654133950621222251625589715514113
Short name T982
Test name
Test status
Simulation time 35743529 ps
CPU time 0.63 seconds
Started Nov 22 01:27:34 PM PST 23
Finished Nov 22 01:27:48 PM PST 23
Peak memory 197856 kb
Host smart-7a796cc5-0058-4b59-9d91-5761fd2a1c3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114981242641709463418818515872877922853358511654133950621222251625589715514113 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.114981242641709463418818515872877922853358511654133950621222251625589715514113
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_stress_all.21102490534059556314938616218338429696297226240989616955789173238454545148050
Short name T808
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.85 seconds
Started Nov 22 01:27:41 PM PST 23
Finished Nov 22 01:27:58 PM PST 23
Peak memory 201272 kb
Host smart-f3cd6432-efb6-41a3-87e8-9522f763bcb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21102490534059556314938616218338429696297226240989616955789173238454545148050 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all.21102490534059556314938616218338429696297226240989616955789173238454545148050
Directory /workspace/43.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/43.pwrmgr_stress_all_with_rand_reset.60372671920127528878110865642712496781158016958531485192861990172529963204726
Short name T107
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.39 seconds
Started Nov 22 01:27:50 PM PST 23
Finished Nov 22 01:28:11 PM PST 23
Peak memory 201464 kb
Host smart-8218ec1a-5cdd-46ed-8eee-0a5d830939f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603726719201275288781108
65642712496781158016958531485192861990172529963204726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all_with_rand_reset.60372
671920127528878110865642712496781158016958531485192861990172529963204726
Directory /workspace/43.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup.90584446913768721986841018791287856028548253935503374062835654609888059519212
Short name T478
Test name
Test status
Simulation time 283777259 ps
CPU time 1.21 seconds
Started Nov 22 01:27:52 PM PST 23
Finished Nov 22 01:28:03 PM PST 23
Peak memory 200040 kb
Host smart-51ff2aed-f535-4fcc-960e-a7e953766eb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90584446913768721986841018791287856028548253935503374062835654609888059519212 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.90584446913768721986841018791287856028548253935503374062835654609888059519212
Directory /workspace/43.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup_reset.59068467188844333949219254344403471298405671382748347039993588315069803681702
Short name T807
Test name
Test status
Simulation time 325437640 ps
CPU time 1.36 seconds
Started Nov 22 01:27:52 PM PST 23
Finished Nov 22 01:28:02 PM PST 23
Peak memory 200684 kb
Host smart-298a36ea-9e82-4eda-b377-9a65effbbb80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59068467188844333949219254344403471298405671382748347039993588315069803681702 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.59068467188844333949219254344403471298405671382748347039993588315069803681702
Directory /workspace/43.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.46682193319256148506716104456167126036996114424008252902001835432932244920048
Short name T693
Test name
Test status
Simulation time 51975542 ps
CPU time 0.81 seconds
Started Nov 22 01:28:00 PM PST 23
Finished Nov 22 01:28:07 PM PST 23
Peak memory 199104 kb
Host smart-cf60b29c-45ae-4325-996c-ab3a0beb8f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46682193319256148506716104456167126036996114424008252902001835432932244920048 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 44.pwrmgr_aborted_low_power.46682193319256148506716104456167126036996114424008252902001835432932244920048
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.73341744523310385159043532060448507598295160459907961476143000846098300446791
Short name T992
Test name
Test status
Simulation time 72403950 ps
CPU time 0.81 seconds
Started Nov 22 01:28:08 PM PST 23
Finished Nov 22 01:28:11 PM PST 23
Peak memory 198168 kb
Host smart-04a4bafd-6b9a-4c20-9584-4b8a53d85592
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73341744523310385159043532060448507598295160459907961476143000846098300446791 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_disable_rom_integrity_check.733417445233103851590435320604485075982951604599079614
76143000846098300446791
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.23123352104112991762830829412571391243050130324041754376435548533368382052023
Short name T432
Test name
Test status
Simulation time 30368572 ps
CPU time 0.62 seconds
Started Nov 22 01:28:25 PM PST 23
Finished Nov 22 01:28:27 PM PST 23
Peak memory 195404 kb
Host smart-95371fb7-d4b0-489d-a2c9-c61f6c6db1a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23123352104112991762830829412571391243050130324041754376435548533368382052023 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst_malfunc.23123352104112991762830829412571391243050130324041754376435548533368382052023
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.10290981882264588342244575243105750577376730455100782637452655825773167535554
Short name T691
Test name
Test status
Simulation time 39672069 ps
CPU time 0.64 seconds
Started Nov 22 01:27:59 PM PST 23
Finished Nov 22 01:28:06 PM PST 23
Peak memory 195492 kb
Host smart-27fa8b25-c48b-4eb1-bd6e-2aaea0a49068
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10290981882264588342244575243105750577376730455100782637452655825773167535554 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.10290981882264588342244575243105750577376730455100782637452655825773167535554
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.78364857588471612822592294653512606635776405376399843555220995926686355369492
Short name T371
Test name
Test status
Simulation time 33172121 ps
CPU time 0.6 seconds
Started Nov 22 01:27:59 PM PST 23
Finished Nov 22 01:28:06 PM PST 23
Peak memory 196824 kb
Host smart-8c55147d-e0f5-4ea8-99a2-259fcdcc9824
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78364857588471612822592294653512606635776405376399843555220995926686355369492 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.78364857588471612822592294653512606635776405376399843555220995926686355369492
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.23137167426401957793648280441159686238361676462332087335915544485752021553875
Short name T443
Test name
Test status
Simulation time 49975558 ps
CPU time 0.72 seconds
Started Nov 22 01:28:39 PM PST 23
Finished Nov 22 01:28:46 PM PST 23
Peak memory 201408 kb
Host smart-6a0b48f9-866f-4e77-8c77-bc500b156772
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23137167426401957793648280441159686238361676462332087335915544485752021553875 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_invalid.23137167426401957793648280441159686238361676462332087335915544485752021553875
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_wakeup_race.68022542752068841025905645429406898162379987582162496279845928688584308868642
Short name T863
Test name
Test status
Simulation time 296241445 ps
CPU time 1.22 seconds
Started Nov 22 01:27:50 PM PST 23
Finished Nov 22 01:28:01 PM PST 23
Peak memory 200084 kb
Host smart-9cb7dc25-6acd-4dd4-89d8-950f7971f30d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68022542752068841025905645429406898162379987582162496279845928688584308868642 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_wakeup_race.68022542752068841025905645429406898162379987582162496279845928688584308868642
Directory /workspace/44.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.37009459233659118677237701799364705201356168442137482570958207474917984539426
Short name T771
Test name
Test status
Simulation time 119707143 ps
CPU time 1.03 seconds
Started Nov 22 01:27:49 PM PST 23
Finished Nov 22 01:28:00 PM PST 23
Peak memory 199340 kb
Host smart-b1abbf27-47d8-4870-84c0-cf10d5c27444
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37009459233659118677237701799364705201356168442137482570958207474917984539426 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.37009459233659118677237701799364705201356168442137482570958207474917984539426
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.110997973501167178067039658955455523294258440117966800115361777599613518016578
Short name T1067
Test name
Test status
Simulation time 108189378 ps
CPU time 0.94 seconds
Started Nov 22 01:28:24 PM PST 23
Finished Nov 22 01:28:27 PM PST 23
Peak memory 209548 kb
Host smart-b4377054-f5f4-47c4-8610-53c65b9bea08
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110997973501167178067039658955455523294258440117966800115361777599613518016578 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.110997973501167178067039658955455523294258440117966800115361777599613518016578
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.5395694042726984975624977686357594220790268502438463779154481092974295925768
Short name T50
Test name
Test status
Simulation time 314830582 ps
CPU time 1.31 seconds
Started Nov 22 01:27:55 PM PST 23
Finished Nov 22 01:28:04 PM PST 23
Peak memory 199916 kb
Host smart-d253149e-6811-437b-a8c9-2bd04d713abc
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5395694042726984975624977686357594220790268502438463779154481092974295925768 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_ctrl_config_regwen.5395694042726984975624977686357594220790268502438463779154
481092974295925768
Directory /workspace/44.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.90124096079407337177650829611340367554130284865025894869739109710668384834529
Short name T449
Test name
Test status
Simulation time 919450745 ps
CPU time 2.87 seconds
Started Nov 22 01:28:40 PM PST 23
Finished Nov 22 01:28:50 PM PST 23
Peak memory 201264 kb
Host smart-3884b27f-de50-4dab-a1d1-c085836d307b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901240960794073371776508296113403675541302848650258948697391
09710668384834529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.90124096079407337177650829
611340367554130284865025894869739109710668384834529
Directory /workspace/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.51392288908865408287786925193961072795731677245168949644509571647919418188568
Short name T886
Test name
Test status
Simulation time 968503924 ps
CPU time 3.09 seconds
Started Nov 22 01:27:55 PM PST 23
Finished Nov 22 01:28:06 PM PST 23
Peak memory 201200 kb
Host smart-ab154d9d-f1a7-43da-8381-cd04b89bd457
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51392288908865408287786925193961072795731677245168949644509
571647919418188568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.513922889088654082877869
25193961072795731677245168949644509571647919418188568
Directory /workspace/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.23341712867927142500325408684060423824677472124581809928016680212082698801066
Short name T782
Test name
Test status
Simulation time 91600225 ps
CPU time 0.89 seconds
Started Nov 22 01:27:54 PM PST 23
Finished Nov 22 01:28:03 PM PST 23
Peak memory 195500 kb
Host smart-362b95b7-63af-4ce9-85d2-de76c13745df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23341712867927142500325408684060423824677472124581809928016680212082698801066 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig_mubi.23341712867927142500325408684060423824677472124581809928016680212082698801066
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.48075807298657758240484284166981813373958008667560616271166742214450333751329
Short name T900
Test name
Test status
Simulation time 35743529 ps
CPU time 0.64 seconds
Started Nov 22 01:27:38 PM PST 23
Finished Nov 22 01:27:51 PM PST 23
Peak memory 197896 kb
Host smart-5eeb5760-a0d1-426b-838c-22f88ce83d51
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48075807298657758240484284166981813373958008667560616271166742214450333751329 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.48075807298657758240484284166981813373958008667560616271166742214450333751329
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_stress_all.87567914266063297141046904338413042711009920067463779200337516192692328698988
Short name T412
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.54 seconds
Started Nov 22 01:28:38 PM PST 23
Finished Nov 22 01:28:47 PM PST 23
Peak memory 201268 kb
Host smart-bbf0718a-8ca2-44bc-b8f2-a9a5fdefed9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87567914266063297141046904338413042711009920067463779200337516192692328698988 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all.87567914266063297141046904338413042711009920067463779200337516192692328698988
Directory /workspace/44.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/44.pwrmgr_stress_all_with_rand_reset.52286893107500359637212812323956204710461616039032889061967565647294344763131
Short name T791
Test name
Test status
Simulation time 4441243999 ps
CPU time 10.41 seconds
Started Nov 22 01:28:06 PM PST 23
Finished Nov 22 01:28:20 PM PST 23
Peak memory 201288 kb
Host smart-9f76490e-60e9-4163-aa49-baed3cb7ccb2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522868931075003596372128
12323956204710461616039032889061967565647294344763131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all_with_rand_reset.52286
893107500359637212812323956204710461616039032889061967565647294344763131
Directory /workspace/44.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup.46500579583852222387678380886918846120099242878611035656675656808331158343708
Short name T1059
Test name
Test status
Simulation time 283777259 ps
CPU time 1.23 seconds
Started Nov 22 01:28:04 PM PST 23
Finished Nov 22 01:28:10 PM PST 23
Peak memory 200100 kb
Host smart-67fe74d7-0b01-4762-9388-fd4be791aa42
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46500579583852222387678380886918846120099242878611035656675656808331158343708 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.46500579583852222387678380886918846120099242878611035656675656808331158343708
Directory /workspace/44.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup_reset.105865727917036912712821832053938718816687751282934129600699913793085068799175
Short name T426
Test name
Test status
Simulation time 325437640 ps
CPU time 1.43 seconds
Started Nov 22 01:28:02 PM PST 23
Finished Nov 22 01:28:09 PM PST 23
Peak memory 200784 kb
Host smart-33ea2b93-aa02-4c8c-b9b0-f815b49966dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105865727917036912712821832053938718816687751282934129600699913793085068799175 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.105865727917036912712821832053938718816687751282934129600699913793085068799175
Directory /workspace/44.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.61287626518858428059315949583950863592066970709030267915335396815672383157197
Short name T1042
Test name
Test status
Simulation time 51975542 ps
CPU time 0.83 seconds
Started Nov 22 01:27:57 PM PST 23
Finished Nov 22 01:28:05 PM PST 23
Peak memory 199108 kb
Host smart-fc461350-4a13-49cf-a457-e613cfd78880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61287626518858428059315949583950863592066970709030267915335396815672383157197 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.pwrmgr_aborted_low_power.61287626518858428059315949583950863592066970709030267915335396815672383157197
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.19899893020233265951845917518116353416879517592148233940198326613620686913427
Short name T531
Test name
Test status
Simulation time 72403950 ps
CPU time 0.74 seconds
Started Nov 22 01:27:56 PM PST 23
Finished Nov 22 01:28:04 PM PST 23
Peak memory 198152 kb
Host smart-f87ce670-0635-4574-8441-623e43f08614
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19899893020233265951845917518116353416879517592148233940198326613620686913427 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_disable_rom_integrity_check.198998930202332659518459175181163534168795175921482339
40198326613620686913427
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.86174398784759864804291678433664988112211710014624417430557797516907924574267
Short name T877
Test name
Test status
Simulation time 30368572 ps
CPU time 0.61 seconds
Started Nov 22 01:27:59 PM PST 23
Finished Nov 22 01:28:06 PM PST 23
Peak memory 195424 kb
Host smart-33d40e08-bb98-408f-a0f0-f6664440b9e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86174398784759864804291678433664988112211710014624417430557797516907924574267 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst_malfunc.86174398784759864804291678433664988112211710014624417430557797516907924574267
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.77279015878046425846289649089157787869298030308166235737874169320960229508723
Short name T906
Test name
Test status
Simulation time 39672069 ps
CPU time 0.65 seconds
Started Nov 22 01:28:02 PM PST 23
Finished Nov 22 01:28:08 PM PST 23
Peak memory 195480 kb
Host smart-4160cd16-536d-4f1b-aea1-ee758625fd3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77279015878046425846289649089157787869298030308166235737874169320960229508723 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.77279015878046425846289649089157787869298030308166235737874169320960229508723
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.445012714505322638625566311118012180963023169231705582977915949466259254484
Short name T374
Test name
Test status
Simulation time 33172121 ps
CPU time 0.6 seconds
Started Nov 22 01:28:00 PM PST 23
Finished Nov 22 01:28:07 PM PST 23
Peak memory 196892 kb
Host smart-d07aa8f9-e2cf-4872-ad0b-04835184a526
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445012714505322638625566311118012180963023169231705582977915949466259254484 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.445012714505322638625566311118012180963023169231705582977915949466259254484
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.33467407916412547184294948924600621657230568220926449201218422858736069601536
Short name T757
Test name
Test status
Simulation time 49975558 ps
CPU time 0.68 seconds
Started Nov 22 01:27:54 PM PST 23
Finished Nov 22 01:28:03 PM PST 23
Peak memory 201376 kb
Host smart-8e5bc56d-4c5a-498b-8766-9ed560a0da4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33467407916412547184294948924600621657230568220926449201218422858736069601536 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_invalid.33467407916412547184294948924600621657230568220926449201218422858736069601536
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_wakeup_race.69025390305947585752506690600288769264740485335914543270762438162093012140521
Short name T983
Test name
Test status
Simulation time 296241445 ps
CPU time 1.18 seconds
Started Nov 22 01:28:37 PM PST 23
Finished Nov 22 01:28:41 PM PST 23
Peak memory 200100 kb
Host smart-5e3a5642-d98f-4238-83cc-8acb160a5dbc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69025390305947585752506690600288769264740485335914543270762438162093012140521 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_wakeup_race.69025390305947585752506690600288769264740485335914543270762438162093012140521
Directory /workspace/45.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.25235474390434090391002493427845352776117549352311484316387264342036604851463
Short name T297
Test name
Test status
Simulation time 119707143 ps
CPU time 1.06 seconds
Started Nov 22 01:28:09 PM PST 23
Finished Nov 22 01:28:13 PM PST 23
Peak memory 199328 kb
Host smart-5dfff71b-7c55-43b6-9578-80b9d7d19f74
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25235474390434090391002493427845352776117549352311484316387264342036604851463 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.25235474390434090391002493427845352776117549352311484316387264342036604851463
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.35019354730595856829068729455844796362116588657030326850877763789720563244299
Short name T524
Test name
Test status
Simulation time 108189378 ps
CPU time 0.84 seconds
Started Nov 22 01:27:56 PM PST 23
Finished Nov 22 01:28:05 PM PST 23
Peak memory 209468 kb
Host smart-0806062d-d3a1-4694-91f8-c021176e1519
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35019354730595856829068729455844796362116588657030326850877763789720563244299 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.35019354730595856829068729455844796362116588657030326850877763789720563244299
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.33480959547647155686313651394818309921807702116703638681953036899198249530190
Short name T653
Test name
Test status
Simulation time 314830582 ps
CPU time 1.36 seconds
Started Nov 22 01:28:11 PM PST 23
Finished Nov 22 01:28:16 PM PST 23
Peak memory 199932 kb
Host smart-8584886c-e188-4d42-af76-6c244483b0a2
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33480959547647155686313651394818309921807702116703638681953036899198249530190 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_ctrl_config_regwen.334809595476471556863136513948183099218077021167036386819
53036899198249530190
Directory /workspace/45.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.78273108396269123429843621530912647107681932868947958799448611247724217344036
Short name T890
Test name
Test status
Simulation time 919450745 ps
CPU time 2.82 seconds
Started Nov 22 01:28:05 PM PST 23
Finished Nov 22 01:28:12 PM PST 23
Peak memory 201104 kb
Host smart-5e206bbc-05c0-4935-be47-bb7391944c5e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782731083962691234298436215309126471076819328689479587994486
11247724217344036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.78273108396269123429843621
530912647107681932868947958799448611247724217344036
Directory /workspace/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.95464784447699438333892752685160815235475827592066568092229283861134787256620
Short name T317
Test name
Test status
Simulation time 968503924 ps
CPU time 3.01 seconds
Started Nov 22 01:28:35 PM PST 23
Finished Nov 22 01:28:43 PM PST 23
Peak memory 201192 kb
Host smart-a8ba0f78-51c0-436e-9fa9-8d1bf9e6d5a8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95464784447699438333892752685160815235475827592066568092229
283861134787256620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.954647844476994383338927
52685160815235475827592066568092229283861134787256620
Directory /workspace/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.85901410985804883794192890991539914733715356764462493482630247791233869394050
Short name T152
Test name
Test status
Simulation time 91600225 ps
CPU time 0.96 seconds
Started Nov 22 01:28:05 PM PST 23
Finished Nov 22 01:28:10 PM PST 23
Peak memory 195520 kb
Host smart-d6f50b75-b76f-4dc1-93b2-ed7c437eefb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85901410985804883794192890991539914733715356764462493482630247791233869394050 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig_mubi.85901410985804883794192890991539914733715356764462493482630247791233869394050
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.88652391970037588947500087003741806221155041710020322551082785421537373885033
Short name T150
Test name
Test status
Simulation time 35743529 ps
CPU time 0.64 seconds
Started Nov 22 01:28:11 PM PST 23
Finished Nov 22 01:28:15 PM PST 23
Peak memory 197716 kb
Host smart-00d4e967-0006-40da-8fa1-1c736b16b498
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88652391970037588947500087003741806221155041710020322551082785421537373885033 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.88652391970037588947500087003741806221155041710020322551082785421537373885033
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_stress_all.16389875891280709221256380969479669089432545579150197619289221890384483096650
Short name T940
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.76 seconds
Started Nov 22 01:28:09 PM PST 23
Finished Nov 22 01:28:18 PM PST 23
Peak memory 201256 kb
Host smart-56b19e02-c728-4942-9711-2e227bee7166
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16389875891280709221256380969479669089432545579150197619289221890384483096650 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all.16389875891280709221256380969479669089432545579150197619289221890384483096650
Directory /workspace/45.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/45.pwrmgr_stress_all_with_rand_reset.91910363817260881561918647949455621025263177652819816613797365294456418706452
Short name T104
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.58 seconds
Started Nov 22 01:28:01 PM PST 23
Finished Nov 22 01:28:19 PM PST 23
Peak memory 201452 kb
Host smart-b6ea4b46-d5f2-4cc5-b5e5-951866006708
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919103638172608815619186
47949455621025263177652819816613797365294456418706452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all_with_rand_reset.91910
363817260881561918647949455621025263177652819816613797365294456418706452
Directory /workspace/45.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup.109907731814075213343684211436780244006798911186315594432992176400933519882756
Short name T492
Test name
Test status
Simulation time 283777259 ps
CPU time 1.17 seconds
Started Nov 22 01:28:08 PM PST 23
Finished Nov 22 01:28:12 PM PST 23
Peak memory 199916 kb
Host smart-70dcb491-baac-4d32-b77d-3758cc0cea6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109907731814075213343684211436780244006798911186315594432992176400933519882756 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup.109907731814075213343684211436780244006798911186315594432992176400933519882756
Directory /workspace/45.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup_reset.87506291440614384203818669216023121743811399167560787715523742973135544373461
Short name T142
Test name
Test status
Simulation time 325437640 ps
CPU time 1.33 seconds
Started Nov 22 01:28:42 PM PST 23
Finished Nov 22 01:28:50 PM PST 23
Peak memory 200780 kb
Host smart-3b5e1dda-b0f5-4e21-b29c-7c519b612367
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87506291440614384203818669216023121743811399167560787715523742973135544373461 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.87506291440614384203818669216023121743811399167560787715523742973135544373461
Directory /workspace/45.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.41069178913807600201227918227162651301803485195969464390445445530559582769456
Short name T357
Test name
Test status
Simulation time 51975542 ps
CPU time 0.79 seconds
Started Nov 22 01:28:01 PM PST 23
Finished Nov 22 01:28:08 PM PST 23
Peak memory 199032 kb
Host smart-e32d9c5d-4737-459d-98ab-9cf64df0e213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41069178913807600201227918227162651301803485195969464390445445530559582769456 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.pwrmgr_aborted_low_power.41069178913807600201227918227162651301803485195969464390445445530559582769456
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.72768581580539009679665004881931499137811482939693803974011802189007166718695
Short name T713
Test name
Test status
Simulation time 72403950 ps
CPU time 0.76 seconds
Started Nov 22 01:27:55 PM PST 23
Finished Nov 22 01:28:04 PM PST 23
Peak memory 198268 kb
Host smart-300d080f-9211-425f-846f-f09620c1a3d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72768581580539009679665004881931499137811482939693803974011802189007166718695 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disable_rom_integrity_check.727685815805390096796650048819314991378114829396938039
74011802189007166718695
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.3494671565513592461097347792667112953765467640535417889691838721886604928072
Short name T697
Test name
Test status
Simulation time 30368572 ps
CPU time 0.59 seconds
Started Nov 22 01:27:57 PM PST 23
Finished Nov 22 01:28:04 PM PST 23
Peak memory 195488 kb
Host smart-3097fb85-f366-4f5f-a519-a69784e7aa93
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494671565513592461097347792667112953765467640535417889691838721886604928072 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst_malfunc.3494671565513592461097347792667112953765467640535417889691838721886604928072
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.21594398541713552862157679617977331805956659865123688903138038255655249095544
Short name T303
Test name
Test status
Simulation time 39672069 ps
CPU time 0.62 seconds
Started Nov 22 01:28:01 PM PST 23
Finished Nov 22 01:28:08 PM PST 23
Peak memory 195468 kb
Host smart-95da63a7-d974-469b-a7f5-5016414e76da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21594398541713552862157679617977331805956659865123688903138038255655249095544 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.21594398541713552862157679617977331805956659865123688903138038255655249095544
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.105845517960909810531401883148868823700600129385575499763713968387293968235641
Short name T174
Test name
Test status
Simulation time 33172121 ps
CPU time 0.6 seconds
Started Nov 22 01:28:02 PM PST 23
Finished Nov 22 01:28:08 PM PST 23
Peak memory 196876 kb
Host smart-b42b8ca7-ebd1-443c-adec-6c77bca7ff6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105845517960909810531401883148868823700600129385575499763713968387293968235641 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.105845517960909810531401883148868823700600129385575499763713968387293968235641
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.98679792303538081503694650375461960039330574683997724878868198677306376082928
Short name T579
Test name
Test status
Simulation time 49975558 ps
CPU time 0.68 seconds
Started Nov 22 01:28:36 PM PST 23
Finished Nov 22 01:28:40 PM PST 23
Peak memory 201404 kb
Host smart-a5698741-8cab-46e3-802a-afc2eca87aa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98679792303538081503694650375461960039330574683997724878868198677306376082928 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_invalid.98679792303538081503694650375461960039330574683997724878868198677306376082928
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_wakeup_race.54143051595540988485066267863449674993177604107309567821817720908343898373378
Short name T844
Test name
Test status
Simulation time 296241445 ps
CPU time 1.24 seconds
Started Nov 22 01:28:02 PM PST 23
Finished Nov 22 01:28:09 PM PST 23
Peak memory 200120 kb
Host smart-d8a77c66-d254-49c9-b98c-2b3ae8e4384f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54143051595540988485066267863449674993177604107309567821817720908343898373378 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_wakeup_race.54143051595540988485066267863449674993177604107309567821817720908343898373378
Directory /workspace/46.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.55947942571661163107955721677560597324756263604815311243001834602581197488910
Short name T947
Test name
Test status
Simulation time 119707143 ps
CPU time 1.11 seconds
Started Nov 22 01:28:34 PM PST 23
Finished Nov 22 01:28:41 PM PST 23
Peak memory 199276 kb
Host smart-345f4fdf-9a86-4a1a-8ae4-0f5a1a532629
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55947942571661163107955721677560597324756263604815311243001834602581197488910 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.55947942571661163107955721677560597324756263604815311243001834602581197488910
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.31609512055639796166408744765601956082680194899803431934827756790382703306741
Short name T796
Test name
Test status
Simulation time 108189378 ps
CPU time 0.92 seconds
Started Nov 22 01:27:57 PM PST 23
Finished Nov 22 01:28:05 PM PST 23
Peak memory 209500 kb
Host smart-ea7f3900-9c92-4a11-8e1c-ab28ec5d2a06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31609512055639796166408744765601956082680194899803431934827756790382703306741 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.31609512055639796166408744765601956082680194899803431934827756790382703306741
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.37499486495812358386552079975884639279257126176042645698804971762496037213273
Short name T302
Test name
Test status
Simulation time 314830582 ps
CPU time 1.37 seconds
Started Nov 22 01:28:02 PM PST 23
Finished Nov 22 01:28:09 PM PST 23
Peak memory 199784 kb
Host smart-c47fc117-9b2c-4ed8-8917-20b019ac9aee
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37499486495812358386552079975884639279257126176042645698804971762496037213273 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_ctrl_config_regwen.374994864958123583865520799758846392792571261760426456988
04971762496037213273
Directory /workspace/46.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.65218320040078781312440578398397088709231967531616512608704941759682780748388
Short name T384
Test name
Test status
Simulation time 919450745 ps
CPU time 3 seconds
Started Nov 22 01:28:09 PM PST 23
Finished Nov 22 01:28:14 PM PST 23
Peak memory 201148 kb
Host smart-428cee50-5994-4df6-bf96-9bb550b07e40
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652183200400787813124405783983970887092319675316165126087049
41759682780748388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.65218320040078781312440578
398397088709231967531616512608704941759682780748388
Directory /workspace/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.14454285353786760154200737683792698015285733190982991611209536764141216479307
Short name T952
Test name
Test status
Simulation time 968503924 ps
CPU time 3.18 seconds
Started Nov 22 01:28:01 PM PST 23
Finished Nov 22 01:28:10 PM PST 23
Peak memory 201200 kb
Host smart-b44c72b8-cdf4-4288-8553-cd50c24051d9
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14454285353786760154200737683792698015285733190982991611209
536764141216479307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.144542853537867601542007
37683792698015285733190982991611209536764141216479307
Directory /workspace/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.100738707015589503886148266058171351806647207147367283144853010571518937054548
Short name T1010
Test name
Test status
Simulation time 91600225 ps
CPU time 0.92 seconds
Started Nov 22 01:27:57 PM PST 23
Finished Nov 22 01:28:05 PM PST 23
Peak memory 195484 kb
Host smart-44426b07-4edf-4e77-b036-db90f35e2416
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100738707015589503886148266058171351806647207147367283144853010571518937054548 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig_mubi.100738707015589503886148266058171351806647207147367283144853010571518937054548
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.5146323060922309970240905111913573266780746792496783171404011171456370274723
Short name T538
Test name
Test status
Simulation time 35743529 ps
CPU time 0.66 seconds
Started Nov 22 01:28:02 PM PST 23
Finished Nov 22 01:28:08 PM PST 23
Peak memory 197840 kb
Host smart-a4df9d2f-6fe0-4adb-a2d3-ec7bf353cde1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5146323060922309970240905111913573266780746792496783171404011171456370274723 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.5146323060922309970240905111913573266780746792496783171404011171456370274723
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_stress_all.55070389509421884279167869846095993066105364293304136342596523905470448094174
Short name T804
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.53 seconds
Started Nov 22 01:28:00 PM PST 23
Finished Nov 22 01:28:12 PM PST 23
Peak memory 201180 kb
Host smart-9a5ff332-3dce-4b4c-9991-de1703ac9c8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55070389509421884279167869846095993066105364293304136342596523905470448094174 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all.55070389509421884279167869846095993066105364293304136342596523905470448094174
Directory /workspace/46.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/46.pwrmgr_stress_all_with_rand_reset.26502377436051539595656614480499588222535553201190320020025666373319340095305
Short name T922
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.97 seconds
Started Nov 22 01:28:02 PM PST 23
Finished Nov 22 01:28:20 PM PST 23
Peak memory 201488 kb
Host smart-fe7b7e5e-0471-4c17-b442-7a134cfe98f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265023774360515395956566
14480499588222535553201190320020025666373319340095305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all_with_rand_reset.26502
377436051539595656614480499588222535553201190320020025666373319340095305
Directory /workspace/46.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup.3752306431335101699404309732219019092250208902400202626372536217170475713935
Short name T891
Test name
Test status
Simulation time 283777259 ps
CPU time 1.22 seconds
Started Nov 22 01:28:01 PM PST 23
Finished Nov 22 01:28:08 PM PST 23
Peak memory 199964 kb
Host smart-65063a45-e2da-4b59-a034-b498465c19bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752306431335101699404309732219019092250208902400202626372536217170475713935 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.3752306431335101699404309732219019092250208902400202626372536217170475713935
Directory /workspace/46.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup_reset.60737749710356888644013695031082734697006407171721439141518191598802558086202
Short name T937
Test name
Test status
Simulation time 325437640 ps
CPU time 1.4 seconds
Started Nov 22 01:27:56 PM PST 23
Finished Nov 22 01:28:05 PM PST 23
Peak memory 200740 kb
Host smart-7b60b459-878d-4b04-bf38-16c71bc6957a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60737749710356888644013695031082734697006407171721439141518191598802558086202 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.60737749710356888644013695031082734697006407171721439141518191598802558086202
Directory /workspace/46.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.63783718677022646664158169514478723593785684432477466136109486343719326921327
Short name T109
Test name
Test status
Simulation time 51975542 ps
CPU time 0.79 seconds
Started Nov 22 01:28:35 PM PST 23
Finished Nov 22 01:28:40 PM PST 23
Peak memory 199004 kb
Host smart-42f85939-25b2-4e49-8e2d-30d020e706ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63783718677022646664158169514478723593785684432477466136109486343719326921327 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.pwrmgr_aborted_low_power.63783718677022646664158169514478723593785684432477466136109486343719326921327
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.44223366140603579009893088086368102270121537324586342307585350896701263540851
Short name T1007
Test name
Test status
Simulation time 72403950 ps
CPU time 0.77 seconds
Started Nov 22 01:28:11 PM PST 23
Finished Nov 22 01:28:15 PM PST 23
Peak memory 198080 kb
Host smart-ff0081c9-b18a-40e4-a7a8-31ddf3a14453
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44223366140603579009893088086368102270121537324586342307585350896701263540851 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_disable_rom_integrity_check.442233661406035790098930880863681022701215373245863423
07585350896701263540851
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.95261098962876578628412475479499523850015612701608983416669255426860051444819
Short name T1056
Test name
Test status
Simulation time 30368572 ps
CPU time 0.61 seconds
Started Nov 22 01:28:24 PM PST 23
Finished Nov 22 01:28:27 PM PST 23
Peak memory 195464 kb
Host smart-cfc01fbf-4ebe-40c0-9bb0-3c0067d0b25d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95261098962876578628412475479499523850015612701608983416669255426860051444819 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst_malfunc.95261098962876578628412475479499523850015612701608983416669255426860051444819
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.27629314716236005676672812179293787233586223886082268070778903619492956163718
Short name T1069
Test name
Test status
Simulation time 39672069 ps
CPU time 0.63 seconds
Started Nov 22 01:28:08 PM PST 23
Finished Nov 22 01:28:11 PM PST 23
Peak memory 195412 kb
Host smart-f2f080fd-179d-4e11-89d9-e785fb7ac0f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27629314716236005676672812179293787233586223886082268070778903619492956163718 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.27629314716236005676672812179293787233586223886082268070778903619492956163718
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.32047516332105663231792829032202680015937078286288101321392633166504451545899
Short name T365
Test name
Test status
Simulation time 33172121 ps
CPU time 0.64 seconds
Started Nov 22 01:28:10 PM PST 23
Finished Nov 22 01:28:14 PM PST 23
Peak memory 196768 kb
Host smart-093e2604-52af-4982-8254-28c1fcbe4dfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32047516332105663231792829032202680015937078286288101321392633166504451545899 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.32047516332105663231792829032202680015937078286288101321392633166504451545899
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.67886279493228128335147059166092215360421501145721976485916052225246173666512
Short name T145
Test name
Test status
Simulation time 49975558 ps
CPU time 0.68 seconds
Started Nov 22 01:28:39 PM PST 23
Finished Nov 22 01:28:46 PM PST 23
Peak memory 201392 kb
Host smart-1ad71122-62bc-4649-a44a-7ada92811165
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67886279493228128335147059166092215360421501145721976485916052225246173666512 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_invalid.67886279493228128335147059166092215360421501145721976485916052225246173666512
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_wakeup_race.73250153051996880205146882307610847167246161982843461942096931782991756578842
Short name T139
Test name
Test status
Simulation time 296241445 ps
CPU time 1.19 seconds
Started Nov 22 01:27:57 PM PST 23
Finished Nov 22 01:28:05 PM PST 23
Peak memory 199980 kb
Host smart-ed762260-6a1f-4187-b5dc-da0ec290462a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73250153051996880205146882307610847167246161982843461942096931782991756578842 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_wakeup_race.73250153051996880205146882307610847167246161982843461942096931782991756578842
Directory /workspace/47.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.77501491593015193842785117616905428687371436910808869496854509594585990380409
Short name T460
Test name
Test status
Simulation time 119707143 ps
CPU time 1 seconds
Started Nov 22 01:27:53 PM PST 23
Finished Nov 22 01:28:03 PM PST 23
Peak memory 199320 kb
Host smart-634fefd6-1a3b-4fe8-bdb1-97086ae8fcc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77501491593015193842785117616905428687371436910808869496854509594585990380409 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.77501491593015193842785117616905428687371436910808869496854509594585990380409
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.67626433096149978827284767929085157850456147187187334391109870818095747384924
Short name T1006
Test name
Test status
Simulation time 108189378 ps
CPU time 0.84 seconds
Started Nov 22 01:27:59 PM PST 23
Finished Nov 22 01:28:06 PM PST 23
Peak memory 209496 kb
Host smart-bf54b6c1-2664-4720-b319-8b302a222c90
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67626433096149978827284767929085157850456147187187334391109870818095747384924 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.67626433096149978827284767929085157850456147187187334391109870818095747384924
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.12723577572188566072019179602762679990504512464315269878307337552851063165871
Short name T517
Test name
Test status
Simulation time 314830582 ps
CPU time 1.32 seconds
Started Nov 22 01:27:59 PM PST 23
Finished Nov 22 01:28:07 PM PST 23
Peak memory 199888 kb
Host smart-9d71ee0a-7823-4b8f-85be-0bde6722cff4
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12723577572188566072019179602762679990504512464315269878307337552851063165871 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_ctrl_config_regwen.127235775721885660720191796027626799905045124643152698783
07337552851063165871
Directory /workspace/47.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.74965229336116062408938522744933972588064233715490670746568680353520530012418
Short name T742
Test name
Test status
Simulation time 919450745 ps
CPU time 3 seconds
Started Nov 22 01:28:12 PM PST 23
Finished Nov 22 01:28:19 PM PST 23
Peak memory 201248 kb
Host smart-0a2f76d4-94f0-4c97-ab11-a5def610e10b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749652293361160624089385227449339725880642337154906707465686
80353520530012418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.74965229336116062408938522
744933972588064233715490670746568680353520530012418
Directory /workspace/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.79892689221894113367787600610136056362226092397507753671734823231698727889326
Short name T865
Test name
Test status
Simulation time 968503924 ps
CPU time 3.06 seconds
Started Nov 22 01:27:57 PM PST 23
Finished Nov 22 01:28:07 PM PST 23
Peak memory 201136 kb
Host smart-3ed2063e-deb8-425d-b3f0-00637643e6cc
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79892689221894113367787600610136056362226092397507753671734
823231698727889326 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.798926892218941133677876
00610136056362226092397507753671734823231698727889326
Directory /workspace/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.58350210664030957599181718556403583551482923207824568058683318856791192404733
Short name T581
Test name
Test status
Simulation time 91600225 ps
CPU time 0.91 seconds
Started Nov 22 01:28:08 PM PST 23
Finished Nov 22 01:28:11 PM PST 23
Peak memory 195520 kb
Host smart-752f1a9f-a8c2-406c-8a7b-8669acc122ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58350210664030957599181718556403583551482923207824568058683318856791192404733 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig_mubi.58350210664030957599181718556403583551482923207824568058683318856791192404733
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.79230246488488728648782000398101515940194745129612355271331417927253254434946
Short name T101
Test name
Test status
Simulation time 35743529 ps
CPU time 0.64 seconds
Started Nov 22 01:27:57 PM PST 23
Finished Nov 22 01:28:04 PM PST 23
Peak memory 197808 kb
Host smart-7bb4094d-0406-45cc-b782-20fba604f393
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79230246488488728648782000398101515940194745129612355271331417927253254434946 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.79230246488488728648782000398101515940194745129612355271331417927253254434946
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_stress_all.81689517488393391850066911967152813467013813436477260852014914559915397082582
Short name T562
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.69 seconds
Started Nov 22 01:28:10 PM PST 23
Finished Nov 22 01:28:18 PM PST 23
Peak memory 201292 kb
Host smart-2048ca5c-094e-423d-b3c6-34e572cc9fee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81689517488393391850066911967152813467013813436477260852014914559915397082582 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.81689517488393391850066911967152813467013813436477260852014914559915397082582
Directory /workspace/47.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/47.pwrmgr_stress_all_with_rand_reset.58542826032030106793920715200764302956340306591366253424063288315081333160697
Short name T688
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.87 seconds
Started Nov 22 01:28:23 PM PST 23
Finished Nov 22 01:28:37 PM PST 23
Peak memory 201444 kb
Host smart-0d1c8c9c-0361-46ec-9003-44c979f3726b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585428260320301067939207
15200764302956340306591366253424063288315081333160697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all_with_rand_reset.58542
826032030106793920715200764302956340306591366253424063288315081333160697
Directory /workspace/47.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup.2616733153365935834918009117540639304786880700664047916997899248543085141791
Short name T718
Test name
Test status
Simulation time 283777259 ps
CPU time 1.24 seconds
Started Nov 22 01:28:01 PM PST 23
Finished Nov 22 01:28:09 PM PST 23
Peak memory 200044 kb
Host smart-afb668a5-47e6-4b4a-9dc6-a1a4c20274bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616733153365935834918009117540639304786880700664047916997899248543085141791 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup.2616733153365935834918009117540639304786880700664047916997899248543085141791
Directory /workspace/47.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup_reset.62897368082009799097030991805893063913684146365475762169033006776264881977279
Short name T589
Test name
Test status
Simulation time 325437640 ps
CPU time 1.45 seconds
Started Nov 22 01:28:10 PM PST 23
Finished Nov 22 01:28:15 PM PST 23
Peak memory 200768 kb
Host smart-0859cbdc-fb9d-4103-8a2e-a5b2dccb5466
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62897368082009799097030991805893063913684146365475762169033006776264881977279 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.62897368082009799097030991805893063913684146365475762169033006776264881977279
Directory /workspace/47.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.114296169737592970650340036287573932668789049662197626197197425515488517432902
Short name T790
Test name
Test status
Simulation time 51975542 ps
CPU time 0.8 seconds
Started Nov 22 01:28:10 PM PST 23
Finished Nov 22 01:28:14 PM PST 23
Peak memory 199144 kb
Host smart-2aa69742-fbbd-4812-8374-ad2c14f84759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114296169737592970650340036287573932668789049662197626197197425515488517432902 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.pwrmgr_aborted_low_power.114296169737592970650340036287573932668789049662197626197197425515488517432902
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.20262147657294895047288265302746335814113806539867882796066908933844109563589
Short name T590
Test name
Test status
Simulation time 72403950 ps
CPU time 0.79 seconds
Started Nov 22 01:28:10 PM PST 23
Finished Nov 22 01:28:14 PM PST 23
Peak memory 198240 kb
Host smart-c1ad36e2-ca29-412a-9d9f-20008fc0c3f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20262147657294895047288265302746335814113806539867882796066908933844109563589 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_disable_rom_integrity_check.202621476572948950472882653027463358141138065398678827
96066908933844109563589
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.50099647080406405148235303005514646279120937563406115964430015439636358724432
Short name T287
Test name
Test status
Simulation time 30368572 ps
CPU time 0.62 seconds
Started Nov 22 01:28:35 PM PST 23
Finished Nov 22 01:28:40 PM PST 23
Peak memory 195464 kb
Host smart-d006b32f-a25f-4027-a179-96b84511ab09
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50099647080406405148235303005514646279120937563406115964430015439636358724432 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst_malfunc.50099647080406405148235303005514646279120937563406115964430015439636358724432
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.36006199905195343599594020531022342777700762271413954216065113560488054489087
Short name T3
Test name
Test status
Simulation time 39672069 ps
CPU time 0.62 seconds
Started Nov 22 01:28:09 PM PST 23
Finished Nov 22 01:28:12 PM PST 23
Peak memory 195484 kb
Host smart-583abf80-d196-4e6a-b87a-cdd0af6b4905
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36006199905195343599594020531022342777700762271413954216065113560488054489087 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.36006199905195343599594020531022342777700762271413954216065113560488054489087
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.26257632295454758005249003197187386754651860481539542907278852292855927714473
Short name T336
Test name
Test status
Simulation time 33172121 ps
CPU time 0.58 seconds
Started Nov 22 01:28:37 PM PST 23
Finished Nov 22 01:28:41 PM PST 23
Peak memory 196848 kb
Host smart-ea6ab6ad-4d56-4d10-b679-4049fccda942
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26257632295454758005249003197187386754651860481539542907278852292855927714473 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.26257632295454758005249003197187386754651860481539542907278852292855927714473
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.43935228270315112378367713172130097036692231348615354504049515436477715919554
Short name T843
Test name
Test status
Simulation time 49975558 ps
CPU time 0.68 seconds
Started Nov 22 01:28:41 PM PST 23
Finished Nov 22 01:28:49 PM PST 23
Peak memory 201388 kb
Host smart-cb4b2eef-2358-4f1f-a947-bb25e0af7979
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43935228270315112378367713172130097036692231348615354504049515436477715919554 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_invalid.43935228270315112378367713172130097036692231348615354504049515436477715919554
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_wakeup_race.114627435275929381468655806921533161089477356551261041014156420556611694276399
Short name T315
Test name
Test status
Simulation time 296241445 ps
CPU time 1.25 seconds
Started Nov 22 01:28:11 PM PST 23
Finished Nov 22 01:28:16 PM PST 23
Peak memory 200052 kb
Host smart-05fbdcdc-acd1-460b-9912-f0026b953eb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114627435275929381468655806921533161089477356551261041014156420556611694276399 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/
coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_wakeup_race.114627435275929381468655806921533161089477356551261041014156420556611694276399
Directory /workspace/48.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.92984484609452445682275041572573213418485408250152955673852454849405228583855
Short name T658
Test name
Test status
Simulation time 119707143 ps
CPU time 0.97 seconds
Started Nov 22 01:28:04 PM PST 23
Finished Nov 22 01:28:10 PM PST 23
Peak memory 199172 kb
Host smart-38203c92-5a75-4c11-aefa-211870bb074c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92984484609452445682275041572573213418485408250152955673852454849405228583855 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.92984484609452445682275041572573213418485408250152955673852454849405228583855
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.55478754986788541791974482214032564716261548460301745888559682610014247901328
Short name T516
Test name
Test status
Simulation time 108189378 ps
CPU time 0.85 seconds
Started Nov 22 01:28:33 PM PST 23
Finished Nov 22 01:28:40 PM PST 23
Peak memory 209524 kb
Host smart-a29e4fe7-933d-4559-9fc5-a3ad31498dfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55478754986788541791974482214032564716261548460301745888559682610014247901328 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.55478754986788541791974482214032564716261548460301745888559682610014247901328
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.2310024444418950641377936090648848345520310869153501967801870150326949200271
Short name T507
Test name
Test status
Simulation time 314830582 ps
CPU time 1.31 seconds
Started Nov 22 01:28:09 PM PST 23
Finished Nov 22 01:28:12 PM PST 23
Peak memory 199888 kb
Host smart-1676cd1d-591d-415b-9a3f-16d818f3637d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310024444418950641377936090648848345520310869153501967801870150326949200271 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_ctrl_config_regwen.2310024444418950641377936090648848345520310869153501967801
870150326949200271
Directory /workspace/48.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.108491171044893613838925314859274752328786388224530525163025726712295464429686
Short name T453
Test name
Test status
Simulation time 919450745 ps
CPU time 2.97 seconds
Started Nov 22 01:28:35 PM PST 23
Finished Nov 22 01:28:42 PM PST 23
Peak memory 201212 kb
Host smart-d18e6e3d-08ea-4a7a-bbe2-4812b9e3d7db
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108491171044893613838925314859274752328786388224530525163025
726712295464429686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1084911710448936138389253
14859274752328786388224530525163025726712295464429686
Directory /workspace/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.14175928933317496927370050858627838112174946312409940556891836552846845465522
Short name T495
Test name
Test status
Simulation time 968503924 ps
CPU time 3.13 seconds
Started Nov 22 01:28:12 PM PST 23
Finished Nov 22 01:28:19 PM PST 23
Peak memory 201204 kb
Host smart-3e104569-6916-4869-81b3-5db6cec017d8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14175928933317496927370050858627838112174946312409940556891
836552846845465522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.141759289333174969273700
50858627838112174946312409940556891836552846845465522
Directory /workspace/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.17778440375711782056291986284817576609489629213152589786472027688276116131146
Short name T604
Test name
Test status
Simulation time 91600225 ps
CPU time 0.89 seconds
Started Nov 22 01:28:38 PM PST 23
Finished Nov 22 01:28:41 PM PST 23
Peak memory 195468 kb
Host smart-ddd60930-8116-4df6-880d-a5ceea803c3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17778440375711782056291986284817576609489629213152589786472027688276116131146 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig_mubi.17778440375711782056291986284817576609489629213152589786472027688276116131146
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.9266144926964232409778371346823354397932150451704639994552445971050719494026
Short name T832
Test name
Test status
Simulation time 35743529 ps
CPU time 0.62 seconds
Started Nov 22 01:28:06 PM PST 23
Finished Nov 22 01:28:10 PM PST 23
Peak memory 197748 kb
Host smart-9774a477-cbf4-49b3-9a2b-658b37f91203
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9266144926964232409778371346823354397932150451704639994552445971050719494026 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.9266144926964232409778371346823354397932150451704639994552445971050719494026
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_stress_all.29661478430279640396712048454507152514201995363278002359098545679713168526959
Short name T560
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.57 seconds
Started Nov 22 01:28:11 PM PST 23
Finished Nov 22 01:28:20 PM PST 23
Peak memory 201280 kb
Host smart-72fef5a4-5a81-430d-b914-ba807873a2f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29661478430279640396712048454507152514201995363278002359098545679713168526959 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all.29661478430279640396712048454507152514201995363278002359098545679713168526959
Directory /workspace/48.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup.112992200657917977378543908726278950081941597627751948210900507038043324599451
Short name T929
Test name
Test status
Simulation time 283777259 ps
CPU time 1.21 seconds
Started Nov 22 01:28:38 PM PST 23
Finished Nov 22 01:28:43 PM PST 23
Peak memory 199984 kb
Host smart-a32ab96d-e277-4795-9de8-9465849e1239
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112992200657917977378543908726278950081941597627751948210900507038043324599451 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.112992200657917977378543908726278950081941597627751948210900507038043324599451
Directory /workspace/48.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup_reset.19370282230720740145564341952674453256010056996232401876578934190142048556128
Short name T660
Test name
Test status
Simulation time 325437640 ps
CPU time 1.43 seconds
Started Nov 22 01:28:09 PM PST 23
Finished Nov 22 01:28:13 PM PST 23
Peak memory 200728 kb
Host smart-5f3e147f-f2a7-45f3-8d67-bedd0caa615f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19370282230720740145564341952674453256010056996232401876578934190142048556128 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.19370282230720740145564341952674453256010056996232401876578934190142048556128
Directory /workspace/48.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.73412205044623352024893418309874764078906397269520477567695686653926210557662
Short name T296
Test name
Test status
Simulation time 51975542 ps
CPU time 0.81 seconds
Started Nov 22 01:28:25 PM PST 23
Finished Nov 22 01:28:28 PM PST 23
Peak memory 199108 kb
Host smart-29a4208a-8701-4f10-850d-852c36c6fb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73412205044623352024893418309874764078906397269520477567695686653926210557662 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.pwrmgr_aborted_low_power.73412205044623352024893418309874764078906397269520477567695686653926210557662
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.63857737663565664019211537506071796774846445628605968112139851083303756692317
Short name T779
Test name
Test status
Simulation time 72403950 ps
CPU time 0.77 seconds
Started Nov 22 01:28:03 PM PST 23
Finished Nov 22 01:28:09 PM PST 23
Peak memory 198276 kb
Host smart-6925007d-48bd-4463-8716-8a2145c8602f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63857737663565664019211537506071796774846445628605968112139851083303756692317 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_disable_rom_integrity_check.638577376635656640192115375060717967748464456286059681
12139851083303756692317
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.47121285195036563771212296170996336779402723989248454798538702833153841314506
Short name T632
Test name
Test status
Simulation time 30368572 ps
CPU time 0.6 seconds
Started Nov 22 01:28:00 PM PST 23
Finished Nov 22 01:28:07 PM PST 23
Peak memory 195348 kb
Host smart-e2f80a52-7809-4e00-948d-48b0792ec53c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47121285195036563771212296170996336779402723989248454798538702833153841314506 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst_malfunc.47121285195036563771212296170996336779402723989248454798538702833153841314506
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.50441955000780889383609165114987708581138448803182787856324254383601592415423
Short name T647
Test name
Test status
Simulation time 39672069 ps
CPU time 0.63 seconds
Started Nov 22 01:28:02 PM PST 23
Finished Nov 22 01:28:08 PM PST 23
Peak memory 195368 kb
Host smart-f09df957-2eb2-4be0-b09a-a6d6213a8403
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50441955000780889383609165114987708581138448803182787856324254383601592415423 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.50441955000780889383609165114987708581138448803182787856324254383601592415423
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.105347694350299594605868934910334944663224129675977302618576258229734586195285
Short name T918
Test name
Test status
Simulation time 33172121 ps
CPU time 0.63 seconds
Started Nov 22 01:28:09 PM PST 23
Finished Nov 22 01:28:12 PM PST 23
Peak memory 196864 kb
Host smart-5a46e2cd-7e20-48ab-97b3-c012e5cc56f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105347694350299594605868934910334944663224129675977302618576258229734586195285 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.105347694350299594605868934910334944663224129675977302618576258229734586195285
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.111183417948747164162810691702660801764757897624279047685866973086027702603849
Short name T613
Test name
Test status
Simulation time 49975558 ps
CPU time 0.68 seconds
Started Nov 22 01:28:06 PM PST 23
Finished Nov 22 01:28:10 PM PST 23
Peak memory 201348 kb
Host smart-eb92d8b8-4081-414c-af83-68d2f545a2e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111183417948747164162810691702660801764757897624279047685866973086027702603849 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_invalid.111183417948747164162810691702660801764757897624279047685866973086027702603849
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_wakeup_race.1489784622222031161049132644025579530604204013012179664053199228771185572263
Short name T421
Test name
Test status
Simulation time 296241445 ps
CPU time 1.18 seconds
Started Nov 22 01:28:37 PM PST 23
Finished Nov 22 01:28:41 PM PST 23
Peak memory 200112 kb
Host smart-e8ab163a-0e58-4929-8e1a-af61ff52acfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489784622222031161049132644025579530604204013012179664053199228771185572263 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_wakeup_race.1489784622222031161049132644025579530604204013012179664053199228771185572263
Directory /workspace/49.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.39091230498401548944855037261712828794239246808370537909265373873549403474728
Short name T37
Test name
Test status
Simulation time 119707143 ps
CPU time 1.04 seconds
Started Nov 22 01:28:08 PM PST 23
Finished Nov 22 01:28:11 PM PST 23
Peak memory 199256 kb
Host smart-4363865e-22a9-4bab-a6df-90cf077cbf5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39091230498401548944855037261712828794239246808370537909265373873549403474728 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.39091230498401548944855037261712828794239246808370537909265373873549403474728
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.5784533244505203338009510711909656284705569646340001530061095723031715023307
Short name T550
Test name
Test status
Simulation time 108189378 ps
CPU time 0.86 seconds
Started Nov 22 01:28:38 PM PST 23
Finished Nov 22 01:28:42 PM PST 23
Peak memory 209548 kb
Host smart-93e965de-1178-4ccc-813e-5461d5215eb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5784533244505203338009510711909656284705569646340001530061095723031715023307 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.5784533244505203338009510711909656284705569646340001530061095723031715023307
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.52585118613908316296669836032275072367551077943201035031982522528447172700291
Short name T690
Test name
Test status
Simulation time 314830582 ps
CPU time 1.41 seconds
Started Nov 22 01:28:09 PM PST 23
Finished Nov 22 01:28:13 PM PST 23
Peak memory 199916 kb
Host smart-86f1164f-1c94-4eee-a207-7589420a8852
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52585118613908316296669836032275072367551077943201035031982522528447172700291 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_ctrl_config_regwen.525851186139083162966698360322750723675510779432010350319
82522528447172700291
Directory /workspace/49.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.115611873780234393568129099580858472685955317597606651901066632867561025742352
Short name T120
Test name
Test status
Simulation time 919450745 ps
CPU time 3.03 seconds
Started Nov 22 01:28:08 PM PST 23
Finished Nov 22 01:28:13 PM PST 23
Peak memory 201168 kb
Host smart-673fc650-cbef-4801-89e2-b05565ae6736
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115611873780234393568129099580858472685955317597606651901066
632867561025742352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1156118737802343935681290
99580858472685955317597606651901066632867561025742352
Directory /workspace/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.102851820910658312831820982434441841896145533127733105790183874813361357892200
Short name T310
Test name
Test status
Simulation time 968503924 ps
CPU time 3.07 seconds
Started Nov 22 01:28:38 PM PST 23
Finished Nov 22 01:28:47 PM PST 23
Peak memory 201216 kb
Host smart-535ed8ed-cb1e-4027-9e3a-1b751d8d5c44
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10285182091065831283182098243444184189614553312773310579018
3874813361357892200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.10285182091065831283182
0982434441841896145533127733105790183874813361357892200
Directory /workspace/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.69347428432194094838558239036396520190864266545844218703325953454613005967516
Short name T499
Test name
Test status
Simulation time 91600225 ps
CPU time 0.87 seconds
Started Nov 22 01:28:06 PM PST 23
Finished Nov 22 01:28:10 PM PST 23
Peak memory 195396 kb
Host smart-8b033737-e188-4706-8d51-e51b67d97f89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69347428432194094838558239036396520190864266545844218703325953454613005967516 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig_mubi.69347428432194094838558239036396520190864266545844218703325953454613005967516
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.75153952694521386334544215120605301277191166433754885446138555872953166233510
Short name T874
Test name
Test status
Simulation time 35743529 ps
CPU time 0.61 seconds
Started Nov 22 01:28:06 PM PST 23
Finished Nov 22 01:28:10 PM PST 23
Peak memory 197700 kb
Host smart-67e02360-b538-48c4-9b64-de9ec5bb949f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75153952694521386334544215120605301277191166433754885446138555872953166233510 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.75153952694521386334544215120605301277191166433754885446138555872953166233510
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_stress_all.85580097369400625428776832762992589751112533189661966335874725593484069310116
Short name T33
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.74 seconds
Started Nov 22 01:28:10 PM PST 23
Finished Nov 22 01:28:19 PM PST 23
Peak memory 201096 kb
Host smart-33ff861a-5b52-429a-b9d9-f869e0695c77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85580097369400625428776832762992589751112533189661966335874725593484069310116 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all.85580097369400625428776832762992589751112533189661966335874725593484069310116
Directory /workspace/49.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/49.pwrmgr_stress_all_with_rand_reset.109998990887146319502696822220540897166872203177931606803538220275096767408181
Short name T830
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.51 seconds
Started Nov 22 01:28:09 PM PST 23
Finished Nov 22 01:28:24 PM PST 23
Peak memory 201468 kb
Host smart-beb37167-acd7-4a98-98b9-a49ed730544a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109998990887146319502696
822220540897166872203177931606803538220275096767408181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all_with_rand_reset.1099
98990887146319502696822220540897166872203177931606803538220275096767408181
Directory /workspace/49.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup.76989109357574686822276676730758228646305920577531350249155622567183110176574
Short name T724
Test name
Test status
Simulation time 283777259 ps
CPU time 1.23 seconds
Started Nov 22 01:28:06 PM PST 23
Finished Nov 22 01:28:10 PM PST 23
Peak memory 200076 kb
Host smart-788d5caa-598f-4f04-959b-7eda87dd7735
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76989109357574686822276676730758228646305920577531350249155622567183110176574 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.76989109357574686822276676730758228646305920577531350249155622567183110176574
Directory /workspace/49.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup_reset.97740282537505558220313261384046335033042401422166082075476170786302430918961
Short name T896
Test name
Test status
Simulation time 325437640 ps
CPU time 1.38 seconds
Started Nov 22 01:28:01 PM PST 23
Finished Nov 22 01:28:09 PM PST 23
Peak memory 200708 kb
Host smart-dbf5c013-2c9b-4b8e-92a5-110fb9f3c658
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97740282537505558220313261384046335033042401422166082075476170786302430918961 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.97740282537505558220313261384046335033042401422166082075476170786302430918961
Directory /workspace/49.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.3075478933634481235134661777345876174264290461933761781234909054391044783720
Short name T827
Test name
Test status
Simulation time 51975542 ps
CPU time 0.78 seconds
Started Nov 22 01:26:19 PM PST 23
Finished Nov 22 01:26:23 PM PST 23
Peak memory 199008 kb
Host smart-77961cbe-7612-4f47-8a6d-9ae64d0a46ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075478933634481235134661777345876174264290461933761781234909054391044783720 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 5.pwrmgr_aborted_low_power.3075478933634481235134661777345876174264290461933761781234909054391044783720
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.14407939297763067196142930025479568731988066257353803289821960902074883919501
Short name T719
Test name
Test status
Simulation time 72403950 ps
CPU time 0.72 seconds
Started Nov 22 01:27:21 PM PST 23
Finished Nov 22 01:27:38 PM PST 23
Peak memory 197904 kb
Host smart-e7f46442-4d04-4690-ba30-c8e5111a10d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14407939297763067196142930025479568731988066257353803289821960902074883919501 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disable_rom_integrity_check.1440793929776306719614293002547956873198806625735380328
9821960902074883919501
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.29910867563073437361653422479728400160018257604969603185117129643599045712782
Short name T798
Test name
Test status
Simulation time 30368572 ps
CPU time 0.58 seconds
Started Nov 22 01:26:19 PM PST 23
Finished Nov 22 01:26:23 PM PST 23
Peak memory 195312 kb
Host smart-53463ca8-fe07-44c8-81b5-559791bb6d61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29910867563073437361653422479728400160018257604969603185117129643599045712782 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_malfunc.29910867563073437361653422479728400160018257604969603185117129643599045712782
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.92650839971645817813580420539540634233638821754830331036024115613077132353816
Short name T122
Test name
Test status
Simulation time 39672069 ps
CPU time 0.68 seconds
Started Nov 22 01:26:08 PM PST 23
Finished Nov 22 01:26:14 PM PST 23
Peak memory 195492 kb
Host smart-6fb04ba9-90b5-41ef-a7ba-2a58c933e14a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92650839971645817813580420539540634233638821754830331036024115613077132353816 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.92650839971645817813580420539540634233638821754830331036024115613077132353816
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.103113366176752571998204706348122218566521173847619995808823921104014885823004
Short name T367
Test name
Test status
Simulation time 33172121 ps
CPU time 0.59 seconds
Started Nov 22 01:27:09 PM PST 23
Finished Nov 22 01:27:27 PM PST 23
Peak memory 196376 kb
Host smart-f4f1e9ee-283e-43d6-b03f-81389b124f26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103113366176752571998204706348122218566521173847619995808823921104014885823004 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.103113366176752571998204706348122218566521173847619995808823921104014885823004
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.107178299511923595404885849919989220036598142667692486922581387773645833343133
Short name T998
Test name
Test status
Simulation time 49975558 ps
CPU time 0.83 seconds
Started Nov 22 01:27:18 PM PST 23
Finished Nov 22 01:27:35 PM PST 23
Peak memory 199052 kb
Host smart-657d2aa1-70d6-4fa6-8f96-faf4f50c93c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107178299511923595404885849919989220036598142667692486922581387773645833343133 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invalid.107178299511923595404885849919989220036598142667692486922581387773645833343133
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_wakeup_race.12467042341115271230535706599702868711896840781178948610080761501176773242912
Short name T811
Test name
Test status
Simulation time 296241445 ps
CPU time 1.2 seconds
Started Nov 22 01:26:19 PM PST 23
Finished Nov 22 01:26:23 PM PST 23
Peak memory 199936 kb
Host smart-4ea75ffa-59f0-4dfc-9fec-8d45c88264a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12467042341115271230535706599702868711896840781178948610080761501176773242912 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wakeup_race.12467042341115271230535706599702868711896840781178948610080761501176773242912
Directory /workspace/5.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.98437737198577196062775787029281968268130079772080323830829474893953715719778
Short name T799
Test name
Test status
Simulation time 119707143 ps
CPU time 1.03 seconds
Started Nov 22 01:26:07 PM PST 23
Finished Nov 22 01:26:13 PM PST 23
Peak memory 199320 kb
Host smart-b8de6cfc-f90f-44d4-b7f8-3c251d399be2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98437737198577196062775787029281968268130079772080323830829474893953715719778 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.98437737198577196062775787029281968268130079772080323830829474893953715719778
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.35617365539727195550794324627754906505038110661556197418278962412660998258048
Short name T509
Test name
Test status
Simulation time 108189378 ps
CPU time 0.85 seconds
Started Nov 22 01:26:52 PM PST 23
Finished Nov 22 01:27:00 PM PST 23
Peak memory 209548 kb
Host smart-5836452f-3e42-4ee8-824d-6c710bed8c3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35617365539727195550794324627754906505038110661556197418278962412660998258048 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.35617365539727195550794324627754906505038110661556197418278962412660998258048
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.57100255924328997058569264102101526795926495446787486008523094138327525893823
Short name T470
Test name
Test status
Simulation time 314830582 ps
CPU time 1.3 seconds
Started Nov 22 01:26:28 PM PST 23
Finished Nov 22 01:26:33 PM PST 23
Peak memory 199764 kb
Host smart-a24b69cc-e071-488e-b18e-4b94aedd6ace
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57100255924328997058569264102101526795926495446787486008523094138327525893823 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_ctrl_config_regwen.5710025592432899705856926410210152679592649544678748600852
3094138327525893823
Directory /workspace/5.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.109340088614637651967470434927026679828974839778361071330606383505652920138023
Short name T1015
Test name
Test status
Simulation time 919450745 ps
CPU time 2.8 seconds
Started Nov 22 01:27:00 PM PST 23
Finished Nov 22 01:27:19 PM PST 23
Peak memory 200420 kb
Host smart-28437169-1596-4d8e-9546-ed277cca5f1a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109340088614637651967470434927026679828974839778361071330606
383505652920138023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.10934008861463765196747043
4927026679828974839778361071330606383505652920138023
Directory /workspace/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.39722764551480897371406034162518859495858084101685442886568377223717110307530
Short name T436
Test name
Test status
Simulation time 968503924 ps
CPU time 2.89 seconds
Started Nov 22 01:26:59 PM PST 23
Finished Nov 22 01:27:19 PM PST 23
Peak memory 199296 kb
Host smart-f2628dea-dbf2-4f1b-a7ac-565036e4064e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39722764551480897371406034162518859495858084101685442886568
377223717110307530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3972276455148089737140603
4162518859495858084101685442886568377223717110307530
Directory /workspace/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.451580399629040177835572248309475736361001788672987000001135850923804262388
Short name T571
Test name
Test status
Simulation time 91600225 ps
CPU time 0.88 seconds
Started Nov 22 01:26:19 PM PST 23
Finished Nov 22 01:26:23 PM PST 23
Peak memory 195380 kb
Host smart-e4410cf8-8b8c-4997-ba49-08b6f49c9fd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451580399629040177835572248309475736361001788672987000001135850923804262388 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_mubi.451580399629040177835572248309475736361001788672987000001135850923804262388
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.99508169423058144427879595527336636193289125953530330239210669725175659373228
Short name T340
Test name
Test status
Simulation time 35743529 ps
CPU time 0.61 seconds
Started Nov 22 01:27:00 PM PST 23
Finished Nov 22 01:27:17 PM PST 23
Peak memory 196776 kb
Host smart-2c283441-0c07-451c-9407-7429e6b8bdcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99508169423058144427879595527336636193289125953530330239210669725175659373228 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.99508169423058144427879595527336636193289125953530330239210669725175659373228
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_stress_all.7815344381953487058462743283133596482249217853179241956910173703044144790283
Short name T522
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.82 seconds
Started Nov 22 01:26:26 PM PST 23
Finished Nov 22 01:26:35 PM PST 23
Peak memory 201176 kb
Host smart-03555724-0b22-4643-ad95-53c52052ad61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7815344381953487058462743283133596482249217853179241956910173703044144790283 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all.7815344381953487058462743283133596482249217853179241956910173703044144790283
Directory /workspace/5.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/5.pwrmgr_stress_all_with_rand_reset.44989308007158884024741173339385196882153063342856389994803088272120584932568
Short name T1041
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.12 seconds
Started Nov 22 01:26:52 PM PST 23
Finished Nov 22 01:27:09 PM PST 23
Peak memory 201228 kb
Host smart-0eb85392-36be-4500-82c0-f400bdf46656
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449893080071588840247411
73339385196882153063342856389994803088272120584932568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all_with_rand_reset.449893
08007158884024741173339385196882153063342856389994803088272120584932568
Directory /workspace/5.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup.71279052350704925830335990510560350431020909954503138110495129316410904803146
Short name T985
Test name
Test status
Simulation time 283777259 ps
CPU time 1.13 seconds
Started Nov 22 01:27:00 PM PST 23
Finished Nov 22 01:27:18 PM PST 23
Peak memory 199596 kb
Host smart-9d7dc055-ccde-4682-934a-f796ae6570e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71279052350704925830335990510560350431020909954503138110495129316410904803146 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.71279052350704925830335990510560350431020909954503138110495129316410904803146
Directory /workspace/5.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup_reset.100721909040088310381904447699633314230879229462621085557251400845623131516182
Short name T314
Test name
Test status
Simulation time 325437640 ps
CPU time 1.32 seconds
Started Nov 22 01:26:19 PM PST 23
Finished Nov 22 01:26:23 PM PST 23
Peak memory 200624 kb
Host smart-2d022fe6-3d51-476a-9f5b-f3de5d037bb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100721909040088310381904447699633314230879229462621085557251400845623131516182 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.100721909040088310381904447699633314230879229462621085557251400845623131516182
Directory /workspace/5.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.76837324551278328144183334752921199975579446460396982823317136637326704507824
Short name T452
Test name
Test status
Simulation time 51975542 ps
CPU time 0.81 seconds
Started Nov 22 01:26:27 PM PST 23
Finished Nov 22 01:26:31 PM PST 23
Peak memory 199184 kb
Host smart-68f05b36-7324-4737-900a-80aaf8b1d5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76837324551278328144183334752921199975579446460396982823317136637326704507824 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 6.pwrmgr_aborted_low_power.76837324551278328144183334752921199975579446460396982823317136637326704507824
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.32843098701409973729607651034919673462324355755040486703564448553183439909911
Short name T5
Test name
Test status
Simulation time 72403950 ps
CPU time 0.75 seconds
Started Nov 22 01:26:02 PM PST 23
Finished Nov 22 01:26:08 PM PST 23
Peak memory 198244 kb
Host smart-66d3bdb6-6857-4142-ba14-8adcce8d69e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32843098701409973729607651034919673462324355755040486703564448553183439909911 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disable_rom_integrity_check.3284309870140997372960765103491967346232435575504048670
3564448553183439909911
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.109937791970294246604339573030066568821998897466772310198291150065862992274127
Short name T659
Test name
Test status
Simulation time 30368572 ps
CPU time 0.75 seconds
Started Nov 22 01:27:06 PM PST 23
Finished Nov 22 01:27:21 PM PST 23
Peak memory 192456 kb
Host smart-c2227029-9d5f-47d0-8e86-9c2971f3afec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109937791970294246604339573030066568821998897466772310198291150065862992274127 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_malfunc.109937791970294246604339573030066568821998897466772310198291150065862992274127
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.41838885294400834024337136755451638405306806377708543009102357856127981010285
Short name T503
Test name
Test status
Simulation time 39672069 ps
CPU time 0.6 seconds
Started Nov 22 01:26:07 PM PST 23
Finished Nov 22 01:26:13 PM PST 23
Peak memory 195392 kb
Host smart-9756f23e-e6cd-451b-871e-3575154db2e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41838885294400834024337136755451638405306806377708543009102357856127981010285 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.41838885294400834024337136755451638405306806377708543009102357856127981010285
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.25834648047728647186716846569937501786309244180412562213766582234995320182756
Short name T650
Test name
Test status
Simulation time 33172121 ps
CPU time 0.6 seconds
Started Nov 22 01:25:51 PM PST 23
Finished Nov 22 01:25:57 PM PST 23
Peak memory 196804 kb
Host smart-ab28682f-f186-4843-836b-a2a430c02859
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25834648047728647186716846569937501786309244180412562213766582234995320182756 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.25834648047728647186716846569937501786309244180412562213766582234995320182756
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.57167047670085484039233914106108549987680994331214651289989006954142455711577
Short name T1031
Test name
Test status
Simulation time 49975558 ps
CPU time 0.67 seconds
Started Nov 22 01:26:03 PM PST 23
Finished Nov 22 01:26:09 PM PST 23
Peak memory 201384 kb
Host smart-4a3c9114-ab46-42cc-bb78-e3096521c52a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57167047670085484039233914106108549987680994331214651289989006954142455711577 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invalid.57167047670085484039233914106108549987680994331214651289989006954142455711577
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_wakeup_race.51820490516117393854556384138969766753680411009045116440167860222290898746195
Short name T1035
Test name
Test status
Simulation time 296241445 ps
CPU time 1.21 seconds
Started Nov 22 01:26:26 PM PST 23
Finished Nov 22 01:26:29 PM PST 23
Peak memory 200036 kb
Host smart-fca4a5cb-8cbb-4608-bc4a-478c78695ad5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51820490516117393854556384138969766753680411009045116440167860222290898746195 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wakeup_race.51820490516117393854556384138969766753680411009045116440167860222290898746195
Directory /workspace/6.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.74559140589215841718543565194603400011612422999913701718494991491256129356158
Short name T875
Test name
Test status
Simulation time 119707143 ps
CPU time 0.99 seconds
Started Nov 22 01:26:35 PM PST 23
Finished Nov 22 01:26:38 PM PST 23
Peak memory 199192 kb
Host smart-7396a7cc-fea7-4c0d-8383-729f26aa6775
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74559140589215841718543565194603400011612422999913701718494991491256129356158 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.74559140589215841718543565194603400011612422999913701718494991491256129356158
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.66402414576155085417523365107604743390803599657910154666006340724520393579672
Short name T945
Test name
Test status
Simulation time 108189378 ps
CPU time 0.8 seconds
Started Nov 22 01:26:06 PM PST 23
Finished Nov 22 01:26:13 PM PST 23
Peak memory 209500 kb
Host smart-3a0ca9de-6b0b-4818-b239-e153332a6c2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66402414576155085417523365107604743390803599657910154666006340724520393579672 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.66402414576155085417523365107604743390803599657910154666006340724520393579672
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.67066910824768122477773986898008222685423554267132709041536955003326252438461
Short name T829
Test name
Test status
Simulation time 314830582 ps
CPU time 1.36 seconds
Started Nov 22 01:26:08 PM PST 23
Finished Nov 22 01:26:14 PM PST 23
Peak memory 199916 kb
Host smart-6e957674-9633-4cbf-94fc-2b1950736ae7
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67066910824768122477773986898008222685423554267132709041536955003326252438461 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_ctrl_config_regwen.6706691082476812247777398689800822268542355426713270904153
6955003326252438461
Directory /workspace/6.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.20856064704565257087592983948601561604887112088491757366491178926731354979913
Short name T932
Test name
Test status
Simulation time 919450745 ps
CPU time 2.8 seconds
Started Nov 22 01:26:24 PM PST 23
Finished Nov 22 01:26:29 PM PST 23
Peak memory 201116 kb
Host smart-84de5599-1c43-43b8-b57a-6b0552b394c7
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208560647045652570875929839486015616048871120884917573664911
78926731354979913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.208560647045652570875929839
48601561604887112088491757366491178926731354979913
Directory /workspace/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.32799320514988706075359260573286549740203150122509289869937317956776632083872
Short name T671
Test name
Test status
Simulation time 968503924 ps
CPU time 3.06 seconds
Started Nov 22 01:26:29 PM PST 23
Finished Nov 22 01:26:35 PM PST 23
Peak memory 201212 kb
Host smart-b711aae8-add2-45f1-8c3c-b0a348e8f28a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32799320514988706075359260573286549740203150122509289869937
317956776632083872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3279932051498870607535926
0573286549740203150122509289869937317956776632083872
Directory /workspace/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.58990442207828383735259419566673000415131872271637142148453240256953069552677
Short name T127
Test name
Test status
Simulation time 91600225 ps
CPU time 0.88 seconds
Started Nov 22 01:25:52 PM PST 23
Finished Nov 22 01:26:00 PM PST 23
Peak memory 195476 kb
Host smart-86f38d1a-b1dc-40f8-9cc3-d9fedc8f12d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58990442207828383735259419566673000415131872271637142148453240256953069552677 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_mubi.58990442207828383735259419566673000415131872271637142148453240256953069552677
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.41392923759553136617512612568813617392126588674639330073127540434426575632520
Short name T153
Test name
Test status
Simulation time 35743529 ps
CPU time 0.6 seconds
Started Nov 22 01:27:00 PM PST 23
Finished Nov 22 01:27:17 PM PST 23
Peak memory 197396 kb
Host smart-44275376-a62b-4be9-8390-b5a05a8b4e51
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41392923759553136617512612568813617392126588674639330073127540434426575632520 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.41392923759553136617512612568813617392126588674639330073127540434426575632520
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_stress_all.105601112417841884942239480265863524949044074207606089122843905890916247818085
Short name T1002
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.5 seconds
Started Nov 22 01:25:51 PM PST 23
Finished Nov 22 01:26:03 PM PST 23
Peak memory 201272 kb
Host smart-77213e13-616f-402d-8871-a6d9d22638ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105601112417841884942239480265863524949044074207606089122843905890916247818085 -assert nopo
stproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.105601112417841884942239480265863524949044074207606089122843905890916247818085
Directory /workspace/6.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/6.pwrmgr_stress_all_with_rand_reset.66472423608683163827449299342047966274794040318815687867987603620078206347906
Short name T761
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.85 seconds
Started Nov 22 01:26:08 PM PST 23
Finished Nov 22 01:26:25 PM PST 23
Peak memory 201436 kb
Host smart-6efe4786-0a48-42c7-87d4-88fbe594930b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664724236086831638274492
99342047966274794040318815687867987603620078206347906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all_with_rand_reset.664724
23608683163827449299342047966274794040318815687867987603620078206347906
Directory /workspace/6.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup.28399433091911999252818549755914744465249451314274449611640556646704617148068
Short name T627
Test name
Test status
Simulation time 283777259 ps
CPU time 1.21 seconds
Started Nov 22 01:26:29 PM PST 23
Finished Nov 22 01:26:33 PM PST 23
Peak memory 199980 kb
Host smart-ee4742e7-566d-4cc5-9089-bc1b27a7c48e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28399433091911999252818549755914744465249451314274449611640556646704617148068 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.28399433091911999252818549755914744465249451314274449611640556646704617148068
Directory /workspace/6.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup_reset.54704396655371251069410989688247949166291014046974817007021292327969082127005
Short name T935
Test name
Test status
Simulation time 325437640 ps
CPU time 1.38 seconds
Started Nov 22 01:26:26 PM PST 23
Finished Nov 22 01:26:30 PM PST 23
Peak memory 200792 kb
Host smart-1594f82e-165c-4080-9068-1e87da37e158
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54704396655371251069410989688247949166291014046974817007021292327969082127005 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.54704396655371251069410989688247949166291014046974817007021292327969082127005
Directory /workspace/6.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.86181783509885682217896650342281158144678229707875076689848095346548087803565
Short name T780
Test name
Test status
Simulation time 51975542 ps
CPU time 0.8 seconds
Started Nov 22 01:26:10 PM PST 23
Finished Nov 22 01:26:17 PM PST 23
Peak memory 199160 kb
Host smart-f3d8fae2-9a6a-405f-b441-860fee32519c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86181783509885682217896650342281158144678229707875076689848095346548087803565 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.pwrmgr_aborted_low_power.86181783509885682217896650342281158144678229707875076689848095346548087803565
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.59337656722199566500567159958993826378805519472996974426792362616389693887096
Short name T943
Test name
Test status
Simulation time 72403950 ps
CPU time 0.73 seconds
Started Nov 22 01:26:04 PM PST 23
Finished Nov 22 01:26:11 PM PST 23
Peak memory 198044 kb
Host smart-9b1cdf5d-041d-443f-9aed-2a183f142af1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59337656722199566500567159958993826378805519472996974426792362616389693887096 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disable_rom_integrity_check.5933765672219956650056715995899382637880551947299697442
6792362616389693887096
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.79872853981528802390387522376178023026085464331437818743664127613143006773755
Short name T760
Test name
Test status
Simulation time 30368572 ps
CPU time 0.61 seconds
Started Nov 22 01:26:08 PM PST 23
Finished Nov 22 01:26:14 PM PST 23
Peak memory 195436 kb
Host smart-2db4aaa0-a28f-4b18-a7fd-5189d57cf9f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79872853981528802390387522376178023026085464331437818743664127613143006773755 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_malfunc.79872853981528802390387522376178023026085464331437818743664127613143006773755
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.41317099967282420106416705606014279796736881451951899354036755889706054031780
Short name T447
Test name
Test status
Simulation time 39672069 ps
CPU time 0.6 seconds
Started Nov 22 01:26:13 PM PST 23
Finished Nov 22 01:26:20 PM PST 23
Peak memory 195480 kb
Host smart-348b45d8-d3cc-447b-a1ef-c2b360c3b339
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41317099967282420106416705606014279796736881451951899354036755889706054031780 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.41317099967282420106416705606014279796736881451951899354036755889706054031780
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.29813052609703657583341469903154957814780489511091344759034020115946763670995
Short name T815
Test name
Test status
Simulation time 33172121 ps
CPU time 0.6 seconds
Started Nov 22 01:26:13 PM PST 23
Finished Nov 22 01:26:20 PM PST 23
Peak memory 196824 kb
Host smart-2e9cb77e-9cf4-4c00-9741-e0db34f83cfe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29813052609703657583341469903154957814780489511091344759034020115946763670995 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.29813052609703657583341469903154957814780489511091344759034020115946763670995
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.83435356860916341924867499946255057109769762529667739948837848754597094630664
Short name T393
Test name
Test status
Simulation time 49975558 ps
CPU time 0.68 seconds
Started Nov 22 01:26:19 PM PST 23
Finished Nov 22 01:26:23 PM PST 23
Peak memory 201236 kb
Host smart-677c51a1-de69-4cc8-ab86-e1bd33bd20ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83435356860916341924867499946255057109769762529667739948837848754597094630664 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invalid.83435356860916341924867499946255057109769762529667739948837848754597094630664
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_wakeup_race.94931650469184883713453632092068331746388697968647120595481951890677484979888
Short name T351
Test name
Test status
Simulation time 296241445 ps
CPU time 1.23 seconds
Started Nov 22 01:26:10 PM PST 23
Finished Nov 22 01:26:17 PM PST 23
Peak memory 200068 kb
Host smart-dc662788-a9e2-44c5-b8d7-dd131cdb8c03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94931650469184883713453632092068331746388697968647120595481951890677484979888 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wakeup_race.94931650469184883713453632092068331746388697968647120595481951890677484979888
Directory /workspace/7.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.6241348323681314734647703119264776289557104945063894641095855118447797325220
Short name T970
Test name
Test status
Simulation time 119707143 ps
CPU time 1.09 seconds
Started Nov 22 01:25:50 PM PST 23
Finished Nov 22 01:25:56 PM PST 23
Peak memory 199328 kb
Host smart-cd9cac50-fee0-42dd-9476-2bf623cf11c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6241348323681314734647703119264776289557104945063894641095855118447797325220 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.6241348323681314734647703119264776289557104945063894641095855118447797325220
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.31919566619359051138019726209550252619949505721959392786500615918741375000114
Short name T286
Test name
Test status
Simulation time 108189378 ps
CPU time 0.82 seconds
Started Nov 22 01:26:05 PM PST 23
Finished Nov 22 01:26:11 PM PST 23
Peak memory 209332 kb
Host smart-1ae80453-8b6d-4d0b-aee4-d31ff0da00c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31919566619359051138019726209550252619949505721959392786500615918741375000114 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.31919566619359051138019726209550252619949505721959392786500615918741375000114
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.37206690736180730273323299428400725126819866249281786381643773643346190180444
Short name T486
Test name
Test status
Simulation time 314830582 ps
CPU time 1.35 seconds
Started Nov 22 01:26:07 PM PST 23
Finished Nov 22 01:26:14 PM PST 23
Peak memory 199804 kb
Host smart-b277596b-276f-4514-8b68-5f1c20bf07bd
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37206690736180730273323299428400725126819866249281786381643773643346190180444 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_ctrl_config_regwen.3720669073618073027332329942840072512681986624928178638164
3773643346190180444
Directory /workspace/7.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.57960838027058087229157670486282913692709663889376727606682608374489478292957
Short name T378
Test name
Test status
Simulation time 919450745 ps
CPU time 2.88 seconds
Started Nov 22 01:25:48 PM PST 23
Finished Nov 22 01:25:55 PM PST 23
Peak memory 201072 kb
Host smart-830cbfe6-199e-4d39-9c0f-5068801657b5
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579608380270580872291576704862829136927096638893767276066826
08374489478292957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.579608380270580872291576704
86282913692709663889376727606682608374489478292957
Directory /workspace/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.14022930339756962347825697994996016773746765114850311803708742628199125313541
Short name T508
Test name
Test status
Simulation time 968503924 ps
CPU time 3.03 seconds
Started Nov 22 01:26:08 PM PST 23
Finished Nov 22 01:26:17 PM PST 23
Peak memory 201056 kb
Host smart-8042f6af-1b7b-4190-8df5-0cd64ba9f86a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14022930339756962347825697994996016773746765114850311803708
742628199125313541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1402293033975696234782569
7994996016773746765114850311803708742628199125313541
Directory /workspace/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.42628604703733970634885825273007502219790347577527345667741981022824569654910
Short name T915
Test name
Test status
Simulation time 91600225 ps
CPU time 0.92 seconds
Started Nov 22 01:26:08 PM PST 23
Finished Nov 22 01:26:14 PM PST 23
Peak memory 195524 kb
Host smart-1d5975e0-08dd-40cf-b0fe-acd125aec2d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42628604703733970634885825273007502219790347577527345667741981022824569654910 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_mubi.42628604703733970634885825273007502219790347577527345667741981022824569654910
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.14258995524524556251408983872991747956260271126604339139772047239546918007987
Short name T642
Test name
Test status
Simulation time 35743529 ps
CPU time 0.65 seconds
Started Nov 22 01:25:52 PM PST 23
Finished Nov 22 01:26:00 PM PST 23
Peak memory 197808 kb
Host smart-68b4153c-00c7-4621-847f-b2d8cca6c03f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14258995524524556251408983872991747956260271126604339139772047239546918007987 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.14258995524524556251408983872991747956260271126604339139772047239546918007987
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_stress_all.86078159405441801833435514773576073749132672695193315438868828586060886407444
Short name T482
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.57 seconds
Started Nov 22 01:26:07 PM PST 23
Finished Nov 22 01:26:18 PM PST 23
Peak memory 201164 kb
Host smart-ee89217b-9b0a-40ae-8c3c-9bf0da8cc3be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86078159405441801833435514773576073749132672695193315438868828586060886407444 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.86078159405441801833435514773576073749132672695193315438868828586060886407444
Directory /workspace/7.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/7.pwrmgr_stress_all_with_rand_reset.63462177217733484772301998800678337484384838038709782556889333523918553289400
Short name T333
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.07 seconds
Started Nov 22 01:26:05 PM PST 23
Finished Nov 22 01:26:22 PM PST 23
Peak memory 201312 kb
Host smart-3fe540bd-43b9-4b7b-8854-54d00d6d73f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634621772177334847723019
98800678337484384838038709782556889333523918553289400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all_with_rand_reset.634621
77217733484772301998800678337484384838038709782556889333523918553289400
Directory /workspace/7.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup.18944422840800487243197762239778599587647396111527507065554479521554082759957
Short name T324
Test name
Test status
Simulation time 283777259 ps
CPU time 1.16 seconds
Started Nov 22 01:25:52 PM PST 23
Finished Nov 22 01:25:59 PM PST 23
Peak memory 199968 kb
Host smart-3bf9199b-bfad-46f3-abe3-354f82feba1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18944422840800487243197762239778599587647396111527507065554479521554082759957 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.18944422840800487243197762239778599587647396111527507065554479521554082759957
Directory /workspace/7.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup_reset.14193279435661102590009934840546882530786793433133764264255480029832941459585
Short name T326
Test name
Test status
Simulation time 325437640 ps
CPU time 1.4 seconds
Started Nov 22 01:25:52 PM PST 23
Finished Nov 22 01:26:00 PM PST 23
Peak memory 200664 kb
Host smart-e11e20b5-0bed-470a-8d68-842c07b1dec4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14193279435661102590009934840546882530786793433133764264255480029832941459585 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.14193279435661102590009934840546882530786793433133764264255480029832941459585
Directory /workspace/7.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.42413599949121866625653897940523834520065893344120515813636727729483936963299
Short name T390
Test name
Test status
Simulation time 51975542 ps
CPU time 0.79 seconds
Started Nov 22 01:26:08 PM PST 23
Finished Nov 22 01:26:14 PM PST 23
Peak memory 199128 kb
Host smart-da5932e1-fcd1-49f2-8c21-f83fbc981960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42413599949121866625653897940523834520065893344120515813636727729483936963299 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.pwrmgr_aborted_low_power.42413599949121866625653897940523834520065893344120515813636727729483936963299
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.31566276986759612917837060847922256935418163153627755335909571640853492999476
Short name T114
Test name
Test status
Simulation time 72403950 ps
CPU time 0.73 seconds
Started Nov 22 01:25:51 PM PST 23
Finished Nov 22 01:25:58 PM PST 23
Peak memory 198276 kb
Host smart-9b03d2e5-f114-4cc1-bf6b-db60cc608e62
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31566276986759612917837060847922256935418163153627755335909571640853492999476 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disable_rom_integrity_check.3156627698675961291783706084792225693541816315362775533
5909571640853492999476
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.32612939293770607485730063668343168858674131428057029923932887569667421702641
Short name T141
Test name
Test status
Simulation time 30368572 ps
CPU time 0.61 seconds
Started Nov 22 01:25:57 PM PST 23
Finished Nov 22 01:26:02 PM PST 23
Peak memory 195412 kb
Host smart-bcce2d66-e809-4016-a3ff-fc44f3326f07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32612939293770607485730063668343168858674131428057029923932887569667421702641 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_malfunc.32612939293770607485730063668343168858674131428057029923932887569667421702641
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.5528601567452528005337506465558149322352145080815415930606700289384392346920
Short name T710
Test name
Test status
Simulation time 39672069 ps
CPU time 0.62 seconds
Started Nov 22 01:25:52 PM PST 23
Finished Nov 22 01:25:59 PM PST 23
Peak memory 195464 kb
Host smart-0d6b5822-ea6c-43ff-a9b0-34f54ad70eea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5528601567452528005337506465558149322352145080815415930606700289384392346920 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.5528601567452528005337506465558149322352145080815415930606700289384392346920
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.8427075393712326503201325693944612710249121738294081767635317710057846259069
Short name T1062
Test name
Test status
Simulation time 33172121 ps
CPU time 0.6 seconds
Started Nov 22 01:26:12 PM PST 23
Finished Nov 22 01:26:18 PM PST 23
Peak memory 196740 kb
Host smart-d85c8d57-3e83-470f-b7ba-3ac7f36fd69f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8427075393712326503201325693944612710249121738294081767635317710057846259069 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.8427075393712326503201325693944612710249121738294081767635317710057846259069
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.49638330855616616416749859968379603084115500858223952999836139848190800366826
Short name T408
Test name
Test status
Simulation time 49975558 ps
CPU time 0.72 seconds
Started Nov 22 01:25:54 PM PST 23
Finished Nov 22 01:26:01 PM PST 23
Peak memory 201216 kb
Host smart-1fb7d812-9262-4ca0-acb5-5b1728737bfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49638330855616616416749859968379603084115500858223952999836139848190800366826 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invalid.49638330855616616416749859968379603084115500858223952999836139848190800366826
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_wakeup_race.57176042119751197001282324301741341851601099415255816737407492997841007880795
Short name T140
Test name
Test status
Simulation time 296241445 ps
CPU time 1.26 seconds
Started Nov 22 01:25:54 PM PST 23
Finished Nov 22 01:26:01 PM PST 23
Peak memory 200056 kb
Host smart-1f44e4c0-fa15-4559-9f7c-68c9201d9be3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57176042119751197001282324301741341851601099415255816737407492997841007880795 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wakeup_race.57176042119751197001282324301741341851601099415255816737407492997841007880795
Directory /workspace/8.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.115316106830677063288562119403394260064356464871129163555888045799507993048179
Short name T586
Test name
Test status
Simulation time 119707143 ps
CPU time 1.05 seconds
Started Nov 22 01:26:13 PM PST 23
Finished Nov 22 01:26:20 PM PST 23
Peak memory 198648 kb
Host smart-c95ff237-a223-4146-bef6-4c19b4fbc016
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115316106830677063288562119403394260064356464871129163555888045799507993048179 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.115316106830677063288562119403394260064356464871129163555888045799507993048179
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.13968317503632884388410169867918932864880036974513901392356260248167801337508
Short name T429
Test name
Test status
Simulation time 108189378 ps
CPU time 0.84 seconds
Started Nov 22 01:25:52 PM PST 23
Finished Nov 22 01:25:59 PM PST 23
Peak memory 209560 kb
Host smart-1f125848-97b9-4ee9-913c-657fa5a7d255
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13968317503632884388410169867918932864880036974513901392356260248167801337508 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.13968317503632884388410169867918932864880036974513901392356260248167801337508
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.33472783335232915243749468095906643857741119105053576329317337846910357335829
Short name T551
Test name
Test status
Simulation time 314830582 ps
CPU time 1.36 seconds
Started Nov 22 01:26:01 PM PST 23
Finished Nov 22 01:26:07 PM PST 23
Peak memory 199904 kb
Host smart-06ec9402-f7e1-4f43-bf38-83ad84fde57b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33472783335232915243749468095906643857741119105053576329317337846910357335829 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_ctrl_config_regwen.3347278333523291524374946809590664385774111910505357632931
7337846910357335829
Directory /workspace/8.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.91617655999534805346922093579191604918407734396427755541558624883026844426702
Short name T19
Test name
Test status
Simulation time 919450745 ps
CPU time 2.75 seconds
Started Nov 22 01:25:53 PM PST 23
Finished Nov 22 01:26:02 PM PST 23
Peak memory 201260 kb
Host smart-75a68eb0-237a-47f3-a140-92ec014c00d9
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916176559995348053469220935791916049184077343964277555415586
24883026844426702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.916176559995348053469220935
79191604918407734396427755541558624883026844426702
Directory /workspace/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.73486149332908347325499449762324114914463000654921652116844196733981429928188
Short name T519
Test name
Test status
Simulation time 968503924 ps
CPU time 3.07 seconds
Started Nov 22 01:26:09 PM PST 23
Finished Nov 22 01:26:19 PM PST 23
Peak memory 201232 kb
Host smart-bd4b8b29-bb89-47c8-b053-1dc70f093292
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73486149332908347325499449762324114914463000654921652116844
196733981429928188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.7348614933290834732549944
9762324114914463000654921652116844196733981429928188
Directory /workspace/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.23554060244816552716402384275830216046859392982862800765503869119136552232896
Short name T614
Test name
Test status
Simulation time 91600225 ps
CPU time 0.93 seconds
Started Nov 22 01:26:13 PM PST 23
Finished Nov 22 01:26:20 PM PST 23
Peak memory 194776 kb
Host smart-eaff8733-83a1-4c8e-aefc-87f3a483e761
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23554060244816552716402384275830216046859392982862800765503869119136552232896 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_mubi.23554060244816552716402384275830216046859392982862800765503869119136552232896
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.47651911780197644728547378872400235668780642668942919100896826827126888993275
Short name T1048
Test name
Test status
Simulation time 35743529 ps
CPU time 0.62 seconds
Started Nov 22 01:26:09 PM PST 23
Finished Nov 22 01:26:15 PM PST 23
Peak memory 197876 kb
Host smart-1c5c472a-a51d-4b2e-b43d-adf23887a4b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47651911780197644728547378872400235668780642668942919100896826827126888993275 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.47651911780197644728547378872400235668780642668942919100896826827126888993275
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_stress_all.95021030720978086565106388575003379047773008986128105668790329170462715893107
Short name T422
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.57 seconds
Started Nov 22 01:25:54 PM PST 23
Finished Nov 22 01:26:05 PM PST 23
Peak memory 201104 kb
Host smart-f49cc09e-bc7b-484f-8c3d-962c2288ea45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95021030720978086565106388575003379047773008986128105668790329170462715893107 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all.95021030720978086565106388575003379047773008986128105668790329170462715893107
Directory /workspace/8.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/8.pwrmgr_stress_all_with_rand_reset.28839788083240797647450580184264563011280485612680438870777100530319646840549
Short name T533
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.36 seconds
Started Nov 22 01:25:56 PM PST 23
Finished Nov 22 01:26:13 PM PST 23
Peak memory 201424 kb
Host smart-9cc4971e-91b5-4ef6-8cf3-6619ef899e69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288397880832407976474505
80184264563011280485612680438870777100530319646840549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all_with_rand_reset.288397
88083240797647450580184264563011280485612680438870777100530319646840549
Directory /workspace/8.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup.66585087034714027933836752596923815476858087936179324448654116089094181679247
Short name T129
Test name
Test status
Simulation time 283777259 ps
CPU time 1.21 seconds
Started Nov 22 01:26:07 PM PST 23
Finished Nov 22 01:26:13 PM PST 23
Peak memory 200060 kb
Host smart-7f7293df-f6b3-4bb1-944e-ea47019a710e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66585087034714027933836752596923815476858087936179324448654116089094181679247 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.66585087034714027933836752596923815476858087936179324448654116089094181679247
Directory /workspace/8.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup_reset.92913592651757959086697919051378196567294732650930331561147134023636735904414
Short name T717
Test name
Test status
Simulation time 325437640 ps
CPU time 1.4 seconds
Started Nov 22 01:26:08 PM PST 23
Finished Nov 22 01:26:14 PM PST 23
Peak memory 200392 kb
Host smart-a2592b7d-edb6-4a26-9624-6cbe47ab0652
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92913592651757959086697919051378196567294732650930331561147134023636735904414 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.92913592651757959086697919051378196567294732650930331561147134023636735904414
Directory /workspace/8.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.1202589117286786295975775334298574946253104858919940394766042636815214584750
Short name T306
Test name
Test status
Simulation time 51975542 ps
CPU time 0.81 seconds
Started Nov 22 01:25:57 PM PST 23
Finished Nov 22 01:26:03 PM PST 23
Peak memory 199136 kb
Host smart-e5e72b22-25d0-4997-b952-3c61a5fbdcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202589117286786295975775334298574946253104858919940394766042636815214584750 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 9.pwrmgr_aborted_low_power.1202589117286786295975775334298574946253104858919940394766042636815214584750
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.47726343711093875847283064184587747365367394925907476481840122271256585287245
Short name T113
Test name
Test status
Simulation time 72403950 ps
CPU time 0.8 seconds
Started Nov 22 01:26:03 PM PST 23
Finished Nov 22 01:26:09 PM PST 23
Peak memory 198224 kb
Host smart-8679113c-44fa-4625-b5b5-5985e9ec541d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47726343711093875847283064184587747365367394925907476481840122271256585287245 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disable_rom_integrity_check.4772634371109387584728306418458774736536739492590747648
1840122271256585287245
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.59906184679652706687562141692144626674538326949445515734272944744171018522340
Short name T1040
Test name
Test status
Simulation time 30368572 ps
CPU time 0.59 seconds
Started Nov 22 01:25:57 PM PST 23
Finished Nov 22 01:26:02 PM PST 23
Peak memory 195456 kb
Host smart-dbfb5be6-1ee2-4efc-853f-4a512d43b801
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59906184679652706687562141692144626674538326949445515734272944744171018522340 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co
verage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_malfunc.59906184679652706687562141692144626674538326949445515734272944744171018522340
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.103387091356229218352468759006751110403639206968584635788516882309915546206148
Short name T573
Test name
Test status
Simulation time 39672069 ps
CPU time 0.6 seconds
Started Nov 22 01:25:57 PM PST 23
Finished Nov 22 01:26:02 PM PST 23
Peak memory 195480 kb
Host smart-0fda1c4e-6238-4565-bbd9-befa68d70f84
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103387091356229218352468759006751110403639206968584635788516882309915546206148 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.103387091356229218352468759006751110403639206968584635788516882309915546206148
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.22651277750559821568843731268521112953264689461688386649789691150968568148199
Short name T176
Test name
Test status
Simulation time 33172121 ps
CPU time 0.58 seconds
Started Nov 22 01:26:09 PM PST 23
Finished Nov 22 01:26:15 PM PST 23
Peak memory 196900 kb
Host smart-22249101-015e-479c-adc7-5f167e3fb21d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22651277750559821568843731268521112953264689461688386649789691150968568148199 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.22651277750559821568843731268521112953264689461688386649789691150968568148199
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.102782993366601352367745855969505946455899683593106296633158655790204212143458
Short name T666
Test name
Test status
Simulation time 49975558 ps
CPU time 0.69 seconds
Started Nov 22 01:25:57 PM PST 23
Finished Nov 22 01:26:03 PM PST 23
Peak memory 201340 kb
Host smart-8abc1c31-3e83-43bd-8c0d-38e72d189601
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102782993366601352367745855969505946455899683593106296633158655790204212143458 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invalid.102782993366601352367745855969505946455899683593106296633158655790204212143458
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_wakeup_race.86708482063473309751820221085177844211788657762784532535581730907016069083265
Short name T939
Test name
Test status
Simulation time 296241445 ps
CPU time 1.14 seconds
Started Nov 22 01:26:09 PM PST 23
Finished Nov 22 01:26:16 PM PST 23
Peak memory 200104 kb
Host smart-6f3d0280-b968-4911-aabe-82b150170bc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86708482063473309751820221085177844211788657762784532535581730907016069083265 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c
overage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wakeup_race.86708482063473309751820221085177844211788657762784532535581730907016069083265
Directory /workspace/9.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.87422236678172556440643397534568468015551088131415525709385023731956219329470
Short name T1064
Test name
Test status
Simulation time 119707143 ps
CPU time 1.02 seconds
Started Nov 22 01:26:08 PM PST 23
Finished Nov 22 01:26:14 PM PST 23
Peak memory 199316 kb
Host smart-2425d5f5-fa2b-49b7-9cf7-75773aba385c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87422236678172556440643397534568468015551088131415525709385023731956219329470 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default
.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.87422236678172556440643397534568468015551088131415525709385023731956219329470
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.89810580936062119766480884711036506719225415127755497017627997911560431291699
Short name T568
Test name
Test status
Simulation time 108189378 ps
CPU time 0.82 seconds
Started Nov 22 01:26:10 PM PST 23
Finished Nov 22 01:26:17 PM PST 23
Peak memory 208728 kb
Host smart-b84a01e0-4c0b-4943-96a5-662f6349e6ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89810580936062119766480884711036506719225415127755497017627997911560431291699 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.89810580936062119766480884711036506719225415127755497017627997911560431291699
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.115365126400167563267243272697700096248854878783923239520492080399874716677837
Short name T48
Test name
Test status
Simulation time 314830582 ps
CPU time 1.34 seconds
Started Nov 22 01:25:58 PM PST 23
Finished Nov 22 01:26:04 PM PST 23
Peak memory 199852 kb
Host smart-3c0df57b-d7de-4633-a255-bb585fc28c10
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115365126400167563267243272697700096248854878783923239520492080399874716677837 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_ctrl_config_regwen.115365126400167563267243272697700096248854878783923239520
492080399874716677837
Directory /workspace/9.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.17594471921747341789159311795435194967499914724126879203660997661748571730218
Short name T312
Test name
Test status
Simulation time 919450745 ps
CPU time 2.97 seconds
Started Nov 22 01:26:00 PM PST 23
Finished Nov 22 01:26:08 PM PST 23
Peak memory 201188 kb
Host smart-2396643a-0fd7-41af-ba22-2136ab8fdc80
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175944719217473417891593117954351949674999147241268792036609
97661748571730218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.175944719217473417891593117
95435194967499914724126879203660997661748571730218
Directory /workspace/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.44922843326248319054259924071154639706795482460531153990130808383131637848731
Short name T1068
Test name
Test status
Simulation time 968503924 ps
CPU time 3.03 seconds
Started Nov 22 01:25:57 PM PST 23
Finished Nov 22 01:26:05 PM PST 23
Peak memory 201136 kb
Host smart-0406c97a-d829-4133-8f8a-70974718940a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44922843326248319054259924071154639706795482460531153990130
808383131637848731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4492284332624831905425992
4071154639706795482460531153990130808383131637848731
Directory /workspace/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.34553515049257304454272914813608193754400094484463233851787979313684522864238
Short name T1039
Test name
Test status
Simulation time 91600225 ps
CPU time 0.89 seconds
Started Nov 22 01:26:08 PM PST 23
Finished Nov 22 01:26:14 PM PST 23
Peak memory 195520 kb
Host smart-44bb7c93-a3a9-4dd6-aa78-7c1a12c4dce5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34553515049257304454272914813608193754400094484463233851787979313684522864238 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_mubi.34553515049257304454272914813608193754400094484463233851787979313684522864238
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.104127520101238022887132951265355009297747086406489401434856654706151832984596
Short name T997
Test name
Test status
Simulation time 35743529 ps
CPU time 0.66 seconds
Started Nov 22 01:25:57 PM PST 23
Finished Nov 22 01:26:03 PM PST 23
Peak memory 197872 kb
Host smart-767bc857-a6b0-484f-a80d-c6b7ebe2715f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104127520101238022887132951265355009297747086406489401434856654706151832984596 -assert nopostpr
oc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.104127520101238022887132951265355009297747086406489401434856654706151832984596
Directory /workspace/9.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_stress_all.35117244220222138503244914011277965013628795055788986303184524602033034315137
Short name T31
Test name
Test status
Simulation time 2072030810 ps
CPU time 5.79 seconds
Started Nov 22 01:26:11 PM PST 23
Finished Nov 22 01:26:23 PM PST 23
Peak memory 201276 kb
Host smart-001197ea-4f1a-4eb0-a08a-3a15f65bb5eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35117244220222138503244914011277965013628795055788986303184524602033034315137 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.35117244220222138503244914011277965013628795055788986303184524602033034315137
Directory /workspace/9.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/9.pwrmgr_stress_all_with_rand_reset.52510073619745534841701972202437738806003294095738131486733919072618265496257
Short name T825
Test name
Test status
Simulation time 4441243999 ps
CPU time 11.22 seconds
Started Nov 22 01:26:07 PM PST 23
Finished Nov 22 01:26:23 PM PST 23
Peak memory 201412 kb
Host smart-718c5b6f-1ef9-4f33-8376-b9582974b682
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525100736197455348417019
72202437738806003294095738131486733919072618265496257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all_with_rand_reset.525100
73619745534841701972202437738806003294095738131486733919072618265496257
Directory /workspace/9.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup.21763298813470145376295971735812504590327238163642524012210950482396545966183
Short name T626
Test name
Test status
Simulation time 283777259 ps
CPU time 1.17 seconds
Started Nov 22 01:26:07 PM PST 23
Finished Nov 22 01:26:13 PM PST 23
Peak memory 200092 kb
Host smart-42fed27e-a709-4e8f-9d2c-b584466e3a5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21763298813470145376295971735812504590327238163642524012210950482396545966183 -assert nopostpro
c +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul
t.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.21763298813470145376295971735812504590327238163642524012210950482396545966183
Directory /workspace/9.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup_reset.7856279863490474302969564322511545336469418555150426680719773808799543678243
Short name T996
Test name
Test status
Simulation time 325437640 ps
CPU time 1.45 seconds
Started Nov 22 01:26:11 PM PST 23
Finished Nov 22 01:26:18 PM PST 23
Peak memory 200788 kb
Host smart-e7bf6184-fc5c-4a28-a318-670969dc3228
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7856279863490474302969564322511545336469418555150426680719773808799543678243 -assert nopostproc
+UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d
efault.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.7856279863490474302969564322511545336469418555150426680719773808799543678243
Directory /workspace/9.pwrmgr_wakeup_reset/latest
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