Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34771

1

T1

16

T3

50

T4

7

auto[1]

33377

1

T1

14

T3

50

T4

8

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34852

1

T1

22

T3

42

T4

10

auto[1]

33296

1

T1

8

T3

58

T4

5

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33440

1

T1

8

T3

50

T4

5

auto[1]

34708

1

T1

22

T3

50

T4

10

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

38738

1

T1

15

T3

50

T4

15

auto[1]

29410

1

T1

15

T3

50

T6

50

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33430

1

T1

20

T3

52

T4

5

auto[1]

34718

1

T1

10

T3

48

T4

10

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35123

1

T1

14

T3

46

T4

7

auto[1]

33025

1

T1

16

T3

54

T4

8

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1140

1

T1

1

T6

1

T8

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

862

1

T1

1

T6

1

T8

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1201

1

T3

1

T6

1

T50

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

902

1

T3

1

T6

1

T50

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1240

1

T3

4

T4

1

T6

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

928

1

T3

4

T6

1

T10

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1911

1

T1

1

T4

1

T6

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1626

1

T1

1

T6

5

T8

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1178

1

T1

1

T6

1

T8

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

891

1

T1

1

T6

1

T8

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1181

1

T1

2

T3

2

T4

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

898

1

T1

2

T3

2

T6

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1214

1

T3

1

T4

1

T6

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

927

1

T3

1

T6

4

T8

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1181

1

T1

1

T3

5

T4

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

896

1

T1

1

T3

5

T8

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1244

1

T3

2

T6

3

T8

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

919

1

T3

2

T6

3

T8

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1175

1

T6

2

T8

1

T10

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

883

1

T6

2

T8

1

T10

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1198

1

T3

1

T6

1

T10

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

881

1

T3

1

T6

1

T10

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1160

1

T1

1

T3

2

T6

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

882

1

T1

1

T3

2

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1188

1

T3

1

T8

1

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

905

1

T3

1

T8

1

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1177

1

T3

4

T8

1

T50

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

910

1

T3

4

T8

1

T15

14

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1171

1

T1

1

T3

2

T4

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

881

1

T1

1

T3

2

T6

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1145

1

T4

1

T6

1

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

876

1

T6

1

T8

1

T9

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1179

1

T3

2

T4

1

T6

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

892

1

T3

2

T6

1

T8

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1266

1

T1

2

T3

1

T4

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

965

1

T1

2

T3

1

T6

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1194

1

T3

1

T4

1

T6

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

892

1

T3

1

T6

2

T8

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1183

1

T1

1

T3

1

T4

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

899

1

T1

1

T3

1

T6

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1182

1

T1

1

T6

1

T8

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

893

1

T1

1

T6

1

T8

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1173

1

T1

1

T3

2

T4

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

884

1

T1

1

T3

2

T8

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1178

1

T6

4

T8

1

T9

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

878

1

T6

4

T8

1

T9

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1156

1

T3

1

T6

2

T8

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

862

1

T3

1

T6

2

T8

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1196

1

T3

2

T6

3

T10

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

906

1

T3

2

T6

3

T10

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1203

1

T1

1

T3

3

T8

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

916

1

T1

1

T3

3

T8

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1232

1

T3

1

T8

4

T50

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

937

1

T3

1

T8

4

T15

22

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1208

1

T3

2

T4

1

T6

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

903

1

T3

2

T6

1

T8

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1203

1

T3

6

T6

1

T8

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

920

1

T3

6

T6

1

T8

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1137

1

T1

1

T4

1

T6

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

861

1

T1

1

T6

1

T8

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1148

1

T3

2

T8

2

T9

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

843

1

T3

2

T8

2

T9

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1196

1

T3

1

T4

1

T8

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

892

1

T3

1

T8

1

T15

20