Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32430 1 T1 5 T3 56 T4 14
auto[1] 31380 1 T1 7 T3 44 T4 25


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32664 1 T1 7 T3 52 T4 19
auto[1] 31146 1 T1 5 T3 48 T4 20


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31442 1 T1 4 T3 38 T4 24
auto[1] 32368 1 T1 8 T3 62 T4 15


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 36154 1 T1 12 T3 50 T4 30
auto[1] 27656 1 T3 50 T4 9 T5 568


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31101 1 T1 8 T3 46 T4 20
auto[1] 32709 1 T1 4 T3 54 T4 19


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32624 1 T1 6 T3 46 T4 20
auto[1] 31186 1 T1 6 T3 54 T4 19


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1133 1 T1 1 T5 29 T10 1
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 871 1 T5 19 T74 1 T21 15
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1120 1 T3 2 T4 1 T5 23
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 839 1 T3 2 T5 17 T33 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1161 1 T3 1 T5 28 T7 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 883 1 T3 1 T5 22 T7 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1712 1 T3 2 T5 33 T7 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1461 1 T3 2 T5 29 T7 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1152 1 T1 1 T3 1 T4 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 869 1 T3 1 T5 18 T33 3
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 1087 1 T3 3 T5 22 T7 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 833 1 T3 3 T5 18 T7 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1095 1 T3 2 T4 2 T5 20
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 841 1 T3 2 T4 1 T5 14
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1057 1 T1 1 T3 3 T4 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 797 1 T3 3 T5 10 T7 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1074 1 T3 3 T4 1 T5 14
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 811 1 T3 3 T5 14 T33 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1124 1 T3 1 T4 1 T5 18
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 853 1 T3 1 T4 1 T5 14
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1092 1 T1 1 T3 1 T5 14
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 846 1 T3 1 T5 12 T7 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1109 1 T3 2 T4 1 T5 27
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 856 1 T3 2 T5 21 T7 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1145 1 T3 3 T4 1 T5 26
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 877 1 T3 3 T4 1 T5 18
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1042 1 T1 1 T3 1 T5 28
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 809 1 T3 1 T5 27 T7 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1079 1 T3 1 T5 23 T9 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 829 1 T3 1 T5 19 T9 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1125 1 T3 2 T4 1 T5 28
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 848 1 T3 2 T5 21 T7 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1132 1 T1 1 T3 2 T4 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 863 1 T3 2 T4 1 T5 20
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1066 1 T1 1 T3 1 T4 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 842 1 T3 1 T5 17 T6 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1162 1 T3 1 T4 2 T5 31
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 894 1 T3 1 T4 1 T5 17
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1106 1 T3 2 T4 1 T5 23
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 820 1 T3 2 T5 15 T7 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1057 1 T5 17 T6 2 T33 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 777 1 T5 16 T6 1 T33 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1145 1 T1 1 T3 2 T5 20
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 856 1 T3 2 T5 13 T33 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1134 1 T3 2 T4 4 T5 21
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 856 1 T3 2 T4 1 T5 17
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1156 1 T1 1 T3 2 T5 26
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 887 1 T3 2 T5 18 T33 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1091 1 T4 1 T5 38 T10 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 818 1 T4 1 T5 27 T33 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1112 1 T1 1 T3 2 T4 2
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 826 1 T3 2 T4 1 T5 15
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1095 1 T3 1 T4 1 T5 27
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 867 1 T3 1 T5 26 T7 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1129 1 T1 1 T3 2 T4 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 856 1 T3 2 T4 1 T5 10
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1099 1 T3 1 T4 3 T5 20
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 825 1 T3 1 T5 17 T7 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1124 1 T1 1 T3 1 T4 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 829 1 T3 1 T5 16 T9 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1144 1 T5 20 T10 1 T21 16
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 870 1 T5 16 T10 1 T21 15
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1095 1 T3 3 T4 1 T5 20
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 847 1 T3 3 T5 15 T9 1

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