Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
17240 |
1 |
|
|
T2 |
5 |
|
T3 |
38 |
|
T5 |
401 |
auto[1] |
27023 |
1 |
|
|
T2 |
2 |
|
T3 |
43 |
|
T5 |
607 |
Summary for Variable reset_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for reset_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37270 |
1 |
|
|
T2 |
6 |
|
T3 |
64 |
|
T4 |
9 |
auto[1] |
9793 |
1 |
|
|
T2 |
1 |
|
T3 |
17 |
|
T5 |
236 |
Summary for Variable sleep_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sleep_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
19520 |
1 |
|
|
T2 |
7 |
|
T3 |
31 |
|
T5 |
440 |
auto[1] |
27543 |
1 |
|
|
T3 |
50 |
|
T4 |
9 |
|
T5 |
568 |
Summary for Cross reset_cross
Samples crossed: reset_cp enable_cp sleep_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for reset_cross
Bins
reset_cp | enable_cp | sleep_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
4543 |
1 |
|
|
T2 |
4 |
|
T3 |
9 |
|
T5 |
100 |
auto[0] |
auto[0] |
auto[1] |
9357 |
1 |
|
|
T3 |
25 |
|
T5 |
214 |
|
T33 |
18 |
auto[0] |
auto[1] |
auto[0] |
5004 |
1 |
|
|
T2 |
2 |
|
T3 |
5 |
|
T5 |
104 |
auto[0] |
auto[1] |
auto[1] |
15566 |
1 |
|
|
T3 |
25 |
|
T5 |
354 |
|
T33 |
32 |
auto[1] |
auto[0] |
auto[0] |
3340 |
1 |
|
|
T2 |
1 |
|
T3 |
4 |
|
T5 |
87 |
auto[1] |
auto[1] |
auto[0] |
6453 |
1 |
|
|
T3 |
13 |
|
T5 |
149 |
|
T14 |
2 |
User Defined Cross Bins for reset_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
illegal |
0 |
Illegal |