Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 34074 1 T1 10 T2 9 T3 6
auto[1] 31991 1 T1 20 T2 9 T4 12


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33627 1 T1 20 T2 10 T3 6
auto[1] 32438 1 T1 10 T2 8 T4 6


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32373 1 T1 14 T2 7 T3 4
auto[1] 33692 1 T1 16 T2 11 T3 2


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 37738 1 T1 15 T2 18 T3 4
auto[1] 28327 1 T1 15 T3 2 T4 12


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 32293 1 T1 16 T2 10 T3 3
auto[1] 33772 1 T1 14 T2 8 T3 3


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33770 1 T1 14 T2 12 T3 3
auto[1] 32295 1 T1 16 T2 6 T3 3


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1162 1 T1 1 T2 1 T7 9
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 866 1 T1 1 T7 6 T25 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1143 1 T2 1 T4 1 T7 15
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 848 1 T4 1 T7 14 T25 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1197 1 T1 1 T2 1 T3 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 887 1 T1 1 T3 1 T4 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1929 1 T1 1 T7 24 T25 5
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1630 1 T1 1 T7 20 T25 5
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1153 1 T2 1 T3 1 T7 11
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 889 1 T7 9 T19 1 T14 8
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 1166 1 T3 1 T4 1 T7 11
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 870 1 T3 1 T4 1 T7 9
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1179 1 T2 1 T7 15 T14 12
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 909 1 T7 12 T14 10 T21 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1128 1 T4 1 T7 13 T25 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 825 1 T4 1 T7 10 T25 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1174 1 T7 10 T25 2 T14 11
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 901 1 T7 9 T25 2 T14 9
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1158 1 T1 1 T2 1 T7 12
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 855 1 T1 1 T7 11 T14 6
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1151 1 T7 14 T25 2 T39 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 840 1 T7 11 T25 2 T19 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1160 1 T1 1 T2 1 T7 13
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 873 1 T1 1 T7 11 T25 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1162 1 T2 1 T7 12 T25 3
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 853 1 T7 12 T25 3 T14 12
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1177 1 T4 1 T7 9 T14 18
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 868 1 T4 1 T7 6 T14 15
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1165 1 T4 1 T7 9 T25 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 885 1 T4 1 T7 9 T25 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1193 1 T2 1 T7 7 T19 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 878 1 T7 6 T19 2 T14 5
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1149 1 T2 1 T7 10 T14 19
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 859 1 T7 8 T14 14 T21 3
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1080 1 T1 1 T2 1 T7 15
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 823 1 T1 1 T7 13 T25 2
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1146 1 T2 1 T7 7 T14 15
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 840 1 T7 7 T14 9 T21 3
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1104 1 T2 1 T7 12 T25 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 822 1 T7 10 T25 1 T19 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1125 1 T1 2 T4 2 T7 7
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 834 1 T1 2 T4 2 T7 4
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1143 1 T1 2 T2 1 T4 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 849 1 T1 2 T4 1 T7 6
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1154 1 T1 1 T7 13 T25 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 845 1 T1 1 T7 12 T25 2
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1181 1 T1 1 T4 2 T7 15
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 892 1 T1 1 T4 2 T7 15
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1236 1 T7 17 T25 2 T39 2
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 910 1 T7 15 T25 2 T14 16
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1152 1 T2 2 T4 1 T7 11
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 876 1 T4 1 T7 9 T39 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1154 1 T1 1 T7 7 T39 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 862 1 T1 1 T7 7 T19 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1142 1 T2 1 T7 11 T25 2
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 841 1 T7 10 T25 2 T14 6
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1146 1 T1 1 T7 6 T25 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 836 1 T1 1 T7 5 T25 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1159 1 T7 14 T25 1 T39 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 871 1 T7 13 T25 1 T39 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1094 1 T7 6 T25 1 T19 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 810 1 T7 6 T25 1 T19 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1176 1 T1 1 T2 1 T7 7
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 880 1 T1 1 T7 5 T25 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%