Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31456

1

T2

12

T3

3

T5

20

auto[1]

30414

1

T2

28

T3

3

T5

10

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31504

1

T2

18

T3

2

T5

10

auto[1]

30366

1

T2

22

T3

4

T5

20

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30360

1

T2

18

T3

5

T5

20

auto[1]

31510

1

T2

22

T3

1

T5

10

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34976

1

T2

20

T3

4

T5

15

auto[1]

26894

1

T2

20

T3

2

T5

15

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30231

1

T2

16

T3

3

T5

10

auto[1]

31639

1

T2

24

T3

3

T5

20

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31525

1

T2

16

T3

2

T5

14

auto[1]

30345

1

T2

24

T3

4

T5

16

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1072

1

T9

1

T10

2

T75

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

786

1

T10

1

T75

1

T42

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1039

1

T2

1

T6

1

T7

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

806

1

T2

1

T6

1

T7

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1076

1

T6

2

T7

2

T8

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

829

1

T6

2

T7

2

T8

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1793

1

T5

1

T6

1

T7

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1517

1

T5

1

T6

1

T7

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1061

1

T5

1

T6

2

T7

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

801

1

T5

1

T6

2

T7

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1058

1

T6

2

T7

3

T9

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

799

1

T6

2

T7

3

T41

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1072

1

T5

1

T6

2

T7

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

812

1

T5

1

T6

2

T7

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1045

1

T2

1

T6

2

T7

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

802

1

T2

1

T6

2

T7

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1038

1

T5

2

T6

1

T9

7

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

813

1

T5

2

T6

1

T9

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1051

1

T6

1

T7

1

T8

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

787

1

T6

1

T7

1

T8

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1071

1

T3

1

T6

1

T7

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

816

1

T3

1

T6

1

T7

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1071

1

T5

1

T6

3

T7

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

794

1

T5

1

T6

3

T7

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1111

1

T2

2

T7

2

T9

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

830

1

T2

2

T7

2

T41

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1076

1

T3

1

T5

1

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

815

1

T5

1

T6

1

T7

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1042

1

T5

1

T6

6

T7

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

801

1

T5

1

T6

6

T7

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1108

1

T2

2

T5

2

T7

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

864

1

T2

2

T5

2

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1064

1

T2

1

T5

1

T6

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

826

1

T2

1

T5

1

T6

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1040

1

T6

3

T7

1

T41

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

790

1

T6

3

T7

1

T41

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1055

1

T2

1

T6

3

T7

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

826

1

T2

1

T6

3

T7

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1098

1

T6

1

T7

2

T9

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

827

1

T6

1

T7

2

T9

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1097

1

T2

2

T3

1

T6

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

886

1

T2

2

T3

1

T6

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1037

1

T2

1

T7

1

T8

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

786

1

T2

1

T7

1

T8

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1089

1

T2

1

T5

1

T6

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

830

1

T2

1

T5

1

T6

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1075

1

T2

1

T7

1

T8

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

810

1

T2

1

T7

1

T8

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1115

1

T7

1

T8

1

T9

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

873

1

T7

1

T8

1

T9

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1107

1

T2

1

T6

3

T7

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

859

1

T2

1

T6

3

T7

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1043

1

T2

1

T5

2

T6

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

787

1

T2

1

T5

2

T6

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1042

1

T2

3

T6

2

T7

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

814

1

T2

3

T6

2

T7

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1076

1

T6

2

T7

1

T8

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

832

1

T6

2

T7

1

T8

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1084

1

T6

1

T7

4

T9

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

816

1

T6

1

T7

4

T147

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1099

1

T2

1

T3

1

T5

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

831

1

T2

1

T5

1

T6

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1071

1

T2

1

T6

1

T9

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

829

1

T2

1

T6

1

T9

1