Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22134

1

T5

2

T14

22

T15

44

auto[1]

21818

1

T14

18

T15

56

T16

1

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22380

1

T5

2

T14

26

T15

36

auto[1]

21572

1

T14

14

T15

64

T16

1

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21324

1

T14

18

T15

50

T16

1

auto[1]

22628

1

T5

2

T14

22

T15

50

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24889

1

T5

1

T14

20

T15

50

auto[1]

19063

1

T5

1

T14

20

T15

50

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21736

1

T14

24

T15

66

T16

2

auto[1]

22216

1

T5

2

T14

16

T15

34

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22357

1

T5

2

T14

20

T15

40

auto[1]

21595

1

T14

20

T15

60

T16

2

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

756

1

T14

1

T15

3

T57

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

571

1

T14

1

T15

3

T47

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

801

1

T15

1

T57

1

T47

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

603

1

T15

1

T47

2

T80

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

757

1

T14

1

T61

3

T47

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

568

1

T14

1

T61

2

T47

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1177

1

T5

1

T14

2

T57

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

981

1

T5

1

T14

2

T46

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

739

1

T15

3

T28

1

T57

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

553

1

T15

3

T28

1

T57

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

766

1

T14

1

T15

2

T16

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

591

1

T14

1

T15

2

T46

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

750

1

T14

2

T15

1

T57

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

577

1

T14

2

T15

1

T57

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

757

1

T15

1

T57

2

T47

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

587

1

T15

1

T57

1

T47

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

745

1

T15

1

T57

2

T61

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

556

1

T15

1

T61

1

T50

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

756

1

T14

2

T15

1

T61

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

580

1

T14

2

T15

1

T47

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

723

1

T46

3

T61

2

T79

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

551

1

T46

3

T79

1

T47

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

772

1

T14

1

T15

2

T57

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

584

1

T14

1

T15

2

T151

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

768

1

T15

3

T57

1

T46

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

586

1

T15

3

T57

1

T46

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

732

1

T15

3

T28

1

T57

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

573

1

T15

3

T28

1

T151

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

733

1

T15

1

T47

2

T30

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

571

1

T15

1

T47

2

T30

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

778

1

T14

1

T57

1

T61

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

592

1

T14

1

T47

1

T80

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

797

1

T14

1

T57

1

T61

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

622

1

T14

1

T79

1

T47

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

794

1

T14

1

T15

2

T61

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

604

1

T14

1

T15

2

T47

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

722

1

T28

1

T57

2

T61

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

547

1

T28

1

T57

1

T79

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

784

1

T15

3

T57

3

T61

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

607

1

T15

3

T61

1

T47

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

751

1

T14

4

T46

2

T61

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

594

1

T14

4

T46

2

T61

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

785

1

T15

1

T57

1

T61

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

585

1

T15

1

T79

2

T47

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

748

1

T15

1

T57

3

T61

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

565

1

T15

1

T57

1

T61

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

765

1

T57

1

T46

1

T61

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

576

1

T46

1

T61

2

T47

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

813

1

T15

1

T57

2

T61

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

617

1

T15

1

T57

1

T61

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

750

1

T14

1

T15

4

T57

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

569

1

T14

1

T15

4

T57

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

709

1

T57

1

T61

1

T47

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

524

1

T61

1

T47

3

T152

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

798

1

T15

2

T28

1

T57

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

619

1

T15

2

T28

1

T57

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

773

1

T15

7

T16

1

T28

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

579

1

T15

7

T28

1

T46

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

805

1

T14

1

T15

1

T57

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

622

1

T14

1

T15

1

T46

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

827

1

T15

4

T57

2

T151

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

632

1

T15

4

T57

2

T151

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

758

1

T14

1

T15

2

T57

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

577

1

T14

1

T15

2

T57

1