Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18650

1

T1

50

T2

1

T3

15

auto[1]

17885

1

T1

50

T2

5

T3

14

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18423

1

T1

48

T2

4

T3

10

auto[1]

18112

1

T1

52

T2

2

T3

19

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18063

1

T1

42

T2

2

T3

19

auto[1]

18472

1

T1

58

T2

4

T3

10

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20719

1

T1

50

T2

4

T3

23

auto[1]

15816

1

T1

50

T2

2

T3

6

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18008

1

T1

58

T2

6

T3

17

auto[1]

18527

1

T1

42

T3

12

T5

3

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18842

1

T1

46

T2

2

T3

20

auto[1]

17693

1

T1

54

T2

4

T3

9

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

638

1

T1

1

T3

2

T5

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

487

1

T1

1

T3

1

T6

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

635

1

T1

1

T26

1

T15

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

498

1

T1

1

T26

1

T15

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

680

1

T1

1

T3

1

T44

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

506

1

T1

1

T3

1

T44

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

931

1

T1

2

T45

1

T26

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

763

1

T1

2

T45

1

T26

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

605

1

T1

3

T45

1

T26

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

450

1

T1

3

T45

1

T26

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

611

1

T1

2

T2

1

T5

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

477

1

T1

2

T5

1

T66

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

610

1

T26

2

T28

2

T15

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

456

1

T26

2

T28

2

T15

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

618

1

T1

1

T26

1

T50

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

470

1

T1

1

T26

1

T50

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

694

1

T1

2

T26

2

T28

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

530

1

T1

2

T26

2

T28

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

656

1

T1

1

T3

2

T26

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

490

1

T1

1

T26

3

T50

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

659

1

T1

1

T3

3

T28

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

504

1

T1

1

T28

3

T15

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

670

1

T1

3

T3

1

T45

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

513

1

T1

3

T3

1

T45

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

631

1

T3

2

T26

1

T60

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

482

1

T3

1

T26

1

T28

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

639

1

T1

2

T26

2

T60

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

491

1

T1

2

T26

2

T28

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

653

1

T1

1

T26

1

T15

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

511

1

T1

1

T26

1

T15

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

625

1

T1

4

T5

2

T26

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

467

1

T1

4

T26

2

T28

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

603

1

T1

2

T3

1

T5

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

464

1

T1

2

T5

1

T26

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

643

1

T1

2

T3

1

T5

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

454

1

T1

2

T5

1

T6

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

622

1

T44

1

T26

2

T66

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

495

1

T44

1

T26

2

T66

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

638

1

T1

1

T5

1

T6

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

482

1

T1

1

T6

1

T26

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

669

1

T1

1

T3

2

T5

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

495

1

T1

1

T26

2

T50

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

672

1

T1

3

T2

2

T26

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

516

1

T1

3

T2

1

T26

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

648

1

T1

3

T44

1

T60

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

502

1

T1

3

T15

2

T22

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

612

1

T1

1

T3

1

T26

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

473

1

T1

1

T26

2

T28

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

661

1

T1

1

T2

1

T3

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

526

1

T1

1

T2

1

T3

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

642

1

T1

3

T3

1

T26

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

485

1

T1

3

T3

1

T26

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

632

1

T1

1

T3

2

T26

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

486

1

T1

1

T26

2

T28

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

662

1

T1

1

T26

3

T28

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

493

1

T1

1

T26

3

T28

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

610

1

T1

3

T3

1

T26

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

460

1

T1

3

T26

2

T28

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

624

1

T1

2

T5

1

T8

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

470

1

T1

2

T5

1

T26

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

624

1

T1

1

T26

2

T28

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

470

1

T1

1

T26

2

T28

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

602

1

T3

2

T26

4

T66

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

450

1

T26

4

T66

1

T15

1