Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22318

1

T3

15

T4

54

T6

6

auto[1]

21603

1

T3

17

T4

46

T6

16

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22435

1

T3

18

T4

42

T6

10

auto[1]

21486

1

T3

14

T4

58

T6

12

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21663

1

T3

14

T4

56

T6

14

auto[1]

22258

1

T3

18

T4

44

T6

8

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24842

1

T3

25

T4

50

T6

11

auto[1]

19079

1

T3

7

T4

50

T6

11

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21631

1

T3

15

T4

52

T6

6

auto[1]

22290

1

T3

17

T4

48

T6

16

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22575

1

T3

15

T4

56

T6

12

auto[1]

21346

1

T3

17

T4

44

T6

10

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

791

1

T9

1

T14

2

T72

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

614

1

T9

1

T14

2

T72

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

750

1

T3

1

T4

3

T9

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

568

1

T3

1

T4

3

T9

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

789

1

T3

1

T4

2

T30

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

599

1

T4

2

T30

4

T14

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1184

1

T3

2

T4

1

T6

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1005

1

T4

1

T6

1

T9

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

803

1

T4

5

T9

2

T30

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

601

1

T4

5

T9

2

T30

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

786

1

T3

1

T9

2

T30

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

608

1

T9

2

T30

2

T14

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

711

1

T9

4

T53

1

T30

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

540

1

T9

4

T53

1

T30

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

739

1

T3

1

T4

3

T57

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

574

1

T4

3

T30

1

T14

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

782

1

T4

2

T30

1

T14

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

587

1

T4

2

T30

1

T14

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

752

1

T3

2

T4

1

T14

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

579

1

T3

1

T4

1

T14

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

751

1

T4

3

T9

1

T10

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

573

1

T4

3

T9

1

T30

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

746

1

T3

2

T4

1

T6

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

593

1

T3

1

T4

1

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

742

1

T3

1

T4

2

T9

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

566

1

T4

2

T9

4

T14

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

750

1

T4

2

T9

2

T30

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

567

1

T4

2

T9

2

T30

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

740

1

T4

1

T6

1

T9

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

569

1

T4

1

T6

1

T9

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

772

1

T3

1

T4

1

T9

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

587

1

T4

1

T9

1

T53

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

775

1

T6

1

T9

4

T10

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

600

1

T6

1

T9

4

T10

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

773

1

T4

1

T53

1

T30

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

571

1

T4

1

T53

1

T30

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

737

1

T3

1

T4

2

T9

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

565

1

T3

1

T4

2

T9

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

797

1

T3

2

T4

1

T30

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

599

1

T4

1

T30

1

T14

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

735

1

T3

2

T9

3

T30

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

550

1

T3

1

T9

3

T30

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

757

1

T3

1

T4

2

T6

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

606

1

T3

1

T4

2

T6

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

821

1

T3

2

T6

2

T9

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

612

1

T6

2

T9

1

T30

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

721

1

T4

1

T53

1

T14

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

554

1

T4

1

T53

1

T14

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

783

1

T4

3

T53

1

T14

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

616

1

T4

3

T53

1

T14

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

770

1

T4

4

T9

2

T57

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

598

1

T4

4

T9

2

T30

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

783

1

T4

3

T6

3

T30

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

593

1

T4

3

T6

3

T30

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

766

1

T4

1

T9

1

T53

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

586

1

T4

1

T9

1

T53

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

770

1

T3

2

T4

1

T9

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

579

1

T4

1

T9

4

T30

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

735

1

T3

1

T6

1

T9

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

567

1

T6

1

T9

3

T30

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

786

1

T3

2

T4

4

T9

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

600

1

T3

1

T4

4

T9

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

745

1

T9

3

T10

1

T53

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

553

1

T9

3

T10

1

T53

1