Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
debug_cp	2	0	2	100.00	100	1	1	0
dft_cp	2	0	2	100.00	100	1	1	0
done_cp	2	0	2	100.00	100	1	1	0
good_cp	2	0	2	100.00	100	1	1	0

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
blockers_cross	16	0	16	100.00	100	1	1	0

Summary for Variable debug_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for debug_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	47049	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

off

154063

1

T1

1

T2

1

T3

1

on

21772

1

T9

244

T28

4

T29

715

---

Summary for Variable dft_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for dft_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43102	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

off

156441

1

T1

1

T2

1

T3

1

on

23341

1

T9

996

T28

7

T29

272

---

Summary for Variable done_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for done_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	182826	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

23427

1

T4

50

T9

52

T30

132

true

16631

1

T1

1

T2

1

T3

1

---

Summary for Variable good_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for good_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	175360	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

14515

1

T4

50

T9

52

T30

66

true

33009

1

T1

1

T2

1

T3

1

---

Summary for Cross blockers_cross

Samples crossed: done_cp good_cp dft_cp debug_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for blockers_cross

Bins

done_cp	good_cp	dft_cp	debug_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
false	false	off	off	11744	1			T4	50		T9	2		T30	66
false	false	off	on	225	1			T9	3		T29	1		T131	1
false	false	on	off	229	1			T9	26		T28	1		T29	2
false	false	on	on	141	1			T9	1		T29	3		T43	1
false	true	off	off	9106	1			T30	66		T14	10		T73	40
false	true	off	on	3	1			T136	1		T137	1		T138	1
false	true	on	off	3	1			T139	1		T140	1		T141	1
false	true	on	on	1	1			T142	1		-	-		-	-
true	false	off	off	51	1			T113	1		T120	2		T123	1
true	false	off	on	16	1			T143	1		T144	1		T145	1
true	false	on	off	28	1			T28	1		T43	1		T120	1
true	false	on	on	71	1			T28	2		T43	3		T113	2
true	true	off	off	10953	1			T1	1		T2	1		T3	1
true	true	off	on	412	1			T9	5		T29	7		T113	1
true	true	on	off	413	1			T9	30		T28	1		T29	5
true	true	on	on	288	1			T9	5		T29	5		T130	8