Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 26495 1 T3 48 T4 10 T9 636
auto[1] 25327 1 T3 52 T4 9 T9 545


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 26606 1 T3 42 T4 9 T9 579
auto[1] 25216 1 T3 58 T4 10 T9 602


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25284 1 T3 54 T4 9 T9 570
auto[1] 26538 1 T3 46 T4 10 T9 611


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29163 1 T3 50 T4 19 T9 668
auto[1] 22659 1 T3 50 T9 513 T19 50


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 25560 1 T3 50 T4 14 T9 586
auto[1] 26262 1 T3 50 T4 5 T9 595


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 26158 1 T3 54 T4 9 T9 536
auto[1] 25664 1 T3 46 T4 10 T9 645


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 879 1 T3 1 T4 1 T9 18
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 703 1 T3 1 T9 12 T19 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 931 1 T3 1 T9 17 T10 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 739 1 T3 1 T9 13 T19 3
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 826 1 T9 13 T19 3 T20 3
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 644 1 T9 10 T19 3 T20 3
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1412 1 T3 3 T9 35 T38 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1214 1 T3 3 T9 28 T38 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 914 1 T3 3 T4 2 T9 29
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 707 1 T3 3 T9 24 T20 5
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 873 1 T4 2 T9 23 T10 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 665 1 T9 17 T19 2 T20 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 887 1 T9 14 T10 1 T19 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 682 1 T9 14 T19 2 T20 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 883 1 T3 2 T9 26 T10 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 686 1 T3 2 T9 23 T19 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 921 1 T3 4 T9 25 T10 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 701 1 T3 4 T9 20 T20 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 915 1 T3 1 T4 1 T9 25
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 705 1 T3 1 T9 19 T19 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 840 1 T3 2 T4 2 T9 21
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 647 1 T3 2 T9 17 T19 3
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 869 1 T3 1 T9 15 T19 3
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 679 1 T3 1 T9 11 T19 3
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 915 1 T3 2 T4 1 T9 22
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 735 1 T3 2 T9 19 T19 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 868 1 T3 1 T9 24 T49 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 663 1 T3 1 T9 18 T49 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 922 1 T3 3 T9 25 T10 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 712 1 T3 3 T9 18 T20 3
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 982 1 T4 1 T9 23 T38 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 776 1 T9 18 T38 1 T34 5
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 905 1 T3 2 T4 1 T9 20
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 682 1 T3 2 T9 16 T20 2
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 907 1 T3 1 T4 2 T9 10
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 714 1 T3 1 T9 7 T19 3
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 903 1 T3 1 T9 12 T19 2
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 711 1 T3 1 T9 8 T19 2
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 892 1 T3 1 T9 19 T19 3
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 700 1 T3 1 T9 18 T19 3
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 929 1 T9 22 T10 1 T19 2
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 721 1 T9 16 T19 2 T20 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 906 1 T3 1 T9 21 T19 2
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 698 1 T3 1 T9 12 T19 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 922 1 T3 3 T9 23 T10 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 690 1 T3 3 T9 16 T19 3
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 942 1 T3 2 T4 1 T9 24
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 739 1 T3 2 T9 19 T19 2
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 868 1 T4 1 T9 14 T10 2
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 652 1 T9 7 T19 1 T20 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 901 1 T3 4 T4 1 T9 18
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 688 1 T3 4 T9 13 T20 4
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 846 1 T3 2 T9 20 T20 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 639 1 T3 2 T9 13 T20 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 866 1 T3 3 T9 25 T19 2
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 659 1 T3 3 T9 17 T19 2
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 909 1 T3 2 T9 27 T20 2
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 717 1 T3 2 T9 24 T20 2
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 863 1 T3 2 T4 2 T9 20
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 666 1 T3 2 T9 14 T19 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 895 1 T3 2 T4 1 T9 17
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 660 1 T3 2 T9 14 T19 5
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 872 1 T9 21 T19 3 T38 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 665 1 T9 18 T19 3 T20 1

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