Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21671

1

T1

46

T2

40

T4

30

auto[1]

20727

1

T1

52

T2

60

T4

36

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21416

1

T1

56

T2

50

T4

33

auto[1]

20982

1

T1

42

T2

50

T4

33

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20817

1

T1

50

T2

52

T4

29

auto[1]

21581

1

T1

48

T2

48

T4

37

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24191

1

T1

49

T2

50

T4

53

auto[1]

18207

1

T1

49

T2

50

T4

13

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20913

1

T1

54

T2

58

T4

28

auto[1]

21485

1

T1

44

T2

42

T4

38

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21600

1

T1

44

T2

56

T4

30

auto[1]

20798

1

T1

54

T2

44

T4

36

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

775

1

T1

1

T2

1

T8

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

586

1

T1

1

T2

1

T8

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

720

1

T1

1

T2

1

T4

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

556

1

T1

1

T2

1

T9

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

756

1

T1

1

T2

1

T4

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

564

1

T1

1

T2

1

T4

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1095

1

T1

3

T2

2

T4

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

901

1

T1

3

T2

2

T9

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

698

1

T1

1

T2

2

T4

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

516

1

T1

1

T2

2

T4

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

731

1

T1

3

T2

2

T4

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

537

1

T1

3

T2

2

T8

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

796

1

T4

1

T8

2

T9

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

587

1

T8

2

T9

2

T10

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

683

1

T1

2

T4

1

T8

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

527

1

T1

2

T4

1

T8

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

757

1

T1

3

T2

2

T8

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

546

1

T1

3

T2

2

T8

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

779

1

T2

1

T9

3

T10

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

575

1

T2

1

T9

3

T10

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

752

1

T1

2

T9

2

T37

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

548

1

T1

2

T9

1

T37

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

779

1

T2

3

T4

2

T9

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

592

1

T2

3

T9

2

T10

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

784

1

T1

2

T2

3

T9

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

573

1

T1

2

T2

3

T9

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

747

1

T2

1

T4

2

T9

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

556

1

T2

1

T9

3

T10

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

763

1

T1

1

T4

3

T8

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

567

1

T1

1

T8

1

T9

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

756

1

T1

3

T2

1

T4

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

569

1

T1

3

T2

1

T8

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

749

1

T1

2

T2

2

T4

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

572

1

T1

2

T2

2

T4

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

751

1

T1

1

T2

3

T4

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

560

1

T1

1

T2

3

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

699

1

T1

2

T2

3

T9

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

518

1

T1

2

T2

3

T9

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

738

1

T1

2

T2

1

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

570

1

T1

2

T2

1

T10

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

727

1

T1

1

T2

3

T4

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

551

1

T1

1

T2

3

T9

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

804

1

T1

4

T2

1

T4

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

608

1

T1

4

T2

1

T9

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

752

1

T1

1

T2

2

T4

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

553

1

T1

1

T2

2

T4

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

716

1

T1

3

T2

1

T4

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

520

1

T1

3

T2

1

T10

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

728

1

T1

2

T2

2

T4

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

539

1

T1

2

T2

2

T4

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

767

1

T1

1

T2

2

T9

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

564

1

T1

1

T2

2

T9

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

718

1

T1

1

T2

3

T4

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

548

1

T1

1

T2

3

T4

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

748

1

T2

1

T4

4

T37

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

550

1

T2

1

T4

1

T37

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

714

1

T1

4

T2

1

T8

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

545

1

T1

4

T2

1

T8

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

720

1

T1

1

T2

2

T4

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

578

1

T1

1

T2

2

T4

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

758

1

T1

1

T2

1

T9

6

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

578

1

T1

1

T2

1

T9

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

731

1

T2

2

T4

1

T9

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

553

1

T2

2

T4

1

T9

1