Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23818

1

T2

2

T4

14

T5

58

auto[1]

22687

1

T2

4

T4

12

T5

42

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23437

1

T2

2

T4

8

T5

52

auto[1]

23068

1

T2

4

T4

18

T5

48

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23025

1

T2

4

T4

10

T5

42

auto[1]

23480

1

T2

2

T4

16

T5

58

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26302

1

T2

4

T4

13

T5

50

auto[1]

20203

1

T2

2

T4

13

T5

50

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22607

1

T4

14

T5

56

T6

6

auto[1]

23898

1

T2

6

T4

12

T5

44

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23747

1

T2

3

T4

8

T5

50

auto[1]

22758

1

T2

3

T4

18

T5

50

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

790

1

T5

2

T7

1

T8

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

591

1

T5

2

T8

1

T9

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

791

1

T5

2

T6

1

T8

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

593

1

T5

2

T8

1

T27

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

799

1

T5

1

T28

1

T15

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

609

1

T5

1

T28

1

T15

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1292

1

T5

3

T8

2

T28

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1098

1

T5

3

T8

2

T28

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

782

1

T5

3

T6

1

T8

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

593

1

T5

3

T8

3

T28

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

804

1

T4

1

T5

1

T8

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

606

1

T4

1

T5

1

T8

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

828

1

T5

1

T6

1

T8

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

611

1

T5

1

T8

2

T15

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

809

1

T4

1

T6

1

T8

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

621

1

T4

1

T8

1

T28

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

852

1

T5

2

T6

1

T7

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

642

1

T5

2

T7

1

T9

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

750

1

T5

2

T7

1

T8

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

582

1

T5

2

T7

1

T8

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

874

1

T2

1

T5

1

T28

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

666

1

T2

1

T5

1

T28

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

816

1

T5

3

T6

1

T7

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

613

1

T5

3

T7

1

T8

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

859

1

T4

1

T5

1

T8

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

660

1

T4

1

T5

1

T8

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

778

1

T4

1

T5

3

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

586

1

T4

1

T5

3

T28

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

826

1

T4

2

T5

2

T7

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

638

1

T4

2

T5

2

T27

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

822

1

T4

1

T5

2

T7

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

637

1

T4

1

T5

2

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

839

1

T5

4

T8

1

T9

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

644

1

T5

4

T8

1

T9

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

735

1

T5

1

T7

1

T8

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

572

1

T5

1

T8

1

T28

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

767

1

T4

1

T7

1

T8

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

578

1

T4

1

T8

3

T28

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

804

1

T5

3

T7

2

T8

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

611

1

T5

3

T7

1

T8

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

782

1

T5

1

T8

3

T28

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

589

1

T5

1

T8

3

T28

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

824

1

T4

1

T5

1

T7

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

637

1

T4

1

T5

1

T7

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

810

1

T2

1

T5

2

T8

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

617

1

T2

1

T5

2

T8

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

809

1

T5

1

T28

4

T27

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

602

1

T5

1

T28

4

T27

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

824

1

T4

1

T7

1

T8

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

632

1

T4

1

T7

1

T8

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

812

1

T4

1

T5

1

T7

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

628

1

T4

1

T5

1

T8

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

807

1

T7

1

T9

1

T15

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

615

1

T9

1

T15

2

T16

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

846

1

T2

1

T4

1

T7

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

675

1

T4

1

T8

4

T28

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

814

1

T5

1

T6

1

T8

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

632

1

T5

1

T8

1

T28

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

775

1

T4

1

T5

3

T6

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

609

1

T4

1

T5

3

T8

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

823

1

T7

2

T8

1

T28

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

632

1

T8

1

T28

1

T49

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

759

1

T2

1

T5

3

T8

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

584

1

T5

3

T8

2

T9

1