Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21790

1

T1

2

T4

21

T5

2

auto[1]

20960

1

T4

15

T6

20

T7

12

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21822

1

T1

2

T4

18

T5

2

auto[1]

20928

1

T4

18

T6

22

T7

12

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21238

1

T4

15

T6

14

T7

14

auto[1]

21512

1

T1

2

T4

21

T5

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24483

1

T1

1

T4

35

T5

1

auto[1]

18267

1

T1

1

T4

1

T5

1

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21195

1

T4

20

T6

18

T7

18

auto[1]

21555

1

T1

2

T4

16

T5

2

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21853

1

T1

2

T4

19

T5

2

auto[1]

20897

1

T4

17

T6

10

T7

14

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

789

1

T4

2

T65

2

T84

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

611

1

T84

1

T29

2

T28

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

738

1

T4

1

T15

1

T24

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

545

1

T84

1

T28

1

T61

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

773

1

T4

1

T6

1

T24

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

593

1

T6

1

T24

1

T84

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1109

1

T1

1

T4

2

T5

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

934

1

T1

1

T4

1

T5

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

781

1

T65

3

T29

3

T66

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

574

1

T29

3

T51

1

T61

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

727

1

T4

3

T7

3

T8

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

520

1

T7

3

T8

1

T47

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

757

1

T4

1

T47

2

T65

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

540

1

T47

2

T29

1

T28

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

738

1

T4

2

T24

5

T45

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

541

1

T24

2

T45

1

T47

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

777

1

T4

2

T7

1

T24

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

579

1

T7

1

T24

1

T45

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

753

1

T4

4

T6

2

T7

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

566

1

T6

2

T7

1

T45

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

725

1

T6

1

T15

1

T24

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

542

1

T6

1

T24

1

T29

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

750

1

T6

1

T8

1

T24

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

555

1

T6

1

T8

1

T45

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

766

1

T4

1

T24

8

T47

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

570

1

T24

4

T47

1

T65

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

756

1

T6

1

T47

1

T65

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

562

1

T6

1

T47

1

T65

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

726

1

T24

1

T45

2

T65

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

545

1

T45

2

T65

1

T29

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

777

1

T4

1

T6

1

T24

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

571

1

T6

1

T84

1

T51

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

750

1

T4

1

T6

1

T7

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

565

1

T6

1

T7

1

T84

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

824

1

T4

1

T24

3

T45

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

614

1

T24

1

T45

1

T171

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

761

1

T4

1

T6

1

T15

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

559

1

T6

1

T29

2

T66

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

675

1

T6

1

T65

3

T29

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

520

1

T6

1

T29

2

T28

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

765

1

T6

1

T24

1

T45

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

563

1

T6

1

T45

1

T171

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

746

1

T24

6

T45

2

T47

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

540

1

T24

1

T45

2

T47

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

763

1

T7

1

T45

1

T65

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

588

1

T7

1

T45

1

T65

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

758

1

T4

2

T6

1

T15

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

561

1

T6

1

T65

1

T29

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

747

1

T6

1

T7

1

T15

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

579

1

T6

1

T7

1

T45

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

747

1

T4

2

T6

2

T65

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

536

1

T6

2

T65

2

T29

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

801

1

T4

1

T6

1

T15

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

583

1

T6

1

T24

1

T45

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

721

1

T47

1

T65

2

T29

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

532

1

T47

1

T29

2

T28

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

742

1

T4

2

T7

2

T24

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

552

1

T7

2

T24

1

T45

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

768

1

T4

1

T6

1

T15

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

543

1

T6

1

T24

1

T29

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

736

1

T4

3

T7

1

T10

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

536

1

T7

1

T10

1

T45

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

737

1

T4

1

T24

8

T65

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

548

1

T24

2

T29

2

T28

3