Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23273

1

T3

2

T6

2

T8

18

auto[1]

22378

1

T3

2

T8

12

T10

2

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23544

1

T3

2

T6

2

T8

16

auto[1]

22107

1

T3

2

T8

14

T10

4

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22695

1

T3

2

T8

10

T10

2

auto[1]

22956

1

T3

2

T6

2

T8

20

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25895

1

T3

2

T6

1

T8

15

auto[1]

19756

1

T3

2

T6

1

T8

15

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22243

1

T3

4

T8

22

T51

12

auto[1]

23408

1

T6

2

T8

8

T10

4

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23279

1

T3

4

T6

2

T8

12

auto[1]

22372

1

T8

18

T10

2

T51

6

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

830

1

T51

1

T26

1

T27

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

637

1

T51

1

T26

1

T27

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

837

1

T3

1

T27

5

T63

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

638

1

T3

1

T27

5

T63

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

807

1

T62

1

T27

2

T63

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

613

1

T62

1

T27

2

T63

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1197

1

T6

1

T62

1

T27

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1018

1

T6

1

T62

1

T27

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

815

1

T8

1

T51

1

T26

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

605

1

T8

1

T51

1

T26

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

801

1

T8

1

T27

1

T39

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

614

1

T8

1

T27

1

T39

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

855

1

T27

2

T154

2

T39

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

655

1

T27

2

T154

2

T39

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

811

1

T8

2

T62

2

T27

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

614

1

T8

2

T62

2

T27

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

790

1

T8

1

T26

1

T52

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

592

1

T8

1

T26

1

T27

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

747

1

T8

2

T26

2

T62

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

563

1

T8

2

T26

2

T62

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

791

1

T51

1

T26

1

T27

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

598

1

T51

1

T26

1

T27

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

788

1

T26

1

T62

1

T63

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

585

1

T26

1

T62

1

T63

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

763

1

T8

1

T26

1

T27

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

592

1

T8

1

T26

1

T27

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

804

1

T8

1

T62

1

T52

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

610

1

T8

1

T62

1

T52

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

825

1

T26

1

T62

1

T63

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

612

1

T26

1

T62

1

T63

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

715

1

T10

1

T62

1

T52

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

551

1

T10

1

T62

1

T39

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

869

1

T12

1

T62

1

T154

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

629

1

T62

1

T154

1

T42

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

778

1

T8

1

T51

1

T26

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

594

1

T8

1

T51

1

T26

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

806

1

T51

1

T26

1

T62

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

613

1

T51

1

T26

1

T62

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

764

1

T27

1

T154

1

T39

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

586

1

T27

1

T154

1

T39

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

772

1

T27

3

T40

1

T42

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

566

1

T27

3

T40

1

T42

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

783

1

T8

2

T62

1

T39

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

593

1

T8

2

T62

1

T39

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

832

1

T8

1

T52

1

T27

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

654

1

T8

1

T52

1

T27

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

773

1

T62

1

T85

1

T154

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

585

1

T62

1

T85

1

T154

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

751

1

T3

1

T26

1

T27

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

569

1

T3

1

T26

1

T27

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

858

1

T8

1

T51

1

T62

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

646

1

T8

1

T51

1

T62

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

815

1

T8

1

T10

1

T27

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

626

1

T8

1

T10

1

T27

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

766

1

T62

1

T63

1

T39

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

578

1

T62

1

T63

1

T39

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

748

1

T51

2

T62

1

T27

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

564

1

T51

2

T62

1

T27

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

726

1

T26

1

T27

1

T63

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

559

1

T26

1

T27

1

T63

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

843

1

T26

2

T12

1

T62

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

658

1

T26

2

T62

1

T63

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

835

1

T26

1

T62

1

T27

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

639

1

T26

1

T62

1

T27

1