Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20964

1

T1

2

T3

8

T6

10

auto[1]

20432

1

T1

8

T3

10

T6

30

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21064

1

T1

6

T3

7

T6

18

auto[1]

20332

1

T1

4

T3

11

T6

22

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20243

1

T1

4

T3

7

T6

20

auto[1]

21153

1

T1

6

T3

11

T6

20

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23316

1

T1

5

T3

18

T6

20

auto[1]

18080

1

T1

5

T6

20

T10

41

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20241

1

T1

6

T3

7

T6

14

auto[1]

21155

1

T1

4

T3

11

T6

26

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21062

1

T1

2

T3

10

T6

24

auto[1]

20334

1

T1

8

T3

8

T6

16

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

707

1

T3

1

T10

1

T40

5

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

531

1

T40

1

T77

1

T20

6

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

713

1

T10

3

T40

1

T20

13

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

538

1

T10

2

T20

9

T38

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

701

1

T6

2

T10

2

T20

10

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

563

1

T6

2

T10

2

T20

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1118

1

T3

1

T6

1

T10

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

927

1

T6

1

T10

6

T77

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

689

1

T40

4

T13

1

T20

14

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

553

1

T40

3

T20

10

T38

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

707

1

T1

1

T10

2

T77

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

562

1

T1

1

T10

1

T77

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

687

1

T10

2

T40

3

T20

22

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

541

1

T10

1

T20

17

T38

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

756

1

T3

1

T10

4

T40

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

585

1

T10

3

T40

1

T20

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

728

1

T3

1

T10

2

T20

18

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

562

1

T10

2

T20

12

T38

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

717

1

T3

1

T10

1

T40

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

557

1

T10

1

T40

1

T20

10

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

706

1

T6

1

T10

1

T20

11

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

541

1

T6

1

T20

11

T38

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

737

1

T10

3

T40

2

T20

10

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

568

1

T10

2

T20

9

T38

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

718

1

T6

1

T10

4

T40

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

551

1

T6

1

T10

2

T40

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

636

1

T3

1

T10

2

T40

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

497

1

T10

2

T40

1

T20

10

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

738

1

T3

1

T40

1

T20

17

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

546

1

T40

1

T20

15

T21

11

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

735

1

T3

1

T10

1

T40

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

549

1

T10

1

T40

1

T20

10

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

712

1

T10

1

T40

1

T20

9

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

534

1

T10

1

T20

5

T38

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

724

1

T6

1

T10

1

T40

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

569

1

T6

1

T10

1

T20

10

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

693

1

T3

2

T6

1

T10

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

537

1

T6

1

T10

1

T20

15

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

695

1

T3

1

T6

1

T10

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

540

1

T6

1

T20

8

T21

9

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

707

1

T1

1

T6

1

T10

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

546

1

T1

1

T6

1

T10

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

784

1

T3

1

T6

1

T10

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

610

1

T6

1

T77

1

T20

13

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

735

1

T6

1

T10

2

T40

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

574

1

T6

1

T10

2

T40

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

691

1

T1

1

T10

1

T40

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

535

1

T1

1

T10

1

T77

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

728

1

T1

1

T6

1

T10

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

582

1

T1

1

T6

1

T10

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

730

1

T6

1

T10

1

T77

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

561

1

T6

1

T77

1

T20

9

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

716

1

T3

1

T6

1

T10

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

544

1

T6

1

T10

1

T20

9

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

736

1

T3

2

T6

2

T10

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

547

1

T6

2

T77

1

T20

10

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

701

1

T3

1

T6

1

T10

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

549

1

T6

1

T10

2

T40

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

700

1

T3

1

T10

3

T20

18

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

538

1

T10

2

T20

13

T38

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

752

1

T10

1

T40

2

T20

13

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

571

1

T10

1

T20

10

T38

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

719

1

T1

1

T3

1

T6

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

572

1

T1

1

T6

3

T77

1