Summary for Variable core_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for core_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
24498 |
1 |
|
|
T1 |
18 |
|
T2 |
64 |
|
T4 |
2 |
auto[1] |
23528 |
1 |
|
|
T1 |
16 |
|
T2 |
36 |
|
T4 |
4 |
Summary for Variable io_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for io_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
24245 |
1 |
|
|
T1 |
18 |
|
T2 |
54 |
|
T4 |
3 |
auto[1] |
23781 |
1 |
|
|
T1 |
16 |
|
T2 |
46 |
|
T4 |
3 |
Summary for Variable main_pd_n_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for main_pd_n_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
23754 |
1 |
|
|
T1 |
10 |
|
T2 |
52 |
|
T4 |
1 |
auto[1] |
24272 |
1 |
|
|
T1 |
24 |
|
T2 |
48 |
|
T4 |
5 |
Summary for Variable sleep_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sleep_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
27352 |
1 |
|
|
T1 |
17 |
|
T2 |
50 |
|
T4 |
4 |
auto[1] |
20674 |
1 |
|
|
T1 |
17 |
|
T2 |
50 |
|
T4 |
2 |
Summary for Variable usb_active_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for usb_active_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
23336 |
1 |
|
|
T1 |
14 |
|
T2 |
48 |
|
T5 |
64 |
auto[1] |
24690 |
1 |
|
|
T1 |
20 |
|
T2 |
52 |
|
T4 |
6 |
Summary for Variable usb_lp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for usb_lp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
24616 |
1 |
|
|
T1 |
16 |
|
T2 |
54 |
|
T4 |
2 |
auto[1] |
23410 |
1 |
|
|
T1 |
18 |
|
T2 |
46 |
|
T4 |
4 |
Summary for Cross control_cross
Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
64 |
0 |
64 |
100.00 |
|
Automatically Generated Cross Bins for control_cross
Bins
core_cp | io_cp | usb_lp_cp | usb_active_cp | main_pd_n_cp | sleep_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
837 |
1 |
|
|
T2 |
2 |
|
T5 |
2 |
|
T10 |
1 |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
621 |
1 |
|
|
T2 |
2 |
|
T5 |
2 |
|
T10 |
1 |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
811 |
1 |
|
|
T2 |
3 |
|
T5 |
4 |
|
T8 |
1 |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
617 |
1 |
|
|
T2 |
3 |
|
T5 |
4 |
|
T8 |
1 |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
864 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T6 |
4 |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
630 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T8 |
2 |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
1328 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T4 |
1 |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
1095 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T4 |
1 |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
814 |
1 |
|
|
T1 |
1 |
|
T5 |
1 |
|
T44 |
2 |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
625 |
1 |
|
|
T1 |
1 |
|
T5 |
1 |
|
T44 |
1 |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
837 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T5 |
3 |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
629 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T5 |
3 |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
860 |
1 |
|
|
T2 |
3 |
|
T5 |
1 |
|
T8 |
2 |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
642 |
1 |
|
|
T2 |
3 |
|
T5 |
1 |
|
T8 |
2 |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
824 |
1 |
|
|
T2 |
2 |
|
T6 |
1 |
|
T8 |
3 |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
630 |
1 |
|
|
T2 |
2 |
|
T8 |
3 |
|
T40 |
1 |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
881 |
1 |
|
|
T2 |
1 |
|
T5 |
2 |
|
T6 |
2 |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
678 |
1 |
|
|
T2 |
1 |
|
T5 |
2 |
|
T8 |
3 |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
841 |
1 |
|
|
T2 |
3 |
|
T8 |
2 |
|
T10 |
2 |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
621 |
1 |
|
|
T2 |
3 |
|
T8 |
2 |
|
T10 |
2 |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
838 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T5 |
2 |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
636 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T5 |
2 |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
850 |
1 |
|
|
T2 |
3 |
|
T8 |
2 |
|
T39 |
1 |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
629 |
1 |
|
|
T2 |
3 |
|
T8 |
2 |
|
T39 |
1 |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
864 |
1 |
|
|
T2 |
4 |
|
T5 |
3 |
|
T8 |
2 |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
633 |
1 |
|
|
T2 |
4 |
|
T5 |
3 |
|
T8 |
2 |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
799 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
2 |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
605 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
2 |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
836 |
1 |
|
|
T2 |
1 |
|
T5 |
2 |
|
T10 |
1 |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
641 |
1 |
|
|
T2 |
1 |
|
T5 |
2 |
|
T10 |
1 |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
842 |
1 |
|
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
2 |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
640 |
1 |
|
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
2 |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
829 |
1 |
|
|
T2 |
1 |
|
T5 |
2 |
|
T8 |
1 |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
617 |
1 |
|
|
T2 |
1 |
|
T5 |
2 |
|
T8 |
1 |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
812 |
1 |
|
|
T2 |
2 |
|
T5 |
2 |
|
T8 |
2 |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
606 |
1 |
|
|
T2 |
2 |
|
T5 |
2 |
|
T8 |
2 |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
854 |
1 |
|
|
T2 |
3 |
|
T5 |
1 |
|
T6 |
1 |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
661 |
1 |
|
|
T2 |
3 |
|
T5 |
1 |
|
T8 |
1 |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
810 |
1 |
|
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
2 |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
619 |
1 |
|
|
T1 |
1 |
|
T5 |
1 |
|
T8 |
2 |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
820 |
1 |
|
|
T5 |
3 |
|
T6 |
1 |
|
T8 |
1 |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
621 |
1 |
|
|
T5 |
3 |
|
T8 |
1 |
|
T39 |
1 |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
811 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
3 |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
617 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
3 |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
814 |
1 |
|
|
T2 |
1 |
|
T5 |
2 |
|
T8 |
4 |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
599 |
1 |
|
|
T2 |
1 |
|
T5 |
2 |
|
T8 |
4 |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
852 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T4 |
1 |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
639 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T5 |
1 |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
auto[0] |
885 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
2 |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
auto[1] |
659 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
2 |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
auto[0] |
819 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
2 |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
auto[1] |
587 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
2 |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
auto[0] |
912 |
1 |
|
|
T5 |
1 |
|
T8 |
1 |
|
T10 |
1 |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
auto[1] |
690 |
1 |
|
|
T5 |
1 |
|
T8 |
1 |
|
T10 |
1 |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
auto[0] |
828 |
1 |
|
|
T1 |
1 |
|
T5 |
3 |
|
T8 |
1 |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
auto[1] |
651 |
1 |
|
|
T1 |
1 |
|
T5 |
3 |
|
T8 |
1 |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
auto[0] |
841 |
1 |
|
|
T2 |
1 |
|
T8 |
2 |
|
T44 |
2 |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
auto[1] |
656 |
1 |
|
|
T2 |
1 |
|
T8 |
2 |
|
T61 |
1 |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
auto[0] |
828 |
1 |
|
|
T2 |
1 |
|
T5 |
1 |
|
T6 |
1 |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
auto[1] |
615 |
1 |
|
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
2 |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
auto[0] |
802 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T4 |
1 |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
auto[1] |
594 |
1 |
|
|
T1 |
1 |
|
T2 |
3 |
|
T39 |
1 |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
auto[0] |
909 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
2 |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
auto[1] |
671 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
2 |