Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24452

1

T1

4

T7

18

T8

8

auto[1]

23252

1

T1

2

T4

6

T7

12

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24594

1

T1

2

T4

3

T7

16

auto[1]

23110

1

T1

4

T4

3

T7

14

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23036

1

T1

4

T4

5

T7

8

auto[1]

24668

1

T1

2

T4

1

T7

22

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27133

1

T1

4

T4

4

T7

15

auto[1]

20571

1

T1

2

T4

2

T7

15

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23407

1

T1

5

T4

4

T7

14

auto[1]

24297

1

T1

1

T4

2

T7

16

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24458

1

T1

3

T4

3

T7

20

auto[1]

23246

1

T1

3

T4

3

T7

10

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

856

1

T1

1

T8

1

T11

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

648

1

T1

1

T8

1

T11

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

868

1

T7

2

T11

2

T37

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

647

1

T7

2

T11

2

T37

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

795

1

T38

1

T40

1

T85

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

603

1

T38

1

T40

1

T60

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1338

1

T7

2

T11

3

T36

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1101

1

T7

2

T11

3

T36

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

820

1

T11

2

T36

1

T37

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

631

1

T11

2

T36

1

T37

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

874

1

T36

1

T37

1

T38

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

650

1

T36

1

T37

1

T38

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

850

1

T7

1

T8

1

T11

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

638

1

T7

1

T8

1

T11

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

810

1

T42

1

T36

1

T40

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

639

1

T42

1

T36

1

T40

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

825

1

T7

1

T11

2

T36

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

619

1

T7

1

T11

2

T36

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

820

1

T7

1

T8

1

T11

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

620

1

T7

1

T8

1

T11

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

797

1

T8

1

T42

1

T11

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

602

1

T8

1

T11

1

T40

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

925

1

T1

1

T7

1

T42

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

675

1

T7

1

T36

2

T37

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

854

1

T11

1

T36

2

T40

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

643

1

T11

1

T36

2

T40

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

884

1

T1

1

T11

1

T40

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

659

1

T11

1

T40

4

T41

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

785

1

T7

1

T11

2

T37

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

584

1

T7

1

T11

2

T37

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

785

1

T36

2

T40

2

T41

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

607

1

T36

2

T40

2

T41

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

801

1

T8

1

T11

3

T36

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

627

1

T8

1

T11

3

T36

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

893

1

T11

2

T36

2

T40

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

663

1

T11

2

T36

2

T40

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

871

1

T4

1

T8

2

T11

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

664

1

T4

1

T8

2

T11

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

844

1

T7

1

T36

1

T37

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

628

1

T7

1

T36

1

T37

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

806

1

T8

2

T11

1

T36

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

606

1

T8

2

T11

1

T36

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

821

1

T4

1

T7

1

T11

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

631

1

T7

1

T11

2

T36

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

854

1

T7

1

T36

1

T37

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

631

1

T7

1

T36

1

T37

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

837

1

T8

2

T11

3

T36

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

649

1

T8

2

T11

3

T36

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

803

1

T4

1

T42

1

T11

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

609

1

T42

1

T11

4

T36

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

820

1

T7

1

T8

1

T11

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

607

1

T7

1

T8

1

T11

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

798

1

T11

1

T36

1

T40

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

595

1

T11

1

T36

1

T40

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

848

1

T7

1

T8

3

T11

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

648

1

T7

1

T8

3

T11

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

819

1

T1

1

T4

1

T36

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

603

1

T1

1

T4

1

T36

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

785

1

T7

1

T11

1

T40

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

595

1

T7

1

T11

1

T40

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

801

1

T8

1

T36

2

T37

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

598

1

T8

1

T36

2

T37

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

846

1

T8

3

T11

1

T36

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

651

1

T8

3

T11

1

T36

4