Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22058

1

T2

10

T6

15

T7

2

auto[1]

21192

1

T2

4

T6

10

T10

48

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22055

1

T2

6

T6

11

T7

2

auto[1]

21195

1

T2

8

T6

14

T10

50

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21226

1

T2

2

T6

9

T10

42

auto[1]

22024

1

T2

12

T6

16

T7

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24470

1

T2

7

T6

21

T7

1

auto[1]

18780

1

T2

7

T6

4

T7

1

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21335

1

T2

4

T6

13

T7

2

auto[1]

21915

1

T2

10

T6

12

T10

46

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22144

1

T2

4

T6

12

T10

48

auto[1]

21106

1

T2

10

T6

13

T7

2

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

781

1

T6

1

T10

2

T20

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

588

1

T10

2

T20

1

T12

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

741

1

T6

1

T10

4

T20

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

559

1

T10

4

T20

1

T12

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

787

1

T6

1

T10

1

T20

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

617

1

T10

1

T20

2

T12

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1157

1

T10

3

T20

1

T12

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

981

1

T10

3

T20

1

T12

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

714

1

T6

1

T10

2

T12

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

555

1

T10

2

T12

1

T14

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

756

1

T2

1

T6

2

T7

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

575

1

T2

1

T6

1

T7

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

769

1

T20

1

T12

4

T47

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

574

1

T20

1

T12

3

T47

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

755

1

T2

1

T6

1

T20

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

581

1

T2

1

T20

2

T12

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

771

1

T10

2

T20

4

T12

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

588

1

T10

2

T20

4

T12

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

753

1

T6

1

T20

2

T12

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

599

1

T20

2

T12

4

T47

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

726

1

T20

1

T12

3

T14

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

536

1

T20

1

T12

1

T14

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

725

1

T2

1

T6

1

T10

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

564

1

T2

1

T6

1

T10

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

726

1

T2

1

T20

1

T14

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

552

1

T2

1

T20

1

T14

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

771

1

T6

1

T10

3

T20

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

592

1

T6

1

T10

3

T20

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

737

1

T6

1

T10

4

T20

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

576

1

T10

4

T20

2

T12

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

769

1

T2

1

T6

1

T20

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

583

1

T2

1

T20

2

T12

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

776

1

T6

2

T10

2

T20

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

580

1

T10

2

T20

1

T12

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

771

1

T12

1

T36

1

T14

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

581

1

T12

1

T36

1

T14

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

718

1

T10

1

T20

3

T12

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

534

1

T10

1

T20

3

T12

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

767

1

T10

3

T39

1

T20

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

579

1

T10

3

T20

1

T12

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

760

1

T20

2

T12

1

T14

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

601

1

T20

2

T14

1

T37

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

738

1

T6

1

T10

2

T20

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

544

1

T10

2

T20

2

T14

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

736

1

T39

1

T20

2

T12

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

557

1

T20

2

T12

1

T14

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

752

1

T2

1

T10

1

T14

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

571

1

T2

1

T10

1

T14

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

770

1

T6

1

T10

2

T20

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

609

1

T10

2

T20

2

T12

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

734

1

T39

1

T20

2

T12

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

553

1

T39

1

T20

2

T12

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

756

1

T6

1

T20

1

T12

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

585

1

T20

1

T12

2

T14

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

761

1

T2

1

T6

1

T10

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

597

1

T2

1

T6

1

T10

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

758

1

T10

2

T20

2

T14

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

589

1

T10

2

T20

2

T14

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

777

1

T10

2

T20

2

T12

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

573

1

T10

2

T20

2

T12

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

737

1

T6

1

T10

3

T12

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

563

1

T10

3

T12

3

T14

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

721

1

T6

2

T10

3

T39

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

544

1

T10

3

T39

1

T20

2