Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 24392 1 T1 66 T2 41 T3 34
auto[1] 23641 1 T1 34 T2 42 T3 22


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 24753 1 T1 48 T2 45 T3 22
auto[1] 23280 1 T1 52 T2 38 T3 34


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 23540 1 T1 56 T2 38 T3 30
auto[1] 24493 1 T1 44 T2 45 T3 26


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 27288 1 T1 50 T2 65 T3 44
auto[1] 20745 1 T1 50 T2 18 T3 12


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 23288 1 T1 40 T2 38 T3 26
auto[1] 24745 1 T1 60 T2 45 T3 30


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 24501 1 T1 52 T2 36 T3 27
auto[1] 23532 1 T1 48 T2 47 T3 29


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 806 1 T1 1 T2 2 T3 3
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 612 1 T1 1 T2 1 T5 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 860 1 T1 2 T2 1 T3 2
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 665 1 T1 2 T5 2 T39 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 817 1 T1 6 T2 2 T3 3
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 622 1 T1 6 T2 1 T5 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1322 1 T1 2 T5 1 T9 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1121 1 T1 2 T5 1 T9 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 805 1 T1 2 T2 1 T3 2
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 618 1 T1 2 T2 1 T3 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 811 1 T1 2 T2 2 T3 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 612 1 T1 2 T2 1 T3 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 833 1 T1 1 T2 2 T5 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 639 1 T1 1 T2 2 T5 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 907 1 T1 1 T2 4 T3 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 704 1 T1 1 T2 2 T17 7
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 860 1 T1 2 T3 1 T5 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 655 1 T1 2 T5 2 T40 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 820 1 T1 1 T2 3 T3 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 613 1 T1 1 T2 2 T40 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 850 1 T1 2 T2 4 T3 4
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 636 1 T1 2 T3 1 T5 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 831 1 T1 2 T15 2 T62 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 616 1 T1 2 T24 10 T25 7
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 820 1 T1 2 T2 3 T3 3
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 623 1 T1 2 T2 1 T3 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 803 1 T1 2 T2 1 T15 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 589 1 T1 2 T17 8 T24 3
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 851 1 T2 3 T3 1 T39 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 649 1 T39 2 T40 1 T17 3
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 812 1 T1 5 T2 2 T3 4
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 610 1 T1 5 T3 3 T39 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 846 1 T2 1 T3 1 T5 2
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 643 1 T3 1 T5 2 T62 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 852 1 T2 5 T3 1 T4 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 655 1 T4 1 T5 2 T17 6
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 888 1 T1 2 T2 2 T5 1
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 672 1 T1 2 T2 1 T5 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 865 1 T1 1 T2 2 T3 2
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 644 1 T1 1 T2 1 T4 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 851 1 T1 2 T2 5 T5 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 630 1 T1 2 T5 1 T62 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 848 1 T2 2 T4 1 T5 2
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 652 1 T2 1 T4 1 T5 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 864 1 T3 1 T15 2 T39 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 654 1 T3 1 T39 1 T40 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 821 1 T1 2 T2 2 T5 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 614 1 T1 2 T2 1 T5 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 792 1 T1 1 T62 1 T17 6
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 591 1 T1 1 T17 5 T24 3
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 795 1 T2 2 T3 1 T5 2
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 618 1 T5 2 T17 3 T24 3
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 822 1 T1 3 T2 2 T3 2
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 612 1 T1 3 T3 1 T5 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 854 1 T1 1 T2 3 T3 3
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 646 1 T1 1 T2 1 T5 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 800 1 T1 2 T3 2 T4 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 616 1 T1 2 T3 1 T4 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 873 1 T1 1 T2 3 T3 2
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 654 1 T1 1 T3 1 T17 3
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 889 1 T1 2 T2 3 T5 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 674 1 T1 2 T2 1 T5 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 820 1 T2 3 T3 2 T5 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 586 1 T2 1 T5 1 T83 1

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