Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
debug_cp	2	0	2	100.00	100	1	1	0
dft_cp	2	0	2	100.00	100	1	1	0
done_cp	2	0	2	100.00	100	1	1	0
good_cp	2	0	2	100.00	100	1	1	0

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
blockers_cross	16	1	15	93.75	100	1	1	0

Summary for Variable debug_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for debug_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45252	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

off

159722

1

T1

259

T2

1

T3

1

on

19326

1

T1

93

T8

7

T27

4

---

Summary for Variable dft_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for dft_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46727	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

off

157789

1

T1

194

T2

1

T3

1

on

19784

1

T1

1015

T8

8

T27

4

---

Summary for Variable done_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for done_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	182813	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

24547

1

T1

53

T5

76

T8

2

true

16940

1

T1

116

T2

1

T3

1

---

Summary for Variable good_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for good_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	175353	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

15100

1

T1

53

T5

38

T8

4

true

33847

1

T1

166

T2

1

T3

1

---

Summary for Cross blockers_cross

Samples crossed: done_cp good_cp dft_cp debug_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for blockers_cross

Uncovered bins

done_cp	good_cp	dft_cp	debug_cp	COUNT	AT LEAST	NUMBER	STATUS
[false]	[true]	[on]	[on]	0	1	1

Covered bins

done_cp

good_cp

dft_cp

debug_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

false

false

off

off

12353

1

T1

1

T5

38

T39

18

false

false

off

on

155

1

T1

3

T41

1

T82

1

false

false

on

off

206

1

T8

1

T48

1

T95

36

false

false

on

on

116

1

T82

1

T91

3

T150

1

false

true

off

off

9654

1

T5

38

T39

18

T40

8

false

true

off

on

6

1

T134

1

T151

1

T152

1

false

true

on

off

5

1

T153

1

T154

1

T155

1

true

false

off

off

65

1

T8

1

T27

2

T41

1

true

false

off

on

16

1

T41

1

T48

1

T144

1

true

false

on

off

22

1

T8

1

T48

1

T143

1

true

false

on

on

90

1

T8

1

T27

1

T41

1

true

true

off

off

11326

1

T1

9

T2

1

T3

1

true

true

off

on

317

1

T1

5

T41

1

T82

4

true

true

on

off

376

1

T1

4

T8

1

T82

3

true

true

on

on

286

1

T1

1

T82

5

T91

6