Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8503

1

T1

54

T3

1

T7

16

auto[1]

8157

1

T1

46

T3

5

T7

8

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8372

1

T1

56

T3

1

T7

12

auto[1]

8288

1

T1

44

T3

5

T7

12

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8175

1

T1

56

T3

4

T7

6

auto[1]

8485

1

T1

44

T3

2

T7

18

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9238

1

T1

50

T3

4

T7

12

auto[1]

7422

1

T1

50

T3

2

T7

12

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8310

1

T1

56

T3

6

T7

8

auto[1]

8350

1

T1

44

T7

16

T9

20

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8342

1

T1

52

T3

1

T7

10

auto[1]

8318

1

T1

48

T3

5

T7

14

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

270

1

T1

3

T3

1

T27

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

215

1

T1

3

T27

2

T28

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

327

1

T1

1

T7

1

T27

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

255

1

T1

1

T7

1

T27

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

306

1

T1

1

T7

1

T9

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

241

1

T1

1

T7

1

T9

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

378

1

T1

3

T9

2

T28

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

328

1

T1

3

T9

2

T28

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

265

1

T1

4

T27

5

T41

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

208

1

T1

4

T27

5

T41

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

269

1

T1

1

T9

1

T27

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

216

1

T1

1

T9

1

T27

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

296

1

T1

4

T9

1

T11

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

240

1

T1

4

T9

1

T11

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

292

1

T1

1

T7

2

T11

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

234

1

T1

1

T7

2

T11

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

293

1

T1

2

T9

1

T11

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

240

1

T1

2

T9

1

T11

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

305

1

T1

3

T9

1

T27

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

240

1

T1

3

T9

1

T27

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

271

1

T7

1

T11

1

T27

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

212

1

T7

1

T11

1

T27

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

270

1

T1

1

T9

1

T11

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

217

1

T1

1

T9

1

T11

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

271

1

T11

1

T27

2

T28

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

233

1

T11

1

T27

2

T28

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

300

1

T1

2

T7

1

T9

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

252

1

T1

2

T7

1

T9

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

328

1

T1

1

T7

1

T11

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

257

1

T1

1

T7

1

T11

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

265

1

T7

1

T9

1

T27

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

209

1

T7

1

T9

1

T27

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

250

1

T1

2

T27

4

T28

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

204

1

T1

2

T27

4

T28

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

282

1

T1

1

T7

1

T9

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

218

1

T1

1

T7

1

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

270

1

T1

1

T9

1

T27

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

226

1

T1

1

T9

1

T27

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

287

1

T1

2

T7

1

T9

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

222

1

T1

2

T7

1

T9

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

301

1

T1

2

T9

1

T11

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

252

1

T1

2

T9

1

T11

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

307

1

T9

1

T27

5

T28

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

246

1

T9

1

T27

5

T28

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

278

1

T1

1

T27

1

T28

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

220

1

T1

1

T27

1

T28

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

259

1

T1

1

T28

1

T16

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

210

1

T1

1

T28

1

T41

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

264

1

T1

1

T9

2

T27

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

221

1

T1

1

T9

2

T27

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

295

1

T1

2

T11

3

T27

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

226

1

T1

2

T11

3

T27

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

289

1

T1

2

T11

1

T41

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

219

1

T1

2

T11

1

T41

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

280

1

T1

1

T9

2

T11

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

221

1

T1

1

T9

2

T11

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

297

1

T1

2

T3

2

T11

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

240

1

T1

2

T3

1

T11

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

307

1

T1

2

T3

1

T7

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

241

1

T1

2

T3

1

T7

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

274

1

T1

2

T41

4

T17

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

224

1

T1

2

T41

4

T25

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

292

1

T1

1

T7

1

T27

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

235

1

T1

1

T7

1

T27

1