Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.72 98.23 96.58 90.98 96.00 96.37 100.00 98.85


Total test records in report: 980
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T805 /workspace/coverage/default/6.pwrmgr_reset_invalid.182756562 Mar 12 12:49:59 PM PDT 24 Mar 12 12:50:00 PM PDT 24 154247947 ps
T806 /workspace/coverage/default/12.pwrmgr_aborted_low_power.3614327707 Mar 12 12:50:11 PM PDT 24 Mar 12 12:50:12 PM PDT 24 42731605 ps
T807 /workspace/coverage/default/47.pwrmgr_lowpower_wakeup_race.1207755799 Mar 12 12:51:55 PM PDT 24 Mar 12 12:51:56 PM PDT 24 191084258 ps
T808 /workspace/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.3105366177 Mar 12 12:51:04 PM PDT 24 Mar 12 12:51:06 PM PDT 24 210775521 ps
T809 /workspace/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2731946411 Mar 12 12:50:42 PM PDT 24 Mar 12 12:50:44 PM PDT 24 987787355 ps
T810 /workspace/coverage/default/10.pwrmgr_reset_invalid.1730754746 Mar 12 12:50:20 PM PDT 24 Mar 12 12:50:21 PM PDT 24 136339784 ps
T811 /workspace/coverage/default/44.pwrmgr_reset.1243150832 Mar 12 12:51:56 PM PDT 24 Mar 12 12:51:56 PM PDT 24 177474985 ps
T812 /workspace/coverage/default/10.pwrmgr_escalation_timeout.501422454 Mar 12 12:50:06 PM PDT 24 Mar 12 12:50:07 PM PDT 24 1068256117 ps
T813 /workspace/coverage/default/49.pwrmgr_wakeup_reset.819457734 Mar 12 12:51:47 PM PDT 24 Mar 12 12:51:48 PM PDT 24 209606524 ps
T814 /workspace/coverage/default/23.pwrmgr_lowpower_invalid.4189592002 Mar 12 12:50:47 PM PDT 24 Mar 12 12:50:48 PM PDT 24 44612944 ps
T815 /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.180391602 Mar 12 12:51:46 PM PDT 24 Mar 12 12:51:47 PM PDT 24 74580852 ps
T816 /workspace/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1693052763 Mar 12 12:49:32 PM PDT 24 Mar 12 12:49:35 PM PDT 24 1155354623 ps
T817 /workspace/coverage/default/25.pwrmgr_wakeup_reset.1269685487 Mar 12 12:50:47 PM PDT 24 Mar 12 12:50:48 PM PDT 24 456946829 ps
T818 /workspace/coverage/default/18.pwrmgr_aborted_low_power.2937794006 Mar 12 12:50:21 PM PDT 24 Mar 12 12:50:22 PM PDT 24 30032260 ps
T819 /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.2825270605 Mar 12 12:49:25 PM PDT 24 Mar 12 12:49:27 PM PDT 24 94015578 ps
T820 /workspace/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1027750688 Mar 12 12:51:04 PM PDT 24 Mar 12 12:51:06 PM PDT 24 1296960664 ps
T821 /workspace/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.2435059167 Mar 12 12:51:53 PM PDT 24 Mar 12 12:51:54 PM PDT 24 257136676 ps
T822 /workspace/coverage/default/42.pwrmgr_wakeup.1692340641 Mar 12 12:51:39 PM PDT 24 Mar 12 12:51:40 PM PDT 24 106435425 ps
T823 /workspace/coverage/default/31.pwrmgr_glitch.2016210401 Mar 12 12:51:27 PM PDT 24 Mar 12 12:51:28 PM PDT 24 51431661 ps
T824 /workspace/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.520001041 Mar 12 12:51:12 PM PDT 24 Mar 12 12:51:15 PM PDT 24 824225643 ps
T825 /workspace/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.470735346 Mar 12 12:51:15 PM PDT 24 Mar 12 12:51:18 PM PDT 24 972978542 ps
T826 /workspace/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.910880826 Mar 12 12:49:55 PM PDT 24 Mar 12 12:49:57 PM PDT 24 163693498 ps
T827 /workspace/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.965955148 Mar 12 12:50:17 PM PDT 24 Mar 12 12:50:19 PM PDT 24 1122365392 ps
T828 /workspace/coverage/default/7.pwrmgr_stress_all.4155984445 Mar 12 12:50:01 PM PDT 24 Mar 12 12:50:06 PM PDT 24 609723427 ps
T829 /workspace/coverage/default/15.pwrmgr_reset_invalid.865941871 Mar 12 12:50:12 PM PDT 24 Mar 12 12:50:13 PM PDT 24 126146116 ps
T830 /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.324534127 Mar 12 12:50:09 PM PDT 24 Mar 12 12:50:10 PM PDT 24 80098897 ps
T831 /workspace/coverage/default/36.pwrmgr_reset_invalid.1178995087 Mar 12 12:51:08 PM PDT 24 Mar 12 12:51:10 PM PDT 24 160232341 ps
T832 /workspace/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3948208482 Mar 12 12:49:31 PM PDT 24 Mar 12 12:49:35 PM PDT 24 867960054 ps
T833 /workspace/coverage/default/35.pwrmgr_glitch.2653665886 Mar 12 12:51:08 PM PDT 24 Mar 12 12:51:10 PM PDT 24 74557554 ps
T834 /workspace/coverage/default/42.pwrmgr_smoke.3636470664 Mar 12 12:51:36 PM PDT 24 Mar 12 12:51:36 PM PDT 24 42495482 ps
T835 /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.282545384 Mar 12 12:51:10 PM PDT 24 Mar 12 12:51:11 PM PDT 24 108779672 ps
T836 /workspace/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.531327244 Mar 12 12:51:03 PM PDT 24 Mar 12 12:51:05 PM PDT 24 971869909 ps
T30 /workspace/coverage/default/4.pwrmgr_sec_cm.2331069648 Mar 12 12:49:48 PM PDT 24 Mar 12 12:49:50 PM PDT 24 669136493 ps
T837 /workspace/coverage/default/17.pwrmgr_escalation_timeout.799732184 Mar 12 12:50:20 PM PDT 24 Mar 12 12:50:21 PM PDT 24 607743270 ps
T838 /workspace/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.421093423 Mar 12 12:51:53 PM PDT 24 Mar 12 12:51:53 PM PDT 24 171929457 ps
T839 /workspace/coverage/default/39.pwrmgr_escalation_timeout.681351712 Mar 12 12:51:19 PM PDT 24 Mar 12 12:51:20 PM PDT 24 169221561 ps
T840 /workspace/coverage/default/47.pwrmgr_wakeup_reset.1773014873 Mar 12 12:51:47 PM PDT 24 Mar 12 12:51:48 PM PDT 24 264660393 ps
T841 /workspace/coverage/default/19.pwrmgr_glitch.1634160189 Mar 12 12:50:27 PM PDT 24 Mar 12 12:50:28 PM PDT 24 54616955 ps
T842 /workspace/coverage/default/34.pwrmgr_smoke.2385936667 Mar 12 12:51:18 PM PDT 24 Mar 12 12:51:19 PM PDT 24 62362293 ps
T843 /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2470204615 Mar 12 12:49:45 PM PDT 24 Mar 12 12:49:46 PM PDT 24 40921894 ps
T844 /workspace/coverage/default/29.pwrmgr_wakeup.2012575041 Mar 12 12:50:56 PM PDT 24 Mar 12 12:50:57 PM PDT 24 152518912 ps
T845 /workspace/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1285447772 Mar 12 12:51:24 PM PDT 24 Mar 12 12:51:26 PM PDT 24 1377349609 ps
T846 /workspace/coverage/default/7.pwrmgr_global_esc.214720795 Mar 12 12:49:59 PM PDT 24 Mar 12 12:50:00 PM PDT 24 218959782 ps
T847 /workspace/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3331455845 Mar 12 12:51:05 PM PDT 24 Mar 12 12:51:07 PM PDT 24 1025076286 ps
T848 /workspace/coverage/default/2.pwrmgr_wakeup_reset.3635775727 Mar 12 12:49:32 PM PDT 24 Mar 12 12:49:33 PM PDT 24 488382399 ps
T849 /workspace/coverage/default/46.pwrmgr_escalation_timeout.520119888 Mar 12 12:51:54 PM PDT 24 Mar 12 12:51:55 PM PDT 24 242067589 ps
T850 /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.338724167 Mar 12 12:50:10 PM PDT 24 Mar 12 12:50:11 PM PDT 24 57983229 ps
T851 /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.1853804294 Mar 12 12:51:55 PM PDT 24 Mar 12 12:51:56 PM PDT 24 221992440 ps
T852 /workspace/coverage/default/15.pwrmgr_reset.608715861 Mar 12 12:50:22 PM PDT 24 Mar 12 12:50:23 PM PDT 24 37302741 ps
T853 /workspace/coverage/default/7.pwrmgr_smoke.1001367829 Mar 12 12:50:03 PM PDT 24 Mar 12 12:50:04 PM PDT 24 43099242 ps
T31 /workspace/coverage/default/1.pwrmgr_sec_cm.3025114341 Mar 12 12:49:32 PM PDT 24 Mar 12 12:49:34 PM PDT 24 355734810 ps
T854 /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.1278921344 Mar 12 12:51:31 PM PDT 24 Mar 12 12:51:38 PM PDT 24 545935169 ps
T855 /workspace/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.174447668 Mar 12 12:50:30 PM PDT 24 Mar 12 12:50:33 PM PDT 24 993990944 ps
T856 /workspace/coverage/default/34.pwrmgr_reset_invalid.1850792681 Mar 12 12:51:06 PM PDT 24 Mar 12 12:51:08 PM PDT 24 98825745 ps
T857 /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.3547774385 Mar 12 12:52:04 PM PDT 24 Mar 12 12:52:05 PM PDT 24 87917619 ps
T858 /workspace/coverage/default/6.pwrmgr_smoke.1582952979 Mar 12 12:49:56 PM PDT 24 Mar 12 12:49:57 PM PDT 24 54313917 ps
T859 /workspace/coverage/default/26.pwrmgr_wakeup_reset.3984315610 Mar 12 12:50:55 PM PDT 24 Mar 12 12:50:56 PM PDT 24 91376604 ps
T860 /workspace/coverage/default/1.pwrmgr_lowpower_invalid.3460645461 Mar 12 12:49:29 PM PDT 24 Mar 12 12:49:30 PM PDT 24 76403625 ps
T861 /workspace/coverage/default/19.pwrmgr_smoke.178172941 Mar 12 12:50:27 PM PDT 24 Mar 12 12:50:27 PM PDT 24 40226518 ps
T862 /workspace/coverage/default/27.pwrmgr_glitch.2768239196 Mar 12 12:50:51 PM PDT 24 Mar 12 12:50:52 PM PDT 24 33613060 ps
T863 /workspace/coverage/default/35.pwrmgr_lowpower_wakeup_race.2609031403 Mar 12 12:51:05 PM PDT 24 Mar 12 12:51:06 PM PDT 24 254896751 ps
T864 /workspace/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2831323990 Mar 12 12:52:13 PM PDT 24 Mar 12 12:52:15 PM PDT 24 2627479230 ps
T865 /workspace/coverage/default/7.pwrmgr_escalation_timeout.2562181742 Mar 12 12:50:00 PM PDT 24 Mar 12 12:50:03 PM PDT 24 510897349 ps
T866 /workspace/coverage/default/33.pwrmgr_reset.1582488975 Mar 12 12:51:08 PM PDT 24 Mar 12 12:51:10 PM PDT 24 122246222 ps
T867 /workspace/coverage/default/31.pwrmgr_lowpower_wakeup_race.634441415 Mar 12 12:51:08 PM PDT 24 Mar 12 12:51:10 PM PDT 24 637295312 ps
T23 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.4274201187 Mar 12 12:28:28 PM PDT 24 Mar 12 12:28:30 PM PDT 24 168607516 ps
T24 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.2746383085 Mar 12 12:28:35 PM PDT 24 Mar 12 12:28:36 PM PDT 24 54116505 ps
T55 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.2311475655 Mar 12 12:28:38 PM PDT 24 Mar 12 12:28:40 PM PDT 24 112590425 ps
T69 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.1607838096 Mar 12 12:28:47 PM PDT 24 Mar 12 12:28:48 PM PDT 24 24571145 ps
T70 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.3536562463 Mar 12 12:28:48 PM PDT 24 Mar 12 12:28:49 PM PDT 24 148211835 ps
T71 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.2854551289 Mar 12 12:28:33 PM PDT 24 Mar 12 12:28:34 PM PDT 24 18548445 ps
T56 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.1260410763 Mar 12 12:28:32 PM PDT 24 Mar 12 12:28:34 PM PDT 24 112838785 ps
T57 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1377541996 Mar 12 12:28:35 PM PDT 24 Mar 12 12:28:37 PM PDT 24 267578549 ps
T139 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.2162401937 Mar 12 12:28:32 PM PDT 24 Mar 12 12:28:33 PM PDT 24 18688152 ps
T868 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.88728526 Mar 12 12:28:32 PM PDT 24 Mar 12 12:28:33 PM PDT 24 21063359 ps
T108 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.4028772950 Mar 12 12:28:35 PM PDT 24 Mar 12 12:28:36 PM PDT 24 31166789 ps
T869 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.591178428 Mar 12 12:28:46 PM PDT 24 Mar 12 12:28:47 PM PDT 24 85207753 ps
T870 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.3836555961 Mar 12 12:28:49 PM PDT 24 Mar 12 12:28:50 PM PDT 24 17876818 ps
T74 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.1136744766 Mar 12 12:28:50 PM PDT 24 Mar 12 12:28:51 PM PDT 24 71185642 ps
T59 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2280267338 Mar 12 12:28:43 PM PDT 24 Mar 12 12:28:44 PM PDT 24 43469687 ps
T66 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1491683889 Mar 12 12:28:43 PM PDT 24 Mar 12 12:28:44 PM PDT 24 40974514 ps
T871 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.100860153 Mar 12 12:28:56 PM PDT 24 Mar 12 12:28:57 PM PDT 24 23695007 ps
T140 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.777841633 Mar 12 12:28:48 PM PDT 24 Mar 12 12:28:49 PM PDT 24 16471326 ps
T141 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3086715329 Mar 12 12:28:50 PM PDT 24 Mar 12 12:28:51 PM PDT 24 30999641 ps
T63 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.1360002232 Mar 12 12:28:32 PM PDT 24 Mar 12 12:28:33 PM PDT 24 205624360 ps
T872 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.4121693225 Mar 12 12:28:38 PM PDT 24 Mar 12 12:28:39 PM PDT 24 51047351 ps
T64 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.1464456864 Mar 12 12:28:24 PM PDT 24 Mar 12 12:28:25 PM PDT 24 53422147 ps
T873 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.3994517033 Mar 12 12:28:37 PM PDT 24 Mar 12 12:28:38 PM PDT 24 31585655 ps
T92 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1130600186 Mar 12 12:28:47 PM PDT 24 Mar 12 12:28:48 PM PDT 24 29687398 ps
T65 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2443377956 Mar 12 12:28:33 PM PDT 24 Mar 12 12:28:33 PM PDT 24 33852941 ps
T93 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.891027169 Mar 12 12:28:34 PM PDT 24 Mar 12 12:28:35 PM PDT 24 46651507 ps
T874 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.951248422 Mar 12 12:28:59 PM PDT 24 Mar 12 12:29:00 PM PDT 24 60621249 ps
T94 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.1170863164 Mar 12 12:28:31 PM PDT 24 Mar 12 12:28:35 PM PDT 24 1223394223 ps
T109 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2722244945 Mar 12 12:28:33 PM PDT 24 Mar 12 12:28:34 PM PDT 24 75896683 ps
T67 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.3237973896 Mar 12 12:28:34 PM PDT 24 Mar 12 12:28:37 PM PDT 24 160815139 ps
T875 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.3406203380 Mar 12 12:28:49 PM PDT 24 Mar 12 12:28:50 PM PDT 24 47439091 ps
T95 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.3774643368 Mar 12 12:28:35 PM PDT 24 Mar 12 12:28:36 PM PDT 24 66561755 ps
T96 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.66352465 Mar 12 12:28:31 PM PDT 24 Mar 12 12:28:33 PM PDT 24 54800547 ps
T81 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2871054716 Mar 12 12:28:43 PM PDT 24 Mar 12 12:28:44 PM PDT 24 92548953 ps
T68 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.2813984476 Mar 12 12:28:33 PM PDT 24 Mar 12 12:28:35 PM PDT 24 978821927 ps
T97 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.1682695847 Mar 12 12:28:26 PM PDT 24 Mar 12 12:28:27 PM PDT 24 54124375 ps
T72 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2602407571 Mar 12 12:28:27 PM PDT 24 Mar 12 12:28:29 PM PDT 24 118571732 ps
T91 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.2926951920 Mar 12 12:28:35 PM PDT 24 Mar 12 12:28:38 PM PDT 24 351832615 ps
T876 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.441771937 Mar 12 12:28:46 PM PDT 24 Mar 12 12:28:46 PM PDT 24 44130770 ps
T142 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.3554649144 Mar 12 12:28:36 PM PDT 24 Mar 12 12:28:37 PM PDT 24 19240053 ps
T877 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.1669273282 Mar 12 12:28:30 PM PDT 24 Mar 12 12:28:31 PM PDT 24 42974967 ps
T58 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3238002114 Mar 12 12:28:30 PM PDT 24 Mar 12 12:28:31 PM PDT 24 287784038 ps
T878 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.4156193365 Mar 12 12:28:32 PM PDT 24 Mar 12 12:28:34 PM PDT 24 449142778 ps
T879 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.870396944 Mar 12 12:28:48 PM PDT 24 Mar 12 12:28:49 PM PDT 24 38499344 ps
T880 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.3219001601 Mar 12 12:28:46 PM PDT 24 Mar 12 12:28:47 PM PDT 24 19198775 ps
T121 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.4200214021 Mar 12 12:28:39 PM PDT 24 Mar 12 12:28:41 PM PDT 24 200112815 ps
T881 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3088037818 Mar 12 12:28:33 PM PDT 24 Mar 12 12:28:34 PM PDT 24 18405937 ps
T98 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.3360165372 Mar 12 12:28:47 PM PDT 24 Mar 12 12:28:49 PM PDT 24 66739953 ps
T882 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.25785372 Mar 12 12:28:39 PM PDT 24 Mar 12 12:28:41 PM PDT 24 108834009 ps
T883 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.3075711276 Mar 12 12:28:43 PM PDT 24 Mar 12 12:28:45 PM PDT 24 250131092 ps
T99 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.1537505268 Mar 12 12:28:32 PM PDT 24 Mar 12 12:28:33 PM PDT 24 78613350 ps
T884 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.1938475289 Mar 12 12:28:47 PM PDT 24 Mar 12 12:28:49 PM PDT 24 19242322 ps
T885 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.201252779 Mar 12 12:28:44 PM PDT 24 Mar 12 12:28:45 PM PDT 24 79031686 ps
T100 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2833595890 Mar 12 12:28:36 PM PDT 24 Mar 12 12:28:37 PM PDT 24 47900373 ps
T886 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.2359455725 Mar 12 12:28:47 PM PDT 24 Mar 12 12:28:48 PM PDT 24 18643880 ps
T887 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.4115341155 Mar 12 12:28:26 PM PDT 24 Mar 12 12:28:29 PM PDT 24 435593675 ps
T110 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2622045036 Mar 12 12:28:49 PM PDT 24 Mar 12 12:28:49 PM PDT 24 48478596 ps
T122 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.176648554 Mar 12 12:28:45 PM PDT 24 Mar 12 12:28:46 PM PDT 24 55107338 ps
T888 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.254996560 Mar 12 12:28:46 PM PDT 24 Mar 12 12:28:47 PM PDT 24 47754002 ps
T889 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1978109061 Mar 12 12:28:36 PM PDT 24 Mar 12 12:28:38 PM PDT 24 56816651 ps
T890 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3424499051 Mar 12 12:28:28 PM PDT 24 Mar 12 12:28:28 PM PDT 24 33930504 ps
T129 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.2125471367 Mar 12 12:28:35 PM PDT 24 Mar 12 12:28:36 PM PDT 24 227831933 ps
T891 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.1987227349 Mar 12 12:28:42 PM PDT 24 Mar 12 12:28:43 PM PDT 24 124344303 ps
T111 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.4163778359 Mar 12 12:28:31 PM PDT 24 Mar 12 12:28:32 PM PDT 24 21529900 ps
T892 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.926235683 Mar 12 12:28:33 PM PDT 24 Mar 12 12:28:36 PM PDT 24 89157039 ps
T893 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.1319671583 Mar 12 12:28:35 PM PDT 24 Mar 12 12:28:36 PM PDT 24 52619877 ps
T894 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.3435287357 Mar 12 12:28:48 PM PDT 24 Mar 12 12:28:49 PM PDT 24 54011691 ps
T130 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.272851726 Mar 12 12:28:39 PM PDT 24 Mar 12 12:28:40 PM PDT 24 104450619 ps
T895 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.96268685 Mar 12 12:28:42 PM PDT 24 Mar 12 12:28:42 PM PDT 24 59116225 ps
T896 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.2968821857 Mar 12 12:28:35 PM PDT 24 Mar 12 12:28:36 PM PDT 24 46097816 ps
T897 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.3928866445 Mar 12 12:28:46 PM PDT 24 Mar 12 12:28:47 PM PDT 24 93807275 ps
T898 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.535369982 Mar 12 12:28:41 PM PDT 24 Mar 12 12:28:42 PM PDT 24 158814094 ps
T899 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.2053170295 Mar 12 12:28:51 PM PDT 24 Mar 12 12:28:52 PM PDT 24 19093943 ps
T75 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.1996464210 Mar 12 12:28:31 PM PDT 24 Mar 12 12:28:33 PM PDT 24 215086291 ps
T900 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.953079750 Mar 12 12:28:43 PM PDT 24 Mar 12 12:28:44 PM PDT 24 35131698 ps
T901 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.3066801059 Mar 12 12:28:46 PM PDT 24 Mar 12 12:28:47 PM PDT 24 91246185 ps
T902 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.2483393984 Mar 12 12:28:45 PM PDT 24 Mar 12 12:28:46 PM PDT 24 53436318 ps
T903 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.213605515 Mar 12 12:28:43 PM PDT 24 Mar 12 12:28:45 PM PDT 24 74454840 ps
T904 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.101295702 Mar 12 12:28:42 PM PDT 24 Mar 12 12:28:43 PM PDT 24 41835929 ps
T905 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.740268582 Mar 12 12:28:45 PM PDT 24 Mar 12 12:28:46 PM PDT 24 23283749 ps
T906 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.18792135 Mar 12 12:28:33 PM PDT 24 Mar 12 12:28:33 PM PDT 24 19947696 ps
T907 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.754382654 Mar 12 12:28:34 PM PDT 24 Mar 12 12:28:35 PM PDT 24 23491445 ps
T908 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3316861246 Mar 12 12:28:47 PM PDT 24 Mar 12 12:28:49 PM PDT 24 207883753 ps
T909 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.4171712534 Mar 12 12:28:32 PM PDT 24 Mar 12 12:28:34 PM PDT 24 133028845 ps
T131 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.844786910 Mar 12 12:28:45 PM PDT 24 Mar 12 12:28:47 PM PDT 24 392086710 ps
T910 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.3508859789 Mar 12 12:28:46 PM PDT 24 Mar 12 12:28:47 PM PDT 24 39413276 ps
T911 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.1493613790 Mar 12 12:28:39 PM PDT 24 Mar 12 12:28:41 PM PDT 24 76734989 ps
T912 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3167389742 Mar 12 12:28:47 PM PDT 24 Mar 12 12:28:48 PM PDT 24 269749926 ps
T913 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.598408047 Mar 12 12:28:43 PM PDT 24 Mar 12 12:28:46 PM PDT 24 161004904 ps
T914 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3084700809 Mar 12 12:28:44 PM PDT 24 Mar 12 12:28:46 PM PDT 24 94720161 ps
T915 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3197883192 Mar 12 12:28:45 PM PDT 24 Mar 12 12:28:46 PM PDT 24 142445607 ps
T916 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.120330111 Mar 12 12:28:31 PM PDT 24 Mar 12 12:28:32 PM PDT 24 313496233 ps
T917 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.306946827 Mar 12 12:28:48 PM PDT 24 Mar 12 12:28:49 PM PDT 24 44574172 ps
T918 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.80218528 Mar 12 12:28:27 PM PDT 24 Mar 12 12:28:29 PM PDT 24 82138589 ps
T919 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.3385974577 Mar 12 12:28:37 PM PDT 24 Mar 12 12:28:39 PM PDT 24 133643568 ps
T920 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3086269409 Mar 12 12:28:36 PM PDT 24 Mar 12 12:28:37 PM PDT 24 22087231 ps
T921 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.2291390606 Mar 12 12:28:35 PM PDT 24 Mar 12 12:28:36 PM PDT 24 68229673 ps
T922 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.616009110 Mar 12 12:28:42 PM PDT 24 Mar 12 12:28:43 PM PDT 24 25800927 ps
T923 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.4057172273 Mar 12 12:28:35 PM PDT 24 Mar 12 12:28:36 PM PDT 24 40579779 ps
T924 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.3304200217 Mar 12 12:28:33 PM PDT 24 Mar 12 12:28:34 PM PDT 24 18809074 ps
T925 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.543002510 Mar 12 12:28:27 PM PDT 24 Mar 12 12:28:29 PM PDT 24 23589794 ps
T926 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.3276669252 Mar 12 12:28:32 PM PDT 24 Mar 12 12:28:34 PM PDT 24 391401192 ps
T927 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.584680040 Mar 12 12:28:36 PM PDT 24 Mar 12 12:28:37 PM PDT 24 266819138 ps
T928 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3666502823 Mar 12 12:28:46 PM PDT 24 Mar 12 12:28:46 PM PDT 24 22217339 ps
T929 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.1232817681 Mar 12 12:28:49 PM PDT 24 Mar 12 12:28:49 PM PDT 24 23469586 ps
T930 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.2962124060 Mar 12 12:28:49 PM PDT 24 Mar 12 12:28:50 PM PDT 24 19321665 ps
T931 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.919872679 Mar 12 12:28:32 PM PDT 24 Mar 12 12:28:33 PM PDT 24 28825766 ps
T932 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1926465492 Mar 12 12:28:31 PM PDT 24 Mar 12 12:28:33 PM PDT 24 435027633 ps
T933 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1053126632 Mar 12 12:28:36 PM PDT 24 Mar 12 12:28:38 PM PDT 24 274892194 ps
T101 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.1623008712 Mar 12 12:28:36 PM PDT 24 Mar 12 12:28:36 PM PDT 24 44618286 ps
T934 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1781920953 Mar 12 12:28:41 PM PDT 24 Mar 12 12:28:42 PM PDT 24 88464877 ps
T935 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2908556972 Mar 12 12:28:48 PM PDT 24 Mar 12 12:28:49 PM PDT 24 19195973 ps
T936 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.686764770 Mar 12 12:28:34 PM PDT 24 Mar 12 12:28:36 PM PDT 24 56642853 ps
T937 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.829638596 Mar 12 12:28:46 PM PDT 24 Mar 12 12:28:47 PM PDT 24 20760218 ps
T938 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.3050752024 Mar 12 12:28:28 PM PDT 24 Mar 12 12:28:29 PM PDT 24 29418216 ps
T939 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.3737701104 Mar 12 12:28:39 PM PDT 24 Mar 12 12:28:40 PM PDT 24 43135503 ps
T940 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.4099694180 Mar 12 12:28:44 PM PDT 24 Mar 12 12:28:45 PM PDT 24 234889074 ps
T102 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2046433763 Mar 12 12:28:39 PM PDT 24 Mar 12 12:28:40 PM PDT 24 50457092 ps
T103 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2110486657 Mar 12 12:28:42 PM PDT 24 Mar 12 12:28:43 PM PDT 24 21849161 ps
T941 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.3334665863 Mar 12 12:28:46 PM PDT 24 Mar 12 12:28:46 PM PDT 24 19484293 ps
T942 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.693069940 Mar 12 12:28:33 PM PDT 24 Mar 12 12:28:34 PM PDT 24 29885119 ps
T943 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.488024749 Mar 12 12:28:45 PM PDT 24 Mar 12 12:28:46 PM PDT 24 88618491 ps
T944 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.2485147694 Mar 12 12:28:38 PM PDT 24 Mar 12 12:28:38 PM PDT 24 63811920 ps
T945 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.534412767 Mar 12 12:28:39 PM PDT 24 Mar 12 12:28:40 PM PDT 24 98093260 ps
T946 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3274781519 Mar 12 12:28:52 PM PDT 24 Mar 12 12:28:53 PM PDT 24 40274556 ps
T947 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1325752136 Mar 12 12:29:06 PM PDT 24 Mar 12 12:29:07 PM PDT 24 16340602 ps
T104 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.233965149 Mar 12 12:28:33 PM PDT 24 Mar 12 12:28:35 PM PDT 24 39515915 ps
T948 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.2905158990 Mar 12 12:28:43 PM PDT 24 Mar 12 12:28:44 PM PDT 24 15397078 ps
T949 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.944445606 Mar 12 12:28:46 PM PDT 24 Mar 12 12:28:47 PM PDT 24 20588714 ps
T950 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3530101973 Mar 12 12:28:57 PM PDT 24 Mar 12 12:28:59 PM PDT 24 49037096 ps
T951 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2191518127 Mar 12 12:28:56 PM PDT 24 Mar 12 12:28:57 PM PDT 24 235570325 ps
T952 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.2990171275 Mar 12 12:28:32 PM PDT 24 Mar 12 12:28:33 PM PDT 24 32030300 ps
T953 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2433919817 Mar 12 12:28:52 PM PDT 24 Mar 12 12:28:54 PM PDT 24 326900538 ps
T954 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3751300695 Mar 12 12:28:32 PM PDT 24 Mar 12 12:28:33 PM PDT 24 44478645 ps
T76 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.1899224099 Mar 12 12:28:31 PM PDT 24 Mar 12 12:28:33 PM PDT 24 184088409 ps
T955 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.3651608801 Mar 12 12:28:30 PM PDT 24 Mar 12 12:28:31 PM PDT 24 49522353 ps
T956 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.3013043398 Mar 12 12:28:29 PM PDT 24 Mar 12 12:28:31 PM PDT 24 82490085 ps
T957 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1377433086 Mar 12 12:28:26 PM PDT 24 Mar 12 12:28:28 PM PDT 24 171210904 ps
T958 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.1658220935 Mar 12 12:28:30 PM PDT 24 Mar 12 12:28:31 PM PDT 24 24527976 ps
T959 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.3127541896 Mar 12 12:28:51 PM PDT 24 Mar 12 12:28:52 PM PDT 24 18527740 ps
T960 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.2103985004 Mar 12 12:28:45 PM PDT 24 Mar 12 12:28:46 PM PDT 24 17952321 ps
T105 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.2629450678 Mar 12 12:28:35 PM PDT 24 Mar 12 12:28:35 PM PDT 24 23034202 ps
T961 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.814468462 Mar 12 12:28:35 PM PDT 24 Mar 12 12:28:38 PM PDT 24 858389170 ps
T962 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.2597497440 Mar 12 12:28:48 PM PDT 24 Mar 12 12:28:49 PM PDT 24 28374368 ps
T963 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3973301448 Mar 12 12:28:54 PM PDT 24 Mar 12 12:28:56 PM PDT 24 46468998 ps
T964 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3054289374 Mar 12 12:28:45 PM PDT 24 Mar 12 12:28:47 PM PDT 24 254501942 ps
T106 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.4277198888 Mar 12 12:28:36 PM PDT 24 Mar 12 12:28:37 PM PDT 24 38906379 ps
T965 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.2066659261 Mar 12 12:28:47 PM PDT 24 Mar 12 12:28:49 PM PDT 24 33725448 ps
T966 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.544162126 Mar 12 12:28:32 PM PDT 24 Mar 12 12:28:34 PM PDT 24 888943189 ps
T107 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.2266785957 Mar 12 12:28:45 PM PDT 24 Mar 12 12:28:46 PM PDT 24 24467888 ps
T967 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1664551121 Mar 12 12:28:31 PM PDT 24 Mar 12 12:28:32 PM PDT 24 116284874 ps
T968 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.4117511100 Mar 12 12:28:47 PM PDT 24 Mar 12 12:28:49 PM PDT 24 20888402 ps
T969 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.1881909353 Mar 12 12:28:38 PM PDT 24 Mar 12 12:28:38 PM PDT 24 23146389 ps
T73 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.716543807 Mar 12 12:28:36 PM PDT 24 Mar 12 12:28:38 PM PDT 24 204662071 ps
T970 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.3032460757 Mar 12 12:28:35 PM PDT 24 Mar 12 12:28:36 PM PDT 24 34257272 ps
T971 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.1021347745 Mar 12 12:28:50 PM PDT 24 Mar 12 12:28:51 PM PDT 24 19188008 ps
T972 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.642726954 Mar 12 12:28:33 PM PDT 24 Mar 12 12:28:35 PM PDT 24 55435851 ps
T973 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.2966762588 Mar 12 12:28:46 PM PDT 24 Mar 12 12:28:47 PM PDT 24 21338687 ps
T974 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.622932659 Mar 12 12:28:34 PM PDT 24 Mar 12 12:28:35 PM PDT 24 25896639 ps
T975 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.741157395 Mar 12 12:28:27 PM PDT 24 Mar 12 12:28:28 PM PDT 24 62484630 ps
T976 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1616749954 Mar 12 12:28:36 PM PDT 24 Mar 12 12:28:37 PM PDT 24 50779312 ps
T977 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.4191235233 Mar 12 12:28:48 PM PDT 24 Mar 12 12:28:49 PM PDT 24 63007055 ps
T978 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.1944167179 Mar 12 12:28:57 PM PDT 24 Mar 12 12:28:58 PM PDT 24 30399997 ps
T979 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.538856287 Mar 12 12:28:45 PM PDT 24 Mar 12 12:28:46 PM PDT 24 84194967 ps
T980 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.2761237914 Mar 12 12:29:00 PM PDT 24 Mar 12 12:29:01 PM PDT 24 21324847 ps

Test location /workspace/coverage/default/43.pwrmgr_lowpower_wakeup_race.1338437226
Short name T9
Test name
Test status
Simulation time 475480522 ps
CPU time 1.01 seconds
Started Mar 12 12:51:41 PM PDT 24
Finished Mar 12 12:51:43 PM PDT 24
Peak memory 195408 kb
Host smart-31421bf2-40e5-4cc9-a13d-ab967e88d54b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338437226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_w
akeup_race.1338437226
Directory /workspace/43.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.3120525241
Short name T2
Test name
Test status
Simulation time 94208345 ps
CPU time 0.87 seconds
Started Mar 12 12:50:42 PM PDT 24
Finished Mar 12 12:50:43 PM PDT 24
Peak memory 205264 kb
Host smart-16657b76-65b1-442c-b0d3-f808bfcb7032
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120525241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.3120525241
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.128196344
Short name T26
Test name
Test status
Simulation time 2551194262 ps
CPU time 2 seconds
Started Mar 12 12:51:24 PM PDT 24
Finished Mar 12 12:51:27 PM PDT 24
Peak memory 201168 kb
Host smart-5c108113-a25a-45b1-ad97-59dda2a17ea4
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128196344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.128196344
Directory /workspace/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2280267338
Short name T59
Test name
Test status
Simulation time 43469687 ps
CPU time 1.07 seconds
Started Mar 12 12:28:43 PM PDT 24
Finished Mar 12 12:28:44 PM PDT 24
Peak memory 200528 kb
Host smart-809bd7ec-394d-4d3a-8103-b1e0a9d9af51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280267338 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.2280267338
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_stress_all.635670814
Short name T18
Test name
Test status
Simulation time 1385714779 ps
CPU time 3.41 seconds
Started Mar 12 12:50:44 PM PDT 24
Finished Mar 12 12:50:47 PM PDT 24
Peak memory 200152 kb
Host smart-dec78e29-30af-40bd-bb80-794a6db93c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635670814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.635670814
Directory /workspace/22.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.3185935711
Short name T3
Test name
Test status
Simulation time 77287089 ps
CPU time 0.66 seconds
Started Mar 12 12:51:08 PM PDT 24
Finished Mar 12 12:51:10 PM PDT 24
Peak memory 195916 kb
Host smart-4c2f0b90-bb80-4ed6-963b-6cb01cb56f9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185935711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_inval
id.3185935711
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.3401489692
Short name T6
Test name
Test status
Simulation time 499693498 ps
CPU time 1.11 seconds
Started Mar 12 12:49:26 PM PDT 24
Finished Mar 12 12:49:29 PM PDT 24
Peak memory 215600 kb
Host smart-1d50c326-436b-4afc-b4f9-4a6b71740f92
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401489692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.3401489692
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.4200214021
Short name T121
Test name
Test status
Simulation time 200112815 ps
CPU time 1.82 seconds
Started Mar 12 12:28:39 PM PDT 24
Finished Mar 12 12:28:41 PM PDT 24
Peak memory 200412 kb
Host smart-a0357377-9f70-4f94-8484-c6cb2d7b1f5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200214021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.4200214021
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.1464456864
Short name T64
Test name
Test status
Simulation time 53422147 ps
CPU time 0.66 seconds
Started Mar 12 12:28:24 PM PDT 24
Finished Mar 12 12:28:25 PM PDT 24
Peak memory 197560 kb
Host smart-4cf491a2-4614-4bb4-91fe-f5f596d41c61
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464456864 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.1
464456864
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.2854551289
Short name T71
Test name
Test status
Simulation time 18548445 ps
CPU time 0.59 seconds
Started Mar 12 12:28:33 PM PDT 24
Finished Mar 12 12:28:34 PM PDT 24
Peak memory 196304 kb
Host smart-9948e8d3-e8eb-43bd-aa60-9df57a79d64c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854551289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.2854551289
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.6476041
Short name T43
Test name
Test status
Simulation time 161890608 ps
CPU time 0.96 seconds
Started Mar 12 12:49:22 PM PDT 24
Finished Mar 12 12:49:24 PM PDT 24
Peak memory 195436 kb
Host smart-c1b3b2b3-5032-4003-a870-c9f525e1ca36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6476041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.6476041
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.37220990
Short name T234
Test name
Test status
Simulation time 85221726 ps
CPU time 0.63 seconds
Started Mar 12 12:50:11 PM PDT 24
Finished Mar 12 12:50:11 PM PDT 24
Peak memory 195344 kb
Host smart-95597b2d-bc26-4788-bc3d-7d2f4cfc112c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37220990 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_co
nfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm
_ctrl_config_regwen.37220990
Directory /workspace/11.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.3378665323
Short name T45
Test name
Test status
Simulation time 58608559 ps
CPU time 0.78 seconds
Started Mar 12 12:49:45 PM PDT 24
Finished Mar 12 12:49:46 PM PDT 24
Peak memory 195452 kb
Host smart-e5a31c3e-31f6-4248-8467-8a3bfcafb3d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378665323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disa
ble_rom_integrity_check.3378665323
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_stress_all_with_rand_reset.98593608
Short name T22
Test name
Test status
Simulation time 7855206894 ps
CPU time 9.97 seconds
Started Mar 12 12:51:56 PM PDT 24
Finished Mar 12 12:52:06 PM PDT 24
Peak memory 201412 kb
Host smart-454e3735-ef51-47fa-be53-48330627e407
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98593608 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all_with_rand_reset.98593608
Directory /workspace/46.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.26448663
Short name T124
Test name
Test status
Simulation time 60142549 ps
CPU time 0.83 seconds
Started Mar 12 12:50:46 PM PDT 24
Finished Mar 12 12:50:47 PM PDT 24
Peak memory 198092 kb
Host smart-37c3e072-dea3-4ab3-86a0-48cb069294de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26448663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_disab
le_rom_integrity_check.26448663
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.2746383085
Short name T24
Test name
Test status
Simulation time 54116505 ps
CPU time 1.12 seconds
Started Mar 12 12:28:35 PM PDT 24
Finished Mar 12 12:28:36 PM PDT 24
Peak memory 200476 kb
Host smart-0205721a-5204-4aec-a334-27ba3909e9fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746383085 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.2746383085
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.844786910
Short name T131
Test name
Test status
Simulation time 392086710 ps
CPU time 1.64 seconds
Started Mar 12 12:28:45 PM PDT 24
Finished Mar 12 12:28:47 PM PDT 24
Peak memory 200600 kb
Host smart-25939118-ba60-42c8-83fa-bdb04d695de7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844786910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_err
.844786910
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.1682695847
Short name T97
Test name
Test status
Simulation time 54124375 ps
CPU time 0.69 seconds
Started Mar 12 12:28:26 PM PDT 24
Finished Mar 12 12:28:27 PM PDT 24
Peak memory 197472 kb
Host smart-383b7327-52e4-4a44-9550-98fe98f2dd84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682695847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.1682695847
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.2359455725
Short name T886
Test name
Test status
Simulation time 18643880 ps
CPU time 0.65 seconds
Started Mar 12 12:28:47 PM PDT 24
Finished Mar 12 12:28:48 PM PDT 24
Peak memory 196156 kb
Host smart-0a3d053a-ef39-40a7-ae39-355359825a0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359455725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.2359455725
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.156858795
Short name T341
Test name
Test status
Simulation time 729477895 ps
CPU time 2.85 seconds
Started Mar 12 12:50:12 PM PDT 24
Finished Mar 12 12:50:15 PM PDT 24
Peak memory 201160 kb
Host smart-35e24b69-12d3-4e3b-bc53-c3b310711a4f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156858795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.156858795
Directory /workspace/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.1801431670
Short name T132
Test name
Test status
Simulation time 64058094 ps
CPU time 0.69 seconds
Started Mar 12 12:50:56 PM PDT 24
Finished Mar 12 12:50:57 PM PDT 24
Peak memory 198184 kb
Host smart-936341ea-4b40-4b1a-9d86-4c00fe59a0eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801431670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.1801431670
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.4274201187
Short name T23
Test name
Test status
Simulation time 168607516 ps
CPU time 2.13 seconds
Started Mar 12 12:28:28 PM PDT 24
Finished Mar 12 12:28:30 PM PDT 24
Peak memory 200608 kb
Host smart-0b1e611d-eae8-4cb4-b1cf-2a55458093f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274201187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.4274201187
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.1996464210
Short name T75
Test name
Test status
Simulation time 215086291 ps
CPU time 1.7 seconds
Started Mar 12 12:28:31 PM PDT 24
Finished Mar 12 12:28:33 PM PDT 24
Peak memory 200512 kb
Host smart-9cc313e1-1ec5-4427-8e18-09d03d9ab9d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996464210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err
.1996464210
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.716543807
Short name T73
Test name
Test status
Simulation time 204662071 ps
CPU time 1.74 seconds
Started Mar 12 12:28:36 PM PDT 24
Finished Mar 12 12:28:38 PM PDT 24
Peak memory 200516 kb
Host smart-2a73b873-3e71-4fff-b1b7-e159df1c14a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716543807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_err
.716543807
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.32193082
Short name T184
Test name
Test status
Simulation time 48492491 ps
CPU time 0.63 seconds
Started Mar 12 12:50:14 PM PDT 24
Finished Mar 12 12:50:15 PM PDT 24
Peak memory 195364 kb
Host smart-13da3e10-c766-4c4a-b629-8626ff7eec6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32193082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.32193082
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.3050752024
Short name T938
Test name
Test status
Simulation time 29418216 ps
CPU time 0.8 seconds
Started Mar 12 12:28:28 PM PDT 24
Finished Mar 12 12:28:29 PM PDT 24
Peak memory 198364 kb
Host smart-1cde9b17-3b69-4dbc-a9f1-3987459cb518
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050752024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.3
050752024
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.4115341155
Short name T887
Test name
Test status
Simulation time 435593675 ps
CPU time 3.11 seconds
Started Mar 12 12:28:26 PM PDT 24
Finished Mar 12 12:28:29 PM PDT 24
Peak memory 199412 kb
Host smart-e1c4c9de-2d49-4128-ab99-eecf53e9f9f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115341155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.4
115341155
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3424499051
Short name T890
Test name
Test status
Simulation time 33930504 ps
CPU time 0.66 seconds
Started Mar 12 12:28:28 PM PDT 24
Finished Mar 12 12:28:28 PM PDT 24
Peak memory 197288 kb
Host smart-54d1f92b-42ab-4b13-b615-a9b2b0938218
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424499051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.3
424499051
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.80218528
Short name T918
Test name
Test status
Simulation time 82138589 ps
CPU time 0.93 seconds
Started Mar 12 12:28:27 PM PDT 24
Finished Mar 12 12:28:29 PM PDT 24
Peak memory 200400 kb
Host smart-23a0817a-5b5a-4722-b2c0-044e0e247f4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80218528 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.80218528
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.3651608801
Short name T955
Test name
Test status
Simulation time 49522353 ps
CPU time 0.62 seconds
Started Mar 12 12:28:30 PM PDT 24
Finished Mar 12 12:28:31 PM PDT 24
Peak memory 196276 kb
Host smart-25c54e75-a4f3-4579-9a00-2e772dcacafd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651608801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.3651608801
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.543002510
Short name T925
Test name
Test status
Simulation time 23589794 ps
CPU time 0.8 seconds
Started Mar 12 12:28:27 PM PDT 24
Finished Mar 12 12:28:29 PM PDT 24
Peak memory 199272 kb
Host smart-3dc3d9ff-1501-46d8-b131-3f5290c44821
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543002510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sam
e_csr_outstanding.543002510
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.3774643368
Short name T95
Test name
Test status
Simulation time 66561755 ps
CPU time 0.77 seconds
Started Mar 12 12:28:35 PM PDT 24
Finished Mar 12 12:28:36 PM PDT 24
Peak memory 198308 kb
Host smart-9adab83e-ac79-4dcd-a67c-c4463f9c84e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774643368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.3
774643368
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.814468462
Short name T961
Test name
Test status
Simulation time 858389170 ps
CPU time 3.58 seconds
Started Mar 12 12:28:35 PM PDT 24
Finished Mar 12 12:28:38 PM PDT 24
Peak memory 199184 kb
Host smart-73161f2a-9bb9-48f3-8aea-82b0865ba923
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814468462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.814468462
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1664551121
Short name T967
Test name
Test status
Simulation time 116284874 ps
CPU time 0.78 seconds
Started Mar 12 12:28:31 PM PDT 24
Finished Mar 12 12:28:32 PM PDT 24
Peak memory 200484 kb
Host smart-0c7e5880-4acd-448e-af3f-4820265c0b80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664551121 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.1664551121
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.4163778359
Short name T111
Test name
Test status
Simulation time 21529900 ps
CPU time 0.64 seconds
Started Mar 12 12:28:31 PM PDT 24
Finished Mar 12 12:28:32 PM PDT 24
Peak memory 197488 kb
Host smart-399ef14b-427f-4b3a-a29f-328cae530696
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163778359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.4163778359
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.741157395
Short name T975
Test name
Test status
Simulation time 62484630 ps
CPU time 0.61 seconds
Started Mar 12 12:28:27 PM PDT 24
Finished Mar 12 12:28:28 PM PDT 24
Peak memory 196260 kb
Host smart-8b9d4f4d-d804-4add-a409-a952f5b51b5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741157395 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.741157395
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.919872679
Short name T931
Test name
Test status
Simulation time 28825766 ps
CPU time 0.96 seconds
Started Mar 12 12:28:32 PM PDT 24
Finished Mar 12 12:28:33 PM PDT 24
Peak memory 199552 kb
Host smart-96a86483-dc78-489d-9ecd-89a57191be9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919872679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sam
e_csr_outstanding.919872679
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2602407571
Short name T72
Test name
Test status
Simulation time 118571732 ps
CPU time 1.59 seconds
Started Mar 12 12:28:27 PM PDT 24
Finished Mar 12 12:28:29 PM PDT 24
Peak memory 200624 kb
Host smart-45bfc83a-47ca-4a71-bf18-73483a695c08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602407571 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.2602407571
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1377433086
Short name T957
Test name
Test status
Simulation time 171210904 ps
CPU time 1.59 seconds
Started Mar 12 12:28:26 PM PDT 24
Finished Mar 12 12:28:28 PM PDT 24
Peak memory 200232 kb
Host smart-183768ba-23b9-4878-8bb5-b2c081854cf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377433086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.1377433086
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.2990171275
Short name T952
Test name
Test status
Simulation time 32030300 ps
CPU time 0.65 seconds
Started Mar 12 12:28:32 PM PDT 24
Finished Mar 12 12:28:33 PM PDT 24
Peak memory 197436 kb
Host smart-07e3aafa-a4b3-408f-84be-71af0a1b8199
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990171275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.2990171275
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.101295702
Short name T904
Test name
Test status
Simulation time 41835929 ps
CPU time 0.6 seconds
Started Mar 12 12:28:42 PM PDT 24
Finished Mar 12 12:28:43 PM PDT 24
Peak memory 196564 kb
Host smart-007dd30b-c9aa-4d7a-95fd-b16f196e5a4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101295702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.101295702
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3086269409
Short name T920
Test name
Test status
Simulation time 22087231 ps
CPU time 0.72 seconds
Started Mar 12 12:28:36 PM PDT 24
Finished Mar 12 12:28:37 PM PDT 24
Peak memory 198204 kb
Host smart-46e06fdd-4670-499a-8598-a2a5d1420b94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086269409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.3086269409
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.2926951920
Short name T91
Test name
Test status
Simulation time 351832615 ps
CPU time 2.04 seconds
Started Mar 12 12:28:35 PM PDT 24
Finished Mar 12 12:28:38 PM PDT 24
Peak memory 200636 kb
Host smart-916df959-8d8f-4b81-8e51-3b719c00a446
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926951920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.2926951920
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.272851726
Short name T130
Test name
Test status
Simulation time 104450619 ps
CPU time 1.17 seconds
Started Mar 12 12:28:39 PM PDT 24
Finished Mar 12 12:28:40 PM PDT 24
Peak memory 200408 kb
Host smart-0bc03e36-6e2b-472b-847c-7ccd9ce0660a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272851726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err
.272851726
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1978109061
Short name T889
Test name
Test status
Simulation time 56816651 ps
CPU time 1.65 seconds
Started Mar 12 12:28:36 PM PDT 24
Finished Mar 12 12:28:38 PM PDT 24
Peak memory 200632 kb
Host smart-8915ead3-cbb1-4ec8-9098-c5ff9c4182d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978109061 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.1978109061
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.754382654
Short name T907
Test name
Test status
Simulation time 23491445 ps
CPU time 0.69 seconds
Started Mar 12 12:28:34 PM PDT 24
Finished Mar 12 12:28:35 PM PDT 24
Peak memory 197572 kb
Host smart-6b97be98-a274-4a0a-a97d-157427832268
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754382654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.754382654
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.4028772950
Short name T108
Test name
Test status
Simulation time 31166789 ps
CPU time 0.78 seconds
Started Mar 12 12:28:35 PM PDT 24
Finished Mar 12 12:28:36 PM PDT 24
Peak memory 199108 kb
Host smart-8090044a-bd14-4c9f-9b9c-17fa1ac0612a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028772950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.4028772950
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.25785372
Short name T882
Test name
Test status
Simulation time 108834009 ps
CPU time 1.43 seconds
Started Mar 12 12:28:39 PM PDT 24
Finished Mar 12 12:28:41 PM PDT 24
Peak memory 200536 kb
Host smart-3e49791d-7eda-41a3-8f43-0c415e5e1150
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25785372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.25785372
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.2125471367
Short name T129
Test name
Test status
Simulation time 227831933 ps
CPU time 1.06 seconds
Started Mar 12 12:28:35 PM PDT 24
Finished Mar 12 12:28:36 PM PDT 24
Peak memory 200604 kb
Host smart-731f49e9-ff3d-4900-ac45-ffaf539bb19e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125471367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.2125471367
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1781920953
Short name T934
Test name
Test status
Simulation time 88464877 ps
CPU time 1.14 seconds
Started Mar 12 12:28:41 PM PDT 24
Finished Mar 12 12:28:42 PM PDT 24
Peak memory 200444 kb
Host smart-8dab4766-47c2-4bde-b5af-95a354c6c500
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781920953 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.1781920953
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2110486657
Short name T103
Test name
Test status
Simulation time 21849161 ps
CPU time 0.68 seconds
Started Mar 12 12:28:42 PM PDT 24
Finished Mar 12 12:28:43 PM PDT 24
Peak memory 197392 kb
Host smart-c9257a91-56d9-4eac-8857-09f8bbf8ce2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110486657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.2110486657
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3088037818
Short name T881
Test name
Test status
Simulation time 18405937 ps
CPU time 0.57 seconds
Started Mar 12 12:28:33 PM PDT 24
Finished Mar 12 12:28:34 PM PDT 24
Peak memory 196236 kb
Host smart-8ab5d5fd-2fc4-45eb-b524-fccf73e390c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088037818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.3088037818
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2622045036
Short name T110
Test name
Test status
Simulation time 48478596 ps
CPU time 0.74 seconds
Started Mar 12 12:28:49 PM PDT 24
Finished Mar 12 12:28:49 PM PDT 24
Peak memory 198344 kb
Host smart-a26df72c-d72e-40cf-a9c3-a6331a561ed5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622045036 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.2622045036
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.3237973896
Short name T67
Test name
Test status
Simulation time 160815139 ps
CPU time 2.43 seconds
Started Mar 12 12:28:34 PM PDT 24
Finished Mar 12 12:28:37 PM PDT 24
Peak memory 200724 kb
Host smart-66763093-a81e-4889-8db5-dd7257b03809
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237973896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.3237973896
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.306946827
Short name T917
Test name
Test status
Simulation time 44574172 ps
CPU time 0.84 seconds
Started Mar 12 12:28:48 PM PDT 24
Finished Mar 12 12:28:49 PM PDT 24
Peak memory 200416 kb
Host smart-218b1bd7-9a77-4a28-bd24-2cf8fe0e6056
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306946827 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.306946827
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.2905158990
Short name T948
Test name
Test status
Simulation time 15397078 ps
CPU time 0.64 seconds
Started Mar 12 12:28:43 PM PDT 24
Finished Mar 12 12:28:44 PM PDT 24
Peak memory 196908 kb
Host smart-785f08c4-555f-4c7d-b940-7b668844be66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905158990 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.2905158990
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.740268582
Short name T905
Test name
Test status
Simulation time 23283749 ps
CPU time 0.62 seconds
Started Mar 12 12:28:45 PM PDT 24
Finished Mar 12 12:28:46 PM PDT 24
Peak memory 196260 kb
Host smart-396e5264-6d30-49a5-8993-96ec5bef21f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740268582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.740268582
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3197883192
Short name T915
Test name
Test status
Simulation time 142445607 ps
CPU time 0.79 seconds
Started Mar 12 12:28:45 PM PDT 24
Finished Mar 12 12:28:46 PM PDT 24
Peak memory 200232 kb
Host smart-0ffe7bfd-f386-4486-9d5c-30530d5959fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197883192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_s
ame_csr_outstanding.3197883192
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.3075711276
Short name T883
Test name
Test status
Simulation time 250131092 ps
CPU time 1.66 seconds
Started Mar 12 12:28:43 PM PDT 24
Finished Mar 12 12:28:45 PM PDT 24
Peak memory 200696 kb
Host smart-0966315b-7f96-47d5-8956-7d349c9667a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075711276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.3075711276
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.4191235233
Short name T977
Test name
Test status
Simulation time 63007055 ps
CPU time 1.11 seconds
Started Mar 12 12:28:48 PM PDT 24
Finished Mar 12 12:28:49 PM PDT 24
Peak memory 200484 kb
Host smart-fea013e1-a740-43c5-a159-409c678cc49a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191235233 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.4191235233
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.953079750
Short name T900
Test name
Test status
Simulation time 35131698 ps
CPU time 0.61 seconds
Started Mar 12 12:28:43 PM PDT 24
Finished Mar 12 12:28:44 PM PDT 24
Peak memory 197688 kb
Host smart-5a77a89a-0210-4cab-8d8b-582146c500b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953079750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.953079750
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.1232817681
Short name T929
Test name
Test status
Simulation time 23469586 ps
CPU time 0.66 seconds
Started Mar 12 12:28:49 PM PDT 24
Finished Mar 12 12:28:49 PM PDT 24
Peak memory 196484 kb
Host smart-23419212-00f6-4b55-bfcd-647cf3f0a086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232817681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.1232817681
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1130600186
Short name T92
Test name
Test status
Simulation time 29687398 ps
CPU time 0.81 seconds
Started Mar 12 12:28:47 PM PDT 24
Finished Mar 12 12:28:48 PM PDT 24
Peak memory 198256 kb
Host smart-08fe5844-ba6f-479b-a015-0fd36d41a722
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130600186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.1130600186
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.3084700809
Short name T914
Test name
Test status
Simulation time 94720161 ps
CPU time 1.41 seconds
Started Mar 12 12:28:44 PM PDT 24
Finished Mar 12 12:28:46 PM PDT 24
Peak memory 200596 kb
Host smart-41a452a1-1d45-41c7-9733-be37a3bb96ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084700809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.3084700809
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3054289374
Short name T964
Test name
Test status
Simulation time 254501942 ps
CPU time 1.5 seconds
Started Mar 12 12:28:45 PM PDT 24
Finished Mar 12 12:28:47 PM PDT 24
Peak memory 200480 kb
Host smart-11c65e8f-5b49-47d9-bc83-079f4282b3d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054289374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er
r.3054289374
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2871054716
Short name T81
Test name
Test status
Simulation time 92548953 ps
CPU time 0.84 seconds
Started Mar 12 12:28:43 PM PDT 24
Finished Mar 12 12:28:44 PM PDT 24
Peak memory 200512 kb
Host smart-1521a161-d90b-4981-aa1e-c02c56b2ebf2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871054716 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.2871054716
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.2066659261
Short name T965
Test name
Test status
Simulation time 33725448 ps
CPU time 0.69 seconds
Started Mar 12 12:28:47 PM PDT 24
Finished Mar 12 12:28:49 PM PDT 24
Peak memory 197332 kb
Host smart-d5583be1-c8dd-45a7-8dfe-18dcb48f5f36
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066659261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.2066659261
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.3066801059
Short name T901
Test name
Test status
Simulation time 91246185 ps
CPU time 0.62 seconds
Started Mar 12 12:28:46 PM PDT 24
Finished Mar 12 12:28:47 PM PDT 24
Peak memory 196204 kb
Host smart-3d99a96b-d7fb-418e-8dad-3be968f687c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066801059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.3066801059
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.616009110
Short name T922
Test name
Test status
Simulation time 25800927 ps
CPU time 0.74 seconds
Started Mar 12 12:28:42 PM PDT 24
Finished Mar 12 12:28:43 PM PDT 24
Peak memory 198240 kb
Host smart-62c27898-1650-4b31-9239-77c034d9b857
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616009110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sa
me_csr_outstanding.616009110
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.2483393984
Short name T902
Test name
Test status
Simulation time 53436318 ps
CPU time 1.22 seconds
Started Mar 12 12:28:45 PM PDT 24
Finished Mar 12 12:28:46 PM PDT 24
Peak memory 200632 kb
Host smart-f45df857-7012-482d-8675-d00b4e620b57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483393984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.2483393984
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2433919817
Short name T953
Test name
Test status
Simulation time 326900538 ps
CPU time 1.63 seconds
Started Mar 12 12:28:52 PM PDT 24
Finished Mar 12 12:28:54 PM PDT 24
Peak memory 200512 kb
Host smart-3d6b419b-39b9-4ebe-bd68-6a10a33ea7e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433919817 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.2433919817
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.3435287357
Short name T894
Test name
Test status
Simulation time 54011691 ps
CPU time 0.88 seconds
Started Mar 12 12:28:48 PM PDT 24
Finished Mar 12 12:28:49 PM PDT 24
Peak memory 200284 kb
Host smart-fb12ce6d-92d9-422d-b2e6-869894768df1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435287357 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.3435287357
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1491683889
Short name T66
Test name
Test status
Simulation time 40974514 ps
CPU time 0.63 seconds
Started Mar 12 12:28:43 PM PDT 24
Finished Mar 12 12:28:44 PM PDT 24
Peak memory 197388 kb
Host smart-bb90ad0b-82e1-40d4-95f6-f59f45610132
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491683889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.1491683889
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.3334665863
Short name T941
Test name
Test status
Simulation time 19484293 ps
CPU time 0.6 seconds
Started Mar 12 12:28:46 PM PDT 24
Finished Mar 12 12:28:46 PM PDT 24
Peak memory 196224 kb
Host smart-51c5056f-881d-49c9-af60-c18f18ef89fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334665863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.3334665863
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3530101973
Short name T950
Test name
Test status
Simulation time 49037096 ps
CPU time 0.98 seconds
Started Mar 12 12:28:57 PM PDT 24
Finished Mar 12 12:28:59 PM PDT 24
Peak memory 199468 kb
Host smart-cb30c36f-f2bc-4027-a5e8-ffbdc9ede42e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530101973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s
ame_csr_outstanding.3530101973
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.3928866445
Short name T897
Test name
Test status
Simulation time 93807275 ps
CPU time 1.37 seconds
Started Mar 12 12:28:46 PM PDT 24
Finished Mar 12 12:28:47 PM PDT 24
Peak memory 200568 kb
Host smart-9fe4516e-a04d-4c26-8ae0-223b6ba9a8e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928866445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.3928866445
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.3316861246
Short name T908
Test name
Test status
Simulation time 207883753 ps
CPU time 1.16 seconds
Started Mar 12 12:28:47 PM PDT 24
Finished Mar 12 12:28:49 PM PDT 24
Peak memory 200492 kb
Host smart-a9cf958c-d70b-48a8-9119-711874ab4728
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316861246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er
r.3316861246
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.176648554
Short name T122
Test name
Test status
Simulation time 55107338 ps
CPU time 0.97 seconds
Started Mar 12 12:28:45 PM PDT 24
Finished Mar 12 12:28:46 PM PDT 24
Peak memory 200484 kb
Host smart-f7cd5e1f-1fae-4919-98c2-f6bdab9b83d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176648554 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.176648554
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.2053170295
Short name T899
Test name
Test status
Simulation time 19093943 ps
CPU time 0.64 seconds
Started Mar 12 12:28:51 PM PDT 24
Finished Mar 12 12:28:52 PM PDT 24
Peak memory 197220 kb
Host smart-26bc1553-c5bd-4886-9dd0-0782b4cf4c39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053170295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.2053170295
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.1021347745
Short name T971
Test name
Test status
Simulation time 19188008 ps
CPU time 0.67 seconds
Started Mar 12 12:28:50 PM PDT 24
Finished Mar 12 12:28:51 PM PDT 24
Peak memory 196264 kb
Host smart-59f5a154-3ed7-4057-8255-582204b44050
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021347745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.1021347745
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.96268685
Short name T895
Test name
Test status
Simulation time 59116225 ps
CPU time 0.68 seconds
Started Mar 12 12:28:42 PM PDT 24
Finished Mar 12 12:28:42 PM PDT 24
Peak memory 198204 kb
Host smart-6ae5c8c7-3d1c-4a26-a3cf-5490ec2dd94e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96268685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sam
e_csr_outstanding.96268685
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.213605515
Short name T903
Test name
Test status
Simulation time 74454840 ps
CPU time 1.54 seconds
Started Mar 12 12:28:43 PM PDT 24
Finished Mar 12 12:28:45 PM PDT 24
Peak memory 200544 kb
Host smart-fcc9555e-32e7-4743-a66e-58831b115087
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213605515 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.213605515
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.4099694180
Short name T940
Test name
Test status
Simulation time 234889074 ps
CPU time 1.08 seconds
Started Mar 12 12:28:44 PM PDT 24
Finished Mar 12 12:28:45 PM PDT 24
Peak memory 200704 kb
Host smart-a31220e7-893a-4cfb-968a-6e38a325236f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099694180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.4099694180
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.1136744766
Short name T74
Test name
Test status
Simulation time 71185642 ps
CPU time 0.77 seconds
Started Mar 12 12:28:50 PM PDT 24
Finished Mar 12 12:28:51 PM PDT 24
Peak memory 200040 kb
Host smart-19e2557b-4c07-4a61-8b59-df677a9a1b30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136744766 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.1136744766
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.3360165372
Short name T98
Test name
Test status
Simulation time 66739953 ps
CPU time 0.74 seconds
Started Mar 12 12:28:47 PM PDT 24
Finished Mar 12 12:28:49 PM PDT 24
Peak memory 197520 kb
Host smart-2d1d9bb5-96ab-41c3-968f-5d90a54bf7e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360165372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.3360165372
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.488024749
Short name T943
Test name
Test status
Simulation time 88618491 ps
CPU time 0.88 seconds
Started Mar 12 12:28:45 PM PDT 24
Finished Mar 12 12:28:46 PM PDT 24
Peak memory 199296 kb
Host smart-c73e1286-c9f3-43e4-92b5-f98f7fa90779
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488024749 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sa
me_csr_outstanding.488024749
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.598408047
Short name T913
Test name
Test status
Simulation time 161004904 ps
CPU time 2.39 seconds
Started Mar 12 12:28:43 PM PDT 24
Finished Mar 12 12:28:46 PM PDT 24
Peak memory 200660 kb
Host smart-3d0dcd57-fb9a-4b2b-8329-d045ed2bc61e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598408047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.598408047
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3167389742
Short name T912
Test name
Test status
Simulation time 269749926 ps
CPU time 1.09 seconds
Started Mar 12 12:28:47 PM PDT 24
Finished Mar 12 12:28:48 PM PDT 24
Peak memory 200384 kb
Host smart-eb6fb79d-b0f9-4cee-a2e6-06480888e6c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167389742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.3167389742
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3274781519
Short name T946
Test name
Test status
Simulation time 40274556 ps
CPU time 0.75 seconds
Started Mar 12 12:28:52 PM PDT 24
Finished Mar 12 12:28:53 PM PDT 24
Peak memory 199604 kb
Host smart-09a3f7e6-ef7a-4e58-8cb5-6a95327e2e61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274781519 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.3274781519
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.2266785957
Short name T107
Test name
Test status
Simulation time 24467888 ps
CPU time 0.71 seconds
Started Mar 12 12:28:45 PM PDT 24
Finished Mar 12 12:28:46 PM PDT 24
Peak memory 197892 kb
Host smart-b07c22b9-d79c-4f41-aafc-c9ce593201b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266785957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.2266785957
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.3406203380
Short name T875
Test name
Test status
Simulation time 47439091 ps
CPU time 0.64 seconds
Started Mar 12 12:28:49 PM PDT 24
Finished Mar 12 12:28:50 PM PDT 24
Peak memory 196372 kb
Host smart-3233202c-f411-4599-8b6b-221ec9b768dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406203380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.3406203380
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3973301448
Short name T963
Test name
Test status
Simulation time 46468998 ps
CPU time 0.71 seconds
Started Mar 12 12:28:54 PM PDT 24
Finished Mar 12 12:28:56 PM PDT 24
Peak memory 198168 kb
Host smart-bdbf8b09-08fe-4852-8ee6-8cf26d939ff0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973301448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s
ame_csr_outstanding.3973301448
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.1944167179
Short name T978
Test name
Test status
Simulation time 30399997 ps
CPU time 1.28 seconds
Started Mar 12 12:28:57 PM PDT 24
Finished Mar 12 12:28:58 PM PDT 24
Peak memory 200624 kb
Host smart-9186b555-23f7-44ac-857e-cd3c75047933
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944167179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.1944167179
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2191518127
Short name T951
Test name
Test status
Simulation time 235570325 ps
CPU time 1.09 seconds
Started Mar 12 12:28:56 PM PDT 24
Finished Mar 12 12:28:57 PM PDT 24
Peak memory 200488 kb
Host smart-e9ae5496-b0ad-49e6-b5c9-4ce65005da46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191518127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.2191518127
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.233965149
Short name T104
Test name
Test status
Simulation time 39515915 ps
CPU time 0.94 seconds
Started Mar 12 12:28:33 PM PDT 24
Finished Mar 12 12:28:35 PM PDT 24
Peak memory 199540 kb
Host smart-0324fa0b-b90e-47b6-beb5-dcbdbee91c91
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233965149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.233965149
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.1170863164
Short name T94
Test name
Test status
Simulation time 1223394223 ps
CPU time 3.43 seconds
Started Mar 12 12:28:31 PM PDT 24
Finished Mar 12 12:28:35 PM PDT 24
Peak memory 199560 kb
Host smart-1bcc450b-cdc4-45c2-997a-7ff07dbc0997
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170863164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.1
170863164
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.4277198888
Short name T106
Test name
Test status
Simulation time 38906379 ps
CPU time 0.76 seconds
Started Mar 12 12:28:36 PM PDT 24
Finished Mar 12 12:28:37 PM PDT 24
Peak memory 197796 kb
Host smart-ab863cfb-a237-477e-a8e2-ef6049eec78a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277198888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.4
277198888
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.1616749954
Short name T976
Test name
Test status
Simulation time 50779312 ps
CPU time 1.05 seconds
Started Mar 12 12:28:36 PM PDT 24
Finished Mar 12 12:28:37 PM PDT 24
Peak memory 200460 kb
Host smart-c21159e0-c723-454d-a34e-7f2427a03516
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616749954 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.1616749954
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.1360002232
Short name T63
Test name
Test status
Simulation time 205624360 ps
CPU time 0.68 seconds
Started Mar 12 12:28:32 PM PDT 24
Finished Mar 12 12:28:33 PM PDT 24
Peak memory 197668 kb
Host smart-043ad137-cd66-438c-8727-e7a4e0c88577
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360002232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.1360002232
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.1658220935
Short name T958
Test name
Test status
Simulation time 24527976 ps
CPU time 0.61 seconds
Started Mar 12 12:28:30 PM PDT 24
Finished Mar 12 12:28:31 PM PDT 24
Peak memory 196256 kb
Host smart-619388bc-a517-46dc-845f-19972f85034f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658220935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.1658220935
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.120330111
Short name T916
Test name
Test status
Simulation time 313496233 ps
CPU time 0.89 seconds
Started Mar 12 12:28:31 PM PDT 24
Finished Mar 12 12:28:32 PM PDT 24
Peak memory 199860 kb
Host smart-0c4cd9d5-db11-48cd-bb5d-28d651358fce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120330111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sam
e_csr_outstanding.120330111
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.534412767
Short name T945
Test name
Test status
Simulation time 98093260 ps
CPU time 1.28 seconds
Started Mar 12 12:28:39 PM PDT 24
Finished Mar 12 12:28:40 PM PDT 24
Peak memory 200660 kb
Host smart-f840d0c7-e493-45ae-b8d6-652ef5407c27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534412767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.534412767
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1377541996
Short name T57
Test name
Test status
Simulation time 267578549 ps
CPU time 1.13 seconds
Started Mar 12 12:28:35 PM PDT 24
Finished Mar 12 12:28:37 PM PDT 24
Peak memory 200584 kb
Host smart-e7d45f88-cb4b-4f23-9de5-69feabf4f454
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377541996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.1377541996
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.3219001601
Short name T880
Test name
Test status
Simulation time 19198775 ps
CPU time 0.64 seconds
Started Mar 12 12:28:46 PM PDT 24
Finished Mar 12 12:28:47 PM PDT 24
Peak memory 196588 kb
Host smart-f6533707-5672-4dca-905a-8db347bc4c62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219001601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.3219001601
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.4117511100
Short name T968
Test name
Test status
Simulation time 20888402 ps
CPU time 0.61 seconds
Started Mar 12 12:28:47 PM PDT 24
Finished Mar 12 12:28:49 PM PDT 24
Peak memory 196228 kb
Host smart-96af60f2-5547-40d1-951f-3cc9d2aaa258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117511100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.4117511100
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.2597497440
Short name T962
Test name
Test status
Simulation time 28374368 ps
CPU time 0.65 seconds
Started Mar 12 12:28:48 PM PDT 24
Finished Mar 12 12:28:49 PM PDT 24
Peak memory 196252 kb
Host smart-c257cc38-df2f-4323-b0c8-09ac66c4f528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597497440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.2597497440
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.1987227349
Short name T891
Test name
Test status
Simulation time 124344303 ps
CPU time 0.6 seconds
Started Mar 12 12:28:42 PM PDT 24
Finished Mar 12 12:28:43 PM PDT 24
Peak memory 196348 kb
Host smart-4bc4c38b-9fe8-4310-8dcc-ca22bd4594e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987227349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.1987227349
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.870396944
Short name T879
Test name
Test status
Simulation time 38499344 ps
CPU time 0.65 seconds
Started Mar 12 12:28:48 PM PDT 24
Finished Mar 12 12:28:49 PM PDT 24
Peak memory 196500 kb
Host smart-645ce8fe-e155-4b69-ad8c-c9892b1df11f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870396944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.870396944
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.100860153
Short name T871
Test name
Test status
Simulation time 23695007 ps
CPU time 0.6 seconds
Started Mar 12 12:28:56 PM PDT 24
Finished Mar 12 12:28:57 PM PDT 24
Peak memory 196484 kb
Host smart-d5a67d14-98da-4b0f-ba8b-93c782e6b8dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100860153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.100860153
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.3666502823
Short name T928
Test name
Test status
Simulation time 22217339 ps
CPU time 0.61 seconds
Started Mar 12 12:28:46 PM PDT 24
Finished Mar 12 12:28:46 PM PDT 24
Peak memory 196276 kb
Host smart-49ddfe03-32d0-44b2-8d07-4a441d2114ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666502823 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.3666502823
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.254996560
Short name T888
Test name
Test status
Simulation time 47754002 ps
CPU time 0.64 seconds
Started Mar 12 12:28:46 PM PDT 24
Finished Mar 12 12:28:47 PM PDT 24
Peak memory 196240 kb
Host smart-38911d42-376f-466e-8fff-f2ef48e45587
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254996560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.254996560
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.2103985004
Short name T960
Test name
Test status
Simulation time 17952321 ps
CPU time 0.63 seconds
Started Mar 12 12:28:45 PM PDT 24
Finished Mar 12 12:28:46 PM PDT 24
Peak memory 196384 kb
Host smart-7d9b2da5-7d53-42aa-99c2-eee76c9787cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103985004 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.2103985004
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.591178428
Short name T869
Test name
Test status
Simulation time 85207753 ps
CPU time 0.63 seconds
Started Mar 12 12:28:46 PM PDT 24
Finished Mar 12 12:28:47 PM PDT 24
Peak memory 196228 kb
Host smart-963f46d2-4d2d-429f-bc4e-ac58ed5ca46b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591178428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.591178428
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.66352465
Short name T96
Test name
Test status
Simulation time 54800547 ps
CPU time 0.83 seconds
Started Mar 12 12:28:31 PM PDT 24
Finished Mar 12 12:28:33 PM PDT 24
Peak memory 198104 kb
Host smart-fac64645-b531-4a51-9a22-012f2ea2e101
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66352465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.66352465
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.3013043398
Short name T956
Test name
Test status
Simulation time 82490085 ps
CPU time 1.76 seconds
Started Mar 12 12:28:29 PM PDT 24
Finished Mar 12 12:28:31 PM PDT 24
Peak memory 199492 kb
Host smart-931a86fa-69e4-42ab-8ed8-50a59881b51b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013043398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.3
013043398
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2046433763
Short name T102
Test name
Test status
Simulation time 50457092 ps
CPU time 0.68 seconds
Started Mar 12 12:28:39 PM PDT 24
Finished Mar 12 12:28:40 PM PDT 24
Peak memory 197496 kb
Host smart-60c458f2-9cbe-4c45-8496-fd4467b5330d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046433763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.2
046433763
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.4057172273
Short name T923
Test name
Test status
Simulation time 40579779 ps
CPU time 0.78 seconds
Started Mar 12 12:28:35 PM PDT 24
Finished Mar 12 12:28:36 PM PDT 24
Peak memory 199572 kb
Host smart-931e7303-d494-47d0-b934-aa1fce326a93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057172273 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.4057172273
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.3994517033
Short name T873
Test name
Test status
Simulation time 31585655 ps
CPU time 0.67 seconds
Started Mar 12 12:28:37 PM PDT 24
Finished Mar 12 12:28:38 PM PDT 24
Peak memory 197316 kb
Host smart-9ec2ddf5-5074-44aa-83b2-d0d541015893
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994517033 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.3994517033
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.1881909353
Short name T969
Test name
Test status
Simulation time 23146389 ps
CPU time 0.61 seconds
Started Mar 12 12:28:38 PM PDT 24
Finished Mar 12 12:28:38 PM PDT 24
Peak memory 196272 kb
Host smart-28424819-f956-4f37-82d4-5ba233a6b659
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881909353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.1881909353
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.2968821857
Short name T896
Test name
Test status
Simulation time 46097816 ps
CPU time 0.7 seconds
Started Mar 12 12:28:35 PM PDT 24
Finished Mar 12 12:28:36 PM PDT 24
Peak memory 198948 kb
Host smart-af9a2498-8164-4c04-9bf7-b0359d6863ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968821857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa
me_csr_outstanding.2968821857
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.926235683
Short name T892
Test name
Test status
Simulation time 89157039 ps
CPU time 2.3 seconds
Started Mar 12 12:28:33 PM PDT 24
Finished Mar 12 12:28:36 PM PDT 24
Peak memory 200636 kb
Host smart-ee504b20-4bb5-43a7-9318-721cdd488f55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926235683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.926235683
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.1899224099
Short name T76
Test name
Test status
Simulation time 184088409 ps
CPU time 1.67 seconds
Started Mar 12 12:28:31 PM PDT 24
Finished Mar 12 12:28:33 PM PDT 24
Peak memory 200420 kb
Host smart-24c3d8c3-3959-4fbf-819a-d1a0a18d78a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899224099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.1899224099
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.1938475289
Short name T884
Test name
Test status
Simulation time 19242322 ps
CPU time 0.61 seconds
Started Mar 12 12:28:47 PM PDT 24
Finished Mar 12 12:28:49 PM PDT 24
Peak memory 196516 kb
Host smart-c6085ad9-8fd8-4be8-846c-9eb535bcafc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938475289 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.1938475289
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.2962124060
Short name T930
Test name
Test status
Simulation time 19321665 ps
CPU time 0.62 seconds
Started Mar 12 12:28:49 PM PDT 24
Finished Mar 12 12:28:50 PM PDT 24
Peak memory 196556 kb
Host smart-bd33935a-a25e-49cd-a5c4-5cadc3dd69d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962124060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.2962124060
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.777841633
Short name T140
Test name
Test status
Simulation time 16471326 ps
CPU time 0.7 seconds
Started Mar 12 12:28:48 PM PDT 24
Finished Mar 12 12:28:49 PM PDT 24
Peak memory 196500 kb
Host smart-467bc9f2-d4ff-42dc-8fbf-68e02c430571
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777841633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.777841633
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.201252779
Short name T885
Test name
Test status
Simulation time 79031686 ps
CPU time 0.62 seconds
Started Mar 12 12:28:44 PM PDT 24
Finished Mar 12 12:28:45 PM PDT 24
Peak memory 196252 kb
Host smart-7390bc4e-b38d-490a-ba79-4730ca06e7be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201252779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.201252779
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2908556972
Short name T935
Test name
Test status
Simulation time 19195973 ps
CPU time 0.6 seconds
Started Mar 12 12:28:48 PM PDT 24
Finished Mar 12 12:28:49 PM PDT 24
Peak memory 196260 kb
Host smart-135a3720-4f6c-4e9f-bd8d-3994c4043edb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908556972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.2908556972
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.3127541896
Short name T959
Test name
Test status
Simulation time 18527740 ps
CPU time 0.64 seconds
Started Mar 12 12:28:51 PM PDT 24
Finished Mar 12 12:28:52 PM PDT 24
Peak memory 196568 kb
Host smart-b4e2a787-36a1-41d0-b231-1a9ad81e3f44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127541896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.3127541896
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.2966762588
Short name T973
Test name
Test status
Simulation time 21338687 ps
CPU time 0.61 seconds
Started Mar 12 12:28:46 PM PDT 24
Finished Mar 12 12:28:47 PM PDT 24
Peak memory 196168 kb
Host smart-df2b41da-19ae-4df5-8506-85d3a2203e5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966762588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.2966762588
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.535369982
Short name T898
Test name
Test status
Simulation time 158814094 ps
CPU time 0.6 seconds
Started Mar 12 12:28:41 PM PDT 24
Finished Mar 12 12:28:42 PM PDT 24
Peak memory 196180 kb
Host smart-e52e9ee7-53c8-48b3-80be-9dbb059cb5d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535369982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.535369982
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.538856287
Short name T979
Test name
Test status
Simulation time 84194967 ps
CPU time 0.62 seconds
Started Mar 12 12:28:45 PM PDT 24
Finished Mar 12 12:28:46 PM PDT 24
Peak memory 196548 kb
Host smart-fbd5771e-5ecf-4d05-b6dc-93cd588e2594
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538856287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.538856287
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.3508859789
Short name T910
Test name
Test status
Simulation time 39413276 ps
CPU time 0.62 seconds
Started Mar 12 12:28:46 PM PDT 24
Finished Mar 12 12:28:47 PM PDT 24
Peak memory 196452 kb
Host smart-95e3d538-1f99-49aa-8146-53a60993f02e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508859789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.3508859789
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.891027169
Short name T93
Test name
Test status
Simulation time 46651507 ps
CPU time 0.79 seconds
Started Mar 12 12:28:34 PM PDT 24
Finished Mar 12 12:28:35 PM PDT 24
Peak memory 198400 kb
Host smart-2dea87a6-948c-4c38-8b14-14885a6925e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891027169 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.891027169
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.544162126
Short name T966
Test name
Test status
Simulation time 888943189 ps
CPU time 2.07 seconds
Started Mar 12 12:28:32 PM PDT 24
Finished Mar 12 12:28:34 PM PDT 24
Peak memory 200732 kb
Host smart-a55d0b14-d5f7-42d8-a1ed-420564cec87a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544162126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.544162126
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.2291390606
Short name T921
Test name
Test status
Simulation time 68229673 ps
CPU time 0.7 seconds
Started Mar 12 12:28:35 PM PDT 24
Finished Mar 12 12:28:36 PM PDT 24
Peak memory 197472 kb
Host smart-4dddb8e4-2aca-49e8-a19e-3d91c969147a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291390606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.2
291390606
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3751300695
Short name T954
Test name
Test status
Simulation time 44478645 ps
CPU time 0.86 seconds
Started Mar 12 12:28:32 PM PDT 24
Finished Mar 12 12:28:33 PM PDT 24
Peak memory 200508 kb
Host smart-082f56cb-21e2-41d3-99b1-205616eebfc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751300695 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.3751300695
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.3554649144
Short name T142
Test name
Test status
Simulation time 19240053 ps
CPU time 0.64 seconds
Started Mar 12 12:28:36 PM PDT 24
Finished Mar 12 12:28:37 PM PDT 24
Peak memory 197604 kb
Host smart-8c1c117d-8c91-4de5-be2d-a28f86bdedcc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554649144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.3554649144
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.3304200217
Short name T924
Test name
Test status
Simulation time 18809074 ps
CPU time 0.65 seconds
Started Mar 12 12:28:33 PM PDT 24
Finished Mar 12 12:28:34 PM PDT 24
Peak memory 196396 kb
Host smart-ac00be51-1f2a-434b-9395-dba62adc3b73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304200217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.3304200217
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.1537505268
Short name T99
Test name
Test status
Simulation time 78613350 ps
CPU time 0.76 seconds
Started Mar 12 12:28:32 PM PDT 24
Finished Mar 12 12:28:33 PM PDT 24
Peak memory 197844 kb
Host smart-a7a32e4b-9532-4ab2-a905-e1e410c9de0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537505268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.1537505268
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.4156193365
Short name T878
Test name
Test status
Simulation time 449142778 ps
CPU time 1.74 seconds
Started Mar 12 12:28:32 PM PDT 24
Finished Mar 12 12:28:34 PM PDT 24
Peak memory 200648 kb
Host smart-b54d37a3-132a-4114-859f-dca54cae704a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156193365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.4156193365
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1926465492
Short name T932
Test name
Test status
Simulation time 435027633 ps
CPU time 1.6 seconds
Started Mar 12 12:28:31 PM PDT 24
Finished Mar 12 12:28:33 PM PDT 24
Peak memory 200576 kb
Host smart-67d2cf7a-484e-4ec5-a3fb-915eb471cf00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926465492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err
.1926465492
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.1607838096
Short name T69
Test name
Test status
Simulation time 24571145 ps
CPU time 0.61 seconds
Started Mar 12 12:28:47 PM PDT 24
Finished Mar 12 12:28:48 PM PDT 24
Peak memory 196300 kb
Host smart-12d1c037-6d17-4979-a3bc-c4f71851d5ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607838096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.1607838096
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.944445606
Short name T949
Test name
Test status
Simulation time 20588714 ps
CPU time 0.65 seconds
Started Mar 12 12:28:46 PM PDT 24
Finished Mar 12 12:28:47 PM PDT 24
Peak memory 196380 kb
Host smart-d06772e7-d3a6-44b9-bf50-347b82fc6c07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944445606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.944445606
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.3536562463
Short name T70
Test name
Test status
Simulation time 148211835 ps
CPU time 0.62 seconds
Started Mar 12 12:28:48 PM PDT 24
Finished Mar 12 12:28:49 PM PDT 24
Peak memory 196652 kb
Host smart-331cf8a5-6758-48b7-91a8-3db0f6ec315b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536562463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.3536562463
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.829638596
Short name T937
Test name
Test status
Simulation time 20760218 ps
CPU time 0.61 seconds
Started Mar 12 12:28:46 PM PDT 24
Finished Mar 12 12:28:47 PM PDT 24
Peak memory 196312 kb
Host smart-bdf0cbd1-edb1-4c13-8cc2-4ff3e9be269c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829638596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.829638596
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.441771937
Short name T876
Test name
Test status
Simulation time 44130770 ps
CPU time 0.63 seconds
Started Mar 12 12:28:46 PM PDT 24
Finished Mar 12 12:28:46 PM PDT 24
Peak memory 196408 kb
Host smart-afc6032d-1b3f-4bbe-b11f-7e341ab32fc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441771937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.441771937
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3086715329
Short name T141
Test name
Test status
Simulation time 30999641 ps
CPU time 0.66 seconds
Started Mar 12 12:28:50 PM PDT 24
Finished Mar 12 12:28:51 PM PDT 24
Peak memory 196616 kb
Host smart-c8ae7865-7527-4e82-940d-d5a299b9cde5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086715329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.3086715329
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.3836555961
Short name T870
Test name
Test status
Simulation time 17876818 ps
CPU time 0.65 seconds
Started Mar 12 12:28:49 PM PDT 24
Finished Mar 12 12:28:50 PM PDT 24
Peak memory 196276 kb
Host smart-9e26dbf3-1b2f-4070-b6b3-08490ec02e59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836555961 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.3836555961
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1325752136
Short name T947
Test name
Test status
Simulation time 16340602 ps
CPU time 0.58 seconds
Started Mar 12 12:29:06 PM PDT 24
Finished Mar 12 12:29:07 PM PDT 24
Peak memory 196508 kb
Host smart-5a9246d1-0bdc-4c7f-9a4a-d277067f4eb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325752136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.1325752136
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.951248422
Short name T874
Test name
Test status
Simulation time 60621249 ps
CPU time 0.66 seconds
Started Mar 12 12:28:59 PM PDT 24
Finished Mar 12 12:29:00 PM PDT 24
Peak memory 196532 kb
Host smart-871881dc-c860-4d75-8248-dc9c7cd89cf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951248422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.951248422
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.2761237914
Short name T980
Test name
Test status
Simulation time 21324847 ps
CPU time 0.71 seconds
Started Mar 12 12:29:00 PM PDT 24
Finished Mar 12 12:29:01 PM PDT 24
Peak memory 196196 kb
Host smart-511c070b-beb3-486c-9cac-12cf4dc4f959
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761237914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.2761237914
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.622932659
Short name T974
Test name
Test status
Simulation time 25896639 ps
CPU time 0.65 seconds
Started Mar 12 12:28:34 PM PDT 24
Finished Mar 12 12:28:35 PM PDT 24
Peak memory 197356 kb
Host smart-58951ed7-c7f9-4b7f-9cb0-c31439cdcefd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622932659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.622932659
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.693069940
Short name T942
Test name
Test status
Simulation time 29885119 ps
CPU time 0.61 seconds
Started Mar 12 12:28:33 PM PDT 24
Finished Mar 12 12:28:34 PM PDT 24
Peak memory 196616 kb
Host smart-5454414a-0892-49cb-a9ba-b66a65b7396c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693069940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.693069940
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2443377956
Short name T65
Test name
Test status
Simulation time 33852941 ps
CPU time 0.83 seconds
Started Mar 12 12:28:33 PM PDT 24
Finished Mar 12 12:28:33 PM PDT 24
Peak memory 197872 kb
Host smart-22bfe792-5c65-48ee-b528-1d8842a67c52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443377956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.2443377956
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.2813984476
Short name T68
Test name
Test status
Simulation time 978821927 ps
CPU time 1.95 seconds
Started Mar 12 12:28:33 PM PDT 24
Finished Mar 12 12:28:35 PM PDT 24
Peak memory 200720 kb
Host smart-79e81e8e-dd6e-4e7c-b784-d52c16c7e4ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813984476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.2813984476
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3238002114
Short name T58
Test name
Test status
Simulation time 287784038 ps
CPU time 1.14 seconds
Started Mar 12 12:28:30 PM PDT 24
Finished Mar 12 12:28:31 PM PDT 24
Peak memory 200380 kb
Host smart-f34b48ae-d41b-4c7c-8a73-01806b0b534e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238002114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.3238002114
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.1669273282
Short name T877
Test name
Test status
Simulation time 42974967 ps
CPU time 1.07 seconds
Started Mar 12 12:28:30 PM PDT 24
Finished Mar 12 12:28:31 PM PDT 24
Peak memory 200936 kb
Host smart-7a57f081-41e2-4c03-94f0-ae1228d7034d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669273282 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.1669273282
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.18792135
Short name T906
Test name
Test status
Simulation time 19947696 ps
CPU time 0.63 seconds
Started Mar 12 12:28:33 PM PDT 24
Finished Mar 12 12:28:33 PM PDT 24
Peak memory 197156 kb
Host smart-27ad123b-79b4-4e81-8fcc-1df389acf19b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18792135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.18792135
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.88728526
Short name T868
Test name
Test status
Simulation time 21063359 ps
CPU time 0.67 seconds
Started Mar 12 12:28:32 PM PDT 24
Finished Mar 12 12:28:33 PM PDT 24
Peak memory 196376 kb
Host smart-1b3ad88c-951c-478f-a871-15b4ee70c27e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88728526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.88728526
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2833595890
Short name T100
Test name
Test status
Simulation time 47900373 ps
CPU time 0.7 seconds
Started Mar 12 12:28:36 PM PDT 24
Finished Mar 12 12:28:37 PM PDT 24
Peak memory 198140 kb
Host smart-451159bf-98fc-4473-809a-b3b80148ff11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833595890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa
me_csr_outstanding.2833595890
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.3385974577
Short name T919
Test name
Test status
Simulation time 133643568 ps
CPU time 2.65 seconds
Started Mar 12 12:28:37 PM PDT 24
Finished Mar 12 12:28:39 PM PDT 24
Peak memory 200708 kb
Host smart-735d7052-3d98-4f78-8499-45937b7d0138
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385974577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.3385974577
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.4171712534
Short name T909
Test name
Test status
Simulation time 133028845 ps
CPU time 1.12 seconds
Started Mar 12 12:28:32 PM PDT 24
Finished Mar 12 12:28:34 PM PDT 24
Peak memory 200200 kb
Host smart-3271b1a2-c4e1-4964-a880-77036d61bb03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171712534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.4171712534
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.686764770
Short name T936
Test name
Test status
Simulation time 56642853 ps
CPU time 1.39 seconds
Started Mar 12 12:28:34 PM PDT 24
Finished Mar 12 12:28:36 PM PDT 24
Peak memory 200668 kb
Host smart-053e6067-e002-4475-bd7d-395103c387c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686764770 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.686764770
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.2629450678
Short name T105
Test name
Test status
Simulation time 23034202 ps
CPU time 0.73 seconds
Started Mar 12 12:28:35 PM PDT 24
Finished Mar 12 12:28:35 PM PDT 24
Peak memory 197808 kb
Host smart-f8235d12-a272-4db0-af00-9215305777a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629450678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.2629450678
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.2162401937
Short name T139
Test name
Test status
Simulation time 18688152 ps
CPU time 0.64 seconds
Started Mar 12 12:28:32 PM PDT 24
Finished Mar 12 12:28:33 PM PDT 24
Peak memory 196336 kb
Host smart-0e3fda87-f35e-4ece-a624-1ac1ef91c4a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162401937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.2162401937
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.2485147694
Short name T944
Test name
Test status
Simulation time 63811920 ps
CPU time 0.75 seconds
Started Mar 12 12:28:38 PM PDT 24
Finished Mar 12 12:28:38 PM PDT 24
Peak memory 199636 kb
Host smart-9e997702-22b2-4ed9-9577-f27c87362d6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485147694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa
me_csr_outstanding.2485147694
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.1053126632
Short name T933
Test name
Test status
Simulation time 274892194 ps
CPU time 1.84 seconds
Started Mar 12 12:28:36 PM PDT 24
Finished Mar 12 12:28:38 PM PDT 24
Peak memory 200648 kb
Host smart-e8102f1e-c499-405d-8961-6d6a6a30b2a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053126632 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.1053126632
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.584680040
Short name T927
Test name
Test status
Simulation time 266819138 ps
CPU time 1.17 seconds
Started Mar 12 12:28:36 PM PDT 24
Finished Mar 12 12:28:37 PM PDT 24
Peak memory 200568 kb
Host smart-f50b58d7-12ce-449d-a601-17f77f8ade6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584680040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err.
584680040
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.642726954
Short name T972
Test name
Test status
Simulation time 55435851 ps
CPU time 1.47 seconds
Started Mar 12 12:28:33 PM PDT 24
Finished Mar 12 12:28:35 PM PDT 24
Peak memory 200592 kb
Host smart-176b5a7c-6038-4606-a28d-bba638e30162
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642726954 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.642726954
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.3032460757
Short name T970
Test name
Test status
Simulation time 34257272 ps
CPU time 0.68 seconds
Started Mar 12 12:28:35 PM PDT 24
Finished Mar 12 12:28:36 PM PDT 24
Peak memory 197660 kb
Host smart-eadd9517-63ee-44e5-b31c-53c62c389b1d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032460757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.3032460757
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.1319671583
Short name T893
Test name
Test status
Simulation time 52619877 ps
CPU time 0.61 seconds
Started Mar 12 12:28:35 PM PDT 24
Finished Mar 12 12:28:36 PM PDT 24
Peak memory 196420 kb
Host smart-51210d6c-e09f-461b-9a53-9b677cb29ad2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319671583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.1319671583
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2722244945
Short name T109
Test name
Test status
Simulation time 75896683 ps
CPU time 0.69 seconds
Started Mar 12 12:28:33 PM PDT 24
Finished Mar 12 12:28:34 PM PDT 24
Peak memory 197984 kb
Host smart-921705a1-e394-47bf-a065-ca48212c3b59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722244945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.2722244945
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.1260410763
Short name T56
Test name
Test status
Simulation time 112838785 ps
CPU time 2.42 seconds
Started Mar 12 12:28:32 PM PDT 24
Finished Mar 12 12:28:34 PM PDT 24
Peak memory 200672 kb
Host smart-5a306e9d-5b0b-4b70-83eb-aa7cf2540952
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260410763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.1260410763
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.1493613790
Short name T911
Test name
Test status
Simulation time 76734989 ps
CPU time 1.52 seconds
Started Mar 12 12:28:39 PM PDT 24
Finished Mar 12 12:28:41 PM PDT 24
Peak memory 200564 kb
Host smart-bc98421a-f07d-43be-bd87-5b9fc05fbcf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493613790 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.1493613790
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.1623008712
Short name T101
Test name
Test status
Simulation time 44618286 ps
CPU time 0.62 seconds
Started Mar 12 12:28:36 PM PDT 24
Finished Mar 12 12:28:36 PM PDT 24
Peak memory 196860 kb
Host smart-fd2e2af1-7e08-4f88-985d-be0c97ade4a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623008712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.1623008712
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.4121693225
Short name T872
Test name
Test status
Simulation time 51047351 ps
CPU time 0.64 seconds
Started Mar 12 12:28:38 PM PDT 24
Finished Mar 12 12:28:39 PM PDT 24
Peak memory 196512 kb
Host smart-a3f76aa2-7867-4366-bf50-3b37a8ff2b8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121693225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.4121693225
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.3737701104
Short name T939
Test name
Test status
Simulation time 43135503 ps
CPU time 0.9 seconds
Started Mar 12 12:28:39 PM PDT 24
Finished Mar 12 12:28:40 PM PDT 24
Peak memory 199452 kb
Host smart-03c66de7-b36f-4677-bbbd-ec1129eba5f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737701104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sa
me_csr_outstanding.3737701104
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.3276669252
Short name T926
Test name
Test status
Simulation time 391401192 ps
CPU time 2.38 seconds
Started Mar 12 12:28:32 PM PDT 24
Finished Mar 12 12:28:34 PM PDT 24
Peak memory 200644 kb
Host smart-f15ac0d0-bce9-44a1-a8b9-6cd3562b74f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276669252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.3276669252
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.2311475655
Short name T55
Test name
Test status
Simulation time 112590425 ps
CPU time 1.26 seconds
Started Mar 12 12:28:38 PM PDT 24
Finished Mar 12 12:28:40 PM PDT 24
Peak memory 200552 kb
Host smart-65415376-8f11-43e4-b3b1-c0928c1bff95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311475655 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err
.2311475655
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.3819331007
Short name T546
Test name
Test status
Simulation time 20831832 ps
CPU time 0.69 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 195324 kb
Host smart-100a1265-4e65-41bf-8d3b-65c65d87ebdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819331007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.3819331007
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.3243031996
Short name T125
Test name
Test status
Simulation time 55533982 ps
CPU time 0.83 seconds
Started Mar 12 12:49:20 PM PDT 24
Finished Mar 12 12:49:21 PM PDT 24
Peak memory 198012 kb
Host smart-c2373057-f435-49a6-a4de-a12c43abdaeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243031996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disa
ble_rom_integrity_check.3243031996
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.74288452
Short name T198
Test name
Test status
Simulation time 31072998 ps
CPU time 0.61 seconds
Started Mar 12 12:49:25 PM PDT 24
Finished Mar 12 12:49:26 PM PDT 24
Peak memory 195324 kb
Host smart-2c893c34-e644-453a-8c92-1e644f54a5d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74288452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_ma
lfunc.74288452
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.2419914795
Short name T500
Test name
Test status
Simulation time 61786072 ps
CPU time 0.6 seconds
Started Mar 12 12:49:25 PM PDT 24
Finished Mar 12 12:49:28 PM PDT 24
Peak memory 195468 kb
Host smart-311aa7d2-0da2-4961-bb9c-e5189e7e110f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419914795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.2419914795
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.2342573050
Short name T50
Test name
Test status
Simulation time 33190612 ps
CPU time 0.6 seconds
Started Mar 12 12:49:26 PM PDT 24
Finished Mar 12 12:49:28 PM PDT 24
Peak memory 195440 kb
Host smart-a2b5f2c9-3b86-4093-9fe2-29171e4b45a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342573050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.2342573050
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.977378411
Short name T208
Test name
Test status
Simulation time 76211145 ps
CPU time 0.64 seconds
Started Mar 12 12:49:26 PM PDT 24
Finished Mar 12 12:49:29 PM PDT 24
Peak memory 195796 kb
Host smart-9b6ac5f0-af75-4aa8-a4c5-7d11cbf406a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977378411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invalid
.977378411
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_wakeup_race.3962491948
Short name T585
Test name
Test status
Simulation time 209459317 ps
CPU time 0.81 seconds
Started Mar 12 12:49:25 PM PDT 24
Finished Mar 12 12:49:26 PM PDT 24
Peak memory 195308 kb
Host smart-aa918e7c-c0a3-4ded-a5cb-ddaf062ba8e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962491948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wa
keup_race.3962491948
Directory /workspace/0.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.3990626037
Short name T679
Test name
Test status
Simulation time 19732580 ps
CPU time 0.62 seconds
Started Mar 12 12:49:26 PM PDT 24
Finished Mar 12 12:49:28 PM PDT 24
Peak memory 197912 kb
Host smart-1dc0e648-6eea-4123-9ce9-9747ad76ee99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990626037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.3990626037
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.3461792171
Short name T731
Test name
Test status
Simulation time 117381339 ps
CPU time 0.92 seconds
Started Mar 12 12:49:23 PM PDT 24
Finished Mar 12 12:49:24 PM PDT 24
Peak memory 205300 kb
Host smart-688269ba-cfb7-49d4-a738-bf7012087286
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461792171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.3461792171
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1451691370
Short name T357
Test name
Test status
Simulation time 1038601914 ps
CPU time 2.6 seconds
Started Mar 12 12:49:26 PM PDT 24
Finished Mar 12 12:49:30 PM PDT 24
Peak memory 201264 kb
Host smart-d15452a2-5f90-4290-84a9-9238b6ae0b0e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451691370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1451691370
Directory /workspace/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1076283497
Short name T276
Test name
Test status
Simulation time 881228126 ps
CPU time 3.12 seconds
Started Mar 12 12:49:25 PM PDT 24
Finished Mar 12 12:49:31 PM PDT 24
Peak memory 195952 kb
Host smart-c8e6290c-3a8b-4d39-8de7-685d0d9ff067
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076283497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1076283497
Directory /workspace/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.3174174854
Short name T395
Test name
Test status
Simulation time 55011347 ps
CPU time 0.89 seconds
Started Mar 12 12:49:27 PM PDT 24
Finished Mar 12 12:49:29 PM PDT 24
Peak memory 195280 kb
Host smart-6e731b6c-fc6f-4ef3-b5fb-a231ef132449
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174174854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3174174854
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.3256280850
Short name T323
Test name
Test status
Simulation time 28059840 ps
CPU time 0.67 seconds
Started Mar 12 12:49:22 PM PDT 24
Finished Mar 12 12:49:23 PM PDT 24
Peak memory 197728 kb
Host smart-c79bcbea-0f55-4d6b-a213-9366429162ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256280850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.3256280850
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup_reset.2602042296
Short name T180
Test name
Test status
Simulation time 276116196 ps
CPU time 0.91 seconds
Started Mar 12 12:49:25 PM PDT 24
Finished Mar 12 12:49:27 PM PDT 24
Peak memory 197912 kb
Host smart-b8fe9b2d-6673-4584-9d5c-3e505e292de3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602042296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.2602042296
Directory /workspace/0.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.4179726718
Short name T490
Test name
Test status
Simulation time 34859004 ps
CPU time 0.72 seconds
Started Mar 12 12:49:26 PM PDT 24
Finished Mar 12 12:49:29 PM PDT 24
Peak memory 195340 kb
Host smart-b971085b-58dc-4ede-ada2-979dc04f9431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179726718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.4179726718
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.646870787
Short name T643
Test name
Test status
Simulation time 74730483 ps
CPU time 0.76 seconds
Started Mar 12 12:49:31 PM PDT 24
Finished Mar 12 12:49:32 PM PDT 24
Peak memory 196676 kb
Host smart-ad09e13b-3712-42d3-83f7-3937c3fa4df4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646870787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disab
le_rom_integrity_check.646870787
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.1392378369
Short name T46
Test name
Test status
Simulation time 37665483 ps
CPU time 0.59 seconds
Started Mar 12 12:49:30 PM PDT 24
Finished Mar 12 12:49:30 PM PDT 24
Peak memory 195260 kb
Host smart-294021e9-d9a9-40b3-b22e-c956c86d06cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392378369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_
malfunc.1392378369
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.2300601174
Short name T793
Test name
Test status
Simulation time 2180123706 ps
CPU time 0.95 seconds
Started Mar 12 12:49:26 PM PDT 24
Finished Mar 12 12:49:29 PM PDT 24
Peak memory 195464 kb
Host smart-ceba60ed-027e-4beb-9b2a-7bfebef0748f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300601174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.2300601174
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.643984796
Short name T352
Test name
Test status
Simulation time 43073427 ps
CPU time 0.58 seconds
Started Mar 12 12:49:19 PM PDT 24
Finished Mar 12 12:49:20 PM PDT 24
Peak memory 195376 kb
Host smart-721a0edb-d36a-405a-ba1e-77e9d6b199e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643984796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.643984796
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.212460232
Short name T436
Test name
Test status
Simulation time 41276513 ps
CPU time 0.61 seconds
Started Mar 12 12:49:21 PM PDT 24
Finished Mar 12 12:49:22 PM PDT 24
Peak memory 195396 kb
Host smart-f5029627-1aa0-446b-b8d6-fdb3e637d544
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212460232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.212460232
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.3460645461
Short name T860
Test name
Test status
Simulation time 76403625 ps
CPU time 0.64 seconds
Started Mar 12 12:49:29 PM PDT 24
Finished Mar 12 12:49:30 PM PDT 24
Peak memory 195908 kb
Host smart-909cac3f-1b8d-47c3-9817-6dc6b8bd5f2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460645461 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.3460645461
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.3562353354
Short name T664
Test name
Test status
Simulation time 272541872 ps
CPU time 0.7 seconds
Started Mar 12 12:49:23 PM PDT 24
Finished Mar 12 12:49:24 PM PDT 24
Peak memory 195340 kb
Host smart-1aefcc09-063e-4079-9c81-c6876e515177
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562353354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wa
keup_race.3562353354
Directory /workspace/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.3602173385
Short name T792
Test name
Test status
Simulation time 138382593 ps
CPU time 0.87 seconds
Started Mar 12 12:49:22 PM PDT 24
Finished Mar 12 12:49:23 PM PDT 24
Peak memory 197728 kb
Host smart-785571a6-3b8e-4341-8e32-6ba9da722415
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602173385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.3602173385
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.2863034273
Short name T488
Test name
Test status
Simulation time 161418229 ps
CPU time 0.78 seconds
Started Mar 12 12:49:34 PM PDT 24
Finished Mar 12 12:49:35 PM PDT 24
Peak memory 205216 kb
Host smart-9d9dceae-05ad-493a-99a9-6247741220d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863034273 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.2863034273
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.3025114341
Short name T31
Test name
Test status
Simulation time 355734810 ps
CPU time 1.24 seconds
Started Mar 12 12:49:32 PM PDT 24
Finished Mar 12 12:49:34 PM PDT 24
Peak memory 214804 kb
Host smart-03c649b1-9cfa-42b1-91ed-c4e0cb63b17f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025114341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.3025114341
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.3028229200
Short name T566
Test name
Test status
Simulation time 271649008 ps
CPU time 0.99 seconds
Started Mar 12 12:49:25 PM PDT 24
Finished Mar 12 12:49:26 PM PDT 24
Peak memory 195352 kb
Host smart-055cc7f8-9621-4a4b-af92-b7957d9a99cb
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028229200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_c
m_ctrl_config_regwen.3028229200
Directory /workspace/1.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1237855216
Short name T651
Test name
Test status
Simulation time 984004217 ps
CPU time 1.94 seconds
Started Mar 12 12:49:21 PM PDT 24
Finished Mar 12 12:49:23 PM PDT 24
Peak memory 200800 kb
Host smart-55f7c159-b4b8-4a46-aa3d-6a8f84ef8389
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237855216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1237855216
Directory /workspace/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.371846847
Short name T673
Test name
Test status
Simulation time 975719921 ps
CPU time 2.17 seconds
Started Mar 12 12:49:25 PM PDT 24
Finished Mar 12 12:49:30 PM PDT 24
Peak memory 195844 kb
Host smart-15faafbc-7ea2-433b-97aa-79da9ef1fcee
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371846847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.371846847
Directory /workspace/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.2825270605
Short name T819
Test name
Test status
Simulation time 94015578 ps
CPU time 0.77 seconds
Started Mar 12 12:49:25 PM PDT 24
Finished Mar 12 12:49:27 PM PDT 24
Peak memory 195380 kb
Host smart-cae033a8-010c-4e2d-8a8d-0810943eeba3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825270605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2825270605
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.3222577482
Short name T661
Test name
Test status
Simulation time 100503209 ps
CPU time 0.63 seconds
Started Mar 12 12:49:26 PM PDT 24
Finished Mar 12 12:49:29 PM PDT 24
Peak memory 195568 kb
Host smart-0762fe21-d2f8-46ca-97a1-96b0f1b6237b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222577482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.3222577482
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup_reset.2820413981
Short name T158
Test name
Test status
Simulation time 922060428 ps
CPU time 0.95 seconds
Started Mar 12 12:49:21 PM PDT 24
Finished Mar 12 12:49:22 PM PDT 24
Peak memory 199056 kb
Host smart-46abffda-ea9a-454d-89f9-fc7ab7883323
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820413981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.2820413981
Directory /workspace/1.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.3316022455
Short name T268
Test name
Test status
Simulation time 126779413 ps
CPU time 0.68 seconds
Started Mar 12 12:50:12 PM PDT 24
Finished Mar 12 12:50:13 PM PDT 24
Peak memory 195336 kb
Host smart-35e3a34d-e752-4aee-a3d7-0b9d5fe1531d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316022455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.3316022455
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.1049448010
Short name T324
Test name
Test status
Simulation time 66343025 ps
CPU time 0.7 seconds
Started Mar 12 12:50:10 PM PDT 24
Finished Mar 12 12:50:11 PM PDT 24
Peak memory 196644 kb
Host smart-a60fd632-c8f0-4291-b743-da83fd528d98
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049448010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.1049448010
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.127540486
Short name T799
Test name
Test status
Simulation time 54160822 ps
CPU time 0.59 seconds
Started Mar 12 12:50:15 PM PDT 24
Finished Mar 12 12:50:16 PM PDT 24
Peak memory 195328 kb
Host smart-41779864-93b8-4e6c-9882-5de428ffb174
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127540486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst_
malfunc.127540486
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.501422454
Short name T812
Test name
Test status
Simulation time 1068256117 ps
CPU time 0.91 seconds
Started Mar 12 12:50:06 PM PDT 24
Finished Mar 12 12:50:07 PM PDT 24
Peak memory 195364 kb
Host smart-ace8ce10-75b5-4191-b26d-602d2eccbe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501422454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.501422454
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.901563366
Short name T627
Test name
Test status
Simulation time 80427812 ps
CPU time 0.64 seconds
Started Mar 12 12:50:07 PM PDT 24
Finished Mar 12 12:50:07 PM PDT 24
Peak memory 195404 kb
Host smart-62d452fe-568d-4b11-aec3-3ccc14b3c73d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901563366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.901563366
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.956687251
Short name T286
Test name
Test status
Simulation time 190181675 ps
CPU time 0.6 seconds
Started Mar 12 12:50:11 PM PDT 24
Finished Mar 12 12:50:11 PM PDT 24
Peak memory 195376 kb
Host smart-7b89c291-6f6d-4dbb-a167-fd108e5a715c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956687251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.956687251
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.1923816139
Short name T374
Test name
Test status
Simulation time 41761017 ps
CPU time 0.73 seconds
Started Mar 12 12:50:17 PM PDT 24
Finished Mar 12 12:50:18 PM PDT 24
Peak memory 195892 kb
Host smart-87479a41-e5a2-43de-ad6b-65a1eb8f1111
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923816139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.1923816139
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_wakeup_race.4106465561
Short name T224
Test name
Test status
Simulation time 42679257 ps
CPU time 0.65 seconds
Started Mar 12 12:50:07 PM PDT 24
Finished Mar 12 12:50:07 PM PDT 24
Peak memory 195444 kb
Host smart-217bda8d-5af8-4a54-a95d-159a07548d2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106465561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_w
akeup_race.4106465561
Directory /workspace/10.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.2272937409
Short name T447
Test name
Test status
Simulation time 105863642 ps
CPU time 0.93 seconds
Started Mar 12 12:50:04 PM PDT 24
Finished Mar 12 12:50:05 PM PDT 24
Peak memory 199160 kb
Host smart-666bfbbb-a9c9-4f26-93fc-591565e6abb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272937409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.2272937409
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.1730754746
Short name T810
Test name
Test status
Simulation time 136339784 ps
CPU time 0.79 seconds
Started Mar 12 12:50:20 PM PDT 24
Finished Mar 12 12:50:21 PM PDT 24
Peak memory 205208 kb
Host smart-7c7b1335-2ee1-46b7-b517-455bb2c54867
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730754746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.1730754746
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.609426170
Short name T482
Test name
Test status
Simulation time 121395113 ps
CPU time 0.75 seconds
Started Mar 12 12:50:18 PM PDT 24
Finished Mar 12 12:50:19 PM PDT 24
Peak memory 195348 kb
Host smart-24ffa2bf-4c2a-421b-8a1b-c5e2f56878fb
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609426170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_c
m_ctrl_config_regwen.609426170
Directory /workspace/10.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3152771309
Short name T650
Test name
Test status
Simulation time 1222874616 ps
CPU time 2.14 seconds
Started Mar 12 12:50:12 PM PDT 24
Finished Mar 12 12:50:14 PM PDT 24
Peak memory 201264 kb
Host smart-93fc86b5-d0c9-45e1-9ff5-d3cc0649c72a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152771309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3152771309
Directory /workspace/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3722071631
Short name T345
Test name
Test status
Simulation time 869339483 ps
CPU time 3.07 seconds
Started Mar 12 12:50:12 PM PDT 24
Finished Mar 12 12:50:15 PM PDT 24
Peak memory 195876 kb
Host smart-6b7d67a6-3632-46ad-a2d1-abf40390283d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722071631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3722071631
Directory /workspace/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.3020452559
Short name T543
Test name
Test status
Simulation time 76428619 ps
CPU time 0.98 seconds
Started Mar 12 12:50:10 PM PDT 24
Finished Mar 12 12:50:11 PM PDT 24
Peak memory 195328 kb
Host smart-fd9f5852-a902-4b5b-b225-7f18b802d6ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020452559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3020452559
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.359207934
Short name T781
Test name
Test status
Simulation time 129451886 ps
CPU time 0.61 seconds
Started Mar 12 12:50:03 PM PDT 24
Finished Mar 12 12:50:04 PM PDT 24
Peak memory 195588 kb
Host smart-4aa80f35-9c24-4245-9034-0a2d8f183708
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359207934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.359207934
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_stress_all.3225427786
Short name T408
Test name
Test status
Simulation time 1666142336 ps
CPU time 2.98 seconds
Started Mar 12 12:50:20 PM PDT 24
Finished Mar 12 12:50:23 PM PDT 24
Peak memory 201036 kb
Host smart-3139c400-eab9-4011-8203-73e7f44ccd19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225427786 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.3225427786
Directory /workspace/10.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup_reset.218654725
Short name T253
Test name
Test status
Simulation time 347227173 ps
CPU time 1 seconds
Started Mar 12 12:50:15 PM PDT 24
Finished Mar 12 12:50:17 PM PDT 24
Peak memory 195564 kb
Host smart-3615094c-b1fb-46cf-90f5-9160dfe06ce0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218654725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.218654725
Directory /workspace/10.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.3613898677
Short name T532
Test name
Test status
Simulation time 147594863 ps
CPU time 0.78 seconds
Started Mar 12 12:50:13 PM PDT 24
Finished Mar 12 12:50:14 PM PDT 24
Peak memory 195308 kb
Host smart-4703d8a0-44ed-4a5a-9dac-a70082661a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613898677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.3613898677
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.3546013326
Short name T327
Test name
Test status
Simulation time 60826676 ps
CPU time 0.74 seconds
Started Mar 12 12:50:10 PM PDT 24
Finished Mar 12 12:50:11 PM PDT 24
Peak memory 195428 kb
Host smart-c2c8cca7-7d4d-4ec9-b570-4254acb725c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546013326 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_dis
able_rom_integrity_check.3546013326
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.3160034059
Short name T719
Test name
Test status
Simulation time 49727341 ps
CPU time 0.56 seconds
Started Mar 12 12:50:11 PM PDT 24
Finished Mar 12 12:50:12 PM PDT 24
Peak memory 195376 kb
Host smart-99e40cc4-4023-4d6f-8701-d3885fb2251e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160034059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.3160034059
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.3158349106
Short name T672
Test name
Test status
Simulation time 166379300 ps
CPU time 0.92 seconds
Started Mar 12 12:50:13 PM PDT 24
Finished Mar 12 12:50:14 PM PDT 24
Peak memory 195424 kb
Host smart-85d12789-0bdc-42b1-8656-7bfaf068285f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158349106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.3158349106
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.2944423520
Short name T537
Test name
Test status
Simulation time 68997990 ps
CPU time 0.59 seconds
Started Mar 12 12:50:10 PM PDT 24
Finished Mar 12 12:50:10 PM PDT 24
Peak memory 195296 kb
Host smart-1323b049-96df-434c-b899-38a0a301a657
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944423520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.2944423520
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.4145005603
Short name T394
Test name
Test status
Simulation time 41078663 ps
CPU time 0.62 seconds
Started Mar 12 12:50:10 PM PDT 24
Finished Mar 12 12:50:10 PM PDT 24
Peak memory 195328 kb
Host smart-8b8f41a3-1a60-4bff-b674-23d2a7a83af3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145005603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.4145005603
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.2638317260
Short name T410
Test name
Test status
Simulation time 63305090 ps
CPU time 0.69 seconds
Started Mar 12 12:50:13 PM PDT 24
Finished Mar 12 12:50:14 PM PDT 24
Peak memory 195900 kb
Host smart-9bd5bfdb-57e7-48df-94f1-adf89610ee96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638317260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_inval
id.2638317260
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.1458352081
Short name T522
Test name
Test status
Simulation time 95920608 ps
CPU time 0.9 seconds
Started Mar 12 12:50:07 PM PDT 24
Finished Mar 12 12:50:08 PM PDT 24
Peak memory 197840 kb
Host smart-261e823e-b7cc-4060-9327-2006a667fb7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458352081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.1458352081
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.3542296161
Short name T219
Test name
Test status
Simulation time 108400952 ps
CPU time 0.97 seconds
Started Mar 12 12:50:12 PM PDT 24
Finished Mar 12 12:50:13 PM PDT 24
Peak memory 205160 kb
Host smart-e05d1218-6268-4187-b8a2-db065c7fe13b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542296161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.3542296161
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1435789947
Short name T126
Test name
Test status
Simulation time 1281529718 ps
CPU time 2.2 seconds
Started Mar 12 12:50:11 PM PDT 24
Finished Mar 12 12:50:14 PM PDT 24
Peak memory 201240 kb
Host smart-cdfcd33f-756a-4aa0-8e03-a9d01dea5e8a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435789947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1435789947
Directory /workspace/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.114730341
Short name T391
Test name
Test status
Simulation time 2951823674 ps
CPU time 1.97 seconds
Started Mar 12 12:50:17 PM PDT 24
Finished Mar 12 12:50:19 PM PDT 24
Peak memory 200956 kb
Host smart-a28d044f-c2bb-4728-a3db-dfc59457efba
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114730341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.114730341
Directory /workspace/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.2534772962
Short name T274
Test name
Test status
Simulation time 94801488 ps
CPU time 0.87 seconds
Started Mar 12 12:50:09 PM PDT 24
Finished Mar 12 12:50:10 PM PDT 24
Peak memory 195332 kb
Host smart-3e3271d5-266b-4db1-8cb6-2820e5bda53e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534772962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2534772962
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.2440966978
Short name T317
Test name
Test status
Simulation time 122335561 ps
CPU time 0.63 seconds
Started Mar 12 12:50:10 PM PDT 24
Finished Mar 12 12:50:11 PM PDT 24
Peak memory 197492 kb
Host smart-44db9fdd-ea13-4bb0-afdc-373748279069
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440966978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.2440966978
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_stress_all.447893323
Short name T678
Test name
Test status
Simulation time 643457297 ps
CPU time 1.31 seconds
Started Mar 12 12:50:17 PM PDT 24
Finished Mar 12 12:50:19 PM PDT 24
Peak memory 195768 kb
Host smart-5d56a084-01e4-448f-916a-c36f3789d401
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447893323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.447893323
Directory /workspace/11.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup.2939650219
Short name T383
Test name
Test status
Simulation time 305264181 ps
CPU time 0.88 seconds
Started Mar 12 12:50:12 PM PDT 24
Finished Mar 12 12:50:13 PM PDT 24
Peak memory 195340 kb
Host smart-301b79b8-378e-4545-bf27-8aa1e4f99e51
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939650219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.2939650219
Directory /workspace/11.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup_reset.4140376321
Short name T728
Test name
Test status
Simulation time 366051943 ps
CPU time 1.24 seconds
Started Mar 12 12:50:15 PM PDT 24
Finished Mar 12 12:50:16 PM PDT 24
Peak memory 195892 kb
Host smart-657a8779-1764-45ec-8ff0-76ef46e2708d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140376321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.4140376321
Directory /workspace/11.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.3614327707
Short name T806
Test name
Test status
Simulation time 42731605 ps
CPU time 0.66 seconds
Started Mar 12 12:50:11 PM PDT 24
Finished Mar 12 12:50:12 PM PDT 24
Peak memory 195328 kb
Host smart-f9f3e1ad-5dd1-4e3f-9eac-aade95a12180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614327707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.3614327707
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.3684909116
Short name T596
Test name
Test status
Simulation time 61361556 ps
CPU time 0.82 seconds
Started Mar 12 12:50:11 PM PDT 24
Finished Mar 12 12:50:12 PM PDT 24
Peak memory 195428 kb
Host smart-fbc21e04-16e0-4e1c-8cd2-6f2453cca4d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684909116 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.3684909116
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.1494584127
Short name T724
Test name
Test status
Simulation time 30746262 ps
CPU time 0.58 seconds
Started Mar 12 12:50:15 PM PDT 24
Finished Mar 12 12:50:21 PM PDT 24
Peak memory 194504 kb
Host smart-65600386-9dc8-41b2-9293-238182c64747
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494584127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.1494584127
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.819935702
Short name T44
Test name
Test status
Simulation time 316798594 ps
CPU time 0.94 seconds
Started Mar 12 12:50:13 PM PDT 24
Finished Mar 12 12:50:14 PM PDT 24
Peak memory 195428 kb
Host smart-237a5c06-8aee-4b2e-a018-13ae9671c088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819935702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.819935702
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.1289349852
Short name T405
Test name
Test status
Simulation time 74519223 ps
CPU time 0.61 seconds
Started Mar 12 12:50:13 PM PDT 24
Finished Mar 12 12:50:14 PM PDT 24
Peak memory 195472 kb
Host smart-85902e03-74e1-4fdf-8ec8-f73687bfb7f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289349852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.1289349852
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.2476691387
Short name T228
Test name
Test status
Simulation time 59013137 ps
CPU time 0.6 seconds
Started Mar 12 12:50:07 PM PDT 24
Finished Mar 12 12:50:08 PM PDT 24
Peak memory 195420 kb
Host smart-9a7fb327-b0e3-4742-89a1-f6c1ea96a593
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476691387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.2476691387
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.2426057120
Short name T150
Test name
Test status
Simulation time 44402171 ps
CPU time 0.71 seconds
Started Mar 12 12:50:11 PM PDT 24
Finished Mar 12 12:50:12 PM PDT 24
Peak memory 195892 kb
Host smart-b17f4165-91e4-41ce-b19c-4fdcc26fe9d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426057120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.2426057120
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_wakeup_race.4017768349
Short name T390
Test name
Test status
Simulation time 26570043 ps
CPU time 0.64 seconds
Started Mar 12 12:50:12 PM PDT 24
Finished Mar 12 12:50:13 PM PDT 24
Peak memory 195376 kb
Host smart-a80a832a-7e4f-407e-8333-d61549821aea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017768349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_w
akeup_race.4017768349
Directory /workspace/12.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.874251416
Short name T540
Test name
Test status
Simulation time 46948896 ps
CPU time 0.81 seconds
Started Mar 12 12:50:06 PM PDT 24
Finished Mar 12 12:50:07 PM PDT 24
Peak memory 197664 kb
Host smart-6574afbe-1b37-449c-b1dc-c41cdec90e08
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874251416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.874251416
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.2066398269
Short name T594
Test name
Test status
Simulation time 102873942 ps
CPU time 0.9 seconds
Started Mar 12 12:50:11 PM PDT 24
Finished Mar 12 12:50:12 PM PDT 24
Peak memory 205020 kb
Host smart-e18c1d23-fb9f-443b-be37-064ce0967f0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066398269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.2066398269
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.4007716228
Short name T690
Test name
Test status
Simulation time 1031395769 ps
CPU time 1.02 seconds
Started Mar 12 12:50:14 PM PDT 24
Finished Mar 12 12:50:15 PM PDT 24
Peak memory 195456 kb
Host smart-a2394cb3-886d-447f-91e4-99195b3fa5fa
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007716228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_
cm_ctrl_config_regwen.4007716228
Directory /workspace/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1597550009
Short name T128
Test name
Test status
Simulation time 860583149 ps
CPU time 2.36 seconds
Started Mar 12 12:50:11 PM PDT 24
Finished Mar 12 12:50:13 PM PDT 24
Peak memory 201192 kb
Host smart-846205a5-ba7f-4f9c-a9f3-9986611f9e7e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597550009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1597550009
Directory /workspace/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2486254458
Short name T778
Test name
Test status
Simulation time 1491225716 ps
CPU time 2.09 seconds
Started Mar 12 12:50:11 PM PDT 24
Finished Mar 12 12:50:13 PM PDT 24
Peak memory 200920 kb
Host smart-30e90787-7227-41e5-84a5-6c177696ccae
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486254458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2486254458
Directory /workspace/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.775812774
Short name T298
Test name
Test status
Simulation time 168748422 ps
CPU time 0.88 seconds
Started Mar 12 12:50:10 PM PDT 24
Finished Mar 12 12:50:11 PM PDT 24
Peak memory 195332 kb
Host smart-bdb3830e-b4ca-49a1-8a52-2535a5f79398
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775812774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig_
mubi.775812774
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.3865525473
Short name T770
Test name
Test status
Simulation time 47522008 ps
CPU time 0.63 seconds
Started Mar 12 12:50:14 PM PDT 24
Finished Mar 12 12:50:15 PM PDT 24
Peak memory 195628 kb
Host smart-c3d16658-521e-487e-b7dd-cf034ed0d13f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865525473 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.3865525473
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup.3780252905
Short name T754
Test name
Test status
Simulation time 144549455 ps
CPU time 0.73 seconds
Started Mar 12 12:50:18 PM PDT 24
Finished Mar 12 12:50:19 PM PDT 24
Peak memory 195344 kb
Host smart-dcd441f7-d0b0-4f7a-975c-3063e4c50c56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780252905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.3780252905
Directory /workspace/12.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup_reset.3402785920
Short name T386
Test name
Test status
Simulation time 801984487 ps
CPU time 1.05 seconds
Started Mar 12 12:50:10 PM PDT 24
Finished Mar 12 12:50:11 PM PDT 24
Peak memory 199040 kb
Host smart-eaea9f9e-132e-4fa1-96e7-64c5010be7d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402785920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.3402785920
Directory /workspace/12.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.1926557789
Short name T501
Test name
Test status
Simulation time 31778845 ps
CPU time 0.75 seconds
Started Mar 12 12:50:13 PM PDT 24
Finished Mar 12 12:50:14 PM PDT 24
Peak memory 197720 kb
Host smart-6a4f2a0b-6a63-43fa-ae5e-325e5c0d5984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926557789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.1926557789
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.3739267513
Short name T305
Test name
Test status
Simulation time 184593798 ps
CPU time 0.66 seconds
Started Mar 12 12:50:10 PM PDT 24
Finished Mar 12 12:50:11 PM PDT 24
Peak memory 197624 kb
Host smart-ad7e124c-ebb4-43b4-9719-7f254795e203
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739267513 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis
able_rom_integrity_check.3739267513
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.305105552
Short name T414
Test name
Test status
Simulation time 28914609 ps
CPU time 0.63 seconds
Started Mar 12 12:50:13 PM PDT 24
Finished Mar 12 12:50:14 PM PDT 24
Peak memory 195336 kb
Host smart-5fc8069f-6865-40bd-96c4-249a619e8b61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305105552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst_
malfunc.305105552
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.2173215560
Short name T602
Test name
Test status
Simulation time 321268910 ps
CPU time 0.99 seconds
Started Mar 12 12:50:15 PM PDT 24
Finished Mar 12 12:50:16 PM PDT 24
Peak memory 195424 kb
Host smart-5f2d46d4-9a5c-4e8c-accb-e597cd02bd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173215560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.2173215560
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.3821368963
Short name T610
Test name
Test status
Simulation time 41467916 ps
CPU time 0.64 seconds
Started Mar 12 12:50:11 PM PDT 24
Finished Mar 12 12:50:12 PM PDT 24
Peak memory 195420 kb
Host smart-499524a0-5d8e-44f1-af43-d2858c6b7457
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821368963 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.3821368963
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.354888399
Short name T13
Test name
Test status
Simulation time 62522090 ps
CPU time 0.61 seconds
Started Mar 12 12:50:17 PM PDT 24
Finished Mar 12 12:50:18 PM PDT 24
Peak memory 195392 kb
Host smart-737b0feb-9c9c-4744-bc27-89533cd0641e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354888399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.354888399
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.1488567183
Short name T336
Test name
Test status
Simulation time 76128869 ps
CPU time 0.67 seconds
Started Mar 12 12:50:29 PM PDT 24
Finished Mar 12 12:50:30 PM PDT 24
Peak memory 195832 kb
Host smart-3e9ae6b9-2c7b-408c-bc5b-e72a65ef0956
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488567183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.1488567183
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.1412501733
Short name T591
Test name
Test status
Simulation time 86896977 ps
CPU time 0.69 seconds
Started Mar 12 12:50:19 PM PDT 24
Finished Mar 12 12:50:20 PM PDT 24
Peak memory 197668 kb
Host smart-9cbc296d-969d-4733-bda1-28edcbdecc4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412501733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.1412501733
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.2937834751
Short name T656
Test name
Test status
Simulation time 136357958 ps
CPU time 0.86 seconds
Started Mar 12 12:50:15 PM PDT 24
Finished Mar 12 12:50:16 PM PDT 24
Peak memory 205336 kb
Host smart-e708f28d-900b-43a8-be89-02409029f8a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937834751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.2937834751
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.770033860
Short name T416
Test name
Test status
Simulation time 72738728 ps
CPU time 0.62 seconds
Started Mar 12 12:50:12 PM PDT 24
Finished Mar 12 12:50:13 PM PDT 24
Peak memory 195448 kb
Host smart-91502df9-3699-4506-a7eb-b513a3c3fa2d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770033860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_c
m_ctrl_config_regwen.770033860
Directory /workspace/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2323262626
Short name T584
Test name
Test status
Simulation time 842545841 ps
CPU time 3.17 seconds
Started Mar 12 12:50:11 PM PDT 24
Finished Mar 12 12:50:15 PM PDT 24
Peak memory 200876 kb
Host smart-702cd21f-e052-4ceb-a4b8-72c0c9403fab
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323262626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2323262626
Directory /workspace/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1463020893
Short name T654
Test name
Test status
Simulation time 1042349687 ps
CPU time 2.08 seconds
Started Mar 12 12:50:11 PM PDT 24
Finished Mar 12 12:50:13 PM PDT 24
Peak memory 195852 kb
Host smart-61902fdd-fdb7-46f5-9434-971ae57911af
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463020893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1463020893
Directory /workspace/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.3822795071
Short name T213
Test name
Test status
Simulation time 69698289 ps
CPU time 0.93 seconds
Started Mar 12 12:50:11 PM PDT 24
Finished Mar 12 12:50:12 PM PDT 24
Peak memory 195364 kb
Host smart-aee4606b-6824-4499-8641-3ee9f4ec2599
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822795071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3822795071
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.2384540010
Short name T659
Test name
Test status
Simulation time 34793494 ps
CPU time 0.65 seconds
Started Mar 12 12:50:15 PM PDT 24
Finished Mar 12 12:50:16 PM PDT 24
Peak memory 195636 kb
Host smart-03553a2c-befd-4262-b173-8aa60b156ecf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384540010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.2384540010
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all.1908434277
Short name T688
Test name
Test status
Simulation time 1048540355 ps
CPU time 4.39 seconds
Started Mar 12 12:50:17 PM PDT 24
Finished Mar 12 12:50:22 PM PDT 24
Peak memory 195996 kb
Host smart-f6fad93e-ce0b-47bb-a2ee-6ebc460c37f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908434277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.1908434277
Directory /workspace/13.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup.3931619012
Short name T470
Test name
Test status
Simulation time 271673423 ps
CPU time 0.93 seconds
Started Mar 12 12:50:16 PM PDT 24
Finished Mar 12 12:50:17 PM PDT 24
Peak memory 195344 kb
Host smart-4da0221a-3f69-439c-9ab9-ce3914290f84
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931619012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.3931619012
Directory /workspace/13.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup_reset.202078586
Short name T153
Test name
Test status
Simulation time 373272585 ps
CPU time 0.79 seconds
Started Mar 12 12:50:11 PM PDT 24
Finished Mar 12 12:50:12 PM PDT 24
Peak memory 198020 kb
Host smart-f169a28a-1bc9-43de-a159-da52f7b95277
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202078586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.202078586
Directory /workspace/13.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.3613071833
Short name T195
Test name
Test status
Simulation time 72115730 ps
CPU time 0.66 seconds
Started Mar 12 12:50:13 PM PDT 24
Finished Mar 12 12:50:14 PM PDT 24
Peak memory 195360 kb
Host smart-b460f856-5911-4ec3-b56e-8ae68e737d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613071833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.3613071833
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.2253548582
Short name T757
Test name
Test status
Simulation time 143702649 ps
CPU time 0.65 seconds
Started Mar 12 12:50:18 PM PDT 24
Finished Mar 12 12:50:19 PM PDT 24
Peak memory 195288 kb
Host smart-45c14c1f-a80b-4b68-b08c-195fe6ae2beb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253548582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.2253548582
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.2550409540
Short name T285
Test name
Test status
Simulation time 34927672 ps
CPU time 0.59 seconds
Started Mar 12 12:50:13 PM PDT 24
Finished Mar 12 12:50:14 PM PDT 24
Peak memory 195332 kb
Host smart-2425e287-619e-47ed-a4ea-039f3c439a3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550409540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.2550409540
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.1750083599
Short name T225
Test name
Test status
Simulation time 161946885 ps
CPU time 0.91 seconds
Started Mar 12 12:50:13 PM PDT 24
Finished Mar 12 12:50:14 PM PDT 24
Peak memory 195316 kb
Host smart-80774b98-a093-482d-bafd-5e886d8c9489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750083599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.1750083599
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.1578484830
Short name T508
Test name
Test status
Simulation time 52576560 ps
CPU time 0.68 seconds
Started Mar 12 12:50:18 PM PDT 24
Finished Mar 12 12:50:18 PM PDT 24
Peak memory 195264 kb
Host smart-85d8fbd6-bc8a-42e0-9661-afaf6d50e7c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578484830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.1578484830
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.341084248
Short name T498
Test name
Test status
Simulation time 89987109 ps
CPU time 0.6 seconds
Started Mar 12 12:50:18 PM PDT 24
Finished Mar 12 12:50:18 PM PDT 24
Peak memory 195216 kb
Host smart-ed8dacbf-a3dc-44fb-a609-d140fdcac73d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341084248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.341084248
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.2781182659
Short name T396
Test name
Test status
Simulation time 77631365 ps
CPU time 0.69 seconds
Started Mar 12 12:50:17 PM PDT 24
Finished Mar 12 12:50:18 PM PDT 24
Peak memory 195896 kb
Host smart-ad396820-adeb-4f4b-97ad-45aa7b30ef33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781182659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval
id.2781182659
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_wakeup_race.923236647
Short name T588
Test name
Test status
Simulation time 178512490 ps
CPU time 0.77 seconds
Started Mar 12 12:50:15 PM PDT 24
Finished Mar 12 12:50:15 PM PDT 24
Peak memory 195380 kb
Host smart-d9d2eec8-bdb2-4970-b803-cf5464d738a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923236647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_wa
keup_race.923236647
Directory /workspace/14.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.545686016
Short name T365
Test name
Test status
Simulation time 52383125 ps
CPU time 0.7 seconds
Started Mar 12 12:50:17 PM PDT 24
Finished Mar 12 12:50:18 PM PDT 24
Peak memory 197496 kb
Host smart-56c85660-be58-4e3f-b0e0-db02b7bce5d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545686016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.545686016
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.1912331674
Short name T460
Test name
Test status
Simulation time 105075803 ps
CPU time 0.94 seconds
Started Mar 12 12:50:17 PM PDT 24
Finished Mar 12 12:50:18 PM PDT 24
Peak memory 205204 kb
Host smart-51488b43-6086-4c01-9551-c48c85e9b4a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912331674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.1912331674
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2834800386
Short name T376
Test name
Test status
Simulation time 974290626 ps
CPU time 2.32 seconds
Started Mar 12 12:50:09 PM PDT 24
Finished Mar 12 12:50:12 PM PDT 24
Peak memory 201136 kb
Host smart-1fe31122-9566-4f4e-b699-755c75343433
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834800386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2834800386
Directory /workspace/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3764496497
Short name T614
Test name
Test status
Simulation time 965831831 ps
CPU time 2.47 seconds
Started Mar 12 12:50:22 PM PDT 24
Finished Mar 12 12:50:25 PM PDT 24
Peak memory 199672 kb
Host smart-1ef7f16b-74c5-4038-8d71-ec0b63212297
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764496497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3764496497
Directory /workspace/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.1545913709
Short name T182
Test name
Test status
Simulation time 51682499 ps
CPU time 0.88 seconds
Started Mar 12 12:50:15 PM PDT 24
Finished Mar 12 12:50:16 PM PDT 24
Peak memory 195340 kb
Host smart-f6f27fa1-74a8-437c-a163-e47517cd9103
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545913709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1545913709
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.2252518671
Short name T290
Test name
Test status
Simulation time 30437020 ps
CPU time 0.68 seconds
Started Mar 12 12:50:10 PM PDT 24
Finished Mar 12 12:50:11 PM PDT 24
Peak memory 197768 kb
Host smart-c2dc404b-cf1b-4e77-b11b-c00e0f48d055
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252518671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.2252518671
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup.1484550417
Short name T155
Test name
Test status
Simulation time 68459798 ps
CPU time 0.76 seconds
Started Mar 12 12:50:15 PM PDT 24
Finished Mar 12 12:50:16 PM PDT 24
Peak memory 195384 kb
Host smart-9bd87e08-4cb0-43f2-a129-40eb325c5000
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484550417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.1484550417
Directory /workspace/14.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup_reset.3988096011
Short name T747
Test name
Test status
Simulation time 288940932 ps
CPU time 0.86 seconds
Started Mar 12 12:50:19 PM PDT 24
Finished Mar 12 12:50:20 PM PDT 24
Peak memory 199180 kb
Host smart-384a4f4e-0006-4751-90a5-bbd46e6b9c6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988096011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.3988096011
Directory /workspace/14.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.1795441872
Short name T741
Test name
Test status
Simulation time 20787176 ps
CPU time 0.67 seconds
Started Mar 12 12:50:27 PM PDT 24
Finished Mar 12 12:50:28 PM PDT 24
Peak memory 197524 kb
Host smart-67ca2887-0c46-4ee5-90c2-63cde14d52ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795441872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.1795441872
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.1383350051
Short name T291
Test name
Test status
Simulation time 56275447 ps
CPU time 0.78 seconds
Started Mar 12 12:50:21 PM PDT 24
Finished Mar 12 12:50:22 PM PDT 24
Peak memory 198156 kb
Host smart-eeb960c0-13ef-4bdb-840a-092390ceeb9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383350051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.1383350051
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.4265809160
Short name T472
Test name
Test status
Simulation time 38333257 ps
CPU time 0.58 seconds
Started Mar 12 12:50:18 PM PDT 24
Finished Mar 12 12:50:19 PM PDT 24
Peak memory 195380 kb
Host smart-098035eb-4184-40c2-87b9-380edc6e3e9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265809160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.4265809160
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.2755888081
Short name T292
Test name
Test status
Simulation time 488306845 ps
CPU time 0.97 seconds
Started Mar 12 12:50:17 PM PDT 24
Finished Mar 12 12:50:19 PM PDT 24
Peak memory 195396 kb
Host smart-8604a4bf-7b83-4901-8052-1bd2476b6372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755888081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.2755888081
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.1071299667
Short name T496
Test name
Test status
Simulation time 73671673 ps
CPU time 0.61 seconds
Started Mar 12 12:50:24 PM PDT 24
Finished Mar 12 12:50:25 PM PDT 24
Peak memory 195388 kb
Host smart-1b1f0a71-1874-4543-8056-5292ad810fb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071299667 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.1071299667
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.23763744
Short name T628
Test name
Test status
Simulation time 34025296 ps
CPU time 0.61 seconds
Started Mar 12 12:50:17 PM PDT 24
Finished Mar 12 12:50:18 PM PDT 24
Peak memory 195368 kb
Host smart-ef109b00-90dc-4b57-add2-1eb83d269605
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23763744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.23763744
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.3841520321
Short name T795
Test name
Test status
Simulation time 72032326 ps
CPU time 0.66 seconds
Started Mar 12 12:50:18 PM PDT 24
Finished Mar 12 12:50:19 PM PDT 24
Peak memory 195864 kb
Host smart-586bbe26-12e2-4c2a-a5b7-a6712b80eaee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841520321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.3841520321
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_wakeup_race.1053711559
Short name T603
Test name
Test status
Simulation time 397203080 ps
CPU time 1 seconds
Started Mar 12 12:50:15 PM PDT 24
Finished Mar 12 12:50:16 PM PDT 24
Peak memory 195312 kb
Host smart-6e83a9ee-9006-4b5a-a8cb-24d100c3f895
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053711559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_w
akeup_race.1053711559
Directory /workspace/15.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.608715861
Short name T852
Test name
Test status
Simulation time 37302741 ps
CPU time 0.77 seconds
Started Mar 12 12:50:22 PM PDT 24
Finished Mar 12 12:50:23 PM PDT 24
Peak memory 197864 kb
Host smart-ec2a59b4-c5af-4999-9cb6-b69f22477bde
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608715861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.608715861
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.865941871
Short name T829
Test name
Test status
Simulation time 126146116 ps
CPU time 0.86 seconds
Started Mar 12 12:50:12 PM PDT 24
Finished Mar 12 12:50:13 PM PDT 24
Peak memory 205208 kb
Host smart-fd6eb377-bd2b-4282-bca1-3279b6ed64a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865941871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.865941871
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1418985509
Short name T716
Test name
Test status
Simulation time 779554369 ps
CPU time 3.15 seconds
Started Mar 12 12:50:13 PM PDT 24
Finished Mar 12 12:50:16 PM PDT 24
Peak memory 201092 kb
Host smart-65bc53c3-7e19-4728-9232-133c57d658d6
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418985509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1418985509
Directory /workspace/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.618698195
Short name T272
Test name
Test status
Simulation time 1421491107 ps
CPU time 2.18 seconds
Started Mar 12 12:50:17 PM PDT 24
Finished Mar 12 12:50:24 PM PDT 24
Peak memory 195992 kb
Host smart-e521c90b-05bf-4004-803a-e2d1b8092dcf
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618698195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.618698195
Directory /workspace/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.790679465
Short name T318
Test name
Test status
Simulation time 66911100 ps
CPU time 0.84 seconds
Started Mar 12 12:50:16 PM PDT 24
Finished Mar 12 12:50:17 PM PDT 24
Peak memory 195344 kb
Host smart-16c2f28b-1528-47f5-8fe9-55ecd9f51496
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790679465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_
mubi.790679465
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.3583980411
Short name T160
Test name
Test status
Simulation time 32961808 ps
CPU time 0.77 seconds
Started Mar 12 12:50:15 PM PDT 24
Finished Mar 12 12:50:16 PM PDT 24
Peak memory 197592 kb
Host smart-112a3964-3a87-47ab-b437-21a1322ef976
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583980411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.3583980411
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_stress_all.600795406
Short name T709
Test name
Test status
Simulation time 444852056 ps
CPU time 1.08 seconds
Started Mar 12 12:50:09 PM PDT 24
Finished Mar 12 12:50:10 PM PDT 24
Peak memory 195504 kb
Host smart-836925f1-14de-4132-bbb9-6b41e2c338a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600795406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.600795406
Directory /workspace/15.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup_reset.482173073
Short name T117
Test name
Test status
Simulation time 821282024 ps
CPU time 1.06 seconds
Started Mar 12 12:50:24 PM PDT 24
Finished Mar 12 12:50:26 PM PDT 24
Peak memory 199204 kb
Host smart-7d65e444-19a6-4141-99c5-191e4c67a660
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482173073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.482173073
Directory /workspace/15.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.2010044464
Short name T442
Test name
Test status
Simulation time 18286955 ps
CPU time 0.66 seconds
Started Mar 12 12:50:13 PM PDT 24
Finished Mar 12 12:50:14 PM PDT 24
Peak memory 195332 kb
Host smart-18955e0e-2ae6-4ca1-b22b-c02b7c55896f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010044464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.2010044464
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.338724167
Short name T850
Test name
Test status
Simulation time 57983229 ps
CPU time 0.81 seconds
Started Mar 12 12:50:10 PM PDT 24
Finished Mar 12 12:50:11 PM PDT 24
Peak memory 197544 kb
Host smart-4ce6bc64-ad08-4959-9d45-54dda6c8e5e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338724167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_disa
ble_rom_integrity_check.338724167
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.1894678648
Short name T440
Test name
Test status
Simulation time 38391701 ps
CPU time 0.62 seconds
Started Mar 12 12:50:14 PM PDT 24
Finished Mar 12 12:50:14 PM PDT 24
Peak memory 195336 kb
Host smart-080b641b-addf-402f-9fee-31577a36ef39
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894678648 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.1894678648
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.4119458291
Short name T14
Test name
Test status
Simulation time 165561788 ps
CPU time 0.95 seconds
Started Mar 12 12:50:12 PM PDT 24
Finished Mar 12 12:50:13 PM PDT 24
Peak memory 195396 kb
Host smart-693e527f-a812-48e6-9d28-06fdff5f5726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119458291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.4119458291
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.841531809
Short name T620
Test name
Test status
Simulation time 49401057 ps
CPU time 0.57 seconds
Started Mar 12 12:50:22 PM PDT 24
Finished Mar 12 12:50:23 PM PDT 24
Peak memory 195252 kb
Host smart-7b9e8b47-1948-43e5-b395-01ad823a87d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841531809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.841531809
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.3760914944
Short name T657
Test name
Test status
Simulation time 25888506 ps
CPU time 0.62 seconds
Started Mar 12 12:50:14 PM PDT 24
Finished Mar 12 12:50:15 PM PDT 24
Peak memory 195396 kb
Host smart-4f1588e5-ea42-42ca-a71d-4f4b1211d8e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760914944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.3760914944
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.666423229
Short name T426
Test name
Test status
Simulation time 45227350 ps
CPU time 0.7 seconds
Started Mar 12 12:50:15 PM PDT 24
Finished Mar 12 12:50:15 PM PDT 24
Peak memory 195872 kb
Host smart-02eea6c9-ad86-4bef-9801-41f252f4cbe6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666423229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_invali
d.666423229
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.1599395810
Short name T801
Test name
Test status
Simulation time 53285719 ps
CPU time 0.66 seconds
Started Mar 12 12:50:27 PM PDT 24
Finished Mar 12 12:50:28 PM PDT 24
Peak memory 195356 kb
Host smart-a684fd91-445f-4fa7-b283-f9321f3fc004
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599395810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.1599395810
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.2269640738
Short name T252
Test name
Test status
Simulation time 96380230 ps
CPU time 0.9 seconds
Started Mar 12 12:50:15 PM PDT 24
Finished Mar 12 12:50:16 PM PDT 24
Peak memory 205372 kb
Host smart-d1bd3da9-cd07-411c-94d6-d811dd118ddf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269640738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.2269640738
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.1234362983
Short name T593
Test name
Test status
Simulation time 215557771 ps
CPU time 1 seconds
Started Mar 12 12:50:16 PM PDT 24
Finished Mar 12 12:50:17 PM PDT 24
Peak memory 195232 kb
Host smart-b31d4817-301b-4272-9008-9cf096cc33fc
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234362983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_
cm_ctrl_config_regwen.1234362983
Directory /workspace/16.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2996892643
Short name T491
Test name
Test status
Simulation time 1307818874 ps
CPU time 2.23 seconds
Started Mar 12 12:50:21 PM PDT 24
Finished Mar 12 12:50:24 PM PDT 24
Peak memory 195964 kb
Host smart-80a83c25-e0cb-434e-b9d9-3c314e45e08a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996892643 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2996892643
Directory /workspace/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.796680087
Short name T400
Test name
Test status
Simulation time 70406210 ps
CPU time 0.81 seconds
Started Mar 12 12:50:22 PM PDT 24
Finished Mar 12 12:50:23 PM PDT 24
Peak memory 195256 kb
Host smart-c8f71ddc-53de-45a1-b06f-07dab04da077
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796680087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig_
mubi.796680087
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.1549232233
Short name T461
Test name
Test status
Simulation time 34104105 ps
CPU time 0.68 seconds
Started Mar 12 12:50:25 PM PDT 24
Finished Mar 12 12:50:26 PM PDT 24
Peak memory 195588 kb
Host smart-efa422c5-4fd5-4593-9951-cf9a5f62a7a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549232233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.1549232233
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_stress_all.1326954089
Short name T683
Test name
Test status
Simulation time 1297768201 ps
CPU time 2.18 seconds
Started Mar 12 12:50:27 PM PDT 24
Finished Mar 12 12:50:29 PM PDT 24
Peak memory 195988 kb
Host smart-70853469-715e-46fc-b573-e4c2254b72bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326954089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.1326954089
Directory /workspace/16.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup.3862350343
Short name T114
Test name
Test status
Simulation time 102826720 ps
CPU time 0.67 seconds
Started Mar 12 12:50:15 PM PDT 24
Finished Mar 12 12:50:16 PM PDT 24
Peak memory 195376 kb
Host smart-b8bdfa04-efdd-4d16-beb1-54012f6dfa2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862350343 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup.3862350343
Directory /workspace/16.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup_reset.3447394356
Short name T616
Test name
Test status
Simulation time 36842717 ps
CPU time 0.65 seconds
Started Mar 12 12:50:22 PM PDT 24
Finished Mar 12 12:50:23 PM PDT 24
Peak memory 195416 kb
Host smart-6d657e64-2714-4edb-9106-e6c7bd3971d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447394356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.3447394356
Directory /workspace/16.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.1521358541
Short name T475
Test name
Test status
Simulation time 64527950 ps
CPU time 0.76 seconds
Started Mar 12 12:50:17 PM PDT 24
Finished Mar 12 12:50:18 PM PDT 24
Peak memory 198820 kb
Host smart-efaf56f4-e7ea-4d80-a385-e0864d25147c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521358541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.1521358541
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.3580277364
Short name T237
Test name
Test status
Simulation time 53303635 ps
CPU time 0.81 seconds
Started Mar 12 12:50:48 PM PDT 24
Finished Mar 12 12:50:49 PM PDT 24
Peak memory 196648 kb
Host smart-0dec364e-f2d9-4cf4-a485-ea5e9d41f77f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580277364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.3580277364
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.3183494563
Short name T193
Test name
Test status
Simulation time 31097477 ps
CPU time 0.7 seconds
Started Mar 12 12:50:14 PM PDT 24
Finished Mar 12 12:50:15 PM PDT 24
Peak memory 195312 kb
Host smart-21d75e16-2759-42f2-a9a6-d7c54979fe3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183494563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst
_malfunc.3183494563
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.799732184
Short name T837
Test name
Test status
Simulation time 607743270 ps
CPU time 1.04 seconds
Started Mar 12 12:50:20 PM PDT 24
Finished Mar 12 12:50:21 PM PDT 24
Peak memory 195384 kb
Host smart-0141d160-ed06-4e5c-9128-a50af4b40510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799732184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.799732184
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.1577800277
Short name T429
Test name
Test status
Simulation time 42095805 ps
CPU time 0.63 seconds
Started Mar 12 12:50:20 PM PDT 24
Finished Mar 12 12:50:21 PM PDT 24
Peak memory 195412 kb
Host smart-a0435b2a-1a84-43a4-b841-9e1624a5231e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577800277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.1577800277
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.403679229
Short name T176
Test name
Test status
Simulation time 122266416 ps
CPU time 0.61 seconds
Started Mar 12 12:50:21 PM PDT 24
Finished Mar 12 12:50:22 PM PDT 24
Peak memory 195388 kb
Host smart-a8ecf49d-e93d-4302-b333-18de623c4bec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403679229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.403679229
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.3197491563
Short name T776
Test name
Test status
Simulation time 167326327 ps
CPU time 0.63 seconds
Started Mar 12 12:50:18 PM PDT 24
Finished Mar 12 12:50:19 PM PDT 24
Peak memory 195944 kb
Host smart-ab0c4a78-63f5-4662-83f5-2a76488b6dbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197491563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.3197491563
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.883466048
Short name T407
Test name
Test status
Simulation time 89798233 ps
CPU time 0.76 seconds
Started Mar 12 12:50:19 PM PDT 24
Finished Mar 12 12:50:20 PM PDT 24
Peak memory 197684 kb
Host smart-5a6b28c4-a5b0-4f4c-bb01-142d4664bc37
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883466048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.883466048
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.69526588
Short name T403
Test name
Test status
Simulation time 115218172 ps
CPU time 0.8 seconds
Started Mar 12 12:50:22 PM PDT 24
Finished Mar 12 12:50:23 PM PDT 24
Peak memory 205244 kb
Host smart-88fd3178-c6fe-405c-b4d2-d2c06372d832
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69526588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.69526588
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.965955148
Short name T827
Test name
Test status
Simulation time 1122365392 ps
CPU time 2.39 seconds
Started Mar 12 12:50:17 PM PDT 24
Finished Mar 12 12:50:19 PM PDT 24
Peak memory 201096 kb
Host smart-419aa6b3-0112-48c0-9223-cabcf6ce5aa9
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965955148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.965955148
Directory /workspace/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2702854672
Short name T545
Test name
Test status
Simulation time 990262347 ps
CPU time 2.09 seconds
Started Mar 12 12:50:18 PM PDT 24
Finished Mar 12 12:50:20 PM PDT 24
Peak memory 195720 kb
Host smart-ea2b9d20-3090-47ec-8984-1433747fe917
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702854672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2702854672
Directory /workspace/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.886157744
Short name T521
Test name
Test status
Simulation time 166054788 ps
CPU time 0.86 seconds
Started Mar 12 12:50:14 PM PDT 24
Finished Mar 12 12:50:15 PM PDT 24
Peak memory 195376 kb
Host smart-36b60116-3305-4a8c-9192-59d7182c09aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886157744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig_
mubi.886157744
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.250908900
Short name T342
Test name
Test status
Simulation time 31799148 ps
CPU time 0.67 seconds
Started Mar 12 12:50:19 PM PDT 24
Finished Mar 12 12:50:20 PM PDT 24
Peak memory 195620 kb
Host smart-1caae3b2-406f-4824-bbf7-c5de812c27be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250908900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.250908900
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup_reset.1821836211
Short name T685
Test name
Test status
Simulation time 90060317 ps
CPU time 0.63 seconds
Started Mar 12 12:50:18 PM PDT 24
Finished Mar 12 12:50:18 PM PDT 24
Peak memory 195384 kb
Host smart-28d91a64-8bdc-45de-a142-009527f72a9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821836211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.1821836211
Directory /workspace/17.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.2937794006
Short name T818
Test name
Test status
Simulation time 30032260 ps
CPU time 0.65 seconds
Started Mar 12 12:50:21 PM PDT 24
Finished Mar 12 12:50:22 PM PDT 24
Peak memory 195356 kb
Host smart-2a78932e-c711-49c1-b234-bcc67a73ca52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937794006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.2937794006
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.3460345231
Short name T669
Test name
Test status
Simulation time 66465582 ps
CPU time 0.69 seconds
Started Mar 12 12:50:23 PM PDT 24
Finished Mar 12 12:50:24 PM PDT 24
Peak memory 197620 kb
Host smart-6034c31a-0c6c-4b04-b26c-4a6539984b78
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460345231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.3460345231
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.521552809
Short name T720
Test name
Test status
Simulation time 30563765 ps
CPU time 0.64 seconds
Started Mar 12 12:50:32 PM PDT 24
Finished Mar 12 12:50:34 PM PDT 24
Peak memory 195320 kb
Host smart-971ff98b-db94-469b-9f1b-621f0dd57d7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521552809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst_
malfunc.521552809
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.3638212116
Short name T800
Test name
Test status
Simulation time 162632015 ps
CPU time 0.96 seconds
Started Mar 12 12:50:27 PM PDT 24
Finished Mar 12 12:50:28 PM PDT 24
Peak memory 195404 kb
Host smart-80bd7e0f-a183-48f9-a902-625fb4c36d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638212116 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.3638212116
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.4270422026
Short name T47
Test name
Test status
Simulation time 52002249 ps
CPU time 0.56 seconds
Started Mar 12 12:50:23 PM PDT 24
Finished Mar 12 12:50:24 PM PDT 24
Peak memory 195436 kb
Host smart-9c6f43ac-5a97-4505-ae62-761052161498
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270422026 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.4270422026
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.1005550347
Short name T548
Test name
Test status
Simulation time 78364077 ps
CPU time 0.72 seconds
Started Mar 12 12:50:30 PM PDT 24
Finished Mar 12 12:50:31 PM PDT 24
Peak memory 195912 kb
Host smart-6ea71b48-3ed0-4355-a110-15e6c8634370
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005550347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_inval
id.1005550347
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_wakeup_race.3984954628
Short name T549
Test name
Test status
Simulation time 109637460 ps
CPU time 0.69 seconds
Started Mar 12 12:50:16 PM PDT 24
Finished Mar 12 12:50:17 PM PDT 24
Peak memory 195308 kb
Host smart-2c88607b-4ba0-420b-a062-0b08306a959a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984954628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_w
akeup_race.3984954628
Directory /workspace/18.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.3635207658
Short name T674
Test name
Test status
Simulation time 75624224 ps
CPU time 0.89 seconds
Started Mar 12 12:50:12 PM PDT 24
Finished Mar 12 12:50:13 PM PDT 24
Peak memory 197768 kb
Host smart-e3a32ede-5e3c-4cce-ad66-759d279368e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635207658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.3635207658
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.1194038366
Short name T444
Test name
Test status
Simulation time 229531079 ps
CPU time 0.77 seconds
Started Mar 12 12:50:28 PM PDT 24
Finished Mar 12 12:50:29 PM PDT 24
Peak memory 205876 kb
Host smart-11254d1d-f997-432a-a376-a384bbff84e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194038366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.1194038366
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3598017556
Short name T561
Test name
Test status
Simulation time 1068233218 ps
CPU time 2.17 seconds
Started Mar 12 12:50:21 PM PDT 24
Finished Mar 12 12:50:28 PM PDT 24
Peak memory 200948 kb
Host smart-38d80e4a-acea-4201-861f-75d1d653dab3
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598017556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3598017556
Directory /workspace/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.473575320
Short name T369
Test name
Test status
Simulation time 925819774 ps
CPU time 2.98 seconds
Started Mar 12 12:50:21 PM PDT 24
Finished Mar 12 12:50:29 PM PDT 24
Peak memory 195864 kb
Host smart-b88db5ec-e010-4384-bc16-2e2a66f28e5c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473575320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.473575320
Directory /workspace/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.962662596
Short name T188
Test name
Test status
Simulation time 69122455 ps
CPU time 0.84 seconds
Started Mar 12 12:50:08 PM PDT 24
Finished Mar 12 12:50:10 PM PDT 24
Peak memory 195332 kb
Host smart-cd6a5ebd-3402-41dc-845e-791bbf2c6018
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962662596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig_
mubi.962662596
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.337446870
Short name T634
Test name
Test status
Simulation time 53051500 ps
CPU time 0.67 seconds
Started Mar 12 12:50:18 PM PDT 24
Finished Mar 12 12:50:19 PM PDT 24
Peak memory 195640 kb
Host smart-b9121c7e-d8e3-4a10-8a28-a1b4800cf6d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337446870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.337446870
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup.1517263055
Short name T445
Test name
Test status
Simulation time 91421395 ps
CPU time 0.62 seconds
Started Mar 12 12:50:15 PM PDT 24
Finished Mar 12 12:50:16 PM PDT 24
Peak memory 194468 kb
Host smart-6ea9ea90-e269-466d-91c1-1d15e35d7ea3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517263055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.1517263055
Directory /workspace/18.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup_reset.3249827396
Short name T306
Test name
Test status
Simulation time 324942729 ps
CPU time 1.01 seconds
Started Mar 12 12:50:21 PM PDT 24
Finished Mar 12 12:50:22 PM PDT 24
Peak memory 198172 kb
Host smart-aea61677-93fd-4d1d-9703-e5b9eab8a1fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249827396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.3249827396
Directory /workspace/18.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.3949313524
Short name T777
Test name
Test status
Simulation time 28087539 ps
CPU time 0.66 seconds
Started Mar 12 12:50:17 PM PDT 24
Finished Mar 12 12:50:17 PM PDT 24
Peak memory 197564 kb
Host smart-080cfec1-4ba3-4e47-9a5b-2e27ed8a5cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949313524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.3949313524
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.1974343224
Short name T570
Test name
Test status
Simulation time 68875947 ps
CPU time 0.89 seconds
Started Mar 12 12:50:48 PM PDT 24
Finished Mar 12 12:50:49 PM PDT 24
Peak memory 195356 kb
Host smart-30efd430-f456-45cb-b7b7-17f02a516494
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974343224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.1974343224
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.579873782
Short name T146
Test name
Test status
Simulation time 30692863 ps
CPU time 0.63 seconds
Started Mar 12 12:50:35 PM PDT 24
Finished Mar 12 12:50:36 PM PDT 24
Peak memory 195360 kb
Host smart-89fe00b2-a0ed-4123-9e3d-4d439e237f3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579873782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst_
malfunc.579873782
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.962273038
Short name T83
Test name
Test status
Simulation time 1005242794 ps
CPU time 0.98 seconds
Started Mar 12 12:50:29 PM PDT 24
Finished Mar 12 12:50:30 PM PDT 24
Peak memory 195408 kb
Host smart-1bf3be5b-d0e6-4307-b318-2dce0619780f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962273038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.962273038
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.1634160189
Short name T841
Test name
Test status
Simulation time 54616955 ps
CPU time 0.71 seconds
Started Mar 12 12:50:27 PM PDT 24
Finished Mar 12 12:50:28 PM PDT 24
Peak memory 195424 kb
Host smart-cb59043e-eb66-45f8-92be-67af633ea33c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634160189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.1634160189
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.1038396108
Short name T337
Test name
Test status
Simulation time 52867157 ps
CPU time 0.6 seconds
Started Mar 12 12:50:48 PM PDT 24
Finished Mar 12 12:50:49 PM PDT 24
Peak memory 195392 kb
Host smart-8312a294-28ff-4881-b4f7-46e9493efe71
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038396108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.1038396108
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.3095171693
Short name T729
Test name
Test status
Simulation time 44901506 ps
CPU time 0.7 seconds
Started Mar 12 12:50:38 PM PDT 24
Finished Mar 12 12:50:39 PM PDT 24
Peak memory 195820 kb
Host smart-f9bb11bb-4e80-49c8-a7ad-31dc17c42463
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095171693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.3095171693
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_wakeup_race.430182034
Short name T203
Test name
Test status
Simulation time 80949356 ps
CPU time 0.72 seconds
Started Mar 12 12:50:44 PM PDT 24
Finished Mar 12 12:50:45 PM PDT 24
Peak memory 195384 kb
Host smart-93212165-52e1-41ae-b4c1-39c1c2a69127
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430182034 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_wa
keup_race.430182034
Directory /workspace/19.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.2127809204
Short name T340
Test name
Test status
Simulation time 28216726 ps
CPU time 0.7 seconds
Started Mar 12 12:50:47 PM PDT 24
Finished Mar 12 12:50:47 PM PDT 24
Peak memory 197552 kb
Host smart-64ce5043-e099-4225-b00a-32f9834469a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127809204 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.2127809204
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.966125783
Short name T518
Test name
Test status
Simulation time 152384092 ps
CPU time 0.81 seconds
Started Mar 12 12:50:33 PM PDT 24
Finished Mar 12 12:50:34 PM PDT 24
Peak memory 205228 kb
Host smart-d8733aa6-b2a2-40b6-b13d-90167e98a927
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966125783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.966125783
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.3191112417
Short name T768
Test name
Test status
Simulation time 150467810 ps
CPU time 1.02 seconds
Started Mar 12 12:50:26 PM PDT 24
Finished Mar 12 12:50:27 PM PDT 24
Peak memory 195380 kb
Host smart-2df4dd21-72ec-4218-9528-b68c858dbc62
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191112417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_
cm_ctrl_config_regwen.3191112417
Directory /workspace/19.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1022310486
Short name T25
Test name
Test status
Simulation time 1155502806 ps
CPU time 1.88 seconds
Started Mar 12 12:50:23 PM PDT 24
Finished Mar 12 12:50:25 PM PDT 24
Peak memory 201136 kb
Host smart-a86d9355-2bcc-4c2a-9d43-8869c324d9c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022310486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1022310486
Directory /workspace/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2157143057
Short name T39
Test name
Test status
Simulation time 900825682 ps
CPU time 2.94 seconds
Started Mar 12 12:50:19 PM PDT 24
Finished Mar 12 12:50:22 PM PDT 24
Peak memory 195820 kb
Host smart-06a1180d-68ed-45f5-a318-5553feb0b87e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157143057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2157143057
Directory /workspace/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.3551074334
Short name T750
Test name
Test status
Simulation time 54805525 ps
CPU time 0.89 seconds
Started Mar 12 12:50:24 PM PDT 24
Finished Mar 12 12:50:25 PM PDT 24
Peak memory 195312 kb
Host smart-6ff2a8a0-fad2-4ade-a4c0-3c87637f0780
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551074334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3551074334
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.178172941
Short name T861
Test name
Test status
Simulation time 40226518 ps
CPU time 0.64 seconds
Started Mar 12 12:50:27 PM PDT 24
Finished Mar 12 12:50:27 PM PDT 24
Peak memory 195604 kb
Host smart-0d15fb57-6b4a-4c01-a04f-d86cfe66beb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178172941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.178172941
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup.3094484211
Short name T520
Test name
Test status
Simulation time 179415903 ps
CPU time 0.74 seconds
Started Mar 12 12:50:30 PM PDT 24
Finished Mar 12 12:50:31 PM PDT 24
Peak memory 195324 kb
Host smart-5bc85236-1041-42d8-aeb6-7fcedf4d8bec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094484211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.3094484211
Directory /workspace/19.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup_reset.2810592674
Short name T464
Test name
Test status
Simulation time 293445172 ps
CPU time 1.03 seconds
Started Mar 12 12:50:35 PM PDT 24
Finished Mar 12 12:50:36 PM PDT 24
Peak memory 199060 kb
Host smart-c7e3506e-9294-4a47-b219-58074345f279
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810592674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.2810592674
Directory /workspace/19.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.1767879506
Short name T649
Test name
Test status
Simulation time 16731905 ps
CPU time 0.63 seconds
Started Mar 12 12:49:32 PM PDT 24
Finished Mar 12 12:49:33 PM PDT 24
Peak memory 197436 kb
Host smart-9fdc44cf-5d43-499f-a52d-ab75d0a4659d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767879506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.1767879506
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.1595897110
Short name T209
Test name
Test status
Simulation time 294545384 ps
CPU time 0.67 seconds
Started Mar 12 12:49:31 PM PDT 24
Finished Mar 12 12:49:32 PM PDT 24
Peak memory 195460 kb
Host smart-fc52a1ef-581c-42d2-b503-14e9c9d2b60f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595897110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.1595897110
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.3183866631
Short name T288
Test name
Test status
Simulation time 28434963 ps
CPU time 0.62 seconds
Started Mar 12 12:49:30 PM PDT 24
Finished Mar 12 12:49:31 PM PDT 24
Peak memory 195308 kb
Host smart-719173e6-6cc0-4c84-b53a-5675f5782063
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183866631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.3183866631
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.3779029959
Short name T163
Test name
Test status
Simulation time 319541201 ps
CPU time 0.94 seconds
Started Mar 12 12:49:34 PM PDT 24
Finished Mar 12 12:49:35 PM PDT 24
Peak memory 195416 kb
Host smart-f6be23d4-27b3-41cd-8149-85fb05034d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779029959 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.3779029959
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.1505757931
Short name T20
Test name
Test status
Simulation time 39797400 ps
CPU time 0.59 seconds
Started Mar 12 12:49:35 PM PDT 24
Finished Mar 12 12:49:36 PM PDT 24
Peak memory 195364 kb
Host smart-c7e23736-1b69-4a93-a92f-1137fc536c4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505757931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.1505757931
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.2356068256
Short name T526
Test name
Test status
Simulation time 70178883 ps
CPU time 0.61 seconds
Started Mar 12 12:49:36 PM PDT 24
Finished Mar 12 12:49:36 PM PDT 24
Peak memory 195224 kb
Host smart-502a386f-8fc7-4952-9921-95d5ee6af059
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356068256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.2356068256
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.2687696434
Short name T157
Test name
Test status
Simulation time 44917415 ps
CPU time 0.68 seconds
Started Mar 12 12:49:29 PM PDT 24
Finished Mar 12 12:49:30 PM PDT 24
Peak memory 195892 kb
Host smart-1ebc902d-abfd-48e4-a04f-e1a3e96602fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687696434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.2687696434
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_wakeup_race.905150539
Short name T417
Test name
Test status
Simulation time 69022329 ps
CPU time 0.7 seconds
Started Mar 12 12:49:33 PM PDT 24
Finished Mar 12 12:49:34 PM PDT 24
Peak memory 195348 kb
Host smart-a801774f-8510-4a7d-b1ae-156fdf1870d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905150539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wak
eup_race.905150539
Directory /workspace/2.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.2586914967
Short name T226
Test name
Test status
Simulation time 110967580 ps
CPU time 0.77 seconds
Started Mar 12 12:49:35 PM PDT 24
Finished Mar 12 12:49:35 PM PDT 24
Peak memory 197604 kb
Host smart-f60eb210-34dc-4ee4-a650-01a9cfd619b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586914967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.2586914967
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.3483873240
Short name T782
Test name
Test status
Simulation time 153773750 ps
CPU time 0.8 seconds
Started Mar 12 12:49:35 PM PDT 24
Finished Mar 12 12:49:36 PM PDT 24
Peak memory 205228 kb
Host smart-300f475d-ade8-43e8-be4c-780f97dfaaf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483873240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.3483873240
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.1334180398
Short name T5
Test name
Test status
Simulation time 303962603 ps
CPU time 1.38 seconds
Started Mar 12 12:49:31 PM PDT 24
Finished Mar 12 12:49:32 PM PDT 24
Peak memory 214336 kb
Host smart-ea9b065b-f711-450d-9d35-f500bb325e4d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334180398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.1334180398
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.101434555
Short name T235
Test name
Test status
Simulation time 420025390 ps
CPU time 1.14 seconds
Started Mar 12 12:49:30 PM PDT 24
Finished Mar 12 12:49:31 PM PDT 24
Peak memory 195536 kb
Host smart-5918405e-2a90-4a87-bae8-35637286b2e5
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101434555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm
_ctrl_config_regwen.101434555
Directory /workspace/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4260022138
Short name T359
Test name
Test status
Simulation time 1162064296 ps
CPU time 2.16 seconds
Started Mar 12 12:49:32 PM PDT 24
Finished Mar 12 12:49:34 PM PDT 24
Peak memory 201200 kb
Host smart-d2ad77b3-71fc-4e93-a719-f0df1629e903
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260022138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4260022138
Directory /workspace/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1693052763
Short name T816
Test name
Test status
Simulation time 1155354623 ps
CPU time 2.24 seconds
Started Mar 12 12:49:32 PM PDT 24
Finished Mar 12 12:49:35 PM PDT 24
Peak memory 195860 kb
Host smart-0e4975c2-e60a-4a6e-870f-7babc5e2a392
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693052763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1693052763
Directory /workspace/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1083984887
Short name T29
Test name
Test status
Simulation time 54710778 ps
CPU time 0.86 seconds
Started Mar 12 12:49:31 PM PDT 24
Finished Mar 12 12:49:32 PM PDT 24
Peak memory 195376 kb
Host smart-96bc8b5c-2085-4377-8c9b-e47a31655bcf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083984887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1083984887
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.3423969097
Short name T732
Test name
Test status
Simulation time 38565839 ps
CPU time 0.68 seconds
Started Mar 12 12:49:33 PM PDT 24
Finished Mar 12 12:49:34 PM PDT 24
Peak memory 197688 kb
Host smart-dd2dc95c-f529-469b-971b-e2ccd7f1ac19
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423969097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.3423969097
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup_reset.3635775727
Short name T848
Test name
Test status
Simulation time 488382399 ps
CPU time 0.95 seconds
Started Mar 12 12:49:32 PM PDT 24
Finished Mar 12 12:49:33 PM PDT 24
Peak memory 195732 kb
Host smart-2a979825-f8a6-4d94-ade9-c9990aa90401
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635775727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.3635775727
Directory /workspace/2.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.2317249858
Short name T693
Test name
Test status
Simulation time 23821686 ps
CPU time 0.76 seconds
Started Mar 12 12:50:49 PM PDT 24
Finished Mar 12 12:50:50 PM PDT 24
Peak memory 197692 kb
Host smart-09426d7f-c9c1-4a3b-bcd5-b5d86012ee57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317249858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.2317249858
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.1318105467
Short name T360
Test name
Test status
Simulation time 56346086 ps
CPU time 0.79 seconds
Started Mar 12 12:50:39 PM PDT 24
Finished Mar 12 12:50:41 PM PDT 24
Peak memory 195496 kb
Host smart-f5870b97-da3e-4034-8d29-97e89ec80422
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318105467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_dis
able_rom_integrity_check.1318105467
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.3804549333
Short name T263
Test name
Test status
Simulation time 53154706 ps
CPU time 0.62 seconds
Started Mar 12 12:50:29 PM PDT 24
Finished Mar 12 12:50:30 PM PDT 24
Peak memory 195332 kb
Host smart-35aed8a7-96fe-409a-87dd-fb1f57f17e31
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804549333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.3804549333
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.391731719
Short name T12
Test name
Test status
Simulation time 319023386 ps
CPU time 1 seconds
Started Mar 12 12:50:20 PM PDT 24
Finished Mar 12 12:50:21 PM PDT 24
Peak memory 195352 kb
Host smart-71b9a440-a1df-4f4a-913e-cb2fd2e63ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391731719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.391731719
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.1201067223
Short name T37
Test name
Test status
Simulation time 47339415 ps
CPU time 0.67 seconds
Started Mar 12 12:50:35 PM PDT 24
Finished Mar 12 12:50:36 PM PDT 24
Peak memory 195436 kb
Host smart-e53c0e2f-1ad0-4ca6-9998-bced5d1101c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201067223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.1201067223
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.2140670124
Short name T604
Test name
Test status
Simulation time 55780042 ps
CPU time 0.58 seconds
Started Mar 12 12:50:30 PM PDT 24
Finished Mar 12 12:50:31 PM PDT 24
Peak memory 195432 kb
Host smart-c3122d8d-a06d-4390-afdf-5fdc5ef3b9f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140670124 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.2140670124
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.2430837638
Short name T164
Test name
Test status
Simulation time 196647438 ps
CPU time 0.7 seconds
Started Mar 12 12:50:42 PM PDT 24
Finished Mar 12 12:50:43 PM PDT 24
Peak memory 195740 kb
Host smart-83ffc44f-192e-473c-83d6-283695d09a33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430837638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.2430837638
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.32550183
Short name T582
Test name
Test status
Simulation time 153482191 ps
CPU time 0.84 seconds
Started Mar 12 12:50:40 PM PDT 24
Finished Mar 12 12:50:42 PM PDT 24
Peak memory 197636 kb
Host smart-58acdae2-a4ca-4b83-94a4-a8c632e803fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32550183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.32550183
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.3738018372
Short name T427
Test name
Test status
Simulation time 119753918 ps
CPU time 0.88 seconds
Started Mar 12 12:50:28 PM PDT 24
Finished Mar 12 12:50:34 PM PDT 24
Peak memory 205276 kb
Host smart-bff39e43-8116-4e60-b59c-2cffd3bf36fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738018372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.3738018372
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.1621238634
Short name T231
Test name
Test status
Simulation time 329323053 ps
CPU time 0.86 seconds
Started Mar 12 12:50:24 PM PDT 24
Finished Mar 12 12:50:25 PM PDT 24
Peak memory 195308 kb
Host smart-261f50a6-75be-474e-8e26-e3a57865bec7
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621238634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_
cm_ctrl_config_regwen.1621238634
Directory /workspace/20.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.174447668
Short name T855
Test name
Test status
Simulation time 993990944 ps
CPU time 2.08 seconds
Started Mar 12 12:50:30 PM PDT 24
Finished Mar 12 12:50:33 PM PDT 24
Peak memory 201224 kb
Host smart-b53c1ef6-e31c-4743-9556-814bd82cfaf9
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174447668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.174447668
Directory /workspace/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1514506622
Short name T378
Test name
Test status
Simulation time 1051099865 ps
CPU time 2.51 seconds
Started Mar 12 12:50:43 PM PDT 24
Finished Mar 12 12:50:46 PM PDT 24
Peak memory 195948 kb
Host smart-aa208d7d-6b4c-463b-a5c6-c2c7ba6f7be6
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514506622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1514506622
Directory /workspace/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.877916826
Short name T278
Test name
Test status
Simulation time 167746448 ps
CPU time 0.85 seconds
Started Mar 12 12:50:36 PM PDT 24
Finished Mar 12 12:50:38 PM PDT 24
Peak memory 195332 kb
Host smart-3b48a7a3-1f60-4d35-b01d-7d8130b29d9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877916826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig_
mubi.877916826
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.1436324620
Short name T174
Test name
Test status
Simulation time 165750251 ps
CPU time 0.62 seconds
Started Mar 12 12:50:19 PM PDT 24
Finished Mar 12 12:50:20 PM PDT 24
Peak memory 195448 kb
Host smart-f25d5d92-0d5d-48f5-bc9f-53482052b44b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436324620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.1436324620
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup.356274852
Short name T192
Test name
Test status
Simulation time 452398661 ps
CPU time 0.88 seconds
Started Mar 12 12:50:49 PM PDT 24
Finished Mar 12 12:50:50 PM PDT 24
Peak memory 195364 kb
Host smart-55569655-e832-4fda-ad1e-a22cc6650c32
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356274852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.356274852
Directory /workspace/20.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup_reset.3718980619
Short name T236
Test name
Test status
Simulation time 135026318 ps
CPU time 1.03 seconds
Started Mar 12 12:50:46 PM PDT 24
Finished Mar 12 12:50:47 PM PDT 24
Peak memory 197888 kb
Host smart-0ab217fb-6ea2-4508-b341-642bbe69139a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718980619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.3718980619
Directory /workspace/20.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.1940512656
Short name T502
Test name
Test status
Simulation time 57690620 ps
CPU time 0.74 seconds
Started Mar 12 12:50:27 PM PDT 24
Finished Mar 12 12:50:28 PM PDT 24
Peak memory 197800 kb
Host smart-8b91a029-c5f0-41c5-ac8f-d2f723f0f0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940512656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.1940512656
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.878817826
Short name T138
Test name
Test status
Simulation time 61904349 ps
CPU time 0.66 seconds
Started Mar 12 12:50:17 PM PDT 24
Finished Mar 12 12:50:18 PM PDT 24
Peak memory 195528 kb
Host smart-3c490fd8-d25a-49ec-84ae-b529deb600c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878817826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_disa
ble_rom_integrity_check.878817826
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.2605443019
Short name T205
Test name
Test status
Simulation time 32086788 ps
CPU time 0.58 seconds
Started Mar 12 12:50:35 PM PDT 24
Finished Mar 12 12:50:36 PM PDT 24
Peak memory 195336 kb
Host smart-dde223f4-e10e-42ee-a16e-8aa53722f5f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605443019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst
_malfunc.2605443019
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.1094700361
Short name T730
Test name
Test status
Simulation time 73972997 ps
CPU time 0.59 seconds
Started Mar 12 12:50:48 PM PDT 24
Finished Mar 12 12:50:48 PM PDT 24
Peak memory 195440 kb
Host smart-afcea380-1c63-4f01-a4bd-8a002a377484
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094700361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.1094700361
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.2813316955
Short name T742
Test name
Test status
Simulation time 55355947 ps
CPU time 0.63 seconds
Started Mar 12 12:50:45 PM PDT 24
Finished Mar 12 12:50:45 PM PDT 24
Peak memory 195324 kb
Host smart-345dc71a-32d7-42b0-9f08-0e08bc0ee419
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813316955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.2813316955
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.3402421962
Short name T590
Test name
Test status
Simulation time 55735707 ps
CPU time 0.69 seconds
Started Mar 12 12:50:50 PM PDT 24
Finished Mar 12 12:50:51 PM PDT 24
Peak memory 195900 kb
Host smart-3ce71162-ca11-49f1-ab82-51e1d2a75c5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402421962 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_inval
id.3402421962
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_wakeup_race.195224396
Short name T465
Test name
Test status
Simulation time 395672020 ps
CPU time 1.07 seconds
Started Mar 12 12:50:30 PM PDT 24
Finished Mar 12 12:50:31 PM PDT 24
Peak memory 195352 kb
Host smart-78ccfc38-e240-410e-957c-1a5106e91e9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195224396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_wa
keup_race.195224396
Directory /workspace/21.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.3185813104
Short name T630
Test name
Test status
Simulation time 153062455 ps
CPU time 0.81 seconds
Started Mar 12 12:50:29 PM PDT 24
Finished Mar 12 12:50:30 PM PDT 24
Peak memory 197744 kb
Host smart-c2da65ae-fc8e-4736-bfda-5998a6fe4507
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185813104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.3185813104
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.2094788057
Short name T223
Test name
Test status
Simulation time 263548469 ps
CPU time 0.71 seconds
Started Mar 12 12:50:32 PM PDT 24
Finished Mar 12 12:50:34 PM PDT 24
Peak memory 195376 kb
Host smart-903d4cb4-1cb5-4880-aa6f-f0be24f742df
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094788057 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_
cm_ctrl_config_regwen.2094788057
Directory /workspace/21.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3912154621
Short name T78
Test name
Test status
Simulation time 1339395422 ps
CPU time 1.79 seconds
Started Mar 12 12:50:32 PM PDT 24
Finished Mar 12 12:50:35 PM PDT 24
Peak memory 201072 kb
Host smart-7f32d200-661f-40f9-abea-48716a8ec0f6
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912154621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3912154621
Directory /workspace/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.353689859
Short name T173
Test name
Test status
Simulation time 805156917 ps
CPU time 3.05 seconds
Started Mar 12 12:50:50 PM PDT 24
Finished Mar 12 12:50:53 PM PDT 24
Peak memory 195856 kb
Host smart-8e15fa90-ef89-4bde-92dc-233b30675d20
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353689859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.353689859
Directory /workspace/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.974987020
Short name T119
Test name
Test status
Simulation time 67404068 ps
CPU time 0.88 seconds
Started Mar 12 12:50:45 PM PDT 24
Finished Mar 12 12:50:46 PM PDT 24
Peak memory 195264 kb
Host smart-097e7bae-9d68-4ec5-887a-593ce22f850f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974987020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig_
mubi.974987020
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.3191869568
Short name T786
Test name
Test status
Simulation time 35941449 ps
CPU time 0.66 seconds
Started Mar 12 12:50:39 PM PDT 24
Finished Mar 12 12:50:41 PM PDT 24
Peak memory 197732 kb
Host smart-8d52a59a-3c42-42a3-93f7-21e600482dda
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191869568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.3191869568
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup.2524273352
Short name T194
Test name
Test status
Simulation time 408384833 ps
CPU time 0.88 seconds
Started Mar 12 12:50:41 PM PDT 24
Finished Mar 12 12:50:43 PM PDT 24
Peak memory 195376 kb
Host smart-ec6bbe17-486e-48a4-958f-6c268b89010f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524273352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.2524273352
Directory /workspace/21.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup_reset.2253971374
Short name T579
Test name
Test status
Simulation time 220941407 ps
CPU time 0.84 seconds
Started Mar 12 12:50:36 PM PDT 24
Finished Mar 12 12:50:37 PM PDT 24
Peak memory 197936 kb
Host smart-3f64cff6-ce9e-4ae1-bedc-110ae65128c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253971374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.2253971374
Directory /workspace/21.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.1628806735
Short name T265
Test name
Test status
Simulation time 19834020 ps
CPU time 0.66 seconds
Started Mar 12 12:50:48 PM PDT 24
Finished Mar 12 12:50:48 PM PDT 24
Peak memory 197584 kb
Host smart-8b8991cc-11f4-4225-8539-24cb4568b4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628806735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.1628806735
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.3594515939
Short name T567
Test name
Test status
Simulation time 31136733 ps
CPU time 0.67 seconds
Started Mar 12 12:50:50 PM PDT 24
Finished Mar 12 12:50:50 PM PDT 24
Peak memory 195332 kb
Host smart-32b8eb00-d30e-4a76-914c-1822ba95e894
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594515939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.3594515939
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.1439875813
Short name T534
Test name
Test status
Simulation time 613827309 ps
CPU time 1.09 seconds
Started Mar 12 12:50:41 PM PDT 24
Finished Mar 12 12:50:43 PM PDT 24
Peak memory 195408 kb
Host smart-d9327213-58cd-4be2-974d-d2e8eae8b6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439875813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.1439875813
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.552966699
Short name T788
Test name
Test status
Simulation time 74107069 ps
CPU time 0.58 seconds
Started Mar 12 12:50:40 PM PDT 24
Finished Mar 12 12:50:41 PM PDT 24
Peak memory 195344 kb
Host smart-9d083b65-ff8f-4fba-8c5e-ca74ba295864
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552966699 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.552966699
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.3690363147
Short name T645
Test name
Test status
Simulation time 160989082 ps
CPU time 0.67 seconds
Started Mar 12 12:50:44 PM PDT 24
Finished Mar 12 12:50:45 PM PDT 24
Peak memory 195400 kb
Host smart-2af22576-43b7-4b2c-860a-d401c2ff9112
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690363147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.3690363147
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.406964776
Short name T516
Test name
Test status
Simulation time 75001931 ps
CPU time 0.64 seconds
Started Mar 12 12:50:53 PM PDT 24
Finished Mar 12 12:50:54 PM PDT 24
Peak memory 195940 kb
Host smart-6a00ab01-f4ce-43b3-a37f-a5bface2e4fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406964776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_invali
d.406964776
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_wakeup_race.68007223
Short name T303
Test name
Test status
Simulation time 220650906 ps
CPU time 0.7 seconds
Started Mar 12 12:50:38 PM PDT 24
Finished Mar 12 12:50:39 PM PDT 24
Peak memory 195340 kb
Host smart-58752fb7-2353-4e33-972d-94d0cf07d986
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68007223 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup
_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_wak
eup_race.68007223
Directory /workspace/22.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.2081715799
Short name T764
Test name
Test status
Simulation time 33242453 ps
CPU time 0.62 seconds
Started Mar 12 12:50:43 PM PDT 24
Finished Mar 12 12:50:44 PM PDT 24
Peak memory 195344 kb
Host smart-7779148f-2876-4397-b933-220aa3694abe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081715799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.2081715799
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.4269711195
Short name T771
Test name
Test status
Simulation time 125895540 ps
CPU time 0.89 seconds
Started Mar 12 12:50:53 PM PDT 24
Finished Mar 12 12:50:54 PM PDT 24
Peak memory 205220 kb
Host smart-ec0879e5-5794-4aba-a018-8af526721044
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269711195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.4269711195
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.1435931528
Short name T551
Test name
Test status
Simulation time 150119358 ps
CPU time 0.84 seconds
Started Mar 12 12:50:42 PM PDT 24
Finished Mar 12 12:50:43 PM PDT 24
Peak memory 195376 kb
Host smart-3c5dbfd4-039b-4936-8b0a-96e95a328e0b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435931528 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_
cm_ctrl_config_regwen.1435931528
Directory /workspace/22.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2789409478
Short name T320
Test name
Test status
Simulation time 824046565 ps
CPU time 3.32 seconds
Started Mar 12 12:50:39 PM PDT 24
Finished Mar 12 12:50:43 PM PDT 24
Peak memory 201188 kb
Host smart-8a02bd8a-6067-454d-9355-acb92ee25e12
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789409478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2789409478
Directory /workspace/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3849316421
Short name T210
Test name
Test status
Simulation time 1060306915 ps
CPU time 1.89 seconds
Started Mar 12 12:50:49 PM PDT 24
Finished Mar 12 12:50:51 PM PDT 24
Peak memory 195820 kb
Host smart-7c8c2bad-8453-4d55-bd7d-92503db6ff34
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849316421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3849316421
Directory /workspace/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3141981266
Short name T233
Test name
Test status
Simulation time 139448702 ps
CPU time 0.86 seconds
Started Mar 12 12:50:45 PM PDT 24
Finished Mar 12 12:50:46 PM PDT 24
Peak memory 195388 kb
Host smart-e1076f2e-024d-433e-9946-0a52c72335b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141981266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3141981266
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.231659557
Short name T279
Test name
Test status
Simulation time 34132328 ps
CPU time 0.65 seconds
Started Mar 12 12:50:47 PM PDT 24
Finished Mar 12 12:50:48 PM PDT 24
Peak memory 195600 kb
Host smart-a4de2581-0651-40b4-b609-258dab493287
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231659557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.231659557
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_wakeup_reset.576312433
Short name T736
Test name
Test status
Simulation time 243595071 ps
CPU time 1.43 seconds
Started Mar 12 12:50:42 PM PDT 24
Finished Mar 12 12:50:44 PM PDT 24
Peak memory 198112 kb
Host smart-67165cf7-046c-4b8e-907e-acb0f8c45fa2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576312433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup_reset.576312433
Directory /workspace/22.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.804787720
Short name T206
Test name
Test status
Simulation time 58465285 ps
CPU time 0.72 seconds
Started Mar 12 12:50:48 PM PDT 24
Finished Mar 12 12:50:49 PM PDT 24
Peak memory 195384 kb
Host smart-9fa39ee8-1902-4f73-9067-a7dfc837f0d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804787720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_disa
ble_rom_integrity_check.804787720
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.2596457046
Short name T88
Test name
Test status
Simulation time 39187995 ps
CPU time 0.6 seconds
Started Mar 12 12:50:45 PM PDT 24
Finished Mar 12 12:50:46 PM PDT 24
Peak memory 195176 kb
Host smart-65bc3c4f-4e1e-4363-8a82-fe8c68fdc928
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596457046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst
_malfunc.2596457046
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.276767859
Short name T434
Test name
Test status
Simulation time 797989718 ps
CPU time 0.95 seconds
Started Mar 12 12:50:42 PM PDT 24
Finished Mar 12 12:50:43 PM PDT 24
Peak memory 195416 kb
Host smart-426dee22-3624-4e41-99ae-20239bf8aa12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276767859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.276767859
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.1453799030
Short name T21
Test name
Test status
Simulation time 57472572 ps
CPU time 0.62 seconds
Started Mar 12 12:50:40 PM PDT 24
Finished Mar 12 12:50:41 PM PDT 24
Peak memory 195368 kb
Host smart-bfadbe4e-c52d-4d77-a29d-15caaa02cfdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453799030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.1453799030
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.3834160732
Short name T450
Test name
Test status
Simulation time 102005045 ps
CPU time 0.61 seconds
Started Mar 12 12:50:44 PM PDT 24
Finished Mar 12 12:50:45 PM PDT 24
Peak memory 195420 kb
Host smart-fb69a7ef-e939-411f-9886-3ddf97c3cb96
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834160732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.3834160732
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.4189592002
Short name T814
Test name
Test status
Simulation time 44612944 ps
CPU time 0.74 seconds
Started Mar 12 12:50:47 PM PDT 24
Finished Mar 12 12:50:48 PM PDT 24
Peak memory 195920 kb
Host smart-4790363b-0037-41d0-a0f6-03080680a552
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189592002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.4189592002
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.3723171247
Short name T433
Test name
Test status
Simulation time 33610657 ps
CPU time 0.79 seconds
Started Mar 12 12:50:51 PM PDT 24
Finished Mar 12 12:50:52 PM PDT 24
Peak memory 197612 kb
Host smart-d495e1a7-1103-4d02-900f-7add65d6ae8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723171247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.3723171247
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.751564664
Short name T557
Test name
Test status
Simulation time 159658157 ps
CPU time 0.88 seconds
Started Mar 12 12:50:47 PM PDT 24
Finished Mar 12 12:50:48 PM PDT 24
Peak memory 205312 kb
Host smart-3fe4b8e5-d2bc-428e-9471-24da3fb9e3b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751564664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.751564664
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2448034438
Short name T623
Test name
Test status
Simulation time 709967379 ps
CPU time 2.7 seconds
Started Mar 12 12:50:31 PM PDT 24
Finished Mar 12 12:50:34 PM PDT 24
Peak memory 200828 kb
Host smart-2f6fb2b7-4969-4051-9915-9016e5df96b4
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448034438 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2448034438
Directory /workspace/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1158652095
Short name T28
Test name
Test status
Simulation time 1214132434 ps
CPU time 2.2 seconds
Started Mar 12 12:50:44 PM PDT 24
Finished Mar 12 12:50:47 PM PDT 24
Peak memory 200576 kb
Host smart-4a7c1335-1623-41ff-aa31-d7dcc963143b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158652095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1158652095
Directory /workspace/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.846899985
Short name T784
Test name
Test status
Simulation time 69498664 ps
CPU time 0.94 seconds
Started Mar 12 12:50:48 PM PDT 24
Finished Mar 12 12:50:50 PM PDT 24
Peak memory 195372 kb
Host smart-fa8b9c28-3d95-4b46-b83a-22f5e80e012f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846899985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig_
mubi.846899985
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.2686217138
Short name T700
Test name
Test status
Simulation time 36608542 ps
CPU time 0.65 seconds
Started Mar 12 12:50:50 PM PDT 24
Finished Mar 12 12:50:51 PM PDT 24
Peak memory 195528 kb
Host smart-fcbb259c-d77c-4f19-b00b-a63f9c7b6cf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686217138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.2686217138
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup.3697018361
Short name T398
Test name
Test status
Simulation time 183847253 ps
CPU time 0.91 seconds
Started Mar 12 12:50:52 PM PDT 24
Finished Mar 12 12:50:53 PM PDT 24
Peak memory 195412 kb
Host smart-6bac9627-a516-41ce-b52c-5e4cfc26c47b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697018361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.3697018361
Directory /workspace/23.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup_reset.3367901901
Short name T42
Test name
Test status
Simulation time 210839943 ps
CPU time 1.32 seconds
Started Mar 12 12:50:47 PM PDT 24
Finished Mar 12 12:50:49 PM PDT 24
Peak memory 199056 kb
Host smart-e06ae1e0-3d1b-4d69-b278-e9438f085a81
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367901901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.3367901901
Directory /workspace/23.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.2213624016
Short name T170
Test name
Test status
Simulation time 112197595 ps
CPU time 0.86 seconds
Started Mar 12 12:50:50 PM PDT 24
Finished Mar 12 12:50:51 PM PDT 24
Peak memory 195392 kb
Host smart-12e22361-7b47-4ef0-a541-03094afddd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213624016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.2213624016
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.3421081186
Short name T392
Test name
Test status
Simulation time 59031760 ps
CPU time 0.82 seconds
Started Mar 12 12:50:59 PM PDT 24
Finished Mar 12 12:51:00 PM PDT 24
Peak memory 197540 kb
Host smart-1788b9bc-3767-4d30-8b01-ed3245d816eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421081186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.3421081186
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.1534241078
Short name T307
Test name
Test status
Simulation time 31020134 ps
CPU time 0.63 seconds
Started Mar 12 12:50:42 PM PDT 24
Finished Mar 12 12:50:42 PM PDT 24
Peak memory 195352 kb
Host smart-88499141-0fe2-4ff1-a1ab-b65a40c5e64c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534241078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.1534241078
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.2183098026
Short name T552
Test name
Test status
Simulation time 325164170 ps
CPU time 0.98 seconds
Started Mar 12 12:50:49 PM PDT 24
Finished Mar 12 12:50:50 PM PDT 24
Peak memory 195396 kb
Host smart-5670288b-c44b-4ec1-b64a-3fed2088102a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183098026 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.2183098026
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.3201331609
Short name T351
Test name
Test status
Simulation time 77971598 ps
CPU time 0.65 seconds
Started Mar 12 12:50:44 PM PDT 24
Finished Mar 12 12:50:45 PM PDT 24
Peak memory 195364 kb
Host smart-79b48d2a-8ae0-4baa-85b8-a02514eca8da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201331609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.3201331609
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.2414539427
Short name T269
Test name
Test status
Simulation time 66196183 ps
CPU time 0.7 seconds
Started Mar 12 12:50:51 PM PDT 24
Finished Mar 12 12:50:52 PM PDT 24
Peak memory 195324 kb
Host smart-e506d8a1-5418-4bae-b061-16a917f4be7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414539427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.2414539427
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.1346985302
Short name T372
Test name
Test status
Simulation time 68813077 ps
CPU time 0.66 seconds
Started Mar 12 12:50:53 PM PDT 24
Finished Mar 12 12:50:53 PM PDT 24
Peak memory 195944 kb
Host smart-94c893c6-b46a-4317-9cd0-1dd7184e7443
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346985302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.1346985302
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.4157148913
Short name T564
Test name
Test status
Simulation time 81417183 ps
CPU time 1 seconds
Started Mar 12 12:50:44 PM PDT 24
Finished Mar 12 12:50:45 PM PDT 24
Peak memory 197728 kb
Host smart-a2bfeded-c40e-4e25-8b0f-1b980ec85f76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157148913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.4157148913
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.75535912
Short name T525
Test name
Test status
Simulation time 160013626 ps
CPU time 0.77 seconds
Started Mar 12 12:50:46 PM PDT 24
Finished Mar 12 12:50:47 PM PDT 24
Peak memory 205968 kb
Host smart-89d407d2-6180-4ec2-ac93-afb608d8e98e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75535912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.75535912
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.3575902193
Short name T477
Test name
Test status
Simulation time 415586057 ps
CPU time 0.95 seconds
Started Mar 12 12:50:46 PM PDT 24
Finished Mar 12 12:50:47 PM PDT 24
Peak memory 195376 kb
Host smart-9cacbdf9-de07-4501-bff9-b4c76ab7c358
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575902193 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_
cm_ctrl_config_regwen.3575902193
Directory /workspace/24.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2731946411
Short name T809
Test name
Test status
Simulation time 987787355 ps
CPU time 1.92 seconds
Started Mar 12 12:50:42 PM PDT 24
Finished Mar 12 12:50:44 PM PDT 24
Peak memory 200700 kb
Host smart-b7a48602-96c9-4f70-8ee4-8f339200c895
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731946411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2731946411
Directory /workspace/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1587523889
Short name T358
Test name
Test status
Simulation time 1262187741 ps
CPU time 2.37 seconds
Started Mar 12 12:50:51 PM PDT 24
Finished Mar 12 12:50:53 PM PDT 24
Peak memory 195932 kb
Host smart-dd22cbee-b2c4-41cf-a0a1-272756ae4b1f
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587523889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1587523889
Directory /workspace/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.3702291729
Short name T238
Test name
Test status
Simulation time 197766957 ps
CPU time 0.85 seconds
Started Mar 12 12:51:02 PM PDT 24
Finished Mar 12 12:51:03 PM PDT 24
Peak memory 195388 kb
Host smart-f95f54a6-fe12-4b40-8852-95848a200e28
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702291729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3702291729
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.486100807
Short name T221
Test name
Test status
Simulation time 58128123 ps
CPU time 0.63 seconds
Started Mar 12 12:50:50 PM PDT 24
Finished Mar 12 12:50:50 PM PDT 24
Peak memory 197556 kb
Host smart-19375f89-d355-4a66-aef4-3685bbdfb498
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486100807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.486100807
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_stress_all.1506735998
Short name T48
Test name
Test status
Simulation time 1216522582 ps
CPU time 1.74 seconds
Started Mar 12 12:50:52 PM PDT 24
Finished Mar 12 12:50:53 PM PDT 24
Peak memory 200180 kb
Host smart-c861125f-2791-4f82-a05b-52e6c0e61482
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506735998 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.1506735998
Directory /workspace/24.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup.594996695
Short name T608
Test name
Test status
Simulation time 308131839 ps
CPU time 0.86 seconds
Started Mar 12 12:50:38 PM PDT 24
Finished Mar 12 12:50:40 PM PDT 24
Peak memory 195192 kb
Host smart-4eafc73a-275f-4392-af76-7dab778e4c9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594996695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.594996695
Directory /workspace/24.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup_reset.698279585
Short name T644
Test name
Test status
Simulation time 327762227 ps
CPU time 1.41 seconds
Started Mar 12 12:50:49 PM PDT 24
Finished Mar 12 12:50:51 PM PDT 24
Peak memory 200416 kb
Host smart-c3174324-2b40-44f8-bbb5-533778de0791
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698279585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.698279585
Directory /workspace/24.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.2497358980
Short name T214
Test name
Test status
Simulation time 57202677 ps
CPU time 0.61 seconds
Started Mar 12 12:50:51 PM PDT 24
Finished Mar 12 12:50:52 PM PDT 24
Peak memory 195372 kb
Host smart-c49bbe84-c4c7-49b6-af59-a851c521229b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497358980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.2497358980
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.4210787007
Short name T255
Test name
Test status
Simulation time 42416467 ps
CPU time 0.57 seconds
Started Mar 12 12:51:07 PM PDT 24
Finished Mar 12 12:51:08 PM PDT 24
Peak memory 195336 kb
Host smart-dad38fea-0295-4b2e-b273-4443aba929a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210787007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst
_malfunc.4210787007
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.293615523
Short name T697
Test name
Test status
Simulation time 604375245 ps
CPU time 0.95 seconds
Started Mar 12 12:50:54 PM PDT 24
Finished Mar 12 12:50:55 PM PDT 24
Peak memory 195428 kb
Host smart-0f1f56e9-f291-4ab7-b075-31bfe84c8160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293615523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.293615523
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.3017444248
Short name T670
Test name
Test status
Simulation time 76289818 ps
CPU time 0.66 seconds
Started Mar 12 12:50:54 PM PDT 24
Finished Mar 12 12:50:55 PM PDT 24
Peak memory 195392 kb
Host smart-cc720ad9-5c35-4eed-964d-27a4a136ab62
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017444248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.3017444248
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.3820713813
Short name T710
Test name
Test status
Simulation time 22035430 ps
CPU time 0.59 seconds
Started Mar 12 12:50:54 PM PDT 24
Finished Mar 12 12:50:54 PM PDT 24
Peak memory 195420 kb
Host smart-314e6833-9b35-4dbe-b27f-e1b301a875ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820713813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.3820713813
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.98140100
Short name T260
Test name
Test status
Simulation time 123864807 ps
CPU time 0.69 seconds
Started Mar 12 12:51:00 PM PDT 24
Finished Mar 12 12:51:01 PM PDT 24
Peak memory 195860 kb
Host smart-1d8197f8-c5c1-4b8a-945e-2aadc0d50d19
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98140100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_invalid
.98140100
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_wakeup_race.2832017778
Short name T493
Test name
Test status
Simulation time 416965776 ps
CPU time 0.95 seconds
Started Mar 12 12:50:47 PM PDT 24
Finished Mar 12 12:50:48 PM PDT 24
Peak memory 195304 kb
Host smart-9e938e9d-e48c-488c-b87b-294403eb2fff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832017778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_w
akeup_race.2832017778
Directory /workspace/25.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.2288925243
Short name T469
Test name
Test status
Simulation time 36271172 ps
CPU time 0.76 seconds
Started Mar 12 12:50:52 PM PDT 24
Finished Mar 12 12:50:53 PM PDT 24
Peak memory 197524 kb
Host smart-23e879a7-f2cb-4e37-a809-5d425e63791f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288925243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.2288925243
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.1942748550
Short name T216
Test name
Test status
Simulation time 556246739 ps
CPU time 0.77 seconds
Started Mar 12 12:51:06 PM PDT 24
Finished Mar 12 12:51:07 PM PDT 24
Peak memory 205264 kb
Host smart-95f38021-3092-4ff5-bcdb-2e72d50b1818
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942748550 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.1942748550
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2920942698
Short name T34
Test name
Test status
Simulation time 1042833138 ps
CPU time 2.54 seconds
Started Mar 12 12:50:46 PM PDT 24
Finished Mar 12 12:50:49 PM PDT 24
Peak memory 201124 kb
Host smart-708eaa4c-f76c-4afd-94da-2dac99780dfb
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920942698 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2920942698
Directory /workspace/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1943455576
Short name T542
Test name
Test status
Simulation time 838571354 ps
CPU time 3.22 seconds
Started Mar 12 12:51:10 PM PDT 24
Finished Mar 12 12:51:14 PM PDT 24
Peak memory 195912 kb
Host smart-cc202c3b-e033-4b21-8950-4ae737925edd
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943455576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1943455576
Directory /workspace/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.140063259
Short name T178
Test name
Test status
Simulation time 74341327 ps
CPU time 0.91 seconds
Started Mar 12 12:51:03 PM PDT 24
Finished Mar 12 12:51:04 PM PDT 24
Peak memory 195292 kb
Host smart-acf57609-0399-4782-a0f2-722f7c476cca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140063259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig_
mubi.140063259
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.2852684853
Short name T246
Test name
Test status
Simulation time 42622096 ps
CPU time 0.65 seconds
Started Mar 12 12:51:00 PM PDT 24
Finished Mar 12 12:51:00 PM PDT 24
Peak memory 195528 kb
Host smart-bc1b305d-57ab-4ccc-a24a-5f4fef25d33b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852684853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.2852684853
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup.3336990331
Short name T181
Test name
Test status
Simulation time 73180104 ps
CPU time 0.61 seconds
Started Mar 12 12:50:46 PM PDT 24
Finished Mar 12 12:50:47 PM PDT 24
Peak memory 195360 kb
Host smart-eba98320-9f31-4540-aa71-574f73a43bac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336990331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.3336990331
Directory /workspace/25.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup_reset.1269685487
Short name T817
Test name
Test status
Simulation time 456946829 ps
CPU time 1.2 seconds
Started Mar 12 12:50:47 PM PDT 24
Finished Mar 12 12:50:48 PM PDT 24
Peak memory 199140 kb
Host smart-d26de284-d171-4539-84a1-bdc41e7cd835
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269685487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.1269685487
Directory /workspace/25.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.733749440
Short name T259
Test name
Test status
Simulation time 34095442 ps
CPU time 0.62 seconds
Started Mar 12 12:51:05 PM PDT 24
Finished Mar 12 12:51:07 PM PDT 24
Peak memory 197468 kb
Host smart-ee596d2a-4844-498c-b919-40ade35143e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733749440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.733749440
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.3363426344
Short name T617
Test name
Test status
Simulation time 49376952 ps
CPU time 0.76 seconds
Started Mar 12 12:50:57 PM PDT 24
Finished Mar 12 12:50:58 PM PDT 24
Peak memory 198956 kb
Host smart-46e2d054-6ec6-4046-b4cd-744f29beed7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363426344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.3363426344
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.2307341719
Short name T611
Test name
Test status
Simulation time 39110765 ps
CPU time 0.58 seconds
Started Mar 12 12:51:02 PM PDT 24
Finished Mar 12 12:51:02 PM PDT 24
Peak memory 195364 kb
Host smart-cfbb350d-0055-44d1-95fc-d09dd13026d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307341719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.2307341719
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.1103787238
Short name T311
Test name
Test status
Simulation time 162799369 ps
CPU time 0.98 seconds
Started Mar 12 12:50:53 PM PDT 24
Finished Mar 12 12:50:54 PM PDT 24
Peak memory 195384 kb
Host smart-ac92a069-cf70-429d-bd44-4fd9b4a16fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103787238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.1103787238
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.199819291
Short name T241
Test name
Test status
Simulation time 37826492 ps
CPU time 0.66 seconds
Started Mar 12 12:51:08 PM PDT 24
Finished Mar 12 12:51:10 PM PDT 24
Peak memory 195464 kb
Host smart-891d9ba1-660b-48a7-a44b-efc21559227a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199819291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.199819291
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.2667372784
Short name T613
Test name
Test status
Simulation time 23917927 ps
CPU time 0.59 seconds
Started Mar 12 12:51:02 PM PDT 24
Finished Mar 12 12:51:03 PM PDT 24
Peak memory 195448 kb
Host smart-9b5b9c62-3218-4a2f-a69b-5855335f907d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667372784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.2667372784
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.3704345434
Short name T474
Test name
Test status
Simulation time 92101138 ps
CPU time 0.67 seconds
Started Mar 12 12:50:56 PM PDT 24
Finished Mar 12 12:50:56 PM PDT 24
Peak memory 195900 kb
Host smart-b215ff06-2ba9-4a8f-97b4-cddd7b2a6828
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704345434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.3704345434
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_wakeup_race.2768060769
Short name T244
Test name
Test status
Simulation time 62282161 ps
CPU time 0.67 seconds
Started Mar 12 12:50:54 PM PDT 24
Finished Mar 12 12:50:55 PM PDT 24
Peak memory 195380 kb
Host smart-d43a41f5-192b-40be-adc7-8b068b07b7d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768060769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_w
akeup_race.2768060769
Directory /workspace/26.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.1028712931
Short name T756
Test name
Test status
Simulation time 56237026 ps
CPU time 0.72 seconds
Started Mar 12 12:50:53 PM PDT 24
Finished Mar 12 12:50:53 PM PDT 24
Peak memory 197816 kb
Host smart-8c72d5b8-2ef6-4beb-a55d-b366cb726f24
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028712931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.1028712931
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.1273795165
Short name T791
Test name
Test status
Simulation time 142020992 ps
CPU time 0.8 seconds
Started Mar 12 12:51:03 PM PDT 24
Finished Mar 12 12:51:04 PM PDT 24
Peak memory 205168 kb
Host smart-77bab2f5-ee32-4bb6-a3ac-f92e6549db6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273795165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.1273795165
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.3874157670
Short name T382
Test name
Test status
Simulation time 66061306 ps
CPU time 0.67 seconds
Started Mar 12 12:50:51 PM PDT 24
Finished Mar 12 12:50:52 PM PDT 24
Peak memory 195380 kb
Host smart-53508b91-669a-4393-852f-3f7dffe8bd8c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874157670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_
cm_ctrl_config_regwen.3874157670
Directory /workspace/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3717252989
Short name T1
Test name
Test status
Simulation time 1201308329 ps
CPU time 2.33 seconds
Started Mar 12 12:50:57 PM PDT 24
Finished Mar 12 12:50:59 PM PDT 24
Peak memory 200984 kb
Host smart-eefaadf5-ae60-4d07-8f4b-40a5cac6c510
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717252989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3717252989
Directory /workspace/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1027750688
Short name T820
Test name
Test status
Simulation time 1296960664 ps
CPU time 1.84 seconds
Started Mar 12 12:51:04 PM PDT 24
Finished Mar 12 12:51:06 PM PDT 24
Peak memory 200968 kb
Host smart-a0fc9037-b439-4810-87ec-bcf4c5460918
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027750688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1027750688
Directory /workspace/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.3318981456
Short name T149
Test name
Test status
Simulation time 92944894 ps
CPU time 0.85 seconds
Started Mar 12 12:50:56 PM PDT 24
Finished Mar 12 12:50:57 PM PDT 24
Peak memory 195340 kb
Host smart-7bc2f032-4a46-4491-92b6-32434ad5b5df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318981456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3318981456
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.119630988
Short name T721
Test name
Test status
Simulation time 28763390 ps
CPU time 0.7 seconds
Started Mar 12 12:50:53 PM PDT 24
Finished Mar 12 12:50:54 PM PDT 24
Peak memory 197760 kb
Host smart-77dc1cd1-397f-4317-a0cc-ef22c9bff1c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119630988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.119630988
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup_reset.3984315610
Short name T859
Test name
Test status
Simulation time 91376604 ps
CPU time 0.66 seconds
Started Mar 12 12:50:55 PM PDT 24
Finished Mar 12 12:50:56 PM PDT 24
Peak memory 197776 kb
Host smart-a0814fd8-bdbd-4f48-a3ba-93077276d480
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984315610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup_reset.3984315610
Directory /workspace/26.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.804876007
Short name T384
Test name
Test status
Simulation time 23766370 ps
CPU time 0.65 seconds
Started Mar 12 12:50:56 PM PDT 24
Finished Mar 12 12:50:57 PM PDT 24
Peak memory 195328 kb
Host smart-e50539b2-c5d7-4a43-9275-076f579a354f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804876007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.804876007
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.1156736422
Short name T137
Test name
Test status
Simulation time 69170706 ps
CPU time 0.69 seconds
Started Mar 12 12:51:02 PM PDT 24
Finished Mar 12 12:51:03 PM PDT 24
Peak memory 195436 kb
Host smart-f5eaf22c-b12f-4e97-9854-ca14aea149ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156736422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis
able_rom_integrity_check.1156736422
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.751705348
Short name T388
Test name
Test status
Simulation time 31014999 ps
CPU time 0.62 seconds
Started Mar 12 12:50:53 PM PDT 24
Finished Mar 12 12:50:53 PM PDT 24
Peak memory 195312 kb
Host smart-4d4e9013-290e-426a-8fb6-5ee1c365a5c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751705348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst_
malfunc.751705348
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.3496737203
Short name T335
Test name
Test status
Simulation time 634406540 ps
CPU time 0.94 seconds
Started Mar 12 12:51:00 PM PDT 24
Finished Mar 12 12:51:01 PM PDT 24
Peak memory 195448 kb
Host smart-3413bc56-8423-421c-b835-a8324b3c45b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496737203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.3496737203
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.2768239196
Short name T862
Test name
Test status
Simulation time 33613060 ps
CPU time 0.63 seconds
Started Mar 12 12:50:51 PM PDT 24
Finished Mar 12 12:50:52 PM PDT 24
Peak memory 195392 kb
Host smart-89a61b06-09f4-4e5f-a0ad-bd9fd7143e16
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768239196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.2768239196
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.2056757211
Short name T698
Test name
Test status
Simulation time 21405535 ps
CPU time 0.6 seconds
Started Mar 12 12:50:58 PM PDT 24
Finished Mar 12 12:50:59 PM PDT 24
Peak memory 195412 kb
Host smart-3fc2c23b-485a-4035-8eac-cad7d0d88353
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056757211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.2056757211
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.2565882976
Short name T704
Test name
Test status
Simulation time 71060213 ps
CPU time 0.67 seconds
Started Mar 12 12:51:04 PM PDT 24
Finished Mar 12 12:51:07 PM PDT 24
Peak memory 195756 kb
Host smart-742a1ff0-3637-4912-8c2d-3063c4b47ca1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565882976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_inval
id.2565882976
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_wakeup_race.4260512413
Short name T310
Test name
Test status
Simulation time 371349642 ps
CPU time 0.93 seconds
Started Mar 12 12:51:07 PM PDT 24
Finished Mar 12 12:51:08 PM PDT 24
Peak memory 195324 kb
Host smart-b95c58c2-21cd-4a8a-9a52-bd670d17142d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260512413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_w
akeup_race.4260512413
Directory /workspace/27.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.1221002742
Short name T165
Test name
Test status
Simulation time 71801365 ps
CPU time 0.83 seconds
Started Mar 12 12:51:02 PM PDT 24
Finished Mar 12 12:51:03 PM PDT 24
Peak memory 198096 kb
Host smart-597a56f9-b6c5-4808-8d8f-445ce18b4ee6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221002742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.1221002742
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.2099808850
Short name T338
Test name
Test status
Simulation time 93531211 ps
CPU time 1.02 seconds
Started Mar 12 12:51:02 PM PDT 24
Finished Mar 12 12:51:04 PM PDT 24
Peak memory 205420 kb
Host smart-0bf52eea-c58f-4e78-bf9d-099e71f9b569
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099808850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.2099808850
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.2123296768
Short name T624
Test name
Test status
Simulation time 407810122 ps
CPU time 0.87 seconds
Started Mar 12 12:51:05 PM PDT 24
Finished Mar 12 12:51:07 PM PDT 24
Peak memory 195380 kb
Host smart-762d2420-9cdd-46d9-a2d6-76aec7261579
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123296768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_
cm_ctrl_config_regwen.2123296768
Directory /workspace/27.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4081032918
Short name T655
Test name
Test status
Simulation time 1190632401 ps
CPU time 2.05 seconds
Started Mar 12 12:50:57 PM PDT 24
Finished Mar 12 12:50:59 PM PDT 24
Peak memory 201156 kb
Host smart-ec15da47-9703-407d-8493-aaf45c83d1b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081032918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4081032918
Directory /workspace/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2722429428
Short name T640
Test name
Test status
Simulation time 887840764 ps
CPU time 3.05 seconds
Started Mar 12 12:51:02 PM PDT 24
Finished Mar 12 12:51:05 PM PDT 24
Peak memory 195780 kb
Host smart-c6aae43f-b399-4dd7-b432-0bdb0e14cbbb
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722429428 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2722429428
Directory /workspace/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.1366557288
Short name T314
Test name
Test status
Simulation time 50962489 ps
CPU time 0.88 seconds
Started Mar 12 12:50:54 PM PDT 24
Finished Mar 12 12:50:55 PM PDT 24
Peak memory 195368 kb
Host smart-866640a9-21f3-479f-95d1-27ec3562524e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366557288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1366557288
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.778072803
Short name T680
Test name
Test status
Simulation time 55278895 ps
CPU time 0.65 seconds
Started Mar 12 12:51:03 PM PDT 24
Finished Mar 12 12:51:05 PM PDT 24
Peak memory 195600 kb
Host smart-50aa60eb-3ec1-4034-944f-67f74e73dc4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778072803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.778072803
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup.121516364
Short name T722
Test name
Test status
Simulation time 396670558 ps
CPU time 0.87 seconds
Started Mar 12 12:50:54 PM PDT 24
Finished Mar 12 12:50:55 PM PDT 24
Peak memory 195344 kb
Host smart-d362433f-a93e-44d2-8ead-1e99058d7e64
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121516364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.121516364
Directory /workspace/27.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup_reset.4153930555
Short name T428
Test name
Test status
Simulation time 66055075 ps
CPU time 0.62 seconds
Started Mar 12 12:51:01 PM PDT 24
Finished Mar 12 12:51:02 PM PDT 24
Peak memory 195476 kb
Host smart-2143fea3-6e4e-4fac-9258-5f9c6df478f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153930555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.4153930555
Directory /workspace/27.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.2659487674
Short name T598
Test name
Test status
Simulation time 33832810 ps
CPU time 0.73 seconds
Started Mar 12 12:50:54 PM PDT 24
Finished Mar 12 12:50:55 PM PDT 24
Peak memory 197748 kb
Host smart-51bbbf10-bf47-44ee-bfb7-2806e59fd6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659487674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.2659487674
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.3046652286
Short name T638
Test name
Test status
Simulation time 55317557 ps
CPU time 0.82 seconds
Started Mar 12 12:51:06 PM PDT 24
Finished Mar 12 12:51:07 PM PDT 24
Peak memory 195536 kb
Host smart-84bc90d2-4c83-469f-8195-e6900f046987
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046652286 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.3046652286
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.1360218009
Short name T302
Test name
Test status
Simulation time 45145963 ps
CPU time 0.61 seconds
Started Mar 12 12:50:55 PM PDT 24
Finished Mar 12 12:50:55 PM PDT 24
Peak memory 195336 kb
Host smart-8664c776-39f0-45a7-bcc9-71c331bd9f85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360218009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.1360218009
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.1851179914
Short name T283
Test name
Test status
Simulation time 667004334 ps
CPU time 0.95 seconds
Started Mar 12 12:51:08 PM PDT 24
Finished Mar 12 12:51:10 PM PDT 24
Peak memory 195424 kb
Host smart-c1155e65-697e-467e-849f-489a916b5d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851179914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.1851179914
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.1359667250
Short name T653
Test name
Test status
Simulation time 43235870 ps
CPU time 0.64 seconds
Started Mar 12 12:50:56 PM PDT 24
Finished Mar 12 12:50:57 PM PDT 24
Peak memory 195400 kb
Host smart-739a645a-8b61-4d7e-904b-bea0aa5719a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359667250 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.1359667250
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.3842329654
Short name T509
Test name
Test status
Simulation time 49368715 ps
CPU time 0.55 seconds
Started Mar 12 12:51:01 PM PDT 24
Finished Mar 12 12:51:01 PM PDT 24
Peak memory 195444 kb
Host smart-9fd21a51-8ad0-4b16-86e5-a41d3314d6c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842329654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.3842329654
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.3593788898
Short name T738
Test name
Test status
Simulation time 75412170 ps
CPU time 0.67 seconds
Started Mar 12 12:51:04 PM PDT 24
Finished Mar 12 12:51:04 PM PDT 24
Peak memory 195880 kb
Host smart-ea04e45a-ca95-444b-9536-22b9f585da5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593788898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_inval
id.3593788898
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_wakeup_race.2552272959
Short name T468
Test name
Test status
Simulation time 132622371 ps
CPU time 0.68 seconds
Started Mar 12 12:51:07 PM PDT 24
Finished Mar 12 12:51:09 PM PDT 24
Peak memory 195304 kb
Host smart-218d3d23-8aab-4fbb-aaf9-c5a1c743e8c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552272959 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_w
akeup_race.2552272959
Directory /workspace/28.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.2998853969
Short name T332
Test name
Test status
Simulation time 112481638 ps
CPU time 0.85 seconds
Started Mar 12 12:50:59 PM PDT 24
Finished Mar 12 12:51:00 PM PDT 24
Peak memory 197740 kb
Host smart-6de574cf-0436-43ec-8d04-b78a4f663faa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998853969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.2998853969
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.1125026683
Short name T51
Test name
Test status
Simulation time 194062950 ps
CPU time 0.79 seconds
Started Mar 12 12:50:57 PM PDT 24
Finished Mar 12 12:50:58 PM PDT 24
Peak memory 205244 kb
Host smart-8ec3184d-a146-4f1a-9b5b-143148ed4b0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125026683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.1125026683
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.429673243
Short name T437
Test name
Test status
Simulation time 882702581 ps
CPU time 3.2 seconds
Started Mar 12 12:51:01 PM PDT 24
Finished Mar 12 12:51:05 PM PDT 24
Peak memory 200696 kb
Host smart-4de57418-dc00-4476-a215-ccccdbc71828
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429673243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.429673243
Directory /workspace/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2473349857
Short name T227
Test name
Test status
Simulation time 785719671 ps
CPU time 2.97 seconds
Started Mar 12 12:50:57 PM PDT 24
Finished Mar 12 12:51:00 PM PDT 24
Peak memory 195928 kb
Host smart-f4909d10-61a4-4121-b142-5e600eccb4a1
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473349857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2473349857
Directory /workspace/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.2205773898
Short name T694
Test name
Test status
Simulation time 135928566 ps
CPU time 0.84 seconds
Started Mar 12 12:51:03 PM PDT 24
Finished Mar 12 12:51:05 PM PDT 24
Peak memory 195340 kb
Host smart-e6a97327-0031-4ebc-8bd2-5e5754528d28
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205773898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2205773898
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.1662816098
Short name T275
Test name
Test status
Simulation time 64883824 ps
CPU time 0.63 seconds
Started Mar 12 12:50:58 PM PDT 24
Finished Mar 12 12:50:59 PM PDT 24
Peak memory 197576 kb
Host smart-2b0b5d22-7c61-4fc0-bd56-b5b7299cb885
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662816098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.1662816098
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup.3964157623
Short name T11
Test name
Test status
Simulation time 322087480 ps
CPU time 0.99 seconds
Started Mar 12 12:51:03 PM PDT 24
Finished Mar 12 12:51:05 PM PDT 24
Peak memory 195348 kb
Host smart-31264b30-0ef7-48e6-bb6c-086f81db6291
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964157623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.3964157623
Directory /workspace/28.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup_reset.3797253867
Short name T632
Test name
Test status
Simulation time 408485343 ps
CPU time 1.02 seconds
Started Mar 12 12:50:54 PM PDT 24
Finished Mar 12 12:50:55 PM PDT 24
Peak memory 197924 kb
Host smart-77a3fe48-b3b4-485f-a174-9d970af8bc11
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797253867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.3797253867
Directory /workspace/28.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.3324617139
Short name T758
Test name
Test status
Simulation time 88655129 ps
CPU time 0.84 seconds
Started Mar 12 12:51:01 PM PDT 24
Finished Mar 12 12:51:02 PM PDT 24
Peak memory 197564 kb
Host smart-6e6f39a9-5efa-402a-9770-b76b77eec078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324617139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.3324617139
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.731687552
Short name T675
Test name
Test status
Simulation time 159430944 ps
CPU time 0.67 seconds
Started Mar 12 12:50:58 PM PDT 24
Finished Mar 12 12:50:59 PM PDT 24
Peak memory 197836 kb
Host smart-7bfa016c-aea2-4a1c-b18a-9fa40af08e96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731687552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_disa
ble_rom_integrity_check.731687552
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.3591491315
Short name T563
Test name
Test status
Simulation time 38626669 ps
CPU time 0.58 seconds
Started Mar 12 12:50:58 PM PDT 24
Finished Mar 12 12:50:59 PM PDT 24
Peak memory 195344 kb
Host smart-93fedd19-3334-4d5e-8b63-0505b4d8b2a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591491315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst
_malfunc.3591491315
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.3742440829
Short name T355
Test name
Test status
Simulation time 426243095 ps
CPU time 0.9 seconds
Started Mar 12 12:50:58 PM PDT 24
Finished Mar 12 12:50:59 PM PDT 24
Peak memory 195404 kb
Host smart-d89c5d62-e03e-4d88-9b86-496e53d0119a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742440829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.3742440829
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.2149932847
Short name T87
Test name
Test status
Simulation time 49019734 ps
CPU time 0.66 seconds
Started Mar 12 12:51:04 PM PDT 24
Finished Mar 12 12:51:05 PM PDT 24
Peak memory 195464 kb
Host smart-60113a37-107f-4a17-abd1-68e7e1212d55
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149932847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.2149932847
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.3807343452
Short name T152
Test name
Test status
Simulation time 52777705 ps
CPU time 0.69 seconds
Started Mar 12 12:50:58 PM PDT 24
Finished Mar 12 12:50:59 PM PDT 24
Peak memory 195412 kb
Host smart-fe8516fd-eba3-44e7-815a-f218690e7aa7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807343452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.3807343452
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.1705148217
Short name T494
Test name
Test status
Simulation time 196865625 ps
CPU time 0.66 seconds
Started Mar 12 12:51:06 PM PDT 24
Finished Mar 12 12:51:07 PM PDT 24
Peak memory 195848 kb
Host smart-c6a734b0-b800-4915-8318-abe073f5bc12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705148217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_inval
id.1705148217
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_wakeup_race.47658711
Short name T485
Test name
Test status
Simulation time 66593802 ps
CPU time 0.68 seconds
Started Mar 12 12:51:03 PM PDT 24
Finished Mar 12 12:51:04 PM PDT 24
Peak memory 195344 kb
Host smart-67c41335-ed13-4204-a657-d75c70fbdf52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47658711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup
_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_wak
eup_race.47658711
Directory /workspace/29.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.4013620674
Short name T606
Test name
Test status
Simulation time 68322313 ps
CPU time 0.84 seconds
Started Mar 12 12:51:07 PM PDT 24
Finished Mar 12 12:51:10 PM PDT 24
Peak memory 197772 kb
Host smart-55d2e798-8dca-41c1-a6ca-f247b06fd37e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013620674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.4013620674
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.4161212513
Short name T605
Test name
Test status
Simulation time 87317078 ps
CPU time 0.98 seconds
Started Mar 12 12:51:01 PM PDT 24
Finished Mar 12 12:51:02 PM PDT 24
Peak memory 196804 kb
Host smart-0882bb66-3965-4e52-b514-f9dfa5291606
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161212513 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.4161212513
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.3105366177
Short name T808
Test name
Test status
Simulation time 210775521 ps
CPU time 0.83 seconds
Started Mar 12 12:51:04 PM PDT 24
Finished Mar 12 12:51:06 PM PDT 24
Peak memory 195352 kb
Host smart-c008a9eb-b341-47ce-9fb1-d511a7eced71
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105366177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_
cm_ctrl_config_regwen.3105366177
Directory /workspace/29.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.640792682
Short name T458
Test name
Test status
Simulation time 2272324473 ps
CPU time 1.97 seconds
Started Mar 12 12:51:00 PM PDT 24
Finished Mar 12 12:51:02 PM PDT 24
Peak memory 201200 kb
Host smart-8c7fc169-c7b5-4090-b45a-55c2cce0f45f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640792682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.640792682
Directory /workspace/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1214485357
Short name T402
Test name
Test status
Simulation time 901249599 ps
CPU time 2.99 seconds
Started Mar 12 12:50:57 PM PDT 24
Finished Mar 12 12:51:00 PM PDT 24
Peak memory 195820 kb
Host smart-f2548c81-d5f2-4eea-a5df-8297310157cb
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214485357 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1214485357
Directory /workspace/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.3793187409
Short name T431
Test name
Test status
Simulation time 78434569 ps
CPU time 1.01 seconds
Started Mar 12 12:50:55 PM PDT 24
Finished Mar 12 12:50:56 PM PDT 24
Peak memory 195336 kb
Host smart-173a5b81-92a5-4625-9e9b-f61f5c941a8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793187409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3793187409
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.3609026801
Short name T77
Test name
Test status
Simulation time 34038823 ps
CPU time 0.65 seconds
Started Mar 12 12:50:57 PM PDT 24
Finished Mar 12 12:50:58 PM PDT 24
Peak memory 195628 kb
Host smart-9fc69356-8158-454d-b9dd-7fd8408e072f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609026801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.3609026801
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_stress_all.1290832101
Short name T80
Test name
Test status
Simulation time 1603197749 ps
CPU time 3.33 seconds
Started Mar 12 12:50:55 PM PDT 24
Finished Mar 12 12:50:58 PM PDT 24
Peak memory 199964 kb
Host smart-4d346a85-b16f-4c09-aeed-1e2942c1063f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290832101 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.1290832101
Directory /workspace/29.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup.2012575041
Short name T844
Test name
Test status
Simulation time 152518912 ps
CPU time 0.66 seconds
Started Mar 12 12:50:56 PM PDT 24
Finished Mar 12 12:50:57 PM PDT 24
Peak memory 195340 kb
Host smart-c48b6f7c-8f54-4b61-9663-21ada74c9dfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012575041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.2012575041
Directory /workspace/29.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup_reset.1277728779
Short name T449
Test name
Test status
Simulation time 168882726 ps
CPU time 1.07 seconds
Started Mar 12 12:51:00 PM PDT 24
Finished Mar 12 12:51:01 PM PDT 24
Peak memory 198064 kb
Host smart-5768898e-00b7-4ab8-b75d-ee80dd32e418
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277728779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.1277728779
Directory /workspace/29.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.3992840856
Short name T52
Test name
Test status
Simulation time 50571650 ps
CPU time 0.68 seconds
Started Mar 12 12:49:32 PM PDT 24
Finished Mar 12 12:49:32 PM PDT 24
Peak memory 195372 kb
Host smart-c7341626-cb88-426c-9633-ec17b40be02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992840856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.3992840856
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2470204615
Short name T843
Test name
Test status
Simulation time 40921894 ps
CPU time 0.59 seconds
Started Mar 12 12:49:45 PM PDT 24
Finished Mar 12 12:49:46 PM PDT 24
Peak memory 195276 kb
Host smart-b71137bb-48f2-4557-a7e6-4686d6e28960
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470204615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.2470204615
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.4186970682
Short name T701
Test name
Test status
Simulation time 166255199 ps
CPU time 0.92 seconds
Started Mar 12 12:49:41 PM PDT 24
Finished Mar 12 12:49:43 PM PDT 24
Peak memory 195416 kb
Host smart-d3f19eee-4b6e-4525-91c5-f3928a5ec375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186970682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.4186970682
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.689070766
Short name T362
Test name
Test status
Simulation time 50984742 ps
CPU time 0.62 seconds
Started Mar 12 12:49:40 PM PDT 24
Finished Mar 12 12:49:41 PM PDT 24
Peak memory 195348 kb
Host smart-6b9d256d-e45a-4746-a10e-05553a92994b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689070766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.689070766
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.2068799854
Short name T453
Test name
Test status
Simulation time 37055760 ps
CPU time 0.61 seconds
Started Mar 12 12:49:46 PM PDT 24
Finished Mar 12 12:49:47 PM PDT 24
Peak memory 195396 kb
Host smart-83c67d85-914c-40e4-92ee-27cdb4fe4466
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068799854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.2068799854
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.1310656640
Short name T682
Test name
Test status
Simulation time 82742630 ps
CPU time 0.65 seconds
Started Mar 12 12:49:48 PM PDT 24
Finished Mar 12 12:49:49 PM PDT 24
Peak memory 195944 kb
Host smart-af3e51dc-df03-421a-be82-077465cf00d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310656640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.1310656640
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_wakeup_race.3615625986
Short name T633
Test name
Test status
Simulation time 372167096 ps
CPU time 0.93 seconds
Started Mar 12 12:49:30 PM PDT 24
Finished Mar 12 12:49:31 PM PDT 24
Peak memory 195344 kb
Host smart-4bbc43db-7cdb-4c27-b8df-1135245705e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615625986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wa
keup_race.3615625986
Directory /workspace/3.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.4217503025
Short name T467
Test name
Test status
Simulation time 115193641 ps
CPU time 0.72 seconds
Started Mar 12 12:49:31 PM PDT 24
Finished Mar 12 12:49:31 PM PDT 24
Peak memory 197628 kb
Host smart-5c4d8aed-62a4-42ac-a073-9aaa27a499c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217503025 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.4217503025
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.886411155
Short name T612
Test name
Test status
Simulation time 126719927 ps
CPU time 0.96 seconds
Started Mar 12 12:49:45 PM PDT 24
Finished Mar 12 12:49:46 PM PDT 24
Peak memory 205224 kb
Host smart-780681ed-023d-4803-b840-4bb9d3ccc38a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886411155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.886411155
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.2276920423
Short name T4
Test name
Test status
Simulation time 458240593 ps
CPU time 1.19 seconds
Started Mar 12 12:49:49 PM PDT 24
Finished Mar 12 12:49:51 PM PDT 24
Peak memory 214332 kb
Host smart-0ba438d7-9978-48a5-b026-d4975bd6d995
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276920423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.2276920423
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.1116925937
Short name T61
Test name
Test status
Simulation time 425954511 ps
CPU time 1.19 seconds
Started Mar 12 12:49:47 PM PDT 24
Finished Mar 12 12:49:49 PM PDT 24
Peak memory 195504 kb
Host smart-f8783109-bc6b-4265-90b5-4f15b7ff5611
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116925937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_c
m_ctrl_config_regwen.1116925937
Directory /workspace/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3948208482
Short name T832
Test name
Test status
Simulation time 867960054 ps
CPU time 3.27 seconds
Started Mar 12 12:49:31 PM PDT 24
Finished Mar 12 12:49:35 PM PDT 24
Peak memory 201156 kb
Host smart-59191f37-f42e-44ed-a265-9c8d4050bc46
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948208482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3948208482
Directory /workspace/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2591363008
Short name T243
Test name
Test status
Simulation time 1018684833 ps
CPU time 2.3 seconds
Started Mar 12 12:49:32 PM PDT 24
Finished Mar 12 12:49:34 PM PDT 24
Peak memory 200300 kb
Host smart-cb7e3e07-8bb4-4fa6-a6b5-307fccacb265
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591363008 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2591363008
Directory /workspace/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2370027624
Short name T296
Test name
Test status
Simulation time 143428864 ps
CPU time 0.85 seconds
Started Mar 12 12:49:43 PM PDT 24
Finished Mar 12 12:49:44 PM PDT 24
Peak memory 195344 kb
Host smart-ed4156a6-65e3-4b7a-97f1-9886a5059a15
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370027624 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2370027624
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.529510173
Short name T459
Test name
Test status
Simulation time 29952530 ps
CPU time 0.68 seconds
Started Mar 12 12:49:36 PM PDT 24
Finished Mar 12 12:49:36 PM PDT 24
Peak memory 195368 kb
Host smart-a5f3037b-1977-4280-9048-f00f4f04c551
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529510173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.529510173
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup.179502176
Short name T432
Test name
Test status
Simulation time 137757836 ps
CPU time 0.67 seconds
Started Mar 12 12:49:34 PM PDT 24
Finished Mar 12 12:49:34 PM PDT 24
Peak memory 195336 kb
Host smart-c189f1d3-0c9a-42b1-8201-f8f6e6ad5d7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179502176 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.179502176
Directory /workspace/3.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup_reset.3009636509
Short name T519
Test name
Test status
Simulation time 81900373 ps
CPU time 0.59 seconds
Started Mar 12 12:49:32 PM PDT 24
Finished Mar 12 12:49:33 PM PDT 24
Peak memory 195616 kb
Host smart-477b9edb-8b9a-4950-8c2f-4d6986617b44
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009636509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.3009636509
Directory /workspace/3.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.3967667099
Short name T665
Test name
Test status
Simulation time 63140095 ps
CPU time 0.64 seconds
Started Mar 12 12:51:05 PM PDT 24
Finished Mar 12 12:51:07 PM PDT 24
Peak memory 195336 kb
Host smart-cdb66ffb-33c6-4861-b59b-ac6a733942f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967667099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.3967667099
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.3032997420
Short name T507
Test name
Test status
Simulation time 52710910 ps
CPU time 0.83 seconds
Started Mar 12 12:51:17 PM PDT 24
Finished Mar 12 12:51:18 PM PDT 24
Peak memory 195472 kb
Host smart-700e3347-26da-452e-9e92-6d5562eb56f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032997420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_dis
able_rom_integrity_check.3032997420
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.3979007256
Short name T587
Test name
Test status
Simulation time 40945580 ps
CPU time 0.61 seconds
Started Mar 12 12:51:05 PM PDT 24
Finished Mar 12 12:51:06 PM PDT 24
Peak memory 195304 kb
Host smart-e6522f80-4579-44f7-8f08-0b66988a4db8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979007256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.3979007256
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.4053807415
Short name T524
Test name
Test status
Simulation time 163939308 ps
CPU time 0.96 seconds
Started Mar 12 12:51:08 PM PDT 24
Finished Mar 12 12:51:10 PM PDT 24
Peak memory 195448 kb
Host smart-70086c43-839d-43ad-bd2f-f192457a4953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053807415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.4053807415
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.2025231112
Short name T702
Test name
Test status
Simulation time 76945611 ps
CPU time 0.61 seconds
Started Mar 12 12:51:11 PM PDT 24
Finished Mar 12 12:51:12 PM PDT 24
Peak memory 195384 kb
Host smart-c224851d-e4cf-46e0-a28d-d53812c43aca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025231112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.2025231112
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.3909125838
Short name T273
Test name
Test status
Simulation time 37651223 ps
CPU time 0.62 seconds
Started Mar 12 12:51:07 PM PDT 24
Finished Mar 12 12:51:09 PM PDT 24
Peak memory 195372 kb
Host smart-0938900c-dfa4-4cec-9507-7ecd07dc3d95
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909125838 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.3909125838
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.4066630257
Short name T53
Test name
Test status
Simulation time 57114587 ps
CPU time 0.69 seconds
Started Mar 12 12:51:12 PM PDT 24
Finished Mar 12 12:51:13 PM PDT 24
Peak memory 195816 kb
Host smart-cef3896d-2e2d-4c4c-b5a9-68f0a392f107
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066630257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.4066630257
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.2997574366
Short name T441
Test name
Test status
Simulation time 76343977 ps
CPU time 0.7 seconds
Started Mar 12 12:50:55 PM PDT 24
Finished Mar 12 12:50:56 PM PDT 24
Peak memory 196688 kb
Host smart-24551e5f-837e-42d3-aa70-751a8e7334ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997574366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.2997574366
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.2014707915
Short name T581
Test name
Test status
Simulation time 148599825 ps
CPU time 0.8 seconds
Started Mar 12 12:51:00 PM PDT 24
Finished Mar 12 12:51:06 PM PDT 24
Peak memory 205884 kb
Host smart-dc17fbff-dd0b-4368-bebc-ba5fbef57b10
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014707915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.2014707915
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.3348998298
Short name T705
Test name
Test status
Simulation time 176359376 ps
CPU time 0.77 seconds
Started Mar 12 12:51:05 PM PDT 24
Finished Mar 12 12:51:06 PM PDT 24
Peak memory 195352 kb
Host smart-90166487-51a2-4ca9-85c7-f87613811c5e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348998298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_
cm_ctrl_config_regwen.3348998298
Directory /workspace/30.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1579674472
Short name T595
Test name
Test status
Simulation time 825387035 ps
CPU time 2.26 seconds
Started Mar 12 12:51:05 PM PDT 24
Finished Mar 12 12:51:08 PM PDT 24
Peak memory 201112 kb
Host smart-a02569a9-ad6f-46ef-b3f3-cda21dd9dd92
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579674472 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1579674472
Directory /workspace/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3331455845
Short name T847
Test name
Test status
Simulation time 1025076286 ps
CPU time 2.09 seconds
Started Mar 12 12:51:05 PM PDT 24
Finished Mar 12 12:51:07 PM PDT 24
Peak memory 195952 kb
Host smart-9899ca94-1773-434a-9655-82d73f373dac
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331455845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3331455845
Directory /workspace/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.630384096
Short name T443
Test name
Test status
Simulation time 64023800 ps
CPU time 0.9 seconds
Started Mar 12 12:51:06 PM PDT 24
Finished Mar 12 12:51:07 PM PDT 24
Peak memory 195344 kb
Host smart-38ec6c90-fa4d-48c3-b578-95a0b7a8bb69
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630384096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig_
mubi.630384096
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.3280850885
Short name T636
Test name
Test status
Simulation time 34178931 ps
CPU time 0.66 seconds
Started Mar 12 12:51:03 PM PDT 24
Finished Mar 12 12:51:04 PM PDT 24
Peak memory 195588 kb
Host smart-383ffb2f-55de-4b87-b08e-e582cd592279
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280850885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.3280850885
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup_reset.531010519
Short name T277
Test name
Test status
Simulation time 366614965 ps
CPU time 1.1 seconds
Started Mar 12 12:51:02 PM PDT 24
Finished Mar 12 12:51:03 PM PDT 24
Peak memory 197920 kb
Host smart-da0e8d43-cf0d-424a-b526-91bc5964d132
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531010519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.531010519
Directory /workspace/30.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.3601220657
Short name T271
Test name
Test status
Simulation time 28582194 ps
CPU time 0.64 seconds
Started Mar 12 12:51:01 PM PDT 24
Finished Mar 12 12:51:03 PM PDT 24
Peak memory 195308 kb
Host smart-da24cf35-4c38-4972-ba3d-804a013515c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601220657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.3601220657
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.1952756042
Short name T769
Test name
Test status
Simulation time 50546653 ps
CPU time 0.68 seconds
Started Mar 12 12:51:06 PM PDT 24
Finished Mar 12 12:51:07 PM PDT 24
Peak memory 197664 kb
Host smart-eb54b0a4-bf04-4b54-9a66-e4dfbd8e6b86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952756042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_dis
able_rom_integrity_check.1952756042
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.1473436327
Short name T284
Test name
Test status
Simulation time 38037358 ps
CPU time 0.61 seconds
Started Mar 12 12:51:20 PM PDT 24
Finished Mar 12 12:51:20 PM PDT 24
Peak memory 195336 kb
Host smart-3f4408e8-fa1c-45d5-a4c1-dcd6441a3a47
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473436327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.1473436327
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.2929340625
Short name T607
Test name
Test status
Simulation time 159200528 ps
CPU time 0.94 seconds
Started Mar 12 12:51:20 PM PDT 24
Finished Mar 12 12:51:21 PM PDT 24
Peak memory 195432 kb
Host smart-349ca8bd-a2a9-4214-829a-2a78e88f8b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929340625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.2929340625
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.2016210401
Short name T823
Test name
Test status
Simulation time 51431661 ps
CPU time 0.63 seconds
Started Mar 12 12:51:27 PM PDT 24
Finished Mar 12 12:51:28 PM PDT 24
Peak memory 195388 kb
Host smart-6b26c19c-cdb3-4c99-a14c-0935f377a910
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016210401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.2016210401
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.884525966
Short name T169
Test name
Test status
Simulation time 77306014 ps
CPU time 0.6 seconds
Started Mar 12 12:51:04 PM PDT 24
Finished Mar 12 12:51:05 PM PDT 24
Peak memory 195384 kb
Host smart-22371f8c-c2e1-47e8-94cd-acd6d1299e6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884525966 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.884525966
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.61801136
Short name T760
Test name
Test status
Simulation time 67134829 ps
CPU time 0.67 seconds
Started Mar 12 12:51:03 PM PDT 24
Finished Mar 12 12:51:04 PM PDT 24
Peak memory 195928 kb
Host smart-8bf482ad-8641-4a01-9e8f-4c928b46f3e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61801136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_invalid
.61801136
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_wakeup_race.634441415
Short name T867
Test name
Test status
Simulation time 637295312 ps
CPU time 0.9 seconds
Started Mar 12 12:51:08 PM PDT 24
Finished Mar 12 12:51:10 PM PDT 24
Peak memory 195312 kb
Host smart-50a4c75c-62cd-4b75-878f-ccd4d0ca9c55
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634441415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_wa
keup_race.634441415
Directory /workspace/31.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/31.pwrmgr_reset.3216815302
Short name T448
Test name
Test status
Simulation time 128869845 ps
CPU time 0.86 seconds
Started Mar 12 12:51:06 PM PDT 24
Finished Mar 12 12:51:08 PM PDT 24
Peak memory 198984 kb
Host smart-8ee859df-ebc9-4176-a4ae-baf142d66139
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216815302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.3216815302
Directory /workspace/31.pwrmgr_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.2648210947
Short name T765
Test name
Test status
Simulation time 157418033 ps
CPU time 0.78 seconds
Started Mar 12 12:51:03 PM PDT 24
Finished Mar 12 12:51:05 PM PDT 24
Peak memory 206044 kb
Host smart-4a809c18-a23e-4920-8aad-1fd00c5bbe9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648210947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.2648210947
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.3118482118
Short name T215
Test name
Test status
Simulation time 135916484 ps
CPU time 0.86 seconds
Started Mar 12 12:51:16 PM PDT 24
Finished Mar 12 12:51:17 PM PDT 24
Peak memory 195408 kb
Host smart-61fa716f-a3cd-456d-9e32-de658ed0e916
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118482118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_
cm_ctrl_config_regwen.3118482118
Directory /workspace/31.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2649210241
Short name T621
Test name
Test status
Simulation time 806089607 ps
CPU time 2.23 seconds
Started Mar 12 12:51:14 PM PDT 24
Finished Mar 12 12:51:17 PM PDT 24
Peak memory 201076 kb
Host smart-43766545-3cd3-445b-885d-ba81920a7620
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649210241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2649210241
Directory /workspace/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.470735346
Short name T825
Test name
Test status
Simulation time 972978542 ps
CPU time 2.6 seconds
Started Mar 12 12:51:15 PM PDT 24
Finished Mar 12 12:51:18 PM PDT 24
Peak memory 195884 kb
Host smart-c9e3a21f-b453-4541-89e3-8558c3826fa3
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470735346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.470735346
Directory /workspace/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.3076872244
Short name T339
Test name
Test status
Simulation time 282947046 ps
CPU time 0.81 seconds
Started Mar 12 12:51:17 PM PDT 24
Finished Mar 12 12:51:18 PM PDT 24
Peak memory 195304 kb
Host smart-0763ddaf-9134-4149-bf65-2f55fa3bd29d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076872244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3076872244
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.684629510
Short name T772
Test name
Test status
Simulation time 31028507 ps
CPU time 0.65 seconds
Started Mar 12 12:51:05 PM PDT 24
Finished Mar 12 12:51:07 PM PDT 24
Peak memory 195592 kb
Host smart-63b9137a-4de7-46f6-8652-b07a594dad07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684629510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.684629510
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_stress_all.1358079239
Short name T462
Test name
Test status
Simulation time 533864960 ps
CPU time 1.79 seconds
Started Mar 12 12:51:10 PM PDT 24
Finished Mar 12 12:51:17 PM PDT 24
Peak memory 195864 kb
Host smart-2b75aad1-513c-4c0e-8986-26492e65bfeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358079239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.1358079239
Directory /workspace/31.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup.3583409535
Short name T366
Test name
Test status
Simulation time 153513536 ps
CPU time 0.99 seconds
Started Mar 12 12:51:03 PM PDT 24
Finished Mar 12 12:51:04 PM PDT 24
Peak memory 195308 kb
Host smart-3524b2a9-6174-4a87-a97c-f43e43946b2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583409535 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.3583409535
Directory /workspace/31.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup_reset.1844114465
Short name T418
Test name
Test status
Simulation time 43468102 ps
CPU time 0.66 seconds
Started Mar 12 12:51:19 PM PDT 24
Finished Mar 12 12:51:20 PM PDT 24
Peak memory 197736 kb
Host smart-866954bc-6da4-4838-a26c-97818fd9e8c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844114465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.1844114465
Directory /workspace/31.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.3910582220
Short name T186
Test name
Test status
Simulation time 61490891 ps
CPU time 0.64 seconds
Started Mar 12 12:51:06 PM PDT 24
Finished Mar 12 12:51:07 PM PDT 24
Peak memory 195332 kb
Host smart-27b28ad8-d6b8-4bb2-8398-3cacedecda1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910582220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.3910582220
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.421822482
Short name T349
Test name
Test status
Simulation time 51861116 ps
CPU time 0.8 seconds
Started Mar 12 12:51:12 PM PDT 24
Finished Mar 12 12:51:13 PM PDT 24
Peak memory 197640 kb
Host smart-a7259ce1-a346-4219-b853-5fd43c774d67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421822482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_disa
ble_rom_integrity_check.421822482
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.2201012400
Short name T393
Test name
Test status
Simulation time 29345987 ps
CPU time 0.64 seconds
Started Mar 12 12:51:18 PM PDT 24
Finished Mar 12 12:51:19 PM PDT 24
Peak memory 195340 kb
Host smart-a501a8f7-5692-4d3b-a293-7dbc834eabf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201012400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst
_malfunc.2201012400
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.2983392353
Short name T744
Test name
Test status
Simulation time 158588227 ps
CPU time 0.98 seconds
Started Mar 12 12:51:04 PM PDT 24
Finished Mar 12 12:51:07 PM PDT 24
Peak memory 195364 kb
Host smart-9353e381-813d-4dbc-9cd9-e76105e1748f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983392353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.2983392353
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.2073905937
Short name T751
Test name
Test status
Simulation time 61124975 ps
CPU time 0.6 seconds
Started Mar 12 12:51:05 PM PDT 24
Finished Mar 12 12:51:06 PM PDT 24
Peak memory 195348 kb
Host smart-c2ca8276-3622-4aee-aea1-ccc9348b7450
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073905937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.2073905937
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.3585075591
Short name T406
Test name
Test status
Simulation time 23434568 ps
CPU time 0.63 seconds
Started Mar 12 12:51:24 PM PDT 24
Finished Mar 12 12:51:25 PM PDT 24
Peak memory 195436 kb
Host smart-c64f061a-253c-40de-b17f-aaa0f35d411e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585075591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.3585075591
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_wakeup_race.3514114237
Short name T328
Test name
Test status
Simulation time 414607923 ps
CPU time 1 seconds
Started Mar 12 12:51:24 PM PDT 24
Finished Mar 12 12:51:26 PM PDT 24
Peak memory 195388 kb
Host smart-608f8635-587d-4e08-a4cc-d6ac08e45734
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514114237 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_w
akeup_race.3514114237
Directory /workspace/32.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.92261644
Short name T425
Test name
Test status
Simulation time 65157815 ps
CPU time 0.93 seconds
Started Mar 12 12:51:19 PM PDT 24
Finished Mar 12 12:51:20 PM PDT 24
Peak memory 197680 kb
Host smart-9c5f7a96-7ac1-4619-a3ad-f7dde6870060
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92261644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.92261644
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.1539349279
Short name T49
Test name
Test status
Simulation time 177996761 ps
CPU time 0.78 seconds
Started Mar 12 12:51:07 PM PDT 24
Finished Mar 12 12:51:09 PM PDT 24
Peak memory 205268 kb
Host smart-5125bd89-4a1f-460e-a65e-ab0a308ca837
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539349279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.1539349279
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3053663468
Short name T538
Test name
Test status
Simulation time 789138646 ps
CPU time 3.07 seconds
Started Mar 12 12:51:12 PM PDT 24
Finished Mar 12 12:51:15 PM PDT 24
Peak memory 201120 kb
Host smart-345c924b-7552-4a00-ab71-ad3a585a91e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053663468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3053663468
Directory /workspace/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2253749463
Short name T196
Test name
Test status
Simulation time 1261645459 ps
CPU time 2.13 seconds
Started Mar 12 12:51:07 PM PDT 24
Finished Mar 12 12:51:10 PM PDT 24
Peak memory 195856 kb
Host smart-5e5e48a6-a6aa-42fb-81f6-9643bcf27df9
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253749463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2253749463
Directory /workspace/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.1015673369
Short name T316
Test name
Test status
Simulation time 94515345 ps
CPU time 0.95 seconds
Started Mar 12 12:51:10 PM PDT 24
Finished Mar 12 12:51:12 PM PDT 24
Peak memory 195368 kb
Host smart-44b3071c-fe8e-4f45-ad61-e054b901e6b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015673369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1015673369
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.2582517584
Short name T699
Test name
Test status
Simulation time 30294512 ps
CPU time 0.71 seconds
Started Mar 12 12:51:16 PM PDT 24
Finished Mar 12 12:51:18 PM PDT 24
Peak memory 197784 kb
Host smart-e00c699f-9d76-4947-b5fe-f0e37bea2d2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582517584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.2582517584
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup.3813812862
Short name T361
Test name
Test status
Simulation time 44733025 ps
CPU time 0.65 seconds
Started Mar 12 12:51:22 PM PDT 24
Finished Mar 12 12:51:23 PM PDT 24
Peak memory 195336 kb
Host smart-6bf8c03a-ed2d-435c-b103-f50989f542d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813812862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.3813812862
Directory /workspace/32.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup_reset.4115788469
Short name T637
Test name
Test status
Simulation time 342553111 ps
CPU time 0.96 seconds
Started Mar 12 12:51:07 PM PDT 24
Finished Mar 12 12:51:10 PM PDT 24
Peak memory 199216 kb
Host smart-1a5262b7-22fa-4255-b16a-fec616165dc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115788469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.4115788469
Directory /workspace/32.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.4007291219
Short name T803
Test name
Test status
Simulation time 41851819 ps
CPU time 0.67 seconds
Started Mar 12 12:51:25 PM PDT 24
Finished Mar 12 12:51:25 PM PDT 24
Peak memory 197520 kb
Host smart-2698b832-7ef9-4e4e-a385-918a3aa8d1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007291219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.4007291219
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.1628536461
Short name T599
Test name
Test status
Simulation time 60147377 ps
CPU time 0.8 seconds
Started Mar 12 12:51:23 PM PDT 24
Finished Mar 12 12:51:24 PM PDT 24
Peak memory 197512 kb
Host smart-f5d87d0e-6709-4ebe-b152-0acd41b5486a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628536461 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.1628536461
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.4029732157
Short name T589
Test name
Test status
Simulation time 74819364 ps
CPU time 0.57 seconds
Started Mar 12 12:51:20 PM PDT 24
Finished Mar 12 12:51:20 PM PDT 24
Peak memory 195364 kb
Host smart-020c711d-b1cf-48ba-b3df-c6f85ee45d7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029732157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.4029732157
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.1051493420
Short name T480
Test name
Test status
Simulation time 165827767 ps
CPU time 0.97 seconds
Started Mar 12 12:51:20 PM PDT 24
Finished Mar 12 12:51:21 PM PDT 24
Peak memory 195432 kb
Host smart-b67b7b90-3371-469e-a926-dcd2eca5ca15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051493420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.1051493420
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.614405409
Short name T510
Test name
Test status
Simulation time 133055041 ps
CPU time 0.56 seconds
Started Mar 12 12:51:31 PM PDT 24
Finished Mar 12 12:51:31 PM PDT 24
Peak memory 195384 kb
Host smart-247e7043-1c71-4252-ae0c-2743b3cbf874
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614405409 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.614405409
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.1881166581
Short name T389
Test name
Test status
Simulation time 51214757 ps
CPU time 0.59 seconds
Started Mar 12 12:51:09 PM PDT 24
Finished Mar 12 12:51:16 PM PDT 24
Peak memory 195440 kb
Host smart-a4902066-f9f4-4953-8546-b81bf2f0108c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881166581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.1881166581
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.2802031367
Short name T489
Test name
Test status
Simulation time 93055376 ps
CPU time 0.68 seconds
Started Mar 12 12:51:29 PM PDT 24
Finished Mar 12 12:51:30 PM PDT 24
Peak memory 195912 kb
Host smart-93f1e8b8-0b4d-4d60-bd07-375bd6888014
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802031367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.2802031367
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.1582488975
Short name T866
Test name
Test status
Simulation time 122246222 ps
CPU time 0.78 seconds
Started Mar 12 12:51:08 PM PDT 24
Finished Mar 12 12:51:10 PM PDT 24
Peak memory 197628 kb
Host smart-5c05ca5c-cf9f-49a5-b942-300174c58273
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582488975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.1582488975
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.3558803288
Short name T191
Test name
Test status
Simulation time 155381109 ps
CPU time 0.81 seconds
Started Mar 12 12:51:26 PM PDT 24
Finished Mar 12 12:51:27 PM PDT 24
Peak memory 205280 kb
Host smart-2d57f273-7003-4be4-a060-ff81a588cdad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558803288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.3558803288
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.596418344
Short name T658
Test name
Test status
Simulation time 113825328 ps
CPU time 0.79 seconds
Started Mar 12 12:51:20 PM PDT 24
Finished Mar 12 12:51:21 PM PDT 24
Peak memory 195440 kb
Host smart-9fb6c282-b67f-4683-9e22-7c7954d6109e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596418344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_c
m_ctrl_config_regwen.596418344
Directory /workspace/33.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1749952526
Short name T127
Test name
Test status
Simulation time 1049485603 ps
CPU time 2.44 seconds
Started Mar 12 12:51:06 PM PDT 24
Finished Mar 12 12:51:09 PM PDT 24
Peak memory 201032 kb
Host smart-1279b0a2-30e1-46dd-873a-ad5e3aa73f5f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749952526 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1749952526
Directory /workspace/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3243330052
Short name T270
Test name
Test status
Simulation time 916116636 ps
CPU time 3.24 seconds
Started Mar 12 12:51:12 PM PDT 24
Finished Mar 12 12:51:16 PM PDT 24
Peak memory 195728 kb
Host smart-915d15fa-b448-46ec-9c29-0d737f07509b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243330052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3243330052
Directory /workspace/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.830663005
Short name T380
Test name
Test status
Simulation time 90049017 ps
CPU time 0.84 seconds
Started Mar 12 12:51:16 PM PDT 24
Finished Mar 12 12:51:18 PM PDT 24
Peak memory 195304 kb
Host smart-855c0af9-1003-4765-b535-e4fe7d83b025
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830663005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig_
mubi.830663005
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.554251469
Short name T739
Test name
Test status
Simulation time 29234080 ps
CPU time 0.65 seconds
Started Mar 12 12:51:23 PM PDT 24
Finished Mar 12 12:51:24 PM PDT 24
Peak memory 195596 kb
Host smart-3d8553df-5449-4401-a0b5-c0dfb3d6a2d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554251469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.554251469
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_wakeup_reset.3238981497
Short name T529
Test name
Test status
Simulation time 270935666 ps
CPU time 1.19 seconds
Started Mar 12 12:51:22 PM PDT 24
Finished Mar 12 12:51:23 PM PDT 24
Peak memory 199244 kb
Host smart-c7d959e2-ec3d-45b4-bf1b-ecc939ae4716
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238981497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.3238981497
Directory /workspace/33.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.2805389178
Short name T763
Test name
Test status
Simulation time 18659117 ps
CPU time 0.63 seconds
Started Mar 12 12:51:11 PM PDT 24
Finished Mar 12 12:51:16 PM PDT 24
Peak memory 197524 kb
Host smart-6e5f42f2-a7a5-4c3d-a53e-a4729aa383c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805389178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.2805389178
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.36326019
Short name T676
Test name
Test status
Simulation time 132423446 ps
CPU time 0.67 seconds
Started Mar 12 12:51:20 PM PDT 24
Finished Mar 12 12:51:21 PM PDT 24
Peak memory 195476 kb
Host smart-330af730-d467-4ce0-aaec-022346bdbd4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36326019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_disab
le_rom_integrity_check.36326019
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.23114104
Short name T167
Test name
Test status
Simulation time 29789752 ps
CPU time 0.6 seconds
Started Mar 12 12:51:24 PM PDT 24
Finished Mar 12 12:51:24 PM PDT 24
Peak memory 195320 kb
Host smart-bdaef496-a5e5-4e41-bb12-736ffb75b3eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23114104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst_m
alfunc.23114104
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.3865394521
Short name T666
Test name
Test status
Simulation time 318937892 ps
CPU time 0.99 seconds
Started Mar 12 12:51:10 PM PDT 24
Finished Mar 12 12:51:12 PM PDT 24
Peak memory 195440 kb
Host smart-25c14515-52a2-4545-a46e-0a41d1444d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865394521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.3865394521
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.2336851971
Short name T175
Test name
Test status
Simulation time 41730952 ps
CPU time 0.64 seconds
Started Mar 12 12:51:20 PM PDT 24
Finished Mar 12 12:51:21 PM PDT 24
Peak memory 195372 kb
Host smart-77092f15-e090-4363-8fc3-2ee1e80e658f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336851971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.2336851971
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.296053431
Short name T367
Test name
Test status
Simulation time 37755683 ps
CPU time 0.65 seconds
Started Mar 12 12:51:06 PM PDT 24
Finished Mar 12 12:51:07 PM PDT 24
Peak memory 195396 kb
Host smart-43357ea8-6253-4d26-9503-d4c568504f73
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296053431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.296053431
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.3516404242
Short name T802
Test name
Test status
Simulation time 46548451 ps
CPU time 0.67 seconds
Started Mar 12 12:51:07 PM PDT 24
Finished Mar 12 12:51:09 PM PDT 24
Peak memory 195872 kb
Host smart-615fb5d6-7f00-4d63-898e-da3f510a9df2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516404242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.3516404242
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.3643768681
Short name T762
Test name
Test status
Simulation time 64253288 ps
CPU time 0.94 seconds
Started Mar 12 12:51:14 PM PDT 24
Finished Mar 12 12:51:15 PM PDT 24
Peak memory 197576 kb
Host smart-7dfea8b6-c2d7-4af0-a9e3-70dad936f8d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643768681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.3643768681
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.1850792681
Short name T856
Test name
Test status
Simulation time 98825745 ps
CPU time 1.02 seconds
Started Mar 12 12:51:06 PM PDT 24
Finished Mar 12 12:51:08 PM PDT 24
Peak memory 205296 kb
Host smart-29af8840-f8e9-4086-8c9b-4c21901e4033
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850792681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.1850792681
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.208999759
Short name T562
Test name
Test status
Simulation time 36022059 ps
CPU time 0.62 seconds
Started Mar 12 12:51:37 PM PDT 24
Finished Mar 12 12:51:38 PM PDT 24
Peak memory 195408 kb
Host smart-f334b455-4ba3-468b-96a8-e2feafb1842b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208999759 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_c
m_ctrl_config_regwen.208999759
Directory /workspace/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2843549889
Short name T639
Test name
Test status
Simulation time 792867817 ps
CPU time 3.14 seconds
Started Mar 12 12:51:15 PM PDT 24
Finished Mar 12 12:51:18 PM PDT 24
Peak memory 201124 kb
Host smart-dd8e1cda-4036-4537-8093-8e9851cbe32c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843549889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2843549889
Directory /workspace/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2461334958
Short name T767
Test name
Test status
Simulation time 1294788423 ps
CPU time 2.32 seconds
Started Mar 12 12:51:27 PM PDT 24
Finished Mar 12 12:51:30 PM PDT 24
Peak memory 195884 kb
Host smart-94c1b73c-275e-40d3-b402-5264605754dd
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461334958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2461334958
Directory /workspace/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.282545384
Short name T835
Test name
Test status
Simulation time 108779672 ps
CPU time 0.87 seconds
Started Mar 12 12:51:10 PM PDT 24
Finished Mar 12 12:51:11 PM PDT 24
Peak memory 195376 kb
Host smart-e7cf3c99-bcd1-4701-b80d-a54222e6b1e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282545384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig_
mubi.282545384
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.2385936667
Short name T842
Test name
Test status
Simulation time 62362293 ps
CPU time 0.6 seconds
Started Mar 12 12:51:18 PM PDT 24
Finished Mar 12 12:51:19 PM PDT 24
Peak memory 195436 kb
Host smart-f0c1eef2-186a-41e1-9ce3-e40e091e441e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385936667 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.2385936667
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup_reset.2542101514
Short name T775
Test name
Test status
Simulation time 422802805 ps
CPU time 1.11 seconds
Started Mar 12 12:51:29 PM PDT 24
Finished Mar 12 12:51:30 PM PDT 24
Peak memory 200360 kb
Host smart-6bbacfd4-4fd5-4fe0-a290-3be2ac26fdc5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542101514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.2542101514
Directory /workspace/34.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.3704388250
Short name T531
Test name
Test status
Simulation time 132253697 ps
CPU time 0.75 seconds
Started Mar 12 12:51:06 PM PDT 24
Finished Mar 12 12:51:08 PM PDT 24
Peak memory 195336 kb
Host smart-e812c411-0dd7-48be-8ed9-dda93827bc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704388250 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.3704388250
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.2725294794
Short name T706
Test name
Test status
Simulation time 69828436 ps
CPU time 0.84 seconds
Started Mar 12 12:51:20 PM PDT 24
Finished Mar 12 12:51:21 PM PDT 24
Peak memory 195432 kb
Host smart-71e9cf53-41ce-4aee-b3b5-511c53ffd0ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725294794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_dis
able_rom_integrity_check.2725294794
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.788234318
Short name T687
Test name
Test status
Simulation time 30453587 ps
CPU time 0.62 seconds
Started Mar 12 12:51:13 PM PDT 24
Finished Mar 12 12:51:14 PM PDT 24
Peak memory 195256 kb
Host smart-16dbf051-2e44-43f8-bbee-4437e850bbe1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788234318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_
malfunc.788234318
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.4109289604
Short name T229
Test name
Test status
Simulation time 636912013 ps
CPU time 0.92 seconds
Started Mar 12 12:51:10 PM PDT 24
Finished Mar 12 12:51:11 PM PDT 24
Peak memory 195428 kb
Host smart-ebe5ad70-4f50-46af-abc4-3580ab594ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109289604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.4109289604
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.2653665886
Short name T833
Test name
Test status
Simulation time 74557554 ps
CPU time 0.61 seconds
Started Mar 12 12:51:08 PM PDT 24
Finished Mar 12 12:51:10 PM PDT 24
Peak memory 195400 kb
Host smart-edbfdd27-7341-401a-8456-140bdd0d9b12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653665886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.2653665886
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.3514732191
Short name T642
Test name
Test status
Simulation time 75218264 ps
CPU time 0.58 seconds
Started Mar 12 12:51:24 PM PDT 24
Finished Mar 12 12:51:25 PM PDT 24
Peak memory 195396 kb
Host smart-74c6c2b9-04b6-4320-876f-cdca5d355bda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514732191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.3514732191
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.818201366
Short name T183
Test name
Test status
Simulation time 274388079 ps
CPU time 0.67 seconds
Started Mar 12 12:51:18 PM PDT 24
Finished Mar 12 12:51:19 PM PDT 24
Peak memory 195904 kb
Host smart-d6a2d4aa-e4d0-44e6-99f9-e367f24f65fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818201366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_invali
d.818201366
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_wakeup_race.2609031403
Short name T863
Test name
Test status
Simulation time 254896751 ps
CPU time 0.8 seconds
Started Mar 12 12:51:05 PM PDT 24
Finished Mar 12 12:51:06 PM PDT 24
Peak memory 195348 kb
Host smart-f6252db3-f752-42a2-b46e-c69fbff60b4c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609031403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_w
akeup_race.2609031403
Directory /workspace/35.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.916604718
Short name T572
Test name
Test status
Simulation time 71444451 ps
CPU time 0.84 seconds
Started Mar 12 12:51:23 PM PDT 24
Finished Mar 12 12:51:23 PM PDT 24
Peak memory 197656 kb
Host smart-64b106af-b66e-4237-b358-4b517cd79e0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916604718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.916604718
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.127018189
Short name T530
Test name
Test status
Simulation time 113596390 ps
CPU time 0.81 seconds
Started Mar 12 12:51:16 PM PDT 24
Finished Mar 12 12:51:17 PM PDT 24
Peak memory 205984 kb
Host smart-f8034dcf-4ad0-4d42-b421-1c683dbaeb3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127018189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.127018189
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3954617208
Short name T232
Test name
Test status
Simulation time 1005635422 ps
CPU time 1.94 seconds
Started Mar 12 12:51:28 PM PDT 24
Finished Mar 12 12:51:31 PM PDT 24
Peak memory 201188 kb
Host smart-7f3c7249-fa2d-494e-b94e-6f64a5d66074
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954617208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3954617208
Directory /workspace/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3996839697
Short name T626
Test name
Test status
Simulation time 868840050 ps
CPU time 3.21 seconds
Started Mar 12 12:51:05 PM PDT 24
Finished Mar 12 12:51:10 PM PDT 24
Peak memory 195800 kb
Host smart-648c3dd4-d8df-4a60-b431-a94fd8899488
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996839697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3996839697
Directory /workspace/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.1327330516
Short name T439
Test name
Test status
Simulation time 74499448 ps
CPU time 0.91 seconds
Started Mar 12 12:51:17 PM PDT 24
Finished Mar 12 12:51:23 PM PDT 24
Peak memory 195304 kb
Host smart-cf2774a3-f33a-4ed0-82ac-9034a03ca2ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327330516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1327330516
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.3845526910
Short name T33
Test name
Test status
Simulation time 47134020 ps
CPU time 0.67 seconds
Started Mar 12 12:51:20 PM PDT 24
Finished Mar 12 12:51:21 PM PDT 24
Peak memory 195608 kb
Host smart-fb1c30dd-b525-40c0-aa69-15c71f437873
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845526910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.3845526910
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup.618711116
Short name T294
Test name
Test status
Simulation time 40126055 ps
CPU time 0.66 seconds
Started Mar 12 12:51:12 PM PDT 24
Finished Mar 12 12:51:13 PM PDT 24
Peak memory 195272 kb
Host smart-cc1b9d19-ec30-41ea-9475-e5eb2eac86ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618711116 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.618711116
Directory /workspace/35.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup_reset.2221320334
Short name T212
Test name
Test status
Simulation time 146130562 ps
CPU time 0.74 seconds
Started Mar 12 12:51:13 PM PDT 24
Finished Mar 12 12:51:15 PM PDT 24
Peak memory 198800 kb
Host smart-cf8bbf24-b3cd-47fd-bbd0-112ad978bb2c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221320334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.2221320334
Directory /workspace/35.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.435621005
Short name T725
Test name
Test status
Simulation time 47501318 ps
CPU time 0.61 seconds
Started Mar 12 12:51:23 PM PDT 24
Finished Mar 12 12:51:24 PM PDT 24
Peak memory 195228 kb
Host smart-21584541-82e1-4b07-8db3-cdab28cb1a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435621005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.435621005
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.4014063530
Short name T82
Test name
Test status
Simulation time 74148121 ps
CPU time 0.72 seconds
Started Mar 12 12:51:33 PM PDT 24
Finished Mar 12 12:51:34 PM PDT 24
Peak memory 195480 kb
Host smart-a4f5534d-379f-4bee-ac7e-f35cc64aad52
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014063530 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.4014063530
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.2809565261
Short name T734
Test name
Test status
Simulation time 30387918 ps
CPU time 0.58 seconds
Started Mar 12 12:51:18 PM PDT 24
Finished Mar 12 12:51:19 PM PDT 24
Peak memory 195176 kb
Host smart-8f68af2a-5c05-4efc-bce7-183f760590c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809565261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.2809565261
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.2632721777
Short name T748
Test name
Test status
Simulation time 545864641 ps
CPU time 0.94 seconds
Started Mar 12 12:51:11 PM PDT 24
Finished Mar 12 12:51:12 PM PDT 24
Peak memory 195448 kb
Host smart-abf81e27-8c36-46b1-ba6d-f730cef53103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632721777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.2632721777
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.840763040
Short name T301
Test name
Test status
Simulation time 105626722 ps
CPU time 0.6 seconds
Started Mar 12 12:51:18 PM PDT 24
Finished Mar 12 12:51:19 PM PDT 24
Peak memory 195412 kb
Host smart-eef702a8-71f6-4c9c-b628-e769ffccb287
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840763040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.840763040
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.4196922769
Short name T177
Test name
Test status
Simulation time 72028662 ps
CPU time 0.59 seconds
Started Mar 12 12:51:21 PM PDT 24
Finished Mar 12 12:51:22 PM PDT 24
Peak memory 195408 kb
Host smart-0b872724-fc18-431d-a0b0-e521950cd973
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196922769 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.4196922769
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.1792031894
Short name T523
Test name
Test status
Simulation time 82304673 ps
CPU time 0.66 seconds
Started Mar 12 12:51:21 PM PDT 24
Finished Mar 12 12:51:22 PM PDT 24
Peak memory 195720 kb
Host smart-f610d430-1c21-4933-abda-064aeea97fe8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792031894 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.1792031894
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_wakeup_race.2903325467
Short name T113
Test name
Test status
Simulation time 279180320 ps
CPU time 0.78 seconds
Started Mar 12 12:51:09 PM PDT 24
Finished Mar 12 12:51:10 PM PDT 24
Peak memory 195380 kb
Host smart-987da8a1-7fad-4a22-9da6-e68171ed77d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903325467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_w
akeup_race.2903325467
Directory /workspace/36.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.1052770652
Short name T239
Test name
Test status
Simulation time 41870924 ps
CPU time 0.74 seconds
Started Mar 12 12:51:13 PM PDT 24
Finished Mar 12 12:51:14 PM PDT 24
Peak memory 197572 kb
Host smart-af0a4660-bca1-4589-ae87-f9d19847575c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052770652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.1052770652
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.1178995087
Short name T831
Test name
Test status
Simulation time 160232341 ps
CPU time 0.79 seconds
Started Mar 12 12:51:08 PM PDT 24
Finished Mar 12 12:51:10 PM PDT 24
Peak memory 205236 kb
Host smart-b540d5b5-d8a8-4c33-825d-ec9aa2820d4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178995087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.1178995087
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.520001041
Short name T824
Test name
Test status
Simulation time 824225643 ps
CPU time 2.35 seconds
Started Mar 12 12:51:12 PM PDT 24
Finished Mar 12 12:51:15 PM PDT 24
Peak memory 200780 kb
Host smart-f1686447-a589-4630-8841-f7a47dea3d0e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520001041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.520001041
Directory /workspace/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3057518585
Short name T696
Test name
Test status
Simulation time 787904580 ps
CPU time 2.94 seconds
Started Mar 12 12:51:20 PM PDT 24
Finished Mar 12 12:51:23 PM PDT 24
Peak memory 195832 kb
Host smart-be06ccc7-2e6d-48be-ba93-391a39b869fc
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057518585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3057518585
Directory /workspace/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.1102839738
Short name T580
Test name
Test status
Simulation time 314381593 ps
CPU time 0.76 seconds
Started Mar 12 12:51:10 PM PDT 24
Finished Mar 12 12:51:11 PM PDT 24
Peak memory 195260 kb
Host smart-9c95720c-38ca-4d07-8cee-e522bbc6c4af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102839738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1102839738
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.177649384
Short name T36
Test name
Test status
Simulation time 49409208 ps
CPU time 0.6 seconds
Started Mar 12 12:51:13 PM PDT 24
Finished Mar 12 12:51:14 PM PDT 24
Peak memory 195604 kb
Host smart-669d24cd-6153-4310-a8cb-5adbb3d5aab4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177649384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.177649384
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_stress_all.2631257460
Short name T785
Test name
Test status
Simulation time 379402352 ps
CPU time 1.4 seconds
Started Mar 12 12:51:06 PM PDT 24
Finished Mar 12 12:51:08 PM PDT 24
Peak memory 195780 kb
Host smart-7ae1ef85-80b5-4455-a110-08c7aaa363f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631257460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.2631257460
Directory /workspace/36.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup_reset.1055151481
Short name T333
Test name
Test status
Simulation time 243859970 ps
CPU time 1.23 seconds
Started Mar 12 12:51:09 PM PDT 24
Finished Mar 12 12:51:11 PM PDT 24
Peak memory 197924 kb
Host smart-ef154ce5-1f62-453f-8f65-7e4db9c9e5c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055151481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.1055151481
Directory /workspace/36.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.1254873543
Short name T217
Test name
Test status
Simulation time 37097099 ps
CPU time 0.83 seconds
Started Mar 12 12:51:03 PM PDT 24
Finished Mar 12 12:51:04 PM PDT 24
Peak memory 197800 kb
Host smart-15dc0a7c-1ac7-4d8c-8194-8b51dc3124fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254873543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.1254873543
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.3587635954
Short name T424
Test name
Test status
Simulation time 60027695 ps
CPU time 0.82 seconds
Started Mar 12 12:51:08 PM PDT 24
Finished Mar 12 12:51:10 PM PDT 24
Peak memory 197944 kb
Host smart-fa30cc15-6377-458c-a321-086ba96b7e1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587635954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.3587635954
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.3385215306
Short name T707
Test name
Test status
Simulation time 29305599 ps
CPU time 0.64 seconds
Started Mar 12 12:51:12 PM PDT 24
Finished Mar 12 12:51:13 PM PDT 24
Peak memory 195260 kb
Host smart-06a1c661-0c5e-45c7-9792-bfdff45aa8c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385215306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst
_malfunc.3385215306
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.3577933927
Short name T452
Test name
Test status
Simulation time 1270501023 ps
CPU time 0.97 seconds
Started Mar 12 12:51:12 PM PDT 24
Finished Mar 12 12:51:14 PM PDT 24
Peak memory 195348 kb
Host smart-f5f43a52-5278-42c2-86cc-46c0f207e012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577933927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.3577933927
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.2180089790
Short name T413
Test name
Test status
Simulation time 26546325 ps
CPU time 0.62 seconds
Started Mar 12 12:51:17 PM PDT 24
Finished Mar 12 12:51:18 PM PDT 24
Peak memory 195436 kb
Host smart-1341ddd7-db88-48b5-ab11-ed0db003efa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180089790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.2180089790
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.2562298351
Short name T118
Test name
Test status
Simulation time 24717400 ps
CPU time 0.61 seconds
Started Mar 12 12:51:17 PM PDT 24
Finished Mar 12 12:51:18 PM PDT 24
Peak memory 195396 kb
Host smart-28c74053-8d6a-48a2-be97-33fdd2bbcbef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562298351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.2562298351
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.3554359259
Short name T321
Test name
Test status
Simulation time 71186951 ps
CPU time 0.68 seconds
Started Mar 12 12:51:05 PM PDT 24
Finished Mar 12 12:51:06 PM PDT 24
Peak memory 195820 kb
Host smart-11daaaeb-e768-4121-bc82-90433d7e1c6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554359259 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_inval
id.3554359259
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.2453425970
Short name T609
Test name
Test status
Simulation time 66907554 ps
CPU time 0.67 seconds
Started Mar 12 12:51:15 PM PDT 24
Finished Mar 12 12:51:16 PM PDT 24
Peak memory 195396 kb
Host smart-29774438-a142-4b8d-bcdc-b663d519ccab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453425970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.2453425970
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.3293161862
Short name T248
Test name
Test status
Simulation time 151566623 ps
CPU time 0.78 seconds
Started Mar 12 12:51:17 PM PDT 24
Finished Mar 12 12:51:18 PM PDT 24
Peak memory 206004 kb
Host smart-6db0f8d9-3c54-4de1-abe3-1befd808d123
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293161862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.3293161862
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2626324085
Short name T220
Test name
Test status
Simulation time 825494981 ps
CPU time 2.83 seconds
Started Mar 12 12:51:06 PM PDT 24
Finished Mar 12 12:51:09 PM PDT 24
Peak memory 201100 kb
Host smart-69125468-4c50-4e37-b02d-ffcb1a913055
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626324085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2626324085
Directory /workspace/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.531327244
Short name T836
Test name
Test status
Simulation time 971869909 ps
CPU time 2.05 seconds
Started Mar 12 12:51:03 PM PDT 24
Finished Mar 12 12:51:05 PM PDT 24
Peak memory 195912 kb
Host smart-c0d59ee9-ac39-4ee0-9701-6c5ecf986485
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531327244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.531327244
Directory /workspace/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.3901991821
Short name T667
Test name
Test status
Simulation time 53540826 ps
CPU time 0.89 seconds
Started Mar 12 12:51:06 PM PDT 24
Finished Mar 12 12:51:07 PM PDT 24
Peak memory 195268 kb
Host smart-7ea6efe6-2a67-472c-b009-755b54fd7436
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901991821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3901991821
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.2741761388
Short name T503
Test name
Test status
Simulation time 31747022 ps
CPU time 0.73 seconds
Started Mar 12 12:51:13 PM PDT 24
Finished Mar 12 12:51:15 PM PDT 24
Peak memory 197748 kb
Host smart-304395ee-ab67-4bf5-b108-41d3f51e35ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741761388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.2741761388
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup.2471595843
Short name T662
Test name
Test status
Simulation time 326521389 ps
CPU time 1.04 seconds
Started Mar 12 12:51:08 PM PDT 24
Finished Mar 12 12:51:11 PM PDT 24
Peak memory 195312 kb
Host smart-6d2fdc3f-2ea6-42fb-a541-97fb94f41d49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471595843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.2471595843
Directory /workspace/37.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup_reset.1536201161
Short name T354
Test name
Test status
Simulation time 123228394 ps
CPU time 0.82 seconds
Started Mar 12 12:51:13 PM PDT 24
Finished Mar 12 12:51:14 PM PDT 24
Peak memory 198032 kb
Host smart-5fc3c373-7b4a-471e-b1b5-3232b756dfe8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536201161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.1536201161
Directory /workspace/37.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.4232524184
Short name T484
Test name
Test status
Simulation time 32276875 ps
CPU time 0.77 seconds
Started Mar 12 12:51:30 PM PDT 24
Finished Mar 12 12:51:31 PM PDT 24
Peak memory 195324 kb
Host smart-bff5c2c8-5831-40a8-a4f7-9e21f0caabe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232524184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.4232524184
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.228903522
Short name T295
Test name
Test status
Simulation time 71719180 ps
CPU time 0.83 seconds
Started Mar 12 12:51:23 PM PDT 24
Finished Mar 12 12:51:24 PM PDT 24
Peak memory 197484 kb
Host smart-98f8e107-0eb6-4f2f-9ef9-c1fd4893ff67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228903522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_disa
ble_rom_integrity_check.228903522
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.3186317399
Short name T201
Test name
Test status
Simulation time 32388483 ps
CPU time 0.59 seconds
Started Mar 12 12:51:20 PM PDT 24
Finished Mar 12 12:51:21 PM PDT 24
Peak memory 194384 kb
Host smart-bf584ff7-e9a9-4918-8985-489b5c421818
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186317399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.3186317399
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.4112444052
Short name T330
Test name
Test status
Simulation time 559144611 ps
CPU time 0.92 seconds
Started Mar 12 12:51:12 PM PDT 24
Finished Mar 12 12:51:13 PM PDT 24
Peak memory 195364 kb
Host smart-a84e9c1a-bd3a-4716-9558-ed33d65250b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112444052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.4112444052
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.3646271529
Short name T790
Test name
Test status
Simulation time 37853963 ps
CPU time 0.64 seconds
Started Mar 12 12:51:14 PM PDT 24
Finished Mar 12 12:51:15 PM PDT 24
Peak memory 195408 kb
Host smart-be3881b0-c7a8-43f9-aa76-153547748c0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646271529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.3646271529
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.42902540
Short name T200
Test name
Test status
Simulation time 56207286 ps
CPU time 0.58 seconds
Started Mar 12 12:51:33 PM PDT 24
Finished Mar 12 12:51:34 PM PDT 24
Peak memory 195384 kb
Host smart-2c8b5f93-f32c-4e66-a725-c41225501c90
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42902540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.42902540
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.2112637125
Short name T325
Test name
Test status
Simulation time 40680972 ps
CPU time 0.67 seconds
Started Mar 12 12:51:38 PM PDT 24
Finished Mar 12 12:51:39 PM PDT 24
Peak memory 195912 kb
Host smart-c4df2b10-45cc-4879-8134-d189f00d0392
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112637125 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_inval
id.2112637125
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_wakeup_race.2553044390
Short name T145
Test name
Test status
Simulation time 374764478 ps
CPU time 0.83 seconds
Started Mar 12 12:51:20 PM PDT 24
Finished Mar 12 12:51:21 PM PDT 24
Peak memory 194448 kb
Host smart-c4c549fe-5199-44ac-a5e7-41f3ddc8b8de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553044390 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_w
akeup_race.2553044390
Directory /workspace/38.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.3608622079
Short name T513
Test name
Test status
Simulation time 50666758 ps
CPU time 0.7 seconds
Started Mar 12 12:51:18 PM PDT 24
Finished Mar 12 12:51:19 PM PDT 24
Peak memory 197544 kb
Host smart-359d6993-8d48-4e46-9583-88807f4bf3ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608622079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.3608622079
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.4141635662
Short name T202
Test name
Test status
Simulation time 164010749 ps
CPU time 0.77 seconds
Started Mar 12 12:51:30 PM PDT 24
Finished Mar 12 12:51:31 PM PDT 24
Peak memory 205956 kb
Host smart-04a7c7bf-6a8a-45c2-96df-3fb881fdc738
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141635662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.4141635662
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2654400794
Short name T322
Test name
Test status
Simulation time 1425571371 ps
CPU time 2.22 seconds
Started Mar 12 12:51:19 PM PDT 24
Finished Mar 12 12:51:21 PM PDT 24
Peak memory 200812 kb
Host smart-8ee8e3b7-4519-420e-bddf-f228dc6ca9b9
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654400794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2654400794
Directory /workspace/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.597858932
Short name T686
Test name
Test status
Simulation time 88894402 ps
CPU time 0.79 seconds
Started Mar 12 12:51:20 PM PDT 24
Finished Mar 12 12:51:21 PM PDT 24
Peak memory 195380 kb
Host smart-81aa2816-57a4-457a-9cde-c394df4a6c03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597858932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig_
mubi.597858932
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.1806432221
Short name T746
Test name
Test status
Simulation time 30948463 ps
CPU time 0.67 seconds
Started Mar 12 12:51:26 PM PDT 24
Finished Mar 12 12:51:27 PM PDT 24
Peak memory 195596 kb
Host smart-4d414679-8359-4a61-837c-c602e089842f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806432221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.1806432221
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup.4264300242
Short name T752
Test name
Test status
Simulation time 105784391 ps
CPU time 0.68 seconds
Started Mar 12 12:51:29 PM PDT 24
Finished Mar 12 12:51:30 PM PDT 24
Peak memory 195384 kb
Host smart-fa01ee46-91b9-4cb3-9af3-d31a611aa2e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264300242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.4264300242
Directory /workspace/38.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup_reset.1307826918
Short name T79
Test name
Test status
Simulation time 173833506 ps
CPU time 0.8 seconds
Started Mar 12 12:51:47 PM PDT 24
Finished Mar 12 12:51:48 PM PDT 24
Peak memory 195596 kb
Host smart-ae7458df-95e9-4c73-9d81-c8d00d84aaff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307826918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.1307826918
Directory /workspace/38.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.1005148520
Short name T419
Test name
Test status
Simulation time 33330276 ps
CPU time 0.78 seconds
Started Mar 12 12:51:23 PM PDT 24
Finished Mar 12 12:51:24 PM PDT 24
Peak memory 195356 kb
Host smart-88ffbfaa-b2fe-48b5-9b55-2ae6dbdf1657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005148520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.1005148520
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.2731382388
Short name T134
Test name
Test status
Simulation time 65929696 ps
CPU time 0.79 seconds
Started Mar 12 12:51:25 PM PDT 24
Finished Mar 12 12:51:26 PM PDT 24
Peak memory 196652 kb
Host smart-08feed95-a078-4e19-a4b7-b8c18cdb4caf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731382388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.2731382388
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.3022666831
Short name T504
Test name
Test status
Simulation time 51294201 ps
CPU time 0.56 seconds
Started Mar 12 12:51:13 PM PDT 24
Finished Mar 12 12:51:13 PM PDT 24
Peak memory 195352 kb
Host smart-e8ec7be3-eea1-44c1-8a51-2015c527df97
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022666831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst
_malfunc.3022666831
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.681351712
Short name T839
Test name
Test status
Simulation time 169221561 ps
CPU time 1.01 seconds
Started Mar 12 12:51:19 PM PDT 24
Finished Mar 12 12:51:20 PM PDT 24
Peak memory 195428 kb
Host smart-51be26ee-12ef-4c2c-ba99-77afb524fa6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681351712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.681351712
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.1370804333
Short name T539
Test name
Test status
Simulation time 38503466 ps
CPU time 0.64 seconds
Started Mar 12 12:51:32 PM PDT 24
Finished Mar 12 12:51:33 PM PDT 24
Peak memory 195416 kb
Host smart-11ea4b61-6f3f-4000-831a-e466efee003d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370804333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.1370804333
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.1976624674
Short name T262
Test name
Test status
Simulation time 94505875 ps
CPU time 0.62 seconds
Started Mar 12 12:51:18 PM PDT 24
Finished Mar 12 12:51:19 PM PDT 24
Peak memory 195404 kb
Host smart-01702d84-ecdc-4015-b8a7-8d056590090c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976624674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.1976624674
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.3788602152
Short name T156
Test name
Test status
Simulation time 55401508 ps
CPU time 0.67 seconds
Started Mar 12 12:51:35 PM PDT 24
Finished Mar 12 12:51:36 PM PDT 24
Peak memory 195908 kb
Host smart-28eda2fb-5aeb-409f-b06e-7e9b90a0b526
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788602152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.3788602152
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_wakeup_race.2176011205
Short name T749
Test name
Test status
Simulation time 230040801 ps
CPU time 0.78 seconds
Started Mar 12 12:51:29 PM PDT 24
Finished Mar 12 12:51:30 PM PDT 24
Peak memory 195308 kb
Host smart-76b79208-3535-46dd-b71f-9ae762ad1511
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176011205 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_w
akeup_race.2176011205
Directory /workspace/39.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.3818792788
Short name T541
Test name
Test status
Simulation time 89793589 ps
CPU time 1.07 seconds
Started Mar 12 12:51:22 PM PDT 24
Finished Mar 12 12:51:23 PM PDT 24
Peak memory 198944 kb
Host smart-4dc18f04-05e7-4925-838a-d65afd8f0b42
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818792788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.3818792788
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.2785573497
Short name T681
Test name
Test status
Simulation time 109573261 ps
CPU time 0.9 seconds
Started Mar 12 12:51:26 PM PDT 24
Finished Mar 12 12:51:27 PM PDT 24
Peak memory 206452 kb
Host smart-07836033-90d5-4e17-8f11-1f4829a35c65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785573497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.2785573497
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.3326965056
Short name T245
Test name
Test status
Simulation time 81023471 ps
CPU time 0.82 seconds
Started Mar 12 12:51:28 PM PDT 24
Finished Mar 12 12:51:29 PM PDT 24
Peak memory 195348 kb
Host smart-1ffab0f3-9010-4f41-aa45-af0a5fde9812
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326965056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_
cm_ctrl_config_regwen.3326965056
Directory /workspace/39.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.227721273
Short name T473
Test name
Test status
Simulation time 836700966 ps
CPU time 3.06 seconds
Started Mar 12 12:51:21 PM PDT 24
Finished Mar 12 12:51:24 PM PDT 24
Peak memory 200848 kb
Host smart-ec97060f-afaa-49cd-8393-376eb4c749ba
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227721273 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.227721273
Directory /workspace/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.899759165
Short name T641
Test name
Test status
Simulation time 912347903 ps
CPU time 3.29 seconds
Started Mar 12 12:51:42 PM PDT 24
Finished Mar 12 12:51:45 PM PDT 24
Peak memory 195840 kb
Host smart-d2a61d4e-d0b2-4817-bf31-ecefd0db8a04
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899759165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.899759165
Directory /workspace/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.3607709103
Short name T714
Test name
Test status
Simulation time 54582871 ps
CPU time 0.86 seconds
Started Mar 12 12:51:22 PM PDT 24
Finished Mar 12 12:51:23 PM PDT 24
Peak memory 195184 kb
Host smart-115a8431-5b64-47f0-9616-72c819e19a1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607709103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3607709103
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.1792068081
Short name T723
Test name
Test status
Simulation time 69822061 ps
CPU time 0.64 seconds
Started Mar 12 12:51:23 PM PDT 24
Finished Mar 12 12:51:24 PM PDT 24
Peak memory 195628 kb
Host smart-f3592307-51aa-428f-83ef-578077fc1c1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792068081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.1792068081
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup.3430668354
Short name T112
Test name
Test status
Simulation time 62772114 ps
CPU time 0.73 seconds
Started Mar 12 12:51:30 PM PDT 24
Finished Mar 12 12:51:31 PM PDT 24
Peak memory 195308 kb
Host smart-75c959f2-cffe-472f-b388-b2cff71a87b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430668354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.3430668354
Directory /workspace/39.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup_reset.304206487
Short name T535
Test name
Test status
Simulation time 276954516 ps
CPU time 1.4 seconds
Started Mar 12 12:51:20 PM PDT 24
Finished Mar 12 12:51:22 PM PDT 24
Peak memory 199020 kb
Host smart-af924fc1-b753-4bd7-89f8-3dcaa5491154
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304206487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.304206487
Directory /workspace/39.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.2904089508
Short name T766
Test name
Test status
Simulation time 23335977 ps
CPU time 0.66 seconds
Started Mar 12 12:49:43 PM PDT 24
Finished Mar 12 12:49:44 PM PDT 24
Peak memory 195368 kb
Host smart-baa9483d-fad7-4030-8000-456b6d7cbbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904089508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.2904089508
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.271375154
Short name T204
Test name
Test status
Simulation time 111349516 ps
CPU time 0.66 seconds
Started Mar 12 12:49:40 PM PDT 24
Finished Mar 12 12:49:41 PM PDT 24
Peak memory 196612 kb
Host smart-e1d58653-e3c8-445e-9dfa-e7ee4c3dc469
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271375154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disab
le_rom_integrity_check.271375154
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.315720629
Short name T280
Test name
Test status
Simulation time 38846458 ps
CPU time 0.67 seconds
Started Mar 12 12:49:45 PM PDT 24
Finished Mar 12 12:49:46 PM PDT 24
Peak memory 195324 kb
Host smart-17ca0b18-547c-49e9-ba67-748f04dffb4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315720629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_m
alfunc.315720629
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.3191214927
Short name T726
Test name
Test status
Simulation time 229118294 ps
CPU time 1.02 seconds
Started Mar 12 12:49:49 PM PDT 24
Finished Mar 12 12:49:50 PM PDT 24
Peak memory 195408 kb
Host smart-21f384b2-6f5e-44c9-b703-48a13d50d603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191214927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.3191214927
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.170445394
Short name T343
Test name
Test status
Simulation time 34441969 ps
CPU time 0.64 seconds
Started Mar 12 12:49:46 PM PDT 24
Finished Mar 12 12:49:47 PM PDT 24
Peak memory 195368 kb
Host smart-19be5647-5c1b-437f-99ed-a992af1bc21c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170445394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.170445394
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.163178638
Short name T486
Test name
Test status
Simulation time 75746039 ps
CPU time 0.63 seconds
Started Mar 12 12:49:46 PM PDT 24
Finished Mar 12 12:49:47 PM PDT 24
Peak memory 195396 kb
Host smart-027c86e0-0e60-492d-a162-915e4e8cec0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163178638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.163178638
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.2520467148
Short name T554
Test name
Test status
Simulation time 43930650 ps
CPU time 0.74 seconds
Started Mar 12 12:49:54 PM PDT 24
Finished Mar 12 12:49:56 PM PDT 24
Peak memory 195848 kb
Host smart-25f791d6-23ea-49b8-b574-35b1b7413fe3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520467148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.2520467148
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_wakeup_race.1745035923
Short name T189
Test name
Test status
Simulation time 198167709 ps
CPU time 0.98 seconds
Started Mar 12 12:49:45 PM PDT 24
Finished Mar 12 12:49:46 PM PDT 24
Peak memory 195344 kb
Host smart-8218e5c3-2412-4afc-a4d4-64daf622054a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745035923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wa
keup_race.1745035923
Directory /workspace/4.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.3904789885
Short name T481
Test name
Test status
Simulation time 25869142 ps
CPU time 0.65 seconds
Started Mar 12 12:49:40 PM PDT 24
Finished Mar 12 12:49:42 PM PDT 24
Peak memory 197532 kb
Host smart-7a76a933-e309-4e51-a951-c31b19d277b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904789885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.3904789885
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.1494936991
Short name T755
Test name
Test status
Simulation time 146294479 ps
CPU time 0.83 seconds
Started Mar 12 12:49:45 PM PDT 24
Finished Mar 12 12:49:46 PM PDT 24
Peak memory 205288 kb
Host smart-9426c016-55fc-4ae3-938a-da4b164ce48e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494936991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.1494936991
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.2331069648
Short name T30
Test name
Test status
Simulation time 669136493 ps
CPU time 2.09 seconds
Started Mar 12 12:49:48 PM PDT 24
Finished Mar 12 12:49:50 PM PDT 24
Peak memory 214388 kb
Host smart-02d00758-788d-483a-8335-f9a1cfdb212e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331069648 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.2331069648
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.910880826
Short name T826
Test name
Test status
Simulation time 163693498 ps
CPU time 0.77 seconds
Started Mar 12 12:49:55 PM PDT 24
Finished Mar 12 12:49:57 PM PDT 24
Peak memory 195276 kb
Host smart-4ed8177b-6676-4a6e-bd05-bcb78ead9f21
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910880826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm
_ctrl_config_regwen.910880826
Directory /workspace/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3923913870
Short name T569
Test name
Test status
Simulation time 926803899 ps
CPU time 2 seconds
Started Mar 12 12:49:43 PM PDT 24
Finished Mar 12 12:49:46 PM PDT 24
Peak memory 201200 kb
Host smart-afb57b62-cc04-4e0b-b43f-5956bb71eee9
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923913870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3923913870
Directory /workspace/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2160436827
Short name T373
Test name
Test status
Simulation time 1035830450 ps
CPU time 2.84 seconds
Started Mar 12 12:49:45 PM PDT 24
Finished Mar 12 12:49:48 PM PDT 24
Peak memory 201076 kb
Host smart-c27e0757-6728-4564-96c3-eb889cfffee4
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160436827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2160436827
Directory /workspace/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.1922879299
Short name T560
Test name
Test status
Simulation time 108751389 ps
CPU time 0.89 seconds
Started Mar 12 12:49:45 PM PDT 24
Finished Mar 12 12:49:46 PM PDT 24
Peak memory 195368 kb
Host smart-e9b2bd94-2e5f-4b56-bb67-40c68534cc5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922879299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1922879299
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.1238057892
Short name T168
Test name
Test status
Simulation time 28454762 ps
CPU time 0.66 seconds
Started Mar 12 12:49:47 PM PDT 24
Finished Mar 12 12:49:48 PM PDT 24
Peak memory 197516 kb
Host smart-d996942d-fef5-418f-b3b0-6bf433fe4067
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238057892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.1238057892
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_stress_all.1626036650
Short name T35
Test name
Test status
Simulation time 591157352 ps
CPU time 2.36 seconds
Started Mar 12 12:49:43 PM PDT 24
Finished Mar 12 12:49:46 PM PDT 24
Peak memory 195788 kb
Host smart-63863340-02f8-4dd9-8516-1497c9d70c2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626036650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.1626036650
Directory /workspace/4.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup.981811860
Short name T528
Test name
Test status
Simulation time 83679980 ps
CPU time 0.7 seconds
Started Mar 12 12:49:45 PM PDT 24
Finished Mar 12 12:49:46 PM PDT 24
Peak memory 195348 kb
Host smart-1b651751-0384-4cc5-b18f-7cf71ecc89c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981811860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.981811860
Directory /workspace/4.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup_reset.392852086
Short name T313
Test name
Test status
Simulation time 175470995 ps
CPU time 1.1 seconds
Started Mar 12 12:49:54 PM PDT 24
Finished Mar 12 12:49:56 PM PDT 24
Peak memory 197936 kb
Host smart-7701341b-1476-49cc-87fd-778a371a10fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392852086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.392852086
Directory /workspace/4.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.1350978897
Short name T592
Test name
Test status
Simulation time 171263196 ps
CPU time 0.74 seconds
Started Mar 12 12:51:30 PM PDT 24
Finished Mar 12 12:51:31 PM PDT 24
Peak memory 197756 kb
Host smart-440996c4-3ae7-4d55-b844-fa04a40b2851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350978897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.1350978897
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.2069974989
Short name T773
Test name
Test status
Simulation time 81216975 ps
CPU time 0.69 seconds
Started Mar 12 12:51:13 PM PDT 24
Finished Mar 12 12:51:15 PM PDT 24
Peak memory 195324 kb
Host smart-a37767ab-d08d-4395-aa13-c3019470d751
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069974989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.2069974989
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.2969589860
Short name T565
Test name
Test status
Simulation time 42605465 ps
CPU time 0.6 seconds
Started Mar 12 12:51:45 PM PDT 24
Finished Mar 12 12:51:46 PM PDT 24
Peak memory 195332 kb
Host smart-5e6c22b8-7116-4249-a726-55b99a72678c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969589860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst
_malfunc.2969589860
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.4093943258
Short name T727
Test name
Test status
Simulation time 1171500925 ps
CPU time 0.95 seconds
Started Mar 12 12:51:19 PM PDT 24
Finished Mar 12 12:51:20 PM PDT 24
Peak memory 195416 kb
Host smart-5bd1d5d5-c688-43bc-9c07-9e71993ea655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093943258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.4093943258
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.135701449
Short name T281
Test name
Test status
Simulation time 49624147 ps
CPU time 0.63 seconds
Started Mar 12 12:51:30 PM PDT 24
Finished Mar 12 12:51:30 PM PDT 24
Peak memory 195428 kb
Host smart-df17a86d-abfb-48c8-b913-325bf9dcc189
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135701449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.135701449
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.213021297
Short name T454
Test name
Test status
Simulation time 31512236 ps
CPU time 0.6 seconds
Started Mar 12 12:51:25 PM PDT 24
Finished Mar 12 12:51:26 PM PDT 24
Peak memory 195412 kb
Host smart-3bdc1a0d-a3f5-49a0-baa0-6e2f8d368319
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213021297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.213021297
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.80945118
Short name T415
Test name
Test status
Simulation time 70010805 ps
CPU time 0.66 seconds
Started Mar 12 12:51:22 PM PDT 24
Finished Mar 12 12:51:23 PM PDT 24
Peak memory 195792 kb
Host smart-f3915282-c0b7-4299-8f57-2fd447f940b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80945118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_invalid
.80945118
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_wakeup_race.3003731183
Short name T761
Test name
Test status
Simulation time 28327440 ps
CPU time 0.67 seconds
Started Mar 12 12:51:39 PM PDT 24
Finished Mar 12 12:51:40 PM PDT 24
Peak memory 195372 kb
Host smart-4116f079-4263-4588-ad94-d9f586aa6601
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003731183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_w
akeup_race.3003731183
Directory /workspace/40.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.2745207578
Short name T308
Test name
Test status
Simulation time 81906534 ps
CPU time 0.68 seconds
Started Mar 12 12:51:29 PM PDT 24
Finished Mar 12 12:51:30 PM PDT 24
Peak memory 197644 kb
Host smart-b59453a4-02d8-49b6-896d-9c912fc35331
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745207578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.2745207578
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.182053227
Short name T631
Test name
Test status
Simulation time 119486476 ps
CPU time 0.8 seconds
Started Mar 12 12:51:22 PM PDT 24
Finished Mar 12 12:51:23 PM PDT 24
Peak memory 206004 kb
Host smart-789765d8-76b8-43da-a0ee-26e5469bdcce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182053227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.182053227
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.2895413362
Short name T397
Test name
Test status
Simulation time 264872003 ps
CPU time 0.73 seconds
Started Mar 12 12:51:20 PM PDT 24
Finished Mar 12 12:51:21 PM PDT 24
Peak memory 195444 kb
Host smart-74333a10-3848-464d-b30b-2304865946be
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895413362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_
cm_ctrl_config_regwen.2895413362
Directory /workspace/40.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1387962121
Short name T527
Test name
Test status
Simulation time 759626219 ps
CPU time 2.95 seconds
Started Mar 12 12:51:21 PM PDT 24
Finished Mar 12 12:51:24 PM PDT 24
Peak memory 201128 kb
Host smart-418cafb4-0cd7-4350-aeb3-24f513e09425
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387962121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1387962121
Directory /workspace/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1285447772
Short name T845
Test name
Test status
Simulation time 1377349609 ps
CPU time 1.91 seconds
Started Mar 12 12:51:24 PM PDT 24
Finished Mar 12 12:51:26 PM PDT 24
Peak memory 195792 kb
Host smart-ce162e26-ba2b-4879-84a9-c590018c8fa0
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285447772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1285447772
Directory /workspace/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.2170446351
Short name T154
Test name
Test status
Simulation time 74020745 ps
CPU time 0.89 seconds
Started Mar 12 12:51:22 PM PDT 24
Finished Mar 12 12:51:23 PM PDT 24
Peak memory 195328 kb
Host smart-cc749ab3-fed1-447c-a100-057b883eceb9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170446351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2170446351
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.2338986794
Short name T412
Test name
Test status
Simulation time 50837686 ps
CPU time 0.63 seconds
Started Mar 12 12:51:41 PM PDT 24
Finished Mar 12 12:51:42 PM PDT 24
Peak memory 195612 kb
Host smart-3e3bd0ce-65b7-4c1d-9b71-05efd0299a32
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338986794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.2338986794
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup.2781800039
Short name T629
Test name
Test status
Simulation time 156019822 ps
CPU time 0.71 seconds
Started Mar 12 12:51:24 PM PDT 24
Finished Mar 12 12:51:24 PM PDT 24
Peak memory 195392 kb
Host smart-554fba85-2850-4773-aea5-e10de508f0b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781800039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.2781800039
Directory /workspace/40.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup_reset.1356038151
Short name T161
Test name
Test status
Simulation time 190741834 ps
CPU time 1.19 seconds
Started Mar 12 12:51:26 PM PDT 24
Finished Mar 12 12:51:27 PM PDT 24
Peak memory 197944 kb
Host smart-45dd9d8f-f1e6-4792-82d9-4359c73b8638
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356038151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.1356038151
Directory /workspace/40.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.2802633194
Short name T17
Test name
Test status
Simulation time 66963423 ps
CPU time 0.68 seconds
Started Mar 12 12:51:45 PM PDT 24
Finished Mar 12 12:51:46 PM PDT 24
Peak memory 197536 kb
Host smart-5334685b-ab2c-4325-ab6e-61edbb30ac5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802633194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.2802633194
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.1510035321
Short name T435
Test name
Test status
Simulation time 80419431 ps
CPU time 0.71 seconds
Started Mar 12 12:51:41 PM PDT 24
Finished Mar 12 12:51:42 PM PDT 24
Peak memory 197608 kb
Host smart-4c7f1dd5-336b-404e-9d19-319478d3bbae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510035321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.1510035321
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.3627322801
Short name T421
Test name
Test status
Simulation time 28810498 ps
CPU time 0.69 seconds
Started Mar 12 12:51:35 PM PDT 24
Finished Mar 12 12:51:36 PM PDT 24
Peak memory 195348 kb
Host smart-ee6b0a7e-5e37-49da-8837-a6f22b0c33d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627322801 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.3627322801
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.3348847760
Short name T409
Test name
Test status
Simulation time 160250897 ps
CPU time 1.06 seconds
Started Mar 12 12:51:38 PM PDT 24
Finished Mar 12 12:51:39 PM PDT 24
Peak memory 195392 kb
Host smart-88b47dd8-de6f-4ec3-9d54-e0855f675155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348847760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.3348847760
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.3638670375
Short name T576
Test name
Test status
Simulation time 54375150 ps
CPU time 0.59 seconds
Started Mar 12 12:51:40 PM PDT 24
Finished Mar 12 12:51:41 PM PDT 24
Peak memory 195392 kb
Host smart-c51cc374-e142-4369-b399-5cd8057e837d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638670375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.3638670375
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.183054923
Short name T364
Test name
Test status
Simulation time 39285188 ps
CPU time 0.66 seconds
Started Mar 12 12:51:43 PM PDT 24
Finished Mar 12 12:51:44 PM PDT 24
Peak memory 195320 kb
Host smart-a1b7241f-a985-41e4-9208-8d4b322de7bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183054923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.183054923
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.745610420
Short name T420
Test name
Test status
Simulation time 39456612 ps
CPU time 0.71 seconds
Started Mar 12 12:51:38 PM PDT 24
Finished Mar 12 12:51:39 PM PDT 24
Peak memory 195860 kb
Host smart-7db48a57-4fe3-4ae3-994a-0cd861b0486b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745610420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_invali
d.745610420
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_wakeup_race.2905918927
Short name T457
Test name
Test status
Simulation time 320658267 ps
CPU time 0.88 seconds
Started Mar 12 12:51:28 PM PDT 24
Finished Mar 12 12:51:29 PM PDT 24
Peak memory 195344 kb
Host smart-20fc3aa1-939e-4857-86a9-9ff051896276
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905918927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_w
akeup_race.2905918927
Directory /workspace/41.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.2652761436
Short name T456
Test name
Test status
Simulation time 74970471 ps
CPU time 0.93 seconds
Started Mar 12 12:51:30 PM PDT 24
Finished Mar 12 12:51:31 PM PDT 24
Peak memory 197704 kb
Host smart-cdcf4e6d-8d52-4d37-98b5-ca7f74effc30
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652761436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.2652761436
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.1449199860
Short name T282
Test name
Test status
Simulation time 129506056 ps
CPU time 0.85 seconds
Started Mar 12 12:51:41 PM PDT 24
Finished Mar 12 12:51:42 PM PDT 24
Peak memory 205176 kb
Host smart-13190138-39f8-4f33-b574-970754cf089e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449199860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.1449199860
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.3719023473
Short name T695
Test name
Test status
Simulation time 342545296 ps
CPU time 1.29 seconds
Started Mar 12 12:51:36 PM PDT 24
Finished Mar 12 12:51:37 PM PDT 24
Peak memory 195692 kb
Host smart-f668f66b-ad3b-49a2-b254-dd678b439c83
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719023473 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_
cm_ctrl_config_regwen.3719023473
Directory /workspace/41.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3307222726
Short name T287
Test name
Test status
Simulation time 2076384709 ps
CPU time 2.01 seconds
Started Mar 12 12:51:39 PM PDT 24
Finished Mar 12 12:51:41 PM PDT 24
Peak memory 201220 kb
Host smart-1a1952a2-8ebf-432e-a3bb-f2929be4a0a1
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307222726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3307222726
Directory /workspace/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3313214700
Short name T497
Test name
Test status
Simulation time 994418289 ps
CPU time 2.62 seconds
Started Mar 12 12:51:54 PM PDT 24
Finished Mar 12 12:51:56 PM PDT 24
Peak memory 195908 kb
Host smart-7fc454c2-7efe-4f0a-a2f1-bfb783d17944
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313214700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3313214700
Directory /workspace/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.1278921344
Short name T854
Test name
Test status
Simulation time 545935169 ps
CPU time 0.88 seconds
Started Mar 12 12:51:31 PM PDT 24
Finished Mar 12 12:51:38 PM PDT 24
Peak memory 195264 kb
Host smart-0a65384f-5007-4ffe-8a92-7d1477bae515
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278921344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1278921344
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.3960378985
Short name T774
Test name
Test status
Simulation time 38270133 ps
CPU time 0.62 seconds
Started Mar 12 12:51:20 PM PDT 24
Finished Mar 12 12:51:21 PM PDT 24
Peak memory 195604 kb
Host smart-f7a62059-c0f8-4037-82c0-361ac2120fa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960378985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.3960378985
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup_reset.3370016329
Short name T32
Test name
Test status
Simulation time 103632606 ps
CPU time 0.71 seconds
Started Mar 12 12:51:29 PM PDT 24
Finished Mar 12 12:51:30 PM PDT 24
Peak memory 197760 kb
Host smart-5001e0f3-110e-4d37-b5b1-6b8531133e6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370016329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.3370016329
Directory /workspace/41.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.292479760
Short name T185
Test name
Test status
Simulation time 40937556 ps
CPU time 0.73 seconds
Started Mar 12 12:51:37 PM PDT 24
Finished Mar 12 12:51:38 PM PDT 24
Peak memory 197736 kb
Host smart-c7e5ee8d-4a3e-4895-92d8-1c3eb794dcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292479760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.292479760
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.1540079541
Short name T136
Test name
Test status
Simulation time 73114511 ps
CPU time 0.67 seconds
Started Mar 12 12:51:58 PM PDT 24
Finished Mar 12 12:51:59 PM PDT 24
Peak memory 196160 kb
Host smart-4f1be036-f343-4c7a-8c84-8b6b1bbc4b43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540079541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_dis
able_rom_integrity_check.1540079541
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.620885534
Short name T689
Test name
Test status
Simulation time 40466425 ps
CPU time 0.61 seconds
Started Mar 12 12:51:35 PM PDT 24
Finished Mar 12 12:51:36 PM PDT 24
Peak memory 195372 kb
Host smart-86ca9c8b-cd83-487c-b453-5b57ccc6c10b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620885534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst_
malfunc.620885534
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.1871389754
Short name T466
Test name
Test status
Simulation time 168409791 ps
CPU time 0.95 seconds
Started Mar 12 12:51:40 PM PDT 24
Finished Mar 12 12:51:41 PM PDT 24
Peak memory 195436 kb
Host smart-cab543b9-0cd5-42ed-91bf-b68a8b22a997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871389754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.1871389754
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.2866068137
Short name T619
Test name
Test status
Simulation time 74241239 ps
CPU time 0.63 seconds
Started Mar 12 12:51:30 PM PDT 24
Finished Mar 12 12:51:36 PM PDT 24
Peak memory 195304 kb
Host smart-de48f569-d727-4526-9f09-a9efae82d51c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866068137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.2866068137
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.2433634361
Short name T715
Test name
Test status
Simulation time 23908228 ps
CPU time 0.56 seconds
Started Mar 12 12:51:40 PM PDT 24
Finished Mar 12 12:51:41 PM PDT 24
Peak memory 195216 kb
Host smart-8b4e7249-c6bb-46ac-8207-ce0c7d42a607
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433634361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.2433634361
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.2221172955
Short name T319
Test name
Test status
Simulation time 69523845 ps
CPU time 0.7 seconds
Started Mar 12 12:51:46 PM PDT 24
Finished Mar 12 12:51:47 PM PDT 24
Peak memory 195848 kb
Host smart-f3d5e537-f04d-4770-b3c5-ab2e756507a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221172955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_inval
id.2221172955
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_wakeup_race.1387523857
Short name T363
Test name
Test status
Simulation time 352555732 ps
CPU time 0.86 seconds
Started Mar 12 12:51:53 PM PDT 24
Finished Mar 12 12:51:54 PM PDT 24
Peak memory 195372 kb
Host smart-b904ed0e-890f-43a6-9b0f-e62113df6498
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387523857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_w
akeup_race.1387523857
Directory /workspace/42.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.3787382366
Short name T677
Test name
Test status
Simulation time 31273233 ps
CPU time 0.7 seconds
Started Mar 12 12:51:28 PM PDT 24
Finished Mar 12 12:51:29 PM PDT 24
Peak memory 197644 kb
Host smart-e907ee72-fa12-437a-ae32-bad4c2ab19c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787382366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.3787382366
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.1928341234
Short name T264
Test name
Test status
Simulation time 188976864 ps
CPU time 0.8 seconds
Started Mar 12 12:51:49 PM PDT 24
Finished Mar 12 12:51:50 PM PDT 24
Peak memory 206172 kb
Host smart-53fab8af-a1ef-4839-a3c5-604dadc6418f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928341234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.1928341234
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.455923878
Short name T660
Test name
Test status
Simulation time 918227594 ps
CPU time 1.09 seconds
Started Mar 12 12:51:47 PM PDT 24
Finished Mar 12 12:51:49 PM PDT 24
Peak memory 195436 kb
Host smart-ea120bdd-99e1-49b0-b140-919c7e749e88
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455923878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_c
m_ctrl_config_regwen.455923878
Directory /workspace/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3403025481
Short name T753
Test name
Test status
Simulation time 982831793 ps
CPU time 2.57 seconds
Started Mar 12 12:51:34 PM PDT 24
Finished Mar 12 12:51:42 PM PDT 24
Peak memory 201132 kb
Host smart-6050be24-0e0c-4420-8c34-6fc04537f3db
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403025481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3403025481
Directory /workspace/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2018688725
Short name T171
Test name
Test status
Simulation time 912034189 ps
CPU time 3.47 seconds
Started Mar 12 12:51:41 PM PDT 24
Finished Mar 12 12:51:45 PM PDT 24
Peak memory 195816 kb
Host smart-41872c98-ffdf-49c4-8fe4-6fa500df137f
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018688725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2018688725
Directory /workspace/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.3265962673
Short name T147
Test name
Test status
Simulation time 84012911 ps
CPU time 0.91 seconds
Started Mar 12 12:51:36 PM PDT 24
Finished Mar 12 12:51:37 PM PDT 24
Peak memory 195352 kb
Host smart-b2b0bdd0-fefb-455b-9320-d0f41a54cd20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265962673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3265962673
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.3636470664
Short name T834
Test name
Test status
Simulation time 42495482 ps
CPU time 0.62 seconds
Started Mar 12 12:51:36 PM PDT 24
Finished Mar 12 12:51:36 PM PDT 24
Peak memory 195604 kb
Host smart-e008660a-7347-4b94-bd33-d4552ef0d8ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636470664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.3636470664
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_stress_all.3280113901
Short name T348
Test name
Test status
Simulation time 4593550697 ps
CPU time 3.35 seconds
Started Mar 12 12:51:49 PM PDT 24
Finished Mar 12 12:51:53 PM PDT 24
Peak memory 201264 kb
Host smart-30fd2eb0-269b-423f-979c-2e977e5aeb06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280113901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.3280113901
Directory /workspace/42.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup.1692340641
Short name T822
Test name
Test status
Simulation time 106435425 ps
CPU time 0.81 seconds
Started Mar 12 12:51:39 PM PDT 24
Finished Mar 12 12:51:40 PM PDT 24
Peak memory 195340 kb
Host smart-6f8574e9-a494-4fb3-8fc8-21b8abb1de6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692340641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.1692340641
Directory /workspace/42.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup_reset.703197563
Short name T573
Test name
Test status
Simulation time 368537662 ps
CPU time 1.05 seconds
Started Mar 12 12:51:35 PM PDT 24
Finished Mar 12 12:51:36 PM PDT 24
Peak memory 197848 kb
Host smart-7fb0bb49-9b34-40da-9d40-0046caa69f60
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703197563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.703197563
Directory /workspace/42.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.2914412285
Short name T116
Test name
Test status
Simulation time 26919291 ps
CPU time 0.71 seconds
Started Mar 12 12:51:39 PM PDT 24
Finished Mar 12 12:51:41 PM PDT 24
Peak memory 197568 kb
Host smart-03d57a49-125f-4304-a4f6-7fa4a3b4ccee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914412285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.2914412285
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.180391602
Short name T815
Test name
Test status
Simulation time 74580852 ps
CPU time 0.66 seconds
Started Mar 12 12:51:46 PM PDT 24
Finished Mar 12 12:51:47 PM PDT 24
Peak memory 195432 kb
Host smart-f39b2532-643f-49e1-95af-e7632a0a6a7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180391602 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_disa
ble_rom_integrity_check.180391602
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.1430710970
Short name T15
Test name
Test status
Simulation time 56102116 ps
CPU time 0.58 seconds
Started Mar 12 12:51:54 PM PDT 24
Finished Mar 12 12:51:55 PM PDT 24
Peak memory 195360 kb
Host smart-7c1ffd93-2808-478b-ab89-e6f435d3509f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430710970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst
_malfunc.1430710970
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.126735544
Short name T411
Test name
Test status
Simulation time 851336718 ps
CPU time 0.94 seconds
Started Mar 12 12:51:58 PM PDT 24
Finished Mar 12 12:51:59 PM PDT 24
Peak memory 195060 kb
Host smart-a2ee6944-f1e2-400d-8fa0-a1c6ae575b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126735544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.126735544
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.364077274
Short name T422
Test name
Test status
Simulation time 47263637 ps
CPU time 0.68 seconds
Started Mar 12 12:51:55 PM PDT 24
Finished Mar 12 12:51:56 PM PDT 24
Peak memory 195388 kb
Host smart-a4273efd-c724-4e28-8ba1-ab247d184493
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364077274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.364077274
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.3819480167
Short name T297
Test name
Test status
Simulation time 72462082 ps
CPU time 0.6 seconds
Started Mar 12 12:52:01 PM PDT 24
Finished Mar 12 12:52:02 PM PDT 24
Peak memory 195456 kb
Host smart-109c75c7-1d66-46ca-9349-3aaeceaec8a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819480167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.3819480167
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.2972552266
Short name T166
Test name
Test status
Simulation time 80493401 ps
CPU time 0.67 seconds
Started Mar 12 12:51:58 PM PDT 24
Finished Mar 12 12:51:58 PM PDT 24
Peak memory 195820 kb
Host smart-618d9180-aae9-47bc-acd1-a48040df1dee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972552266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval
id.2972552266
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.2913156055
Short name T299
Test name
Test status
Simulation time 123376904 ps
CPU time 0.83 seconds
Started Mar 12 12:51:54 PM PDT 24
Finished Mar 12 12:51:55 PM PDT 24
Peak memory 197676 kb
Host smart-684ad7e4-a9e3-490c-ad48-715d21964128
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913156055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.2913156055
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.29077725
Short name T478
Test name
Test status
Simulation time 150987750 ps
CPU time 0.82 seconds
Started Mar 12 12:51:58 PM PDT 24
Finished Mar 12 12:51:59 PM PDT 24
Peak memory 206180 kb
Host smart-3f5f3240-e377-4e04-b518-4a8e3e1c8555
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29077725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.29077725
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.3618344388
Short name T797
Test name
Test status
Simulation time 278980441 ps
CPU time 0.9 seconds
Started Mar 12 12:51:49 PM PDT 24
Finished Mar 12 12:51:50 PM PDT 24
Peak memory 195364 kb
Host smart-9e45859a-a49b-4f6b-82d8-542644d4fee4
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618344388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_
cm_ctrl_config_regwen.3618344388
Directory /workspace/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3618660795
Short name T401
Test name
Test status
Simulation time 891085457 ps
CPU time 2.44 seconds
Started Mar 12 12:52:11 PM PDT 24
Finished Mar 12 12:52:13 PM PDT 24
Peak memory 200924 kb
Host smart-eb9dad77-8914-442a-82c2-0a9d9863768a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618660795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3618660795
Directory /workspace/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1324651842
Short name T558
Test name
Test status
Simulation time 3484514927 ps
CPU time 1.85 seconds
Started Mar 12 12:51:44 PM PDT 24
Finished Mar 12 12:51:46 PM PDT 24
Peak memory 200968 kb
Host smart-b8425d09-2baf-44ef-b21f-02cf142c278e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324651842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1324651842
Directory /workspace/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.3924297293
Short name T353
Test name
Test status
Simulation time 147849846 ps
CPU time 0.9 seconds
Started Mar 12 12:51:44 PM PDT 24
Finished Mar 12 12:51:45 PM PDT 24
Peak memory 195392 kb
Host smart-ae1aacfd-04a7-45e9-8014-387f66e78903
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924297293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3924297293
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.751081901
Short name T713
Test name
Test status
Simulation time 48653269 ps
CPU time 0.6 seconds
Started Mar 12 12:51:57 PM PDT 24
Finished Mar 12 12:51:58 PM PDT 24
Peak memory 195600 kb
Host smart-91a9e7fe-3181-40d5-89b4-84e1c96c2fed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751081901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.751081901
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_stress_all.2752374944
Short name T16
Test name
Test status
Simulation time 83641591 ps
CPU time 0.72 seconds
Started Mar 12 12:51:53 PM PDT 24
Finished Mar 12 12:51:54 PM PDT 24
Peak memory 195404 kb
Host smart-8dacac34-6e91-49ec-87d6-8b212428168c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752374944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all.2752374944
Directory /workspace/43.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup_reset.40091549
Short name T162
Test name
Test status
Simulation time 187847498 ps
CPU time 0.81 seconds
Started Mar 12 12:51:55 PM PDT 24
Finished Mar 12 12:51:56 PM PDT 24
Peak memory 197872 kb
Host smart-6054a98b-d110-4d69-acc9-6f2e7b064e1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40091549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.40091549
Directory /workspace/43.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.1109218555
Short name T315
Test name
Test status
Simulation time 78029418 ps
CPU time 0.72 seconds
Started Mar 12 12:51:56 PM PDT 24
Finished Mar 12 12:51:56 PM PDT 24
Peak memory 195264 kb
Host smart-853ec90e-32b0-457c-89c1-b3962d9b264a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109218555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.1109218555
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.2827986258
Short name T123
Test name
Test status
Simulation time 52077213 ps
CPU time 0.82 seconds
Started Mar 12 12:51:36 PM PDT 24
Finished Mar 12 12:51:37 PM PDT 24
Peak memory 197704 kb
Host smart-919424eb-7b99-4a8d-95dc-b9c2d6499388
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827986258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.2827986258
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.3703982787
Short name T780
Test name
Test status
Simulation time 36720768 ps
CPU time 0.57 seconds
Started Mar 12 12:51:45 PM PDT 24
Finished Mar 12 12:51:45 PM PDT 24
Peak memory 195328 kb
Host smart-73c80cab-a93c-4084-9ca6-b3b2e54312b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703982787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst
_malfunc.3703982787
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.3990672097
Short name T159
Test name
Test status
Simulation time 166492245 ps
CPU time 1.04 seconds
Started Mar 12 12:51:54 PM PDT 24
Finished Mar 12 12:51:56 PM PDT 24
Peak memory 195424 kb
Host smart-cdc51e41-e19c-4b59-8854-ac39af23efab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990672097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.3990672097
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.2903614736
Short name T759
Test name
Test status
Simulation time 58413160 ps
CPU time 0.63 seconds
Started Mar 12 12:51:39 PM PDT 24
Finished Mar 12 12:51:40 PM PDT 24
Peak memory 195420 kb
Host smart-408b7836-b147-4438-8bc8-8a2bdb2daa76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903614736 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.2903614736
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.2094393252
Short name T385
Test name
Test status
Simulation time 55017494 ps
CPU time 0.62 seconds
Started Mar 12 12:51:36 PM PDT 24
Finished Mar 12 12:51:38 PM PDT 24
Peak memory 195388 kb
Host smart-f6d728aa-e5ef-48f1-bf14-399a718f7873
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094393252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.2094393252
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.2096475996
Short name T54
Test name
Test status
Simulation time 41340198 ps
CPU time 0.77 seconds
Started Mar 12 12:51:51 PM PDT 24
Finished Mar 12 12:51:52 PM PDT 24
Peak memory 195900 kb
Host smart-0bf82b68-c8ab-469c-9dc8-d324c6b5cf4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096475996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.2096475996
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.1243150832
Short name T811
Test name
Test status
Simulation time 177474985 ps
CPU time 0.87 seconds
Started Mar 12 12:51:56 PM PDT 24
Finished Mar 12 12:51:56 PM PDT 24
Peak memory 197848 kb
Host smart-eeed2e39-ecd2-40d4-8467-7256ac0af7d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243150832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.1243150832
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.3922884897
Short name T684
Test name
Test status
Simulation time 114949411 ps
CPU time 0.92 seconds
Started Mar 12 12:51:46 PM PDT 24
Finished Mar 12 12:51:47 PM PDT 24
Peak memory 206496 kb
Host smart-d7ed53c4-27c3-4609-972f-b955354404ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922884897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.3922884897
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.2435059167
Short name T821
Test name
Test status
Simulation time 257136676 ps
CPU time 0.67 seconds
Started Mar 12 12:51:53 PM PDT 24
Finished Mar 12 12:51:54 PM PDT 24
Peak memory 195336 kb
Host smart-6d90791d-5915-4174-83c1-f8c3f4c75171
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435059167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_
cm_ctrl_config_regwen.2435059167
Directory /workspace/44.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1206717338
Short name T574
Test name
Test status
Simulation time 1206756590 ps
CPU time 2.14 seconds
Started Mar 12 12:51:57 PM PDT 24
Finished Mar 12 12:51:59 PM PDT 24
Peak memory 200704 kb
Host smart-e2d1a6e9-e835-4fa4-ae07-d680021fe2e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206717338 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1206717338
Directory /workspace/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2807094992
Short name T515
Test name
Test status
Simulation time 1832748912 ps
CPU time 1.99 seconds
Started Mar 12 12:51:54 PM PDT 24
Finished Mar 12 12:51:56 PM PDT 24
Peak memory 195916 kb
Host smart-3b0a6855-4294-4821-8fb3-0a5f1c5dc1fb
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807094992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2807094992
Directory /workspace/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.2662366128
Short name T512
Test name
Test status
Simulation time 63863486 ps
CPU time 0.85 seconds
Started Mar 12 12:51:54 PM PDT 24
Finished Mar 12 12:51:55 PM PDT 24
Peak memory 195372 kb
Host smart-c0584138-8688-4b2e-8c6a-154717773ca9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662366128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2662366128
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.1757030334
Short name T267
Test name
Test status
Simulation time 29855076 ps
CPU time 0.71 seconds
Started Mar 12 12:51:54 PM PDT 24
Finished Mar 12 12:51:55 PM PDT 24
Peak memory 197716 kb
Host smart-271bdf50-ab7a-41df-8631-7e65cd67c6b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757030334 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.1757030334
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup.2007491389
Short name T495
Test name
Test status
Simulation time 225069142 ps
CPU time 0.74 seconds
Started Mar 12 12:51:36 PM PDT 24
Finished Mar 12 12:51:37 PM PDT 24
Peak memory 195356 kb
Host smart-745c6aaf-7f78-4b3d-a2d0-b43b982e2edb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007491389 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.2007491389
Directory /workspace/44.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup_reset.718650467
Short name T737
Test name
Test status
Simulation time 131882935 ps
CPU time 0.84 seconds
Started Mar 12 12:51:48 PM PDT 24
Finished Mar 12 12:51:49 PM PDT 24
Peak memory 197784 kb
Host smart-f3f665b7-66c0-4639-97b2-004c41e60776
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718650467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.718650467
Directory /workspace/44.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.3853200999
Short name T135
Test name
Test status
Simulation time 50696943 ps
CPU time 0.86 seconds
Started Mar 12 12:51:55 PM PDT 24
Finished Mar 12 12:51:56 PM PDT 24
Peak memory 195552 kb
Host smart-a27aa7ea-f711-47a1-8f7f-56ba044cb015
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853200999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.3853200999
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.3273802095
Short name T387
Test name
Test status
Simulation time 29666979 ps
CPU time 0.63 seconds
Started Mar 12 12:51:50 PM PDT 24
Finished Mar 12 12:51:51 PM PDT 24
Peak memory 195312 kb
Host smart-d56df584-ea66-4642-adb4-5d15d9d30843
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273802095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.3273802095
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.594115425
Short name T197
Test name
Test status
Simulation time 764097789 ps
CPU time 0.98 seconds
Started Mar 12 12:51:46 PM PDT 24
Finished Mar 12 12:51:47 PM PDT 24
Peak memory 195324 kb
Host smart-a518cae3-1f21-4c89-ae9e-2e1617b89b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594115425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.594115425
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.2669569939
Short name T242
Test name
Test status
Simulation time 33954852 ps
CPU time 0.62 seconds
Started Mar 12 12:51:51 PM PDT 24
Finished Mar 12 12:51:52 PM PDT 24
Peak memory 195416 kb
Host smart-4eaf13ff-8251-4c69-901f-ca2e0dd159bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669569939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.2669569939
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.1727778417
Short name T745
Test name
Test status
Simulation time 32839304 ps
CPU time 0.6 seconds
Started Mar 12 12:51:40 PM PDT 24
Finished Mar 12 12:51:41 PM PDT 24
Peak memory 195408 kb
Host smart-5adf9d61-58ad-4aeb-b832-e1a71213a2a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727778417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.1727778417
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.3303488095
Short name T144
Test name
Test status
Simulation time 44520719 ps
CPU time 0.72 seconds
Started Mar 12 12:51:36 PM PDT 24
Finished Mar 12 12:51:37 PM PDT 24
Peak memory 195956 kb
Host smart-6f5a8712-abb5-4cdc-9783-3927c4d65e2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303488095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.3303488095
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_wakeup_race.3849330939
Short name T326
Test name
Test status
Simulation time 94486288 ps
CPU time 0.81 seconds
Started Mar 12 12:51:39 PM PDT 24
Finished Mar 12 12:51:40 PM PDT 24
Peak memory 195380 kb
Host smart-c306b15b-a66e-4f8e-828c-f27deaa9ed3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849330939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_w
akeup_race.3849330939
Directory /workspace/45.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.1341568478
Short name T211
Test name
Test status
Simulation time 192716833 ps
CPU time 0.78 seconds
Started Mar 12 12:51:53 PM PDT 24
Finished Mar 12 12:51:54 PM PDT 24
Peak memory 197720 kb
Host smart-7be830a2-059e-448b-874b-ef2247dd1f40
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341568478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.1341568478
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.196113248
Short name T544
Test name
Test status
Simulation time 127486495 ps
CPU time 0.84 seconds
Started Mar 12 12:51:45 PM PDT 24
Finished Mar 12 12:51:46 PM PDT 24
Peak memory 205336 kb
Host smart-0fdafb4a-b8af-44cc-9ac6-b42c90b3cd5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196113248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.196113248
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.281132640
Short name T38
Test name
Test status
Simulation time 836575638 ps
CPU time 3.02 seconds
Started Mar 12 12:51:52 PM PDT 24
Finished Mar 12 12:51:55 PM PDT 24
Peak memory 200724 kb
Host smart-28f08499-61f4-479c-a914-416d02bb1473
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281132640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.281132640
Directory /workspace/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3354287812
Short name T251
Test name
Test status
Simulation time 825346483 ps
CPU time 3.03 seconds
Started Mar 12 12:51:45 PM PDT 24
Finished Mar 12 12:51:48 PM PDT 24
Peak memory 195940 kb
Host smart-e89a2dc9-7a13-4d57-81ab-7bd7efb11de6
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354287812 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3354287812
Directory /workspace/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.432642216
Short name T708
Test name
Test status
Simulation time 64282116 ps
CPU time 0.83 seconds
Started Mar 12 12:51:51 PM PDT 24
Finished Mar 12 12:51:52 PM PDT 24
Peak memory 195332 kb
Host smart-3d43a047-30cd-45e9-897d-6ea0b97b5da6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432642216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig_
mubi.432642216
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.1034588266
Short name T187
Test name
Test status
Simulation time 55562035 ps
CPU time 0.63 seconds
Started Mar 12 12:51:54 PM PDT 24
Finished Mar 12 12:51:55 PM PDT 24
Peak memory 195592 kb
Host smart-53f89ee7-b194-48ce-b871-5c8842a53809
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034588266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.1034588266
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup.1322514847
Short name T7
Test name
Test status
Simulation time 238176018 ps
CPU time 0.91 seconds
Started Mar 12 12:51:55 PM PDT 24
Finished Mar 12 12:51:56 PM PDT 24
Peak memory 195348 kb
Host smart-63520322-b2eb-43e1-a6c0-8166025a6911
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322514847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup.1322514847
Directory /workspace/45.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup_reset.1691547752
Short name T455
Test name
Test status
Simulation time 291829082 ps
CPU time 0.95 seconds
Started Mar 12 12:51:40 PM PDT 24
Finished Mar 12 12:51:41 PM PDT 24
Peak memory 197920 kb
Host smart-ac73269f-2fba-4e67-9feb-01f44c98cc5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691547752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.1691547752
Directory /workspace/45.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.256775758
Short name T207
Test name
Test status
Simulation time 69947554 ps
CPU time 0.74 seconds
Started Mar 12 12:51:59 PM PDT 24
Finished Mar 12 12:52:00 PM PDT 24
Peak memory 197620 kb
Host smart-a79be9e5-720c-4824-be75-2b86be59935d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256775758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disa
ble_rom_integrity_check.256775758
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.358304133
Short name T451
Test name
Test status
Simulation time 34930469 ps
CPU time 0.57 seconds
Started Mar 12 12:52:12 PM PDT 24
Finished Mar 12 12:52:12 PM PDT 24
Peak memory 195360 kb
Host smart-90b0ccb8-097b-4770-9539-8aeb14363ed0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358304133 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst_
malfunc.358304133
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.520119888
Short name T849
Test name
Test status
Simulation time 242067589 ps
CPU time 0.94 seconds
Started Mar 12 12:51:54 PM PDT 24
Finished Mar 12 12:51:55 PM PDT 24
Peak memory 195420 kb
Host smart-6ceb00b2-7d1f-4e10-bf0d-f47e1bcd507e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520119888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.520119888
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.757251804
Short name T19
Test name
Test status
Simulation time 47432469 ps
CPU time 0.59 seconds
Started Mar 12 12:52:02 PM PDT 24
Finished Mar 12 12:52:03 PM PDT 24
Peak memory 195352 kb
Host smart-b1341cc7-ae47-4bb5-8b84-b4c3a34bbe71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757251804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.757251804
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.493681240
Short name T804
Test name
Test status
Simulation time 55549202 ps
CPU time 0.59 seconds
Started Mar 12 12:51:56 PM PDT 24
Finished Mar 12 12:51:56 PM PDT 24
Peak memory 195444 kb
Host smart-1874f501-15bc-40a5-9dde-3fae4f491a7e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493681240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.493681240
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.618798505
Short name T331
Test name
Test status
Simulation time 64924237 ps
CPU time 0.64 seconds
Started Mar 12 12:51:56 PM PDT 24
Finished Mar 12 12:51:57 PM PDT 24
Peak memory 195820 kb
Host smart-e938f694-df71-447d-a470-9028f6176d0f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618798505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_invali
d.618798505
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.3337989198
Short name T266
Test name
Test status
Simulation time 62414038 ps
CPU time 0.79 seconds
Started Mar 12 12:51:49 PM PDT 24
Finished Mar 12 12:51:50 PM PDT 24
Peak memory 197632 kb
Host smart-411ab83c-dd22-4e2f-950c-9fd23ec7dec2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337989198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.3337989198
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.3565186744
Short name T172
Test name
Test status
Simulation time 168320573 ps
CPU time 0.77 seconds
Started Mar 12 12:51:59 PM PDT 24
Finished Mar 12 12:52:00 PM PDT 24
Peak memory 205244 kb
Host smart-cd84040f-a306-489b-9926-06f40cd99b49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565186744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.3565186744
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.2184739418
Short name T553
Test name
Test status
Simulation time 317303957 ps
CPU time 1.14 seconds
Started Mar 12 12:51:59 PM PDT 24
Finished Mar 12 12:52:00 PM PDT 24
Peak memory 195620 kb
Host smart-a8fc374d-b368-4904-b737-0b7394414d28
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184739418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_
cm_ctrl_config_regwen.2184739418
Directory /workspace/46.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2687431249
Short name T350
Test name
Test status
Simulation time 871814672 ps
CPU time 3.12 seconds
Started Mar 12 12:52:04 PM PDT 24
Finished Mar 12 12:52:07 PM PDT 24
Peak memory 200948 kb
Host smart-e6e88bb6-cf58-453e-9c4e-c83b455aa438
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687431249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2687431249
Directory /workspace/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3562474735
Short name T586
Test name
Test status
Simulation time 1296097497 ps
CPU time 1.84 seconds
Started Mar 12 12:51:53 PM PDT 24
Finished Mar 12 12:51:55 PM PDT 24
Peak memory 195988 kb
Host smart-f09ed453-1133-46ad-a046-fe26b9fad18c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562474735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3562474735
Directory /workspace/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.1507947174
Short name T356
Test name
Test status
Simulation time 62104474 ps
CPU time 0.8 seconds
Started Mar 12 12:52:01 PM PDT 24
Finished Mar 12 12:52:02 PM PDT 24
Peak memory 195384 kb
Host smart-5eb6a69c-497e-47ec-911f-518251511a41
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507947174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1507947174
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.3610128912
Short name T346
Test name
Test status
Simulation time 30204317 ps
CPU time 0.75 seconds
Started Mar 12 12:51:54 PM PDT 24
Finished Mar 12 12:51:55 PM PDT 24
Peak memory 197768 kb
Host smart-22a7fb93-b451-4b66-a8a3-807c1a040d33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610128912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.3610128912
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup.3749531898
Short name T571
Test name
Test status
Simulation time 140253667 ps
CPU time 0.83 seconds
Started Mar 12 12:51:58 PM PDT 24
Finished Mar 12 12:51:59 PM PDT 24
Peak memory 195340 kb
Host smart-136e64a4-6bd1-47b6-a5ae-8d824b48cb85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749531898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.3749531898
Directory /workspace/46.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup_reset.1629455652
Short name T86
Test name
Test status
Simulation time 90933147 ps
CPU time 0.78 seconds
Started Mar 12 12:51:59 PM PDT 24
Finished Mar 12 12:52:00 PM PDT 24
Peak memory 197952 kb
Host smart-00a5886c-335b-4fb7-ae73-97aa2ce858e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629455652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.1629455652
Directory /workspace/46.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.3718893509
Short name T647
Test name
Test status
Simulation time 16165137 ps
CPU time 0.61 seconds
Started Mar 12 12:51:56 PM PDT 24
Finished Mar 12 12:51:56 PM PDT 24
Peak memory 195392 kb
Host smart-a57ad790-4c27-4160-bd1a-32ad9572ae1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718893509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.3718893509
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.3600879113
Short name T550
Test name
Test status
Simulation time 77235390 ps
CPU time 0.74 seconds
Started Mar 12 12:51:49 PM PDT 24
Finished Mar 12 12:51:50 PM PDT 24
Peak memory 197680 kb
Host smart-0671df94-162f-467d-897c-768edfb68c40
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600879113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.3600879113
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.3348022597
Short name T671
Test name
Test status
Simulation time 41133614 ps
CPU time 0.6 seconds
Started Mar 12 12:52:02 PM PDT 24
Finished Mar 12 12:52:03 PM PDT 24
Peak memory 195336 kb
Host smart-fbc77d4f-c9ff-4ccc-90c2-0e4f2c853694
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348022597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst
_malfunc.3348022597
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.3226234306
Short name T90
Test name
Test status
Simulation time 313677268 ps
CPU time 0.97 seconds
Started Mar 12 12:51:43 PM PDT 24
Finished Mar 12 12:51:44 PM PDT 24
Peak memory 195428 kb
Host smart-1b54cee1-9e83-40da-ba8f-6d9b272e94a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226234306 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.3226234306
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.810758874
Short name T309
Test name
Test status
Simulation time 39868891 ps
CPU time 0.58 seconds
Started Mar 12 12:52:00 PM PDT 24
Finished Mar 12 12:52:01 PM PDT 24
Peak memory 195368 kb
Host smart-aca6bdc7-c636-481b-a6ee-85f2dee9c013
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810758874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.810758874
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.2769508119
Short name T10
Test name
Test status
Simulation time 36488106 ps
CPU time 0.64 seconds
Started Mar 12 12:52:14 PM PDT 24
Finished Mar 12 12:52:15 PM PDT 24
Peak memory 195408 kb
Host smart-15ddbebf-c708-45dd-a155-31c6c3832540
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769508119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.2769508119
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.2698620241
Short name T615
Test name
Test status
Simulation time 163633781 ps
CPU time 0.64 seconds
Started Mar 12 12:51:54 PM PDT 24
Finished Mar 12 12:51:55 PM PDT 24
Peak memory 195832 kb
Host smart-e69757b0-c506-412e-81f2-c3bffd444c82
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698620241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.2698620241
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_wakeup_race.1207755799
Short name T807
Test name
Test status
Simulation time 191084258 ps
CPU time 0.85 seconds
Started Mar 12 12:51:55 PM PDT 24
Finished Mar 12 12:51:56 PM PDT 24
Peak memory 195308 kb
Host smart-4572abd4-44e8-4891-aaad-ce11915d0cdf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207755799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_w
akeup_race.1207755799
Directory /workspace/47.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.473429758
Short name T743
Test name
Test status
Simulation time 67993849 ps
CPU time 0.91 seconds
Started Mar 12 12:51:42 PM PDT 24
Finished Mar 12 12:51:43 PM PDT 24
Peak memory 197756 kb
Host smart-32eff0cf-47a6-4efc-bf71-a1e19f3efd1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473429758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.473429758
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.1687145450
Short name T347
Test name
Test status
Simulation time 108753681 ps
CPU time 0.94 seconds
Started Mar 12 12:52:00 PM PDT 24
Finished Mar 12 12:52:01 PM PDT 24
Peak memory 205260 kb
Host smart-f6bfb37b-4312-4e64-8543-11a68bd50dfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687145450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.1687145450
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.421093423
Short name T838
Test name
Test status
Simulation time 171929457 ps
CPU time 0.68 seconds
Started Mar 12 12:51:53 PM PDT 24
Finished Mar 12 12:51:53 PM PDT 24
Peak memory 195268 kb
Host smart-bb0835d6-870a-4a30-9012-a903388e324e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421093423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_c
m_ctrl_config_regwen.421093423
Directory /workspace/47.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.968354291
Short name T779
Test name
Test status
Simulation time 778143008 ps
CPU time 3.04 seconds
Started Mar 12 12:51:58 PM PDT 24
Finished Mar 12 12:52:01 PM PDT 24
Peak memory 200988 kb
Host smart-1ecf51a1-c29b-48af-8b97-cf0f657a4852
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968354291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.968354291
Directory /workspace/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1961403172
Short name T691
Test name
Test status
Simulation time 993537592 ps
CPU time 2.46 seconds
Started Mar 12 12:51:55 PM PDT 24
Finished Mar 12 12:51:58 PM PDT 24
Peak memory 195808 kb
Host smart-026086d5-c041-40f0-ae5f-0dfbfb26f13c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961403172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1961403172
Directory /workspace/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.3547774385
Short name T857
Test name
Test status
Simulation time 87917619 ps
CPU time 0.83 seconds
Started Mar 12 12:52:04 PM PDT 24
Finished Mar 12 12:52:05 PM PDT 24
Peak memory 195356 kb
Host smart-c1701544-b55d-42f4-a97b-a57e1673342a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547774385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3547774385
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.2231392758
Short name T377
Test name
Test status
Simulation time 53740724 ps
CPU time 0.65 seconds
Started Mar 12 12:51:53 PM PDT 24
Finished Mar 12 12:51:54 PM PDT 24
Peak memory 197708 kb
Host smart-38b0be09-34b7-46e8-b154-bb6e41ce9584
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231392758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.2231392758
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup.3319174099
Short name T249
Test name
Test status
Simulation time 117458514 ps
CPU time 0.85 seconds
Started Mar 12 12:51:59 PM PDT 24
Finished Mar 12 12:52:00 PM PDT 24
Peak memory 195316 kb
Host smart-37142c55-8908-4cfe-80fd-fc19db35d5f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319174099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup.3319174099
Directory /workspace/47.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup_reset.1773014873
Short name T840
Test name
Test status
Simulation time 264660393 ps
CPU time 1.35 seconds
Started Mar 12 12:51:47 PM PDT 24
Finished Mar 12 12:51:48 PM PDT 24
Peak memory 199452 kb
Host smart-2ffcb575-0ee0-42d6-88ed-5a4310b094a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773014873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.1773014873
Directory /workspace/47.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.1853804294
Short name T851
Test name
Test status
Simulation time 221992440 ps
CPU time 0.71 seconds
Started Mar 12 12:51:55 PM PDT 24
Finished Mar 12 12:51:56 PM PDT 24
Peak memory 195516 kb
Host smart-752d9f73-9eb5-4ae6-8bda-92d44be40fc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853804294 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.1853804294
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.528411416
Short name T796
Test name
Test status
Simulation time 29468806 ps
CPU time 0.66 seconds
Started Mar 12 12:52:01 PM PDT 24
Finished Mar 12 12:52:02 PM PDT 24
Peak memory 195296 kb
Host smart-fd746f3c-b463-454d-8e75-b19a4f38291c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528411416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst_
malfunc.528411416
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.316189031
Short name T536
Test name
Test status
Simulation time 159661251 ps
CPU time 0.99 seconds
Started Mar 12 12:52:01 PM PDT 24
Finished Mar 12 12:52:02 PM PDT 24
Peak memory 195360 kb
Host smart-609188bb-1530-4c9a-9eeb-1688adc35bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316189031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.316189031
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.3454871406
Short name T463
Test name
Test status
Simulation time 71146972 ps
CPU time 0.6 seconds
Started Mar 12 12:52:03 PM PDT 24
Finished Mar 12 12:52:04 PM PDT 24
Peak memory 195444 kb
Host smart-c162c2ed-d9f2-4afd-ba28-f0ff5eaff1c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454871406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.3454871406
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.3257042246
Short name T261
Test name
Test status
Simulation time 60489603 ps
CPU time 0.6 seconds
Started Mar 12 12:51:55 PM PDT 24
Finished Mar 12 12:51:56 PM PDT 24
Peak memory 195400 kb
Host smart-46bd58d5-c7de-4338-9854-f8ca43f3a55f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257042246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.3257042246
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.65078729
Short name T399
Test name
Test status
Simulation time 42201693 ps
CPU time 0.72 seconds
Started Mar 12 12:52:09 PM PDT 24
Finished Mar 12 12:52:10 PM PDT 24
Peak memory 195880 kb
Host smart-c56821f8-ddce-4178-a594-d21bb7916b3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65078729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_invalid
.65078729
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.517913089
Short name T787
Test name
Test status
Simulation time 120919812 ps
CPU time 0.8 seconds
Started Mar 12 12:51:54 PM PDT 24
Finished Mar 12 12:51:55 PM PDT 24
Peak memory 197716 kb
Host smart-45bbb64f-2d26-4f2a-81e9-529b4d78bdb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517913089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.517913089
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.2800992739
Short name T505
Test name
Test status
Simulation time 157389201 ps
CPU time 0.81 seconds
Started Mar 12 12:51:59 PM PDT 24
Finished Mar 12 12:52:00 PM PDT 24
Peak memory 204524 kb
Host smart-ecb6ba8a-0a9f-4eb5-aafb-bd0248a73d42
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800992739 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.2800992739
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.3639237139
Short name T218
Test name
Test status
Simulation time 389099629 ps
CPU time 0.99 seconds
Started Mar 12 12:51:56 PM PDT 24
Finished Mar 12 12:51:57 PM PDT 24
Peak memory 195348 kb
Host smart-d4f85c0f-2cf4-4432-870b-25243e35e016
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639237139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_
cm_ctrl_config_regwen.3639237139
Directory /workspace/48.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2508935427
Short name T652
Test name
Test status
Simulation time 998747629 ps
CPU time 2.09 seconds
Started Mar 12 12:51:56 PM PDT 24
Finished Mar 12 12:51:58 PM PDT 24
Peak memory 200920 kb
Host smart-bd90107d-0d13-4727-b09d-904a4da2df0b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508935427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2508935427
Directory /workspace/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2910840368
Short name T375
Test name
Test status
Simulation time 1493682739 ps
CPU time 2.23 seconds
Started Mar 12 12:51:52 PM PDT 24
Finished Mar 12 12:51:54 PM PDT 24
Peak memory 195980 kb
Host smart-aca5a02e-b19a-43f7-be66-5994c395026e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910840368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2910840368
Directory /workspace/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1488406446
Short name T247
Test name
Test status
Simulation time 63114206 ps
CPU time 0.82 seconds
Started Mar 12 12:51:48 PM PDT 24
Finished Mar 12 12:51:49 PM PDT 24
Peak memory 195328 kb
Host smart-1ffb01e0-486b-4064-a45a-e478f7febe91
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488406446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1488406446
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.881474299
Short name T798
Test name
Test status
Simulation time 67742480 ps
CPU time 0.62 seconds
Started Mar 12 12:51:44 PM PDT 24
Finished Mar 12 12:51:45 PM PDT 24
Peak memory 195620 kb
Host smart-32c88418-b463-41f6-ac6b-b5a18784197c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881474299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.881474299
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup.2467505637
Short name T179
Test name
Test status
Simulation time 272719958 ps
CPU time 0.88 seconds
Started Mar 12 12:51:45 PM PDT 24
Finished Mar 12 12:51:46 PM PDT 24
Peak memory 195340 kb
Host smart-690f40e3-fe42-4a7c-aa88-d56406f29a71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467505637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.2467505637
Directory /workspace/48.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup_reset.693823968
Short name T368
Test name
Test status
Simulation time 289088250 ps
CPU time 0.93 seconds
Started Mar 12 12:51:53 PM PDT 24
Finished Mar 12 12:51:54 PM PDT 24
Peak memory 197964 kb
Host smart-6edb911e-5ae6-428e-bcbc-b6d9caa14803
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693823968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.693823968
Directory /workspace/48.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.1803821839
Short name T533
Test name
Test status
Simulation time 32691154 ps
CPU time 0.62 seconds
Started Mar 12 12:51:52 PM PDT 24
Finished Mar 12 12:51:53 PM PDT 24
Peak memory 197492 kb
Host smart-ce60142f-a427-41d1-b1f8-2334844168aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803821839 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.1803821839
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.1111195606
Short name T476
Test name
Test status
Simulation time 79329436 ps
CPU time 0.71 seconds
Started Mar 12 12:51:58 PM PDT 24
Finished Mar 12 12:51:58 PM PDT 24
Peak memory 196524 kb
Host smart-b80c6681-d043-44fb-9942-eaeb83c20fb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111195606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.1111195606
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.928278383
Short name T370
Test name
Test status
Simulation time 38919613 ps
CPU time 0.59 seconds
Started Mar 12 12:51:55 PM PDT 24
Finished Mar 12 12:51:55 PM PDT 24
Peak memory 195340 kb
Host smart-9adb23c7-32d6-4221-8bb4-6874353f8eea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928278383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst_
malfunc.928278383
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.1391917666
Short name T568
Test name
Test status
Simulation time 167172016 ps
CPU time 0.96 seconds
Started Mar 12 12:52:08 PM PDT 24
Finished Mar 12 12:52:10 PM PDT 24
Peak memory 195420 kb
Host smart-6eac732c-e029-4c14-a64e-1590801b349b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391917666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.1391917666
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.3923888073
Short name T483
Test name
Test status
Simulation time 46634299 ps
CPU time 0.66 seconds
Started Mar 12 12:52:00 PM PDT 24
Finished Mar 12 12:52:00 PM PDT 24
Peak memory 195364 kb
Host smart-cc3f5700-7107-4975-b12d-7e247dccd0cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923888073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.3923888073
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.688712031
Short name T300
Test name
Test status
Simulation time 31335846 ps
CPU time 0.63 seconds
Started Mar 12 12:51:58 PM PDT 24
Finished Mar 12 12:51:59 PM PDT 24
Peak memory 195436 kb
Host smart-514aac15-cfff-47c5-b1c1-338b881f9832
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688712031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.688712031
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.2414605656
Short name T789
Test name
Test status
Simulation time 43028434 ps
CPU time 0.68 seconds
Started Mar 12 12:52:07 PM PDT 24
Finished Mar 12 12:52:08 PM PDT 24
Peak memory 195776 kb
Host smart-852509e3-3a24-40d9-8e0d-3c598b33956a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414605656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.2414605656
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.2346196234
Short name T635
Test name
Test status
Simulation time 84187979 ps
CPU time 0.9 seconds
Started Mar 12 12:51:54 PM PDT 24
Finished Mar 12 12:51:55 PM PDT 24
Peak memory 197756 kb
Host smart-5118c2cf-622c-47e7-82b1-5be81693d89e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346196234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.2346196234
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.1449768644
Short name T711
Test name
Test status
Simulation time 165300151 ps
CPU time 0.78 seconds
Started Mar 12 12:51:58 PM PDT 24
Finished Mar 12 12:51:58 PM PDT 24
Peak memory 205948 kb
Host smart-25870ea7-6416-436d-9dd3-ff4bcc000282
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449768644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.1449768644
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.3786581016
Short name T62
Test name
Test status
Simulation time 108637037 ps
CPU time 0.7 seconds
Started Mar 12 12:51:56 PM PDT 24
Finished Mar 12 12:51:57 PM PDT 24
Peak memory 195392 kb
Host smart-df12b28a-9a8b-4ebb-b12d-26000d43a2b1
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786581016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_
cm_ctrl_config_regwen.3786581016
Directory /workspace/49.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3669767147
Short name T312
Test name
Test status
Simulation time 919062083 ps
CPU time 2.49 seconds
Started Mar 12 12:52:02 PM PDT 24
Finished Mar 12 12:52:05 PM PDT 24
Peak memory 201164 kb
Host smart-4c2b0456-2575-4772-9843-9a85a4808267
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669767147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3669767147
Directory /workspace/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2831323990
Short name T864
Test name
Test status
Simulation time 2627479230 ps
CPU time 2.1 seconds
Started Mar 12 12:52:13 PM PDT 24
Finished Mar 12 12:52:15 PM PDT 24
Peak memory 196016 kb
Host smart-45c005be-e2dd-4367-a16c-96ee6ce86587
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831323990 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2831323990
Directory /workspace/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.2132885892
Short name T625
Test name
Test status
Simulation time 146748979 ps
CPU time 0.82 seconds
Started Mar 12 12:51:55 PM PDT 24
Finished Mar 12 12:51:56 PM PDT 24
Peak memory 195376 kb
Host smart-a968877e-28ca-4e6f-a4fd-09f6b9c757df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132885892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2132885892
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.2432223687
Short name T371
Test name
Test status
Simulation time 30205395 ps
CPU time 0.71 seconds
Started Mar 12 12:51:51 PM PDT 24
Finished Mar 12 12:51:52 PM PDT 24
Peak memory 195628 kb
Host smart-088c34d3-e83f-490d-adda-82df9ae296fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432223687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.2432223687
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup.2151096653
Short name T492
Test name
Test status
Simulation time 163368091 ps
CPU time 1.03 seconds
Started Mar 12 12:51:59 PM PDT 24
Finished Mar 12 12:52:00 PM PDT 24
Peak memory 194540 kb
Host smart-76e80ace-1070-4ffc-abd1-e61797592bea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151096653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.2151096653
Directory /workspace/49.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup_reset.819457734
Short name T813
Test name
Test status
Simulation time 209606524 ps
CPU time 0.85 seconds
Started Mar 12 12:51:47 PM PDT 24
Finished Mar 12 12:51:48 PM PDT 24
Peak memory 197876 kb
Host smart-c8b397d3-dbd0-4714-bf36-78b808669418
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819457734 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.819457734
Directory /workspace/49.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.17709410
Short name T423
Test name
Test status
Simulation time 34073859 ps
CPU time 0.74 seconds
Started Mar 12 12:49:43 PM PDT 24
Finished Mar 12 12:49:44 PM PDT 24
Peak memory 195308 kb
Host smart-eed8f3e4-8fca-469b-936e-60c329411e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17709410 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.17709410
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.2813166073
Short name T583
Test name
Test status
Simulation time 64454563 ps
CPU time 0.82 seconds
Started Mar 12 12:50:05 PM PDT 24
Finished Mar 12 12:50:06 PM PDT 24
Peak memory 197628 kb
Host smart-e4f5afdd-fe50-46cf-ac86-3637d5ec36fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813166073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.2813166073
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.1311348822
Short name T151
Test name
Test status
Simulation time 31070165 ps
CPU time 0.66 seconds
Started Mar 12 12:50:00 PM PDT 24
Finished Mar 12 12:50:03 PM PDT 24
Peak memory 195340 kb
Host smart-ad9f49e9-7e36-4d2b-adb3-0c406c620551
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311348822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_
malfunc.1311348822
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.2039322447
Short name T648
Test name
Test status
Simulation time 162167437 ps
CPU time 0.97 seconds
Started Mar 12 12:49:57 PM PDT 24
Finished Mar 12 12:49:59 PM PDT 24
Peak memory 195416 kb
Host smart-1b326c8d-bd11-485d-bae5-05ecb9cf2b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039322447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.2039322447
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.1049843795
Short name T506
Test name
Test status
Simulation time 76043089 ps
CPU time 0.71 seconds
Started Mar 12 12:49:59 PM PDT 24
Finished Mar 12 12:50:00 PM PDT 24
Peak memory 195348 kb
Host smart-208a098e-1a91-48d8-ad08-01bfaadf036a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049843795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.1049843795
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.1118730023
Short name T712
Test name
Test status
Simulation time 37396917 ps
CPU time 0.57 seconds
Started Mar 12 12:50:07 PM PDT 24
Finished Mar 12 12:50:08 PM PDT 24
Peak memory 195448 kb
Host smart-97ea0a48-cbf0-4353-ba47-d3dc96e4575d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118730023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.1118730023
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.2694409727
Short name T718
Test name
Test status
Simulation time 54168807 ps
CPU time 0.67 seconds
Started Mar 12 12:50:04 PM PDT 24
Finished Mar 12 12:50:05 PM PDT 24
Peak memory 195836 kb
Host smart-a069973a-2746-4780-ae90-0e9e1178515e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694409727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali
d.2694409727
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_wakeup_race.122065473
Short name T258
Test name
Test status
Simulation time 445518665 ps
CPU time 0.93 seconds
Started Mar 12 12:49:46 PM PDT 24
Finished Mar 12 12:49:47 PM PDT 24
Peak memory 195336 kb
Host smart-9b6d0c46-305f-4200-bdf8-bb044b0c47e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122065473 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wak
eup_race.122065473
Directory /workspace/5.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.3242375368
Short name T783
Test name
Test status
Simulation time 54748327 ps
CPU time 0.8 seconds
Started Mar 12 12:49:42 PM PDT 24
Finished Mar 12 12:49:43 PM PDT 24
Peak memory 197612 kb
Host smart-3a4e78ec-7f27-45fe-abcc-1574ef98d931
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242375368 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.3242375368
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.3968175210
Short name T740
Test name
Test status
Simulation time 95901480 ps
CPU time 1.02 seconds
Started Mar 12 12:49:57 PM PDT 24
Finished Mar 12 12:50:00 PM PDT 24
Peak memory 196436 kb
Host smart-17773850-b57e-4338-8f59-b54764bcb896
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968175210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.3968175210
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.3391141590
Short name T60
Test name
Test status
Simulation time 806343789 ps
CPU time 0.95 seconds
Started Mar 12 12:49:59 PM PDT 24
Finished Mar 12 12:50:02 PM PDT 24
Peak memory 195384 kb
Host smart-3f8b4afb-e092-4a3e-a6ff-5ae38ab85a8d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391141590 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_c
m_ctrl_config_regwen.3391141590
Directory /workspace/5.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2838674354
Short name T89
Test name
Test status
Simulation time 1308062710 ps
CPU time 2.08 seconds
Started Mar 12 12:49:53 PM PDT 24
Finished Mar 12 12:49:55 PM PDT 24
Peak memory 201044 kb
Host smart-c6c0f919-386a-42b0-9db9-e04646f82244
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838674354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2838674354
Directory /workspace/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1930282378
Short name T148
Test name
Test status
Simulation time 902917846 ps
CPU time 3.31 seconds
Started Mar 12 12:49:43 PM PDT 24
Finished Mar 12 12:49:47 PM PDT 24
Peak memory 195872 kb
Host smart-8b6a186a-5571-4ca9-96ea-015bfe607b1c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930282378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1930282378
Directory /workspace/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3659204210
Short name T471
Test name
Test status
Simulation time 166025080 ps
CPU time 0.89 seconds
Started Mar 12 12:49:57 PM PDT 24
Finished Mar 12 12:50:00 PM PDT 24
Peak memory 195388 kb
Host smart-95574120-0697-4664-bcf2-847c35efd1b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659204210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3659204210
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.3477673963
Short name T600
Test name
Test status
Simulation time 29147452 ps
CPU time 0.62 seconds
Started Mar 12 12:49:40 PM PDT 24
Finished Mar 12 12:49:43 PM PDT 24
Peak memory 195632 kb
Host smart-4062ebff-66a5-40c1-96eb-9383b89b9e2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477673963 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.3477673963
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup.550747907
Short name T257
Test name
Test status
Simulation time 32706019 ps
CPU time 0.65 seconds
Started Mar 12 12:49:49 PM PDT 24
Finished Mar 12 12:49:50 PM PDT 24
Peak memory 195412 kb
Host smart-d9afe524-dde4-493b-859e-8ea63eecaca7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550747907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.550747907
Directory /workspace/5.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup_reset.1321320920
Short name T735
Test name
Test status
Simulation time 236062276 ps
CPU time 1.3 seconds
Started Mar 12 12:49:41 PM PDT 24
Finished Mar 12 12:49:44 PM PDT 24
Peak memory 197808 kb
Host smart-f38f8474-5071-41c4-84ee-be9a2888d531
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321320920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.1321320920
Directory /workspace/5.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.1691291066
Short name T578
Test name
Test status
Simulation time 71323129 ps
CPU time 0.72 seconds
Started Mar 12 12:50:08 PM PDT 24
Finished Mar 12 12:50:09 PM PDT 24
Peak memory 195264 kb
Host smart-c51b97b8-4be0-4606-8425-0192a52af4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691291066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.1691291066
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.2529904843
Short name T254
Test name
Test status
Simulation time 58521825 ps
CPU time 0.84 seconds
Started Mar 12 12:50:01 PM PDT 24
Finished Mar 12 12:50:04 PM PDT 24
Peak memory 197604 kb
Host smart-2603e92b-82e8-4350-8911-4ee9095cac49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529904843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.2529904843
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.3969467020
Short name T199
Test name
Test status
Simulation time 36333359 ps
CPU time 0.61 seconds
Started Mar 12 12:50:07 PM PDT 24
Finished Mar 12 12:50:08 PM PDT 24
Peak memory 195360 kb
Host smart-fb4ff737-8cfb-4230-a3fd-49cb521b61c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969467020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.3969467020
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.3823995923
Short name T601
Test name
Test status
Simulation time 166473046 ps
CPU time 1 seconds
Started Mar 12 12:50:04 PM PDT 24
Finished Mar 12 12:50:05 PM PDT 24
Peak memory 195380 kb
Host smart-f222524a-ed32-462c-ac55-fb092fba5a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823995923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.3823995923
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.3236639867
Short name T120
Test name
Test status
Simulation time 38555170 ps
CPU time 0.58 seconds
Started Mar 12 12:50:01 PM PDT 24
Finished Mar 12 12:50:04 PM PDT 24
Peak memory 195372 kb
Host smart-3aea4824-c04b-439a-a12d-c84244c54c8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236639867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.3236639867
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.2088761371
Short name T499
Test name
Test status
Simulation time 54410738 ps
CPU time 0.65 seconds
Started Mar 12 12:50:09 PM PDT 24
Finished Mar 12 12:50:10 PM PDT 24
Peak memory 195448 kb
Host smart-bf76c9d3-1add-431f-a30b-57a6f83f469b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088761371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.2088761371
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.1051298058
Short name T143
Test name
Test status
Simulation time 61478254 ps
CPU time 0.67 seconds
Started Mar 12 12:50:01 PM PDT 24
Finished Mar 12 12:50:04 PM PDT 24
Peak memory 195940 kb
Host smart-85adfc73-754c-48d6-9c01-3bd7406ffee1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051298058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invali
d.1051298058
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.1228886533
Short name T115
Test name
Test status
Simulation time 76634104 ps
CPU time 0.96 seconds
Started Mar 12 12:50:00 PM PDT 24
Finished Mar 12 12:50:04 PM PDT 24
Peak memory 198772 kb
Host smart-d780b9dc-d967-49bc-924e-c40383617cd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228886533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.1228886533
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.182756562
Short name T805
Test name
Test status
Simulation time 154247947 ps
CPU time 0.84 seconds
Started Mar 12 12:49:59 PM PDT 24
Finished Mar 12 12:50:00 PM PDT 24
Peak memory 205336 kb
Host smart-3fb29ee4-c89e-471f-8afd-8d6b40bc7959
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182756562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.182756562
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.1559944245
Short name T556
Test name
Test status
Simulation time 389273789 ps
CPU time 1.01 seconds
Started Mar 12 12:50:08 PM PDT 24
Finished Mar 12 12:50:10 PM PDT 24
Peak memory 195644 kb
Host smart-1b178f2a-f61e-4671-9028-a513fbdaab13
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559944245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_c
m_ctrl_config_regwen.1559944245
Directory /workspace/6.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.550418586
Short name T430
Test name
Test status
Simulation time 894283523 ps
CPU time 3.24 seconds
Started Mar 12 12:49:58 PM PDT 24
Finished Mar 12 12:50:03 PM PDT 24
Peak memory 201188 kb
Host smart-aecb0c30-e357-4433-921d-0e51eee460e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550418586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.550418586
Directory /workspace/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.730958048
Short name T27
Test name
Test status
Simulation time 1336802353 ps
CPU time 2.31 seconds
Started Mar 12 12:50:01 PM PDT 24
Finished Mar 12 12:50:05 PM PDT 24
Peak memory 195800 kb
Host smart-18d055cf-2d7d-4760-af50-745723355e21
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730958048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.730958048
Directory /workspace/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.319643103
Short name T703
Test name
Test status
Simulation time 64335474 ps
CPU time 0.89 seconds
Started Mar 12 12:50:04 PM PDT 24
Finished Mar 12 12:50:05 PM PDT 24
Peak memory 195348 kb
Host smart-051c1c20-cb0a-4082-8b2c-d80373d200fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319643103 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.319643103
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.1582952979
Short name T858
Test name
Test status
Simulation time 54313917 ps
CPU time 0.6 seconds
Started Mar 12 12:49:56 PM PDT 24
Finished Mar 12 12:49:57 PM PDT 24
Peak memory 195612 kb
Host smart-50d609ff-ea0e-45af-b893-99a813fdd02a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582952979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.1582952979
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup.2941738346
Short name T379
Test name
Test status
Simulation time 309265968 ps
CPU time 0.9 seconds
Started Mar 12 12:50:07 PM PDT 24
Finished Mar 12 12:50:08 PM PDT 24
Peak memory 195372 kb
Host smart-2d18faa6-0db4-42b9-9171-80dde8293dc7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941738346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.2941738346
Directory /workspace/6.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup_reset.2367944035
Short name T334
Test name
Test status
Simulation time 89146563 ps
CPU time 0.64 seconds
Started Mar 12 12:49:57 PM PDT 24
Finished Mar 12 12:49:58 PM PDT 24
Peak memory 195560 kb
Host smart-e0298654-a46c-4c90-a065-6dd69c3fa50f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367944035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.2367944035
Directory /workspace/6.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.4213773376
Short name T547
Test name
Test status
Simulation time 26278388 ps
CPU time 0.64 seconds
Started Mar 12 12:49:56 PM PDT 24
Finished Mar 12 12:49:58 PM PDT 24
Peak memory 195192 kb
Host smart-5f406565-44ce-431c-ada5-75ee4a79fd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213773376 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.4213773376
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.324534127
Short name T830
Test name
Test status
Simulation time 80098897 ps
CPU time 0.71 seconds
Started Mar 12 12:50:09 PM PDT 24
Finished Mar 12 12:50:10 PM PDT 24
Peak memory 195536 kb
Host smart-a607cceb-0892-4010-b524-50a2e4c6abf0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324534127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disab
le_rom_integrity_check.324534127
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2976245442
Short name T344
Test name
Test status
Simulation time 28639972 ps
CPU time 0.62 seconds
Started Mar 12 12:50:10 PM PDT 24
Finished Mar 12 12:50:11 PM PDT 24
Peak memory 194912 kb
Host smart-79c10009-4f49-4407-86b0-c77be17585bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976245442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.2976245442
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.2562181742
Short name T865
Test name
Test status
Simulation time 510897349 ps
CPU time 0.98 seconds
Started Mar 12 12:50:00 PM PDT 24
Finished Mar 12 12:50:03 PM PDT 24
Peak memory 195396 kb
Host smart-52a79415-de79-4570-94b3-c10cbb008e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562181742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.2562181742
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.2342616917
Short name T222
Test name
Test status
Simulation time 50021827 ps
CPU time 0.61 seconds
Started Mar 12 12:50:12 PM PDT 24
Finished Mar 12 12:50:13 PM PDT 24
Peak memory 195364 kb
Host smart-0cf593fe-cce2-450d-ba30-ff41fa417c1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342616917 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.2342616917
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.214720795
Short name T846
Test name
Test status
Simulation time 218959782 ps
CPU time 0.59 seconds
Started Mar 12 12:49:59 PM PDT 24
Finished Mar 12 12:50:00 PM PDT 24
Peak memory 195452 kb
Host smart-b5bc648d-e04a-49cd-ad08-34de9d16a2b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214720795 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.214720795
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.4175387420
Short name T190
Test name
Test status
Simulation time 41196444 ps
CPU time 0.75 seconds
Started Mar 12 12:50:06 PM PDT 24
Finished Mar 12 12:50:07 PM PDT 24
Peak memory 195944 kb
Host smart-40ea132f-c97e-4d3d-b7f2-5ba76fe51252
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175387420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.4175387420
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.1745159824
Short name T256
Test name
Test status
Simulation time 68586587 ps
CPU time 0.88 seconds
Started Mar 12 12:49:56 PM PDT 24
Finished Mar 12 12:49:59 PM PDT 24
Peak memory 197636 kb
Host smart-0eb84a16-2e2e-4ab2-b1ed-e453ecca0d2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745159824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.1745159824
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.1285624638
Short name T8
Test name
Test status
Simulation time 183866904 ps
CPU time 0.77 seconds
Started Mar 12 12:50:07 PM PDT 24
Finished Mar 12 12:50:08 PM PDT 24
Peak memory 205996 kb
Host smart-c9368c5e-cd9e-453b-a17d-cab1af556c95
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285624638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.1285624638
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1812364022
Short name T663
Test name
Test status
Simulation time 738837051 ps
CPU time 2.8 seconds
Started Mar 12 12:49:58 PM PDT 24
Finished Mar 12 12:50:03 PM PDT 24
Peak memory 201204 kb
Host smart-e4e903e0-5cd7-4d3f-a586-66b45ef149fa
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812364022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1812364022
Directory /workspace/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3165576348
Short name T559
Test name
Test status
Simulation time 873675485 ps
CPU time 3.25 seconds
Started Mar 12 12:50:04 PM PDT 24
Finished Mar 12 12:50:08 PM PDT 24
Peak memory 195964 kb
Host smart-cad321fb-3aaa-4501-a609-b643398b3ff6
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165576348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3165576348
Directory /workspace/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.2971360335
Short name T517
Test name
Test status
Simulation time 177442464 ps
CPU time 0.84 seconds
Started Mar 12 12:50:00 PM PDT 24
Finished Mar 12 12:50:03 PM PDT 24
Peak memory 195328 kb
Host smart-64cba3ae-95e4-4139-b7e3-37ed6f630d9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971360335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2971360335
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.1001367829
Short name T853
Test name
Test status
Simulation time 43099242 ps
CPU time 0.68 seconds
Started Mar 12 12:50:03 PM PDT 24
Finished Mar 12 12:50:04 PM PDT 24
Peak memory 195540 kb
Host smart-4982f92a-fb49-4906-9d97-851716d71d03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001367829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.1001367829
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_stress_all.4155984445
Short name T828
Test name
Test status
Simulation time 609723427 ps
CPU time 2.52 seconds
Started Mar 12 12:50:01 PM PDT 24
Finished Mar 12 12:50:06 PM PDT 24
Peak memory 201144 kb
Host smart-0c2c1a19-af05-4d9b-9faa-e639b7056b0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155984445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.4155984445
Directory /workspace/7.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup.3542370028
Short name T514
Test name
Test status
Simulation time 49919322 ps
CPU time 0.61 seconds
Started Mar 12 12:49:59 PM PDT 24
Finished Mar 12 12:50:02 PM PDT 24
Peak memory 195388 kb
Host smart-2a2dfd21-b42d-4619-9981-ba8f571f143d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542370028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.3542370028
Directory /workspace/7.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup_reset.306027213
Short name T446
Test name
Test status
Simulation time 222512867 ps
CPU time 1.12 seconds
Started Mar 12 12:50:12 PM PDT 24
Finished Mar 12 12:50:14 PM PDT 24
Peak memory 197940 kb
Host smart-df1b22ee-5875-44f6-b1e7-44163d8cf6e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306027213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.306027213
Directory /workspace/7.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.2681572210
Short name T438
Test name
Test status
Simulation time 63432470 ps
CPU time 0.72 seconds
Started Mar 12 12:50:00 PM PDT 24
Finished Mar 12 12:50:03 PM PDT 24
Peak memory 197596 kb
Host smart-d92e9d02-896a-4814-a82c-08ebfde1e0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681572210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.2681572210
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.1764215991
Short name T133
Test name
Test status
Simulation time 42312173 ps
CPU time 0.75 seconds
Started Mar 12 12:50:03 PM PDT 24
Finished Mar 12 12:50:04 PM PDT 24
Peak memory 197664 kb
Host smart-4a9752db-c1bc-40e6-a5f2-8df1d2b27e7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764215991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.1764215991
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.1253212484
Short name T304
Test name
Test status
Simulation time 38095045 ps
CPU time 0.59 seconds
Started Mar 12 12:50:10 PM PDT 24
Finished Mar 12 12:50:11 PM PDT 24
Peak memory 195336 kb
Host smart-14fb0785-d37b-484d-8d95-782c3a5d7178
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253212484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.1253212484
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.3297115976
Short name T511
Test name
Test status
Simulation time 165197549 ps
CPU time 0.93 seconds
Started Mar 12 12:50:02 PM PDT 24
Finished Mar 12 12:50:04 PM PDT 24
Peak memory 195408 kb
Host smart-f293a16d-8b06-49bf-9cfe-964e13ea5a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297115976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.3297115976
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.2177246175
Short name T329
Test name
Test status
Simulation time 52825760 ps
CPU time 0.7 seconds
Started Mar 12 12:50:07 PM PDT 24
Finished Mar 12 12:50:07 PM PDT 24
Peak memory 195396 kb
Host smart-9d386e81-fe22-4cff-9f08-da32549be47e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177246175 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.2177246175
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.946542105
Short name T479
Test name
Test status
Simulation time 164143326 ps
CPU time 0.58 seconds
Started Mar 12 12:50:10 PM PDT 24
Finished Mar 12 12:50:10 PM PDT 24
Peak memory 195372 kb
Host smart-b8437559-95f1-4a8e-94bf-937fd243b810
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946542105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.946542105
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.1686589537
Short name T692
Test name
Test status
Simulation time 44297099 ps
CPU time 0.7 seconds
Started Mar 12 12:50:09 PM PDT 24
Finished Mar 12 12:50:10 PM PDT 24
Peak memory 195932 kb
Host smart-835e9b66-9ed7-41c3-a526-20280199cd3b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686589537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali
d.1686589537
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.810268523
Short name T40
Test name
Test status
Simulation time 50414253 ps
CPU time 0.8 seconds
Started Mar 12 12:50:07 PM PDT 24
Finished Mar 12 12:50:08 PM PDT 24
Peak memory 197736 kb
Host smart-24cbb252-ea05-48e2-8803-d2178b43a4a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810268523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.810268523
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.4256322808
Short name T487
Test name
Test status
Simulation time 106249510 ps
CPU time 1.08 seconds
Started Mar 12 12:50:11 PM PDT 24
Finished Mar 12 12:50:12 PM PDT 24
Peak memory 205284 kb
Host smart-9331d3c6-f4e4-422a-9c3b-6e51b1326284
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256322808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.4256322808
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.256697494
Short name T794
Test name
Test status
Simulation time 1229764497 ps
CPU time 2.27 seconds
Started Mar 12 12:50:00 PM PDT 24
Finished Mar 12 12:50:05 PM PDT 24
Peak memory 201208 kb
Host smart-51343850-8c16-43d8-8973-bcc81ffef18c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256697494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.256697494
Directory /workspace/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1522260010
Short name T230
Test name
Test status
Simulation time 1425815733 ps
CPU time 2.25 seconds
Started Mar 12 12:50:05 PM PDT 24
Finished Mar 12 12:50:07 PM PDT 24
Peak memory 195928 kb
Host smart-1b401b26-7a09-49fc-b2c7-c9cbf67e118a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522260010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1522260010
Directory /workspace/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.1926039301
Short name T646
Test name
Test status
Simulation time 90490082 ps
CPU time 0.79 seconds
Started Mar 12 12:50:02 PM PDT 24
Finished Mar 12 12:50:04 PM PDT 24
Peak memory 195344 kb
Host smart-b22ba3a9-d291-4352-b505-88aba7caf529
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926039301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1926039301
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.1648202637
Short name T555
Test name
Test status
Simulation time 31618908 ps
CPU time 0.66 seconds
Started Mar 12 12:50:01 PM PDT 24
Finished Mar 12 12:50:04 PM PDT 24
Peak memory 195624 kb
Host smart-45bc6f90-289e-4cf8-b35f-1d352833a594
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648202637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.1648202637
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup.1242602552
Short name T618
Test name
Test status
Simulation time 352247267 ps
CPU time 0.95 seconds
Started Mar 12 12:50:01 PM PDT 24
Finished Mar 12 12:50:04 PM PDT 24
Peak memory 195256 kb
Host smart-0c52219d-2986-4a1d-b59e-6abfb7767bb4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242602552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.1242602552
Directory /workspace/8.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup_reset.626002703
Short name T575
Test name
Test status
Simulation time 399230543 ps
CPU time 0.98 seconds
Started Mar 12 12:50:00 PM PDT 24
Finished Mar 12 12:50:03 PM PDT 24
Peak memory 195528 kb
Host smart-72d0d9f5-9500-468f-85c9-f1eb6a1734d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626002703 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.626002703
Directory /workspace/8.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.26633234
Short name T85
Test name
Test status
Simulation time 56143958 ps
CPU time 0.68 seconds
Started Mar 12 12:50:01 PM PDT 24
Finished Mar 12 12:50:04 PM PDT 24
Peak memory 195316 kb
Host smart-68b5070d-6125-4b83-aa40-7f05cbc593be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26633234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.26633234
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.3804092498
Short name T250
Test name
Test status
Simulation time 53069618 ps
CPU time 0.78 seconds
Started Mar 12 12:50:01 PM PDT 24
Finished Mar 12 12:50:04 PM PDT 24
Peak memory 198120 kb
Host smart-bd5397b4-59b1-462e-8dcd-9dd2aad6610f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804092498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disa
ble_rom_integrity_check.3804092498
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.938769977
Short name T668
Test name
Test status
Simulation time 30324670 ps
CPU time 0.64 seconds
Started Mar 12 12:50:00 PM PDT 24
Finished Mar 12 12:50:03 PM PDT 24
Peak memory 195332 kb
Host smart-b1eaf8e7-fc34-4611-8564-d7fc132ba858
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938769977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_m
alfunc.938769977
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.3248834003
Short name T289
Test name
Test status
Simulation time 602354786 ps
CPU time 0.96 seconds
Started Mar 12 12:50:06 PM PDT 24
Finished Mar 12 12:50:07 PM PDT 24
Peak memory 195416 kb
Host smart-da9d0043-2c54-43c7-b912-b8e84f81c28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248834003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.3248834003
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.747959475
Short name T622
Test name
Test status
Simulation time 63534057 ps
CPU time 0.65 seconds
Started Mar 12 12:50:08 PM PDT 24
Finished Mar 12 12:50:08 PM PDT 24
Peak memory 195336 kb
Host smart-6dd10b47-2b42-4161-b7d0-504e55390438
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747959475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.747959475
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.429106171
Short name T733
Test name
Test status
Simulation time 93034454 ps
CPU time 0.63 seconds
Started Mar 12 12:50:08 PM PDT 24
Finished Mar 12 12:50:08 PM PDT 24
Peak memory 195400 kb
Host smart-229e4fc5-cb0c-490e-b8e8-be084ff47cd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429106171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.429106171
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.2004264359
Short name T293
Test name
Test status
Simulation time 50182598 ps
CPU time 0.69 seconds
Started Mar 12 12:50:04 PM PDT 24
Finished Mar 12 12:50:05 PM PDT 24
Peak memory 195904 kb
Host smart-0842cd70-b7d0-411c-a832-27a88aab195a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004264359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.2004264359
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_wakeup_race.995382403
Short name T240
Test name
Test status
Simulation time 71824474 ps
CPU time 0.73 seconds
Started Mar 12 12:50:02 PM PDT 24
Finished Mar 12 12:50:04 PM PDT 24
Peak memory 195300 kb
Host smart-8930c948-51a1-46b4-9778-3bb1dd00408f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995382403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wak
eup_race.995382403
Directory /workspace/9.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.1069259811
Short name T381
Test name
Test status
Simulation time 87886291 ps
CPU time 0.73 seconds
Started Mar 12 12:50:02 PM PDT 24
Finished Mar 12 12:50:04 PM PDT 24
Peak memory 197604 kb
Host smart-9a3f0bbe-cb22-4afa-ab3b-24568a97ee80
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069259811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.1069259811
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.340335558
Short name T577
Test name
Test status
Simulation time 156848409 ps
CPU time 0.78 seconds
Started Mar 12 12:50:07 PM PDT 24
Finished Mar 12 12:50:08 PM PDT 24
Peak memory 205272 kb
Host smart-d4fda6fa-81f5-4c30-afe1-e62bfc2ed1f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340335558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.340335558
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1762639876
Short name T717
Test name
Test status
Simulation time 1245850297 ps
CPU time 2.25 seconds
Started Mar 12 12:50:07 PM PDT 24
Finished Mar 12 12:50:10 PM PDT 24
Peak memory 200912 kb
Host smart-6b35c155-f6ae-49ae-ba32-7c4a32d73eac
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762639876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1762639876
Directory /workspace/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.831589512
Short name T41
Test name
Test status
Simulation time 1575860378 ps
CPU time 1.78 seconds
Started Mar 12 12:50:00 PM PDT 24
Finished Mar 12 12:50:05 PM PDT 24
Peak memory 195776 kb
Host smart-4f2bdc36-d6c8-47dd-aa2d-de45a1062a06
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831589512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.831589512
Directory /workspace/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.3627383352
Short name T84
Test name
Test status
Simulation time 59014700 ps
CPU time 0.82 seconds
Started Mar 12 12:50:00 PM PDT 24
Finished Mar 12 12:50:03 PM PDT 24
Peak memory 195360 kb
Host smart-67463038-cdb3-45e9-87b3-9010282f95ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627383352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3627383352
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.3023139192
Short name T404
Test name
Test status
Simulation time 28506644 ps
CPU time 0.67 seconds
Started Mar 12 12:50:02 PM PDT 24
Finished Mar 12 12:50:04 PM PDT 24
Peak memory 197716 kb
Host smart-cb5ce2b3-ba77-4ab4-9a73-719f1b588c45
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023139192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.3023139192
Directory /workspace/9.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup_reset.998624626
Short name T597
Test name
Test status
Simulation time 99385909 ps
CPU time 0.87 seconds
Started Mar 12 12:50:02 PM PDT 24
Finished Mar 12 12:50:04 PM PDT 24
Peak memory 197768 kb
Host smart-62b1be20-0c29-44b4-9591-aacfea6ace35
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998624626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.998624626
Directory /workspace/9.pwrmgr_wakeup_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%