Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10824

1

T4

16

T5

2

T6

2

auto[1]

10440

1

T4

4

T6

8

T8

4

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10758

1

T4

12

T5

2

T6

8

auto[1]

10506

1

T4

8

T6

2

T8

2

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10706

1

T4

10

T8

2

T9

2

auto[1]

10558

1

T4

10

T5

2

T6

10

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11810

1

T4

10

T5

1

T6

5

auto[1]

9454

1

T4

10

T5

1

T6

5

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10479

1

T4

8

T6

6

T8

2

auto[1]

10785

1

T4

12

T5

2

T6

4

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10777

1

T4

10

T5

2

T6

6

auto[1]

10487

1

T4

10

T6

4

T8

2

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

392

1

T10

1

T43

4

T26

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

304

1

T10

1

T26

2

T27

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

377

1

T4

1

T10

1

T43

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

291

1

T4

1

T43

1

T15

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

341

1

T9

1

T26

3

T78

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

265

1

T9

1

T26

3

T78

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

486

1

T4

1

T5

1

T6

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

411

1

T4

1

T5

1

T6

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

375

1

T10

1

T43

5

T26

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

290

1

T43

2

T26

3

T78

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

380

1

T4

1

T10

1

T43

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

299

1

T4

1

T26

3

T79

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

398

1

T43

2

T26

1

T27

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

318

1

T26

1

T27

2

T143

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

341

1

T4

2

T43

2

T27

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

271

1

T4

2

T27

1

T16

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

358

1

T4

1

T43

3

T26

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

293

1

T4

1

T43

2

T26

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

346

1

T43

1

T26

1

T27

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

271

1

T43

1

T26

1

T27

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

409

1

T4

1

T43

1

T26

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

333

1

T4

1

T43

1

T26

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

367

1

T43

4

T26

2

T27

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

308

1

T43

2

T26

2

T27

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

344

1

T43

2

T26

1

T27

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

278

1

T26

1

T27

1

T63

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

361

1

T43

1

T26

2

T27

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

284

1

T26

2

T27

5

T78

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

383

1

T4

1

T27

1

T61

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

313

1

T4

1

T27

1

T144

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

353

1

T10

1

T43

2

T26

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

284

1

T10

1

T26

1

T27

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

369

1

T10

1

T43

4

T26

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

297

1

T43

2

T26

1

T27

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

352

1

T6

1

T9

1

T43

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

277

1

T6

1

T9

1

T43

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

359

1

T10

1

T43

2

T26

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

279

1

T26

2

T27

1

T78

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

382

1

T6

1

T43

2

T26

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

306

1

T6

1

T26

2

T27

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

353

1

T43

5

T26

5

T27

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

296

1

T43

2

T26

5

T27

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

354

1

T6

1

T10

1

T43

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

279

1

T6

1

T27

1

T63

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

370

1

T4

1

T10

1

T43

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

300

1

T4

1

T26

3

T78

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

353

1

T8

1

T43

1

T26

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

293

1

T8

1

T26

1

T27

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

373

1

T4

1

T8

1

T10

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

304

1

T4

1

T8

1

T27

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

368

1

T9

1

T43

3

T26

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

291

1

T9

1

T43

1

T26

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

364

1

T43

4

T26

2

T27

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

291

1

T43

3

T26

2

T27

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

347

1

T10

1

T43

5

T26

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

266

1

T10

1

T43

1

T26

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

374

1

T10

2

T43

2

T16

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

291

1

T16

1

T52

2

T79

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

370

1

T6

1

T9

1

T43

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

288

1

T6

1

T9

1

T43

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

376

1

T10

1

T43

3

T26

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

316

1

T10

1

T26

1

T27

7

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

335

1

T10

1

T43

2

T26

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

267

1

T26

1

T27

1

T143

2