Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11436

1

T1

77

T3

45

T8

13

auto[1]

11106

1

T1

130

T3

39

T8

7

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11570

1

T1

116

T3

41

T8

13

auto[1]

10972

1

T1

91

T3

43

T8

7

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11128

1

T1

99

T3

49

T8

12

auto[1]

11414

1

T1

108

T3

35

T8

8

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

12576

1

T1

111

T3

43

T8

16

auto[1]

9966

1

T1

96

T3

41

T8

4

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10998

1

T1

106

T3

45

T8

9

auto[1]

11544

1

T1

101

T3

39

T8

11

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

11377

1

T1

107

T3

41

T8

13

auto[1]

11165

1

T1

100

T3

43

T8

7

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

374

1

T1

4

T3

1

T8

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

303

1

T1

4

T3

1

T8

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

370

1

T1

2

T12

1

T22

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

286

1

T1

2

T12

1

T22

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

396

1

T1

5

T3

2

T8

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

313

1

T1

4

T3

2

T12

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

555

1

T1

2

T3

1

T8

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

468

1

T1

2

T3

1

T8

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

405

1

T3

1

T8

1

T12

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

320

1

T3

1

T12

1

T22

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

392

1

T1

6

T3

1

T22

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

303

1

T1

5

T3

1

T22

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

411

1

T1

4

T3

2

T12

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

329

1

T1

4

T3

2

T12

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

397

1

T1

1

T3

2

T12

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

308

1

T1

1

T3

1

T12

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

379

1

T1

2

T3

3

T8

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

302

1

T1

2

T3

3

T12

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

389

1

T1

3

T12

5

T31

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

315

1

T1

3

T12

5

T32

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

373

1

T1

1

T3

3

T8

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

282

1

T1

1

T3

3

T12

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

400

1

T1

2

T3

1

T12

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

316

1

T1

2

T3

1

T12

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

381

1

T1

2

T3

1

T22

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

305

1

T1

1

T3

1

T22

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

359

1

T1

3

T3

4

T8

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

285

1

T1

2

T3

4

T12

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

398

1

T1

1

T12

3

T22

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

305

1

T1

1

T12

3

T22

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

402

1

T1

3

T3

1

T12

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

315

1

T1

2

T3

1

T12

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

406

1

T1

2

T3

2

T12

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

319

1

T1

2

T3

2

T12

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

391

1

T1

6

T3

1

T12

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

308

1

T1

5

T3

1

T12

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

399

1

T1

5

T3

3

T12

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

311

1

T1

5

T3

3

T12

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

402

1

T1

4

T3

1

T8

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

312

1

T1

3

T3

1

T8

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

390

1

T1

5

T3

2

T12

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

305

1

T1

5

T3

2

T12

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

392

1

T1

5

T3

1

T8

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

316

1

T1

3

T3

1

T12

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

375

1

T1

6

T3

1

T8

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

300

1

T1

6

T3

1

T12

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

391

1

T1

4

T12

1

T22

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

323

1

T1

4

T12

1

T22

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

383

1

T1

4

T3

1

T22

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

304

1

T1

4

T22

1

T26

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

369

1

T1

4

T3

1

T12

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

291

1

T1

4

T3

1

T12

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

365

1

T1

3

T12

1

T22

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

293

1

T1

3

T12

1

T22

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

399

1

T1

7

T3

1

T12

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

304

1

T1

5

T3

1

T12

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

395

1

T1

4

T3

2

T8

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

307

1

T1

3

T3

2

T8

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

363

1

T1

5

T3

2

T22

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

291

1

T1

4

T3

2

T22

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

391

1

T1

3

T3

1

T8

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

309

1

T1

3

T3

1

T12

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

384

1

T1

3

T3

1

T22

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

318

1

T1

1

T3

1

T22

1