Summary for Variable enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
6713 |
1 |
|
|
T1 |
68 |
|
T3 |
14 |
|
T9 |
3 |
auto[1] |
9771 |
1 |
|
|
T1 |
93 |
|
T3 |
59 |
|
T9 |
4 |
Summary for Variable reset_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for reset_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13394 |
1 |
|
|
T1 |
127 |
|
T2 |
3 |
|
T3 |
50 |
auto[1] |
4389 |
1 |
|
|
T1 |
35 |
|
T3 |
23 |
|
T9 |
2 |
Summary for Variable sleep_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sleep_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7917 |
1 |
|
|
T1 |
66 |
|
T2 |
3 |
|
T3 |
32 |
auto[1] |
9866 |
1 |
|
|
T1 |
96 |
|
T3 |
41 |
|
T8 |
4 |
Summary for Cross reset_cross
Samples crossed: reset_cp enable_cp sleep_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for reset_cross
Bins
reset_cp | enable_cp | sleep_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
1566 |
1 |
|
|
T1 |
17 |
|
T3 |
6 |
|
T9 |
3 |
auto[0] |
auto[0] |
auto[1] |
3678 |
1 |
|
|
T1 |
33 |
|
T3 |
4 |
|
T12 |
15 |
auto[0] |
auto[1] |
auto[0] |
1678 |
1 |
|
|
T1 |
14 |
|
T3 |
3 |
|
T9 |
2 |
auto[0] |
auto[1] |
auto[1] |
5173 |
1 |
|
|
T1 |
62 |
|
T3 |
37 |
|
T12 |
35 |
auto[1] |
auto[0] |
auto[0] |
1469 |
1 |
|
|
T1 |
18 |
|
T3 |
4 |
|
T10 |
1 |
auto[1] |
auto[1] |
auto[0] |
2920 |
1 |
|
|
T1 |
17 |
|
T3 |
19 |
|
T9 |
2 |
User Defined Cross Bins for reset_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
illegal |
0 |
Illegal |