Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.72 98.23 96.58 90.98 96.00 96.37 100.00 98.85


Total test records in report: 991
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T806 /workspace/coverage/default/26.pwrmgr_glitch.1572667067 Mar 19 03:07:32 PM PDT 24 Mar 19 03:07:34 PM PDT 24 38971288 ps
T807 /workspace/coverage/default/22.pwrmgr_reset_invalid.4114108604 Mar 19 03:07:25 PM PDT 24 Mar 19 03:07:26 PM PDT 24 111623409 ps
T808 /workspace/coverage/default/28.pwrmgr_escalation_timeout.3702170002 Mar 19 03:07:37 PM PDT 24 Mar 19 03:07:38 PM PDT 24 185889103 ps
T809 /workspace/coverage/default/27.pwrmgr_reset.986273076 Mar 19 03:07:45 PM PDT 24 Mar 19 03:07:46 PM PDT 24 94083053 ps
T810 /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.4231898211 Mar 19 03:08:12 PM PDT 24 Mar 19 03:08:12 PM PDT 24 48269767 ps
T811 /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.3404779321 Mar 19 03:06:37 PM PDT 24 Mar 19 03:06:37 PM PDT 24 77505705 ps
T812 /workspace/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3461294297 Mar 19 03:06:47 PM PDT 24 Mar 19 03:06:50 PM PDT 24 942942421 ps
T813 /workspace/coverage/default/11.pwrmgr_aborted_low_power.27466088 Mar 19 03:06:55 PM PDT 24 Mar 19 03:06:56 PM PDT 24 35391433 ps
T814 /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.2222013112 Mar 19 03:08:22 PM PDT 24 Mar 19 03:08:23 PM PDT 24 51699340 ps
T815 /workspace/coverage/default/32.pwrmgr_escalation_timeout.2606540878 Mar 19 03:07:45 PM PDT 24 Mar 19 03:07:46 PM PDT 24 159913391 ps
T816 /workspace/coverage/default/31.pwrmgr_reset_invalid.4043517080 Mar 19 03:07:49 PM PDT 24 Mar 19 03:07:53 PM PDT 24 107071272 ps
T817 /workspace/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.3858691106 Mar 19 03:07:41 PM PDT 24 Mar 19 03:07:41 PM PDT 24 32719387 ps
T818 /workspace/coverage/default/18.pwrmgr_wakeup.3420163854 Mar 19 03:07:09 PM PDT 24 Mar 19 03:07:10 PM PDT 24 82107176 ps
T819 /workspace/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4013842533 Mar 19 03:08:00 PM PDT 24 Mar 19 03:08:03 PM PDT 24 752512384 ps
T820 /workspace/coverage/default/29.pwrmgr_reset_invalid.3658987760 Mar 19 03:07:27 PM PDT 24 Mar 19 03:07:28 PM PDT 24 263936795 ps
T821 /workspace/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.729393460 Mar 19 03:06:45 PM PDT 24 Mar 19 03:06:46 PM PDT 24 491272056 ps
T822 /workspace/coverage/default/20.pwrmgr_lowpower_invalid.1575271619 Mar 19 03:07:19 PM PDT 24 Mar 19 03:07:21 PM PDT 24 77829736 ps
T823 /workspace/coverage/default/24.pwrmgr_wakeup.846633291 Mar 19 03:07:14 PM PDT 24 Mar 19 03:07:15 PM PDT 24 322164939 ps
T824 /workspace/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1461139887 Mar 19 03:06:57 PM PDT 24 Mar 19 03:07:01 PM PDT 24 904909856 ps
T825 /workspace/coverage/default/8.pwrmgr_reset.1185678537 Mar 19 03:06:47 PM PDT 24 Mar 19 03:06:49 PM PDT 24 68747372 ps
T826 /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.1438132350 Mar 19 03:07:43 PM PDT 24 Mar 19 03:07:44 PM PDT 24 31564874 ps
T827 /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.3730672773 Mar 19 03:08:26 PM PDT 24 Mar 19 03:08:27 PM PDT 24 30902939 ps
T828 /workspace/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1804003130 Mar 19 03:07:43 PM PDT 24 Mar 19 03:07:46 PM PDT 24 1056196378 ps
T829 /workspace/coverage/default/23.pwrmgr_glitch.3488475490 Mar 19 03:07:32 PM PDT 24 Mar 19 03:07:34 PM PDT 24 55516131 ps
T830 /workspace/coverage/default/1.pwrmgr_lowpower_invalid.1987519895 Mar 19 03:06:07 PM PDT 24 Mar 19 03:06:08 PM PDT 24 69778917 ps
T831 /workspace/coverage/default/8.pwrmgr_lowpower_invalid.556461340 Mar 19 03:06:49 PM PDT 24 Mar 19 03:06:50 PM PDT 24 42079247 ps
T832 /workspace/coverage/default/41.pwrmgr_stress_all.1979304146 Mar 19 03:08:18 PM PDT 24 Mar 19 03:08:20 PM PDT 24 852266366 ps
T833 /workspace/coverage/default/22.pwrmgr_global_esc.919146808 Mar 19 03:07:02 PM PDT 24 Mar 19 03:07:03 PM PDT 24 95152986 ps
T834 /workspace/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2395506804 Mar 19 03:07:53 PM PDT 24 Mar 19 03:07:55 PM PDT 24 1200341915 ps
T835 /workspace/coverage/default/1.pwrmgr_wakeup_reset.3886370916 Mar 19 03:06:04 PM PDT 24 Mar 19 03:06:05 PM PDT 24 447317853 ps
T836 /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.2864000941 Mar 19 03:08:17 PM PDT 24 Mar 19 03:08:18 PM PDT 24 117035260 ps
T837 /workspace/coverage/default/1.pwrmgr_stress_all.2891072821 Mar 19 03:06:15 PM PDT 24 Mar 19 03:06:19 PM PDT 24 1663675386 ps
T838 /workspace/coverage/default/3.pwrmgr_global_esc.2136770453 Mar 19 03:06:19 PM PDT 24 Mar 19 03:06:21 PM PDT 24 48711720 ps
T839 /workspace/coverage/default/19.pwrmgr_lowpower_invalid.3059466364 Mar 19 03:06:58 PM PDT 24 Mar 19 03:06:59 PM PDT 24 41915735 ps
T840 /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.2433099825 Mar 19 03:07:29 PM PDT 24 Mar 19 03:07:30 PM PDT 24 29890787 ps
T841 /workspace/coverage/default/31.pwrmgr_lowpower_invalid.578303167 Mar 19 03:07:43 PM PDT 24 Mar 19 03:07:44 PM PDT 24 84002328 ps
T842 /workspace/coverage/default/0.pwrmgr_stress_all.3170768983 Mar 19 03:06:09 PM PDT 24 Mar 19 03:06:11 PM PDT 24 276456125 ps
T843 /workspace/coverage/default/46.pwrmgr_wakeup_reset.222063836 Mar 19 03:08:23 PM PDT 24 Mar 19 03:08:24 PM PDT 24 410537760 ps
T844 /workspace/coverage/default/20.pwrmgr_wakeup.292703245 Mar 19 03:07:11 PM PDT 24 Mar 19 03:07:11 PM PDT 24 60472235 ps
T845 /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.2583705147 Mar 19 03:06:26 PM PDT 24 Mar 19 03:06:27 PM PDT 24 29560324 ps
T846 /workspace/coverage/default/31.pwrmgr_wakeup_reset.1341811478 Mar 19 03:07:46 PM PDT 24 Mar 19 03:07:48 PM PDT 24 229362104 ps
T847 /workspace/coverage/default/6.pwrmgr_wakeup_reset.473409028 Mar 19 03:06:32 PM PDT 24 Mar 19 03:06:33 PM PDT 24 94929997 ps
T848 /workspace/coverage/default/49.pwrmgr_reset.1833250895 Mar 19 03:08:24 PM PDT 24 Mar 19 03:08:25 PM PDT 24 99624447 ps
T849 /workspace/coverage/default/21.pwrmgr_global_esc.1204778555 Mar 19 03:07:19 PM PDT 24 Mar 19 03:07:21 PM PDT 24 31848473 ps
T850 /workspace/coverage/default/30.pwrmgr_wakeup.2970536686 Mar 19 03:07:31 PM PDT 24 Mar 19 03:07:32 PM PDT 24 309490526 ps
T851 /workspace/coverage/default/35.pwrmgr_smoke.2117114943 Mar 19 03:07:46 PM PDT 24 Mar 19 03:07:46 PM PDT 24 39747334 ps
T852 /workspace/coverage/default/40.pwrmgr_glitch.3999574863 Mar 19 03:07:59 PM PDT 24 Mar 19 03:08:00 PM PDT 24 66961736 ps
T853 /workspace/coverage/default/40.pwrmgr_wakeup.744725053 Mar 19 03:08:02 PM PDT 24 Mar 19 03:08:04 PM PDT 24 184905273 ps
T854 /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.2028599823 Mar 19 03:07:15 PM PDT 24 Mar 19 03:07:16 PM PDT 24 56350369 ps
T855 /workspace/coverage/default/13.pwrmgr_reset.4194128899 Mar 19 03:06:47 PM PDT 24 Mar 19 03:06:49 PM PDT 24 62807609 ps
T856 /workspace/coverage/default/11.pwrmgr_lowpower_invalid.3294903521 Mar 19 03:06:54 PM PDT 24 Mar 19 03:06:55 PM PDT 24 45770605 ps
T857 /workspace/coverage/default/1.pwrmgr_smoke.1767479947 Mar 19 03:06:18 PM PDT 24 Mar 19 03:06:19 PM PDT 24 32615565 ps
T858 /workspace/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.221953723 Mar 19 03:06:50 PM PDT 24 Mar 19 03:06:52 PM PDT 24 981048378 ps
T859 /workspace/coverage/default/12.pwrmgr_wakeup_reset.3041006743 Mar 19 03:06:47 PM PDT 24 Mar 19 03:06:48 PM PDT 24 106084249 ps
T860 /workspace/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.1915348469 Mar 19 03:07:48 PM PDT 24 Mar 19 03:07:53 PM PDT 24 59047719 ps
T861 /workspace/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2582818072 Mar 19 03:07:43 PM PDT 24 Mar 19 03:07:46 PM PDT 24 872894254 ps
T862 /workspace/coverage/default/6.pwrmgr_wakeup.2604335362 Mar 19 03:06:42 PM PDT 24 Mar 19 03:06:43 PM PDT 24 314550100 ps
T863 /workspace/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.3465455211 Mar 19 03:06:58 PM PDT 24 Mar 19 03:06:59 PM PDT 24 44324637 ps
T864 /workspace/coverage/default/15.pwrmgr_reset_invalid.652629325 Mar 19 03:06:48 PM PDT 24 Mar 19 03:06:50 PM PDT 24 98709678 ps
T865 /workspace/coverage/default/9.pwrmgr_wakeup.2278105559 Mar 19 03:06:37 PM PDT 24 Mar 19 03:06:38 PM PDT 24 269223795 ps
T866 /workspace/coverage/default/38.pwrmgr_reset_invalid.3168422366 Mar 19 03:07:49 PM PDT 24 Mar 19 03:07:53 PM PDT 24 111766201 ps
T867 /workspace/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.4063031946 Mar 19 03:06:38 PM PDT 24 Mar 19 03:06:39 PM PDT 24 59950085 ps
T868 /workspace/coverage/default/44.pwrmgr_glitch.773860337 Mar 19 03:08:10 PM PDT 24 Mar 19 03:08:10 PM PDT 24 29287078 ps
T869 /workspace/coverage/default/44.pwrmgr_aborted_low_power.2619628671 Mar 19 03:08:04 PM PDT 24 Mar 19 03:08:05 PM PDT 24 60421422 ps
T870 /workspace/coverage/default/38.pwrmgr_lowpower_invalid.3113677418 Mar 19 03:07:53 PM PDT 24 Mar 19 03:07:53 PM PDT 24 269841625 ps
T871 /workspace/coverage/default/45.pwrmgr_wakeup.142769626 Mar 19 03:08:14 PM PDT 24 Mar 19 03:08:16 PM PDT 24 242588322 ps
T872 /workspace/coverage/default/0.pwrmgr_reset.2256968484 Mar 19 03:06:03 PM PDT 24 Mar 19 03:06:04 PM PDT 24 83960790 ps
T873 /workspace/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1930045399 Mar 19 03:08:09 PM PDT 24 Mar 19 03:08:12 PM PDT 24 902103436 ps
T874 /workspace/coverage/default/14.pwrmgr_lowpower_wakeup_race.524605806 Mar 19 03:07:09 PM PDT 24 Mar 19 03:07:10 PM PDT 24 353408140 ps
T875 /workspace/coverage/default/15.pwrmgr_global_esc.1992560652 Mar 19 03:07:05 PM PDT 24 Mar 19 03:07:05 PM PDT 24 49071506 ps
T876 /workspace/coverage/default/12.pwrmgr_escalation_timeout.2960328024 Mar 19 03:06:50 PM PDT 24 Mar 19 03:06:52 PM PDT 24 320008122 ps
T877 /workspace/coverage/default/14.pwrmgr_wakeup.1453062970 Mar 19 03:07:04 PM PDT 24 Mar 19 03:07:04 PM PDT 24 28885201 ps
T878 /workspace/coverage/default/1.pwrmgr_aborted_low_power.483339091 Mar 19 03:06:20 PM PDT 24 Mar 19 03:06:21 PM PDT 24 22495913 ps
T879 /workspace/coverage/default/16.pwrmgr_glitch.1929452554 Mar 19 03:06:53 PM PDT 24 Mar 19 03:06:54 PM PDT 24 31849687 ps
T880 /workspace/coverage/default/48.pwrmgr_aborted_low_power.2833889615 Mar 19 03:08:22 PM PDT 24 Mar 19 03:08:23 PM PDT 24 21980174 ps
T881 /workspace/coverage/default/20.pwrmgr_smoke.3869909876 Mar 19 03:07:01 PM PDT 24 Mar 19 03:07:02 PM PDT 24 32765277 ps
T40 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.2876557132 Mar 19 12:43:54 PM PDT 24 Mar 19 12:43:56 PM PDT 24 75298570 ps
T46 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1599956879 Mar 19 12:43:48 PM PDT 24 Mar 19 12:43:49 PM PDT 24 45280165 ps
T47 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.326667125 Mar 19 12:44:01 PM PDT 24 Mar 19 12:44:03 PM PDT 24 72755871 ps
T50 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.3798484137 Mar 19 12:43:55 PM PDT 24 Mar 19 12:43:56 PM PDT 24 18010317 ps
T37 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.1870705692 Mar 19 12:43:52 PM PDT 24 Mar 19 12:43:53 PM PDT 24 117605233 ps
T38 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.4136818115 Mar 19 12:43:47 PM PDT 24 Mar 19 12:43:48 PM PDT 24 113663593 ps
T81 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.172768263 Mar 19 12:43:46 PM PDT 24 Mar 19 12:43:50 PM PDT 24 3325387148 ps
T48 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3436477806 Mar 19 12:43:54 PM PDT 24 Mar 19 12:43:55 PM PDT 24 42743121 ps
T49 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.4202529449 Mar 19 12:43:59 PM PDT 24 Mar 19 12:44:01 PM PDT 24 34507074 ps
T39 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.733081605 Mar 19 12:43:58 PM PDT 24 Mar 19 12:44:00 PM PDT 24 110411157 ps
T135 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.532435228 Mar 19 12:43:58 PM PDT 24 Mar 19 12:43:59 PM PDT 24 43074987 ps
T139 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.984453672 Mar 19 12:43:57 PM PDT 24 Mar 19 12:43:58 PM PDT 24 33296541 ps
T97 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.2883449699 Mar 19 12:43:57 PM PDT 24 Mar 19 12:43:58 PM PDT 24 121478727 ps
T51 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.34920002 Mar 19 12:43:59 PM PDT 24 Mar 19 12:44:01 PM PDT 24 112888182 ps
T55 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.1291650570 Mar 19 12:43:58 PM PDT 24 Mar 19 12:43:59 PM PDT 24 126921847 ps
T136 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.3226487081 Mar 19 12:44:02 PM PDT 24 Mar 19 12:44:03 PM PDT 24 33708890 ps
T882 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.1177544634 Mar 19 12:44:01 PM PDT 24 Mar 19 12:44:03 PM PDT 24 33693444 ps
T82 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.775491774 Mar 19 12:43:51 PM PDT 24 Mar 19 12:43:52 PM PDT 24 85744176 ps
T883 /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.1988422420 Mar 19 12:43:59 PM PDT 24 Mar 19 12:44:01 PM PDT 24 23952153 ps
T137 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.2178568651 Mar 19 12:43:47 PM PDT 24 Mar 19 12:43:48 PM PDT 24 18227541 ps
T83 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1567950113 Mar 19 12:43:47 PM PDT 24 Mar 19 12:43:48 PM PDT 24 55867458 ps
T84 /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1052321211 Mar 19 12:43:54 PM PDT 24 Mar 19 12:43:55 PM PDT 24 74622556 ps
T138 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.1599142950 Mar 19 12:44:04 PM PDT 24 Mar 19 12:44:05 PM PDT 24 18256329 ps
T101 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.4179429401 Mar 19 12:44:10 PM PDT 24 Mar 19 12:44:11 PM PDT 24 18165476 ps
T884 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.2803376152 Mar 19 12:43:59 PM PDT 24 Mar 19 12:44:01 PM PDT 24 33680648 ps
T41 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.2866358939 Mar 19 12:43:50 PM PDT 24 Mar 19 12:43:51 PM PDT 24 52240256 ps
T885 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.3999148132 Mar 19 12:44:01 PM PDT 24 Mar 19 12:44:03 PM PDT 24 22013914 ps
T886 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.547330227 Mar 19 12:43:59 PM PDT 24 Mar 19 12:43:59 PM PDT 24 54575913 ps
T42 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1212582056 Mar 19 12:44:04 PM PDT 24 Mar 19 12:44:05 PM PDT 24 67481845 ps
T43 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.3520683276 Mar 19 12:43:57 PM PDT 24 Mar 19 12:43:59 PM PDT 24 49793116 ps
T65 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1010845457 Mar 19 12:44:09 PM PDT 24 Mar 19 12:44:10 PM PDT 24 57000422 ps
T77 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.1093860482 Mar 19 12:44:05 PM PDT 24 Mar 19 12:44:06 PM PDT 24 113099370 ps
T887 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.2856744696 Mar 19 12:44:10 PM PDT 24 Mar 19 12:44:10 PM PDT 24 83790072 ps
T57 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2126116364 Mar 19 12:43:50 PM PDT 24 Mar 19 12:43:52 PM PDT 24 341522516 ps
T888 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.4208542094 Mar 19 12:44:11 PM PDT 24 Mar 19 12:44:12 PM PDT 24 36186737 ps
T102 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2664966115 Mar 19 12:43:56 PM PDT 24 Mar 19 12:43:58 PM PDT 24 504344947 ps
T889 /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.309557372 Mar 19 12:44:06 PM PDT 24 Mar 19 12:44:06 PM PDT 24 20468605 ps
T66 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.1608620843 Mar 19 12:43:52 PM PDT 24 Mar 19 12:43:54 PM PDT 24 407709039 ps
T85 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.2764849945 Mar 19 12:43:47 PM PDT 24 Mar 19 12:43:48 PM PDT 24 82650642 ps
T86 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.4114244771 Mar 19 12:43:58 PM PDT 24 Mar 19 12:43:59 PM PDT 24 61434500 ps
T890 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2273603383 Mar 19 12:44:05 PM PDT 24 Mar 19 12:44:06 PM PDT 24 93747357 ps
T891 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.2965874585 Mar 19 12:44:00 PM PDT 24 Mar 19 12:44:02 PM PDT 24 40900329 ps
T892 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3837414220 Mar 19 12:44:00 PM PDT 24 Mar 19 12:44:01 PM PDT 24 50128596 ps
T87 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.3998702706 Mar 19 12:43:56 PM PDT 24 Mar 19 12:43:56 PM PDT 24 16586925 ps
T98 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.3339536581 Mar 19 12:43:43 PM PDT 24 Mar 19 12:43:44 PM PDT 24 51531692 ps
T893 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.1716170443 Mar 19 12:44:02 PM PDT 24 Mar 19 12:44:03 PM PDT 24 17135495 ps
T67 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3297170835 Mar 19 12:44:04 PM PDT 24 Mar 19 12:44:06 PM PDT 24 113377669 ps
T78 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.4175584603 Mar 19 12:43:48 PM PDT 24 Mar 19 12:43:50 PM PDT 24 70741292 ps
T99 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.516437534 Mar 19 12:43:56 PM PDT 24 Mar 19 12:43:57 PM PDT 24 25160750 ps
T88 /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.1602856983 Mar 19 12:43:59 PM PDT 24 Mar 19 12:44:01 PM PDT 24 23361045 ps
T894 /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.1971952005 Mar 19 12:44:10 PM PDT 24 Mar 19 12:44:11 PM PDT 24 18647529 ps
T895 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.2965669166 Mar 19 12:43:59 PM PDT 24 Mar 19 12:44:01 PM PDT 24 24167913 ps
T896 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2114992114 Mar 19 12:43:47 PM PDT 24 Mar 19 12:43:50 PM PDT 24 221525521 ps
T79 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.632806122 Mar 19 12:44:04 PM PDT 24 Mar 19 12:44:06 PM PDT 24 32495394 ps
T897 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.1817276407 Mar 19 12:44:02 PM PDT 24 Mar 19 12:44:04 PM PDT 24 31638709 ps
T898 /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.3032935602 Mar 19 12:44:12 PM PDT 24 Mar 19 12:44:13 PM PDT 24 23084611 ps
T899 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1239789424 Mar 19 12:44:10 PM PDT 24 Mar 19 12:44:10 PM PDT 24 18450867 ps
T900 /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.34747244 Mar 19 12:44:05 PM PDT 24 Mar 19 12:44:05 PM PDT 24 22468134 ps
T100 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.1610584934 Mar 19 12:43:51 PM PDT 24 Mar 19 12:43:52 PM PDT 24 33081128 ps
T56 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.2192276824 Mar 19 12:43:58 PM PDT 24 Mar 19 12:44:00 PM PDT 24 167961043 ps
T901 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1902408327 Mar 19 12:44:08 PM PDT 24 Mar 19 12:44:09 PM PDT 24 27823198 ps
T902 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.472605567 Mar 19 12:43:57 PM PDT 24 Mar 19 12:43:59 PM PDT 24 125811148 ps
T903 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.4021053157 Mar 19 12:43:48 PM PDT 24 Mar 19 12:43:49 PM PDT 24 18725413 ps
T904 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.1068678311 Mar 19 12:43:42 PM PDT 24 Mar 19 12:43:43 PM PDT 24 51853584 ps
T80 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1644309693 Mar 19 12:43:54 PM PDT 24 Mar 19 12:43:55 PM PDT 24 57552865 ps
T905 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.1177448650 Mar 19 12:44:03 PM PDT 24 Mar 19 12:44:06 PM PDT 24 478465990 ps
T906 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.4183552379 Mar 19 12:43:52 PM PDT 24 Mar 19 12:43:53 PM PDT 24 62379550 ps
T89 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3451081513 Mar 19 12:43:56 PM PDT 24 Mar 19 12:43:57 PM PDT 24 79222053 ps
T907 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.4056665076 Mar 19 12:43:42 PM PDT 24 Mar 19 12:43:43 PM PDT 24 20575163 ps
T908 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.3511002950 Mar 19 12:43:57 PM PDT 24 Mar 19 12:43:58 PM PDT 24 147698541 ps
T909 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2450040717 Mar 19 12:43:44 PM PDT 24 Mar 19 12:43:45 PM PDT 24 23502542 ps
T126 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3971318588 Mar 19 12:43:52 PM PDT 24 Mar 19 12:43:54 PM PDT 24 208511000 ps
T910 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.3290680888 Mar 19 12:43:57 PM PDT 24 Mar 19 12:43:57 PM PDT 24 56355868 ps
T52 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.1260656255 Mar 19 12:43:51 PM PDT 24 Mar 19 12:43:53 PM PDT 24 1088474306 ps
T911 /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.247788500 Mar 19 12:44:16 PM PDT 24 Mar 19 12:44:16 PM PDT 24 18732662 ps
T912 /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.53497118 Mar 19 12:43:47 PM PDT 24 Mar 19 12:43:48 PM PDT 24 17009658 ps
T90 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.760116623 Mar 19 12:43:55 PM PDT 24 Mar 19 12:43:56 PM PDT 24 27966714 ps
T913 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.890901896 Mar 19 12:44:05 PM PDT 24 Mar 19 12:44:05 PM PDT 24 54386719 ps
T914 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.1846575964 Mar 19 12:43:57 PM PDT 24 Mar 19 12:43:58 PM PDT 24 241573545 ps
T915 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3513597295 Mar 19 12:43:53 PM PDT 24 Mar 19 12:43:54 PM PDT 24 56009680 ps
T916 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.3213003280 Mar 19 12:44:14 PM PDT 24 Mar 19 12:44:17 PM PDT 24 136913412 ps
T917 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.3530321206 Mar 19 12:43:48 PM PDT 24 Mar 19 12:43:50 PM PDT 24 303258985 ps
T918 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.1249642182 Mar 19 12:43:59 PM PDT 24 Mar 19 12:44:01 PM PDT 24 16646604 ps
T919 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.2068504841 Mar 19 12:44:04 PM PDT 24 Mar 19 12:44:04 PM PDT 24 43458365 ps
T920 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2505461013 Mar 19 12:43:41 PM PDT 24 Mar 19 12:43:42 PM PDT 24 56111990 ps
T921 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.127158953 Mar 19 12:43:48 PM PDT 24 Mar 19 12:43:49 PM PDT 24 39348911 ps
T91 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.3963233360 Mar 19 12:43:45 PM PDT 24 Mar 19 12:43:46 PM PDT 24 28110678 ps
T922 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.41085717 Mar 19 12:44:06 PM PDT 24 Mar 19 12:44:07 PM PDT 24 100932815 ps
T92 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.414348606 Mar 19 12:44:05 PM PDT 24 Mar 19 12:44:06 PM PDT 24 38204607 ps
T923 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.3646180044 Mar 19 12:44:00 PM PDT 24 Mar 19 12:44:02 PM PDT 24 47538507 ps
T924 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1767314475 Mar 19 12:44:00 PM PDT 24 Mar 19 12:44:02 PM PDT 24 42534998 ps
T925 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.1971177498 Mar 19 12:44:05 PM PDT 24 Mar 19 12:44:06 PM PDT 24 17997810 ps
T926 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.1972711014 Mar 19 12:43:54 PM PDT 24 Mar 19 12:43:54 PM PDT 24 54845671 ps
T927 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.1805753212 Mar 19 12:43:42 PM PDT 24 Mar 19 12:43:43 PM PDT 24 32544745 ps
T928 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1681334584 Mar 19 12:44:07 PM PDT 24 Mar 19 12:44:08 PM PDT 24 57305627 ps
T929 /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.1657144198 Mar 19 12:44:01 PM PDT 24 Mar 19 12:44:03 PM PDT 24 55667123 ps
T93 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.3133688257 Mar 19 12:43:47 PM PDT 24 Mar 19 12:43:48 PM PDT 24 52020911 ps
T96 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1282540872 Mar 19 12:43:54 PM PDT 24 Mar 19 12:43:58 PM PDT 24 275063034 ps
T930 /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1081889287 Mar 19 12:43:48 PM PDT 24 Mar 19 12:43:49 PM PDT 24 76708816 ps
T931 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.952514757 Mar 19 12:43:56 PM PDT 24 Mar 19 12:43:58 PM PDT 24 65451302 ps
T53 /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3937517894 Mar 19 12:43:58 PM PDT 24 Mar 19 12:43:59 PM PDT 24 348904577 ps
T932 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.3284984199 Mar 19 12:43:59 PM PDT 24 Mar 19 12:44:01 PM PDT 24 20881846 ps
T933 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3737849005 Mar 19 12:43:48 PM PDT 24 Mar 19 12:43:49 PM PDT 24 108506005 ps
T127 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.4208671032 Mar 19 12:43:43 PM PDT 24 Mar 19 12:43:44 PM PDT 24 191724966 ps
T934 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.10972723 Mar 19 12:43:59 PM PDT 24 Mar 19 12:44:01 PM PDT 24 23321302 ps
T935 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.3793211471 Mar 19 12:43:56 PM PDT 24 Mar 19 12:43:57 PM PDT 24 16201840 ps
T936 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3260810986 Mar 19 12:44:00 PM PDT 24 Mar 19 12:44:01 PM PDT 24 257305447 ps
T937 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.3837977417 Mar 19 12:43:52 PM PDT 24 Mar 19 12:43:53 PM PDT 24 189395365 ps
T938 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.3614436913 Mar 19 12:43:45 PM PDT 24 Mar 19 12:43:47 PM PDT 24 181149053 ps
T125 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.4219858597 Mar 19 12:43:57 PM PDT 24 Mar 19 12:43:58 PM PDT 24 130339737 ps
T94 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2495107276 Mar 19 12:43:48 PM PDT 24 Mar 19 12:43:49 PM PDT 24 35719611 ps
T939 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3355657544 Mar 19 12:43:48 PM PDT 24 Mar 19 12:43:49 PM PDT 24 46455972 ps
T940 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2463424902 Mar 19 12:44:07 PM PDT 24 Mar 19 12:44:14 PM PDT 24 54696349 ps
T941 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.625910128 Mar 19 12:44:15 PM PDT 24 Mar 19 12:44:16 PM PDT 24 34325654 ps
T95 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.2707733069 Mar 19 12:43:50 PM PDT 24 Mar 19 12:43:51 PM PDT 24 147345869 ps
T942 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.1632917490 Mar 19 12:44:03 PM PDT 24 Mar 19 12:44:05 PM PDT 24 210651836 ps
T943 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.761107500 Mar 19 12:44:00 PM PDT 24 Mar 19 12:44:01 PM PDT 24 31637564 ps
T944 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3083333658 Mar 19 12:43:58 PM PDT 24 Mar 19 12:44:00 PM PDT 24 312411244 ps
T945 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.2335033019 Mar 19 12:43:55 PM PDT 24 Mar 19 12:43:56 PM PDT 24 63667298 ps
T946 /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.633110439 Mar 19 12:43:48 PM PDT 24 Mar 19 12:43:50 PM PDT 24 61144329 ps
T947 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.1942526284 Mar 19 12:44:00 PM PDT 24 Mar 19 12:44:02 PM PDT 24 17929426 ps
T948 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.1431254788 Mar 19 12:43:57 PM PDT 24 Mar 19 12:43:59 PM PDT 24 253852842 ps
T949 /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.2125147184 Mar 19 12:44:11 PM PDT 24 Mar 19 12:44:12 PM PDT 24 46780125 ps
T950 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.1365340821 Mar 19 12:44:01 PM PDT 24 Mar 19 12:44:03 PM PDT 24 123781049 ps
T951 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.608248072 Mar 19 12:43:59 PM PDT 24 Mar 19 12:44:01 PM PDT 24 54968127 ps
T952 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.375142635 Mar 19 12:43:43 PM PDT 24 Mar 19 12:43:43 PM PDT 24 46581436 ps
T953 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.1115855921 Mar 19 12:43:45 PM PDT 24 Mar 19 12:43:46 PM PDT 24 226367800 ps
T954 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.2559122889 Mar 19 12:44:02 PM PDT 24 Mar 19 12:44:03 PM PDT 24 42270353 ps
T955 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.2066538724 Mar 19 12:44:06 PM PDT 24 Mar 19 12:44:06 PM PDT 24 55301891 ps
T956 /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.553796432 Mar 19 12:43:54 PM PDT 24 Mar 19 12:43:55 PM PDT 24 40243109 ps
T957 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.3535968030 Mar 19 12:44:08 PM PDT 24 Mar 19 12:44:09 PM PDT 24 362825061 ps
T958 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.4205189248 Mar 19 12:43:58 PM PDT 24 Mar 19 12:43:59 PM PDT 24 50456527 ps
T959 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3637746796 Mar 19 12:44:07 PM PDT 24 Mar 19 12:44:09 PM PDT 24 206739749 ps
T960 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2265497792 Mar 19 12:43:50 PM PDT 24 Mar 19 12:43:51 PM PDT 24 55772666 ps
T961 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.2655963878 Mar 19 12:44:04 PM PDT 24 Mar 19 12:44:05 PM PDT 24 71727077 ps
T962 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.3969265155 Mar 19 12:43:58 PM PDT 24 Mar 19 12:43:59 PM PDT 24 88444544 ps
T963 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.3669260860 Mar 19 12:43:57 PM PDT 24 Mar 19 12:43:58 PM PDT 24 110451706 ps
T964 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.2727178681 Mar 19 12:43:51 PM PDT 24 Mar 19 12:43:52 PM PDT 24 22591355 ps
T965 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.2502937127 Mar 19 12:44:00 PM PDT 24 Mar 19 12:44:02 PM PDT 24 201762926 ps
T966 /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.1107828275 Mar 19 12:43:51 PM PDT 24 Mar 19 12:43:51 PM PDT 24 66599185 ps
T967 /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.1562203431 Mar 19 12:44:08 PM PDT 24 Mar 19 12:44:08 PM PDT 24 41551059 ps
T968 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.3653009676 Mar 19 12:43:57 PM PDT 24 Mar 19 12:43:58 PM PDT 24 290585794 ps
T969 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.287391597 Mar 19 12:44:01 PM PDT 24 Mar 19 12:44:03 PM PDT 24 90999641 ps
T970 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1013680206 Mar 19 12:43:46 PM PDT 24 Mar 19 12:43:48 PM PDT 24 45862819 ps
T971 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.711521255 Mar 19 12:43:55 PM PDT 24 Mar 19 12:43:56 PM PDT 24 19765713 ps
T972 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.847564976 Mar 19 12:44:01 PM PDT 24 Mar 19 12:44:03 PM PDT 24 52935637 ps
T973 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.1339263916 Mar 19 12:44:08 PM PDT 24 Mar 19 12:44:09 PM PDT 24 50779031 ps
T974 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2367222549 Mar 19 12:43:57 PM PDT 24 Mar 19 12:43:58 PM PDT 24 23618003 ps
T975 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1955267270 Mar 19 12:43:47 PM PDT 24 Mar 19 12:43:48 PM PDT 24 52086437 ps
T976 /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.469065196 Mar 19 12:43:49 PM PDT 24 Mar 19 12:43:50 PM PDT 24 63640659 ps
T977 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.54737714 Mar 19 12:43:47 PM PDT 24 Mar 19 12:43:49 PM PDT 24 27236276 ps
T978 /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.985190640 Mar 19 12:43:58 PM PDT 24 Mar 19 12:44:01 PM PDT 24 130090834 ps
T979 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.1381062344 Mar 19 12:44:01 PM PDT 24 Mar 19 12:44:04 PM PDT 24 42824214 ps
T980 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.731849859 Mar 19 12:44:05 PM PDT 24 Mar 19 12:44:06 PM PDT 24 28028984 ps
T981 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.578694158 Mar 19 12:43:46 PM PDT 24 Mar 19 12:43:47 PM PDT 24 43053446 ps
T982 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.2847805939 Mar 19 12:44:06 PM PDT 24 Mar 19 12:44:08 PM PDT 24 249912022 ps
T983 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.1439961362 Mar 19 12:44:00 PM PDT 24 Mar 19 12:44:04 PM PDT 24 1064102215 ps
T984 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.2975364548 Mar 19 12:44:10 PM PDT 24 Mar 19 12:44:12 PM PDT 24 153328936 ps
T985 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.732378058 Mar 19 12:43:50 PM PDT 24 Mar 19 12:43:52 PM PDT 24 102315797 ps
T986 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3514896721 Mar 19 12:44:05 PM PDT 24 Mar 19 12:44:06 PM PDT 24 38047475 ps
T987 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2899253695 Mar 19 12:43:51 PM PDT 24 Mar 19 12:43:52 PM PDT 24 73739181 ps
T988 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2409040781 Mar 19 12:43:48 PM PDT 24 Mar 19 12:43:50 PM PDT 24 75431617 ps
T989 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.4195028265 Mar 19 12:43:56 PM PDT 24 Mar 19 12:43:57 PM PDT 24 168508784 ps
T990 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.2596273516 Mar 19 12:43:48 PM PDT 24 Mar 19 12:43:49 PM PDT 24 65979671 ps
T991 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.736110344 Mar 19 12:43:47 PM PDT 24 Mar 19 12:43:49 PM PDT 24 28116364 ps

Test location /workspace/coverage/default/11.pwrmgr_stress_all.1115952808
Short name T3
Test name
Test status
Simulation time 1797746315 ps
CPU time 1.93 seconds
Started Mar 19 03:06:50 PM PDT 24
Finished Mar 19 03:06:52 PM PDT 24
Peak memory 200728 kb
Host smart-b1c0b2cf-c9e8-4780-bb18-0daf7b4bcadf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115952808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.1115952808
Directory /workspace/11.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.3806690761
Short name T10
Test name
Test status
Simulation time 145596011 ps
CPU time 0.82 seconds
Started Mar 19 03:07:54 PM PDT 24
Finished Mar 19 03:07:54 PM PDT 24
Peak memory 208908 kb
Host smart-d7b584a1-4de2-4dcc-b3f8-973a1c14dca1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806690761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.3806690761
Directory /workspace/42.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.4136818115
Short name T38
Test name
Test status
Simulation time 113663593 ps
CPU time 1.15 seconds
Started Mar 19 12:43:47 PM PDT 24
Finished Mar 19 12:43:48 PM PDT 24
Peak memory 200404 kb
Host smart-b53e1f2a-a7be-4fe5-ba8a-1fce389c6f54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136818115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.4136818115
Directory /workspace/2.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2971341694
Short name T22
Test name
Test status
Simulation time 1457258114 ps
CPU time 2.15 seconds
Started Mar 19 03:08:03 PM PDT 24
Finished Mar 19 03:08:06 PM PDT 24
Peak memory 200584 kb
Host smart-0011ec3e-9250-465b-bf9d-87d0c3febc40
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971341694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2971341694
Directory /workspace/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.959077881
Short name T35
Test name
Test status
Simulation time 43331714 ps
CPU time 0.67 seconds
Started Mar 19 03:08:11 PM PDT 24
Finished Mar 19 03:08:12 PM PDT 24
Peak memory 200776 kb
Host smart-77ef2493-8eee-4b04-89ae-9134df0b88b8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959077881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_invali
d.959077881
Directory /workspace/44.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.2876557132
Short name T40
Test name
Test status
Simulation time 75298570 ps
CPU time 1.53 seconds
Started Mar 19 12:43:54 PM PDT 24
Finished Mar 19 12:43:56 PM PDT 24
Peak memory 196008 kb
Host smart-c201b970-8ea8-4d09-8687-89f642d03015
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876557132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.2876557132
Directory /workspace/5.pwrmgr_tl_errors/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm.2147449089
Short name T6
Test name
Test status
Simulation time 390438646 ps
CPU time 1.27 seconds
Started Mar 19 03:06:20 PM PDT 24
Finished Mar 19 03:06:22 PM PDT 24
Peak memory 217224 kb
Host smart-79ce9e4b-cd46-410f-9b20-c5a9387cadf3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147449089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.2147449089
Directory /workspace/0.pwrmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.775491774
Short name T82
Test name
Test status
Simulation time 85744176 ps
CPU time 0.98 seconds
Started Mar 19 12:43:51 PM PDT 24
Finished Mar 19 12:43:52 PM PDT 24
Peak memory 194864 kb
Host smart-428ef6fa-e6b8-4cd6-b7e2-0e2f2a27c87a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775491774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.775491774
Directory /workspace/2.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.326667125
Short name T47
Test name
Test status
Simulation time 72755871 ps
CPU time 0.6 seconds
Started Mar 19 12:44:01 PM PDT 24
Finished Mar 19 12:44:03 PM PDT 24
Peak memory 194868 kb
Host smart-e4c7a9d0-c75e-438f-b44a-d4b0adcf8ced
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326667125 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.326667125
Directory /workspace/10.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.2421592514
Short name T8
Test name
Test status
Simulation time 115267132 ps
CPU time 0.73 seconds
Started Mar 19 03:06:54 PM PDT 24
Finished Mar 19 03:06:55 PM PDT 24
Peak memory 198852 kb
Host smart-b4f7c809-3bda-41ed-97ba-d8c09f42e61a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421592514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_
cm_ctrl_config_regwen.2421592514
Directory /workspace/15.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.733081605
Short name T39
Test name
Test status
Simulation time 110411157 ps
CPU time 1.21 seconds
Started Mar 19 12:43:58 PM PDT 24
Finished Mar 19 12:44:00 PM PDT 24
Peak memory 200060 kb
Host smart-06e46dc8-faf7-4856-9dc1-65ebcac18909
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733081605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_err
.733081605
Directory /workspace/16.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.1849275225
Short name T156
Test name
Test status
Simulation time 40004286 ps
CPU time 0.58 seconds
Started Mar 19 03:06:47 PM PDT 24
Finished Mar 19 03:06:48 PM PDT 24
Peak memory 197436 kb
Host smart-9853f3dc-9db9-429e-8b25-52cbcd0d445e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849275225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.1849275225
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_stress_all.1711935800
Short name T1
Test name
Test status
Simulation time 7153717885 ps
CPU time 3.8 seconds
Started Mar 19 03:07:22 PM PDT 24
Finished Mar 19 03:07:26 PM PDT 24
Peak memory 200760 kb
Host smart-82249b50-0fc9-4b19-92df-0c1c62e32201
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711935800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.1711935800
Directory /workspace/22.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.1452616713
Short name T9
Test name
Test status
Simulation time 69142211 ps
CPU time 0.76 seconds
Started Mar 19 03:06:30 PM PDT 24
Finished Mar 19 03:06:32 PM PDT 24
Peak memory 198272 kb
Host smart-1fd73676-687b-46b6-a029-65b2deafbfbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452616713 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.1452616713
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_stress_all_with_rand_reset.3860962115
Short name T18
Test name
Test status
Simulation time 5139387430 ps
CPU time 7.08 seconds
Started Mar 19 03:06:26 PM PDT 24
Finished Mar 19 03:06:33 PM PDT 24
Peak memory 200924 kb
Host smart-c410a69f-ac0a-4547-9551-7e72357abf0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860962115 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all_with_rand_reset.3860962115
Directory /workspace/3.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.1260656255
Short name T52
Test name
Test status
Simulation time 1088474306 ps
CPU time 1.45 seconds
Started Mar 19 12:43:51 PM PDT 24
Finished Mar 19 12:43:53 PM PDT 24
Peak memory 200176 kb
Host smart-ce0d95a3-166c-4f0d-a981-4ce49f7ba9ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260656255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.1260656255
Directory /workspace/5.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.1610584934
Short name T100
Test name
Test status
Simulation time 33081128 ps
CPU time 0.64 seconds
Started Mar 19 12:43:51 PM PDT 24
Finished Mar 19 12:43:52 PM PDT 24
Peak memory 197316 kb
Host smart-1f38b419-d2c3-4a33-afee-5b75044a868c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610584934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.1610584934
Directory /workspace/1.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.1971952005
Short name T894
Test name
Test status
Simulation time 18647529 ps
CPU time 0.61 seconds
Started Mar 19 12:44:10 PM PDT 24
Finished Mar 19 12:44:11 PM PDT 24
Peak memory 194848 kb
Host smart-1ec947d0-396d-4120-9e78-93fe1f7af10d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971952005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.1971952005
Directory /workspace/13.pwrmgr_intr_test/latest

Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.3031543188
Short name T431
Test name
Test status
Simulation time 53005857 ps
CPU time 0.83 seconds
Started Mar 19 03:06:06 PM PDT 24
Finished Mar 19 03:06:07 PM PDT 24
Peak memory 198632 kb
Host smart-14503048-1a1d-4258-bc16-71f50b93da92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031543188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.3031543188
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.1423187385
Short name T130
Test name
Test status
Simulation time 59655652 ps
CPU time 0.65 seconds
Started Mar 19 03:06:54 PM PDT 24
Finished Mar 19 03:06:55 PM PDT 24
Peak memory 198384 kb
Host smart-8f31b1ba-b540-4d01-b250-0e16e99b3d1f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423187385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis
able_rom_integrity_check.1423187385
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_glitch.1068427658
Short name T303
Test name
Test status
Simulation time 45486478 ps
CPU time 0.66 seconds
Started Mar 19 03:06:43 PM PDT 24
Finished Mar 19 03:06:44 PM PDT 24
Peak memory 196772 kb
Host smart-45328e42-5aad-41b0-9262-d37cc84392a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068427658 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.1068427658
Directory /workspace/12.pwrmgr_glitch/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.3133688257
Short name T93
Test name
Test status
Simulation time 52020911 ps
CPU time 1.02 seconds
Started Mar 19 12:43:47 PM PDT 24
Finished Mar 19 12:43:48 PM PDT 24
Peak memory 198408 kb
Host smart-50ca0601-ae1e-4d78-ba43-7f10954cfe0a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133688257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.3
133688257
Directory /workspace/0.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.172768263
Short name T81
Test name
Test status
Simulation time 3325387148 ps
CPU time 3.52 seconds
Started Mar 19 12:43:46 PM PDT 24
Finished Mar 19 12:43:50 PM PDT 24
Peak memory 195212 kb
Host smart-303e038b-959a-4446-8efe-398be5088bdf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172768263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.172768263
Directory /workspace/0.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.1805753212
Short name T927
Test name
Test status
Simulation time 32544745 ps
CPU time 0.72 seconds
Started Mar 19 12:43:42 PM PDT 24
Finished Mar 19 12:43:43 PM PDT 24
Peak memory 196108 kb
Host smart-9a8bbe7d-f267-4630-83b7-b967d24dae7d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805753212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.1
805753212
Directory /workspace/0.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2505461013
Short name T920
Test name
Test status
Simulation time 56111990 ps
CPU time 0.99 seconds
Started Mar 19 12:43:41 PM PDT 24
Finished Mar 19 12:43:42 PM PDT 24
Peak memory 195948 kb
Host smart-274bdb11-1fd7-472a-ba37-6a1fc207549a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505461013 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.2505461013
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.1068678311
Short name T904
Test name
Test status
Simulation time 51853584 ps
CPU time 0.62 seconds
Started Mar 19 12:43:42 PM PDT 24
Finished Mar 19 12:43:43 PM PDT 24
Peak memory 197120 kb
Host smart-37f1d2df-f8f5-44dd-8f8c-e19cda3e4713
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068678311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.1068678311
Directory /workspace/0.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.2596273516
Short name T990
Test name
Test status
Simulation time 65979671 ps
CPU time 0.59 seconds
Started Mar 19 12:43:48 PM PDT 24
Finished Mar 19 12:43:49 PM PDT 24
Peak memory 194912 kb
Host smart-5013dae9-b6e0-488d-bea0-bde5f4aa1de8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596273516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.2596273516
Directory /workspace/0.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2450040717
Short name T909
Test name
Test status
Simulation time 23502542 ps
CPU time 0.78 seconds
Started Mar 19 12:43:44 PM PDT 24
Finished Mar 19 12:43:45 PM PDT 24
Peak memory 194908 kb
Host smart-ddeae954-92cb-49dd-b46e-9569867d58ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450040717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa
me_csr_outstanding.2450040717
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.1115855921
Short name T953
Test name
Test status
Simulation time 226367800 ps
CPU time 1.43 seconds
Started Mar 19 12:43:45 PM PDT 24
Finished Mar 19 12:43:46 PM PDT 24
Peak memory 195208 kb
Host smart-c3e43cfc-ab0f-48aa-972f-363bcc288e17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115855921 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.1115855921
Directory /workspace/0.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.4208671032
Short name T127
Test name
Test status
Simulation time 191724966 ps
CPU time 1.64 seconds
Started Mar 19 12:43:43 PM PDT 24
Finished Mar 19 12:43:44 PM PDT 24
Peak memory 200208 kb
Host smart-f0dc24fe-67b3-44e2-bee8-df122fc70d5b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208671032 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err
.4208671032
Directory /workspace/0.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1567950113
Short name T83
Test name
Test status
Simulation time 55867458 ps
CPU time 0.9 seconds
Started Mar 19 12:43:47 PM PDT 24
Finished Mar 19 12:43:48 PM PDT 24
Peak memory 194876 kb
Host smart-d961b4f0-e350-4637-95cd-37b19b001f8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567950113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.1
567950113
Directory /workspace/1.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.2114992114
Short name T896
Test name
Test status
Simulation time 221525521 ps
CPU time 3.22 seconds
Started Mar 19 12:43:47 PM PDT 24
Finished Mar 19 12:43:50 PM PDT 24
Peak memory 198672 kb
Host smart-a6ce5f43-4a5d-4b86-b8d5-94117bf7fd3a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114992114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.2
114992114
Directory /workspace/1.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.3963233360
Short name T91
Test name
Test status
Simulation time 28110678 ps
CPU time 0.7 seconds
Started Mar 19 12:43:45 PM PDT 24
Finished Mar 19 12:43:46 PM PDT 24
Peak memory 194844 kb
Host smart-21e5c4d1-5d96-4127-a03d-6f824a0c3762
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963233360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.3
963233360
Directory /workspace/1.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1955267270
Short name T975
Test name
Test status
Simulation time 52086437 ps
CPU time 0.87 seconds
Started Mar 19 12:43:47 PM PDT 24
Finished Mar 19 12:43:48 PM PDT 24
Peak memory 195028 kb
Host smart-e9a69a73-2eac-4f08-a0c0-250ea0afcbd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955267270 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.1955267270
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.375142635
Short name T952
Test name
Test status
Simulation time 46581436 ps
CPU time 0.62 seconds
Started Mar 19 12:43:43 PM PDT 24
Finished Mar 19 12:43:43 PM PDT 24
Peak memory 194868 kb
Host smart-5b9b120b-63ab-45ce-9dda-31a5f3705f8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375142635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.375142635
Directory /workspace/1.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.2764849945
Short name T85
Test name
Test status
Simulation time 82650642 ps
CPU time 0.78 seconds
Started Mar 19 12:43:47 PM PDT 24
Finished Mar 19 12:43:48 PM PDT 24
Peak memory 197328 kb
Host smart-3286620d-165e-4d94-b854-95bad1f109f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764849945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sa
me_csr_outstanding.2764849945
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.2265497792
Short name T960
Test name
Test status
Simulation time 55772666 ps
CPU time 1.41 seconds
Started Mar 19 12:43:50 PM PDT 24
Finished Mar 19 12:43:51 PM PDT 24
Peak memory 196160 kb
Host smart-0eea7db1-017d-46dc-bfea-707b83f6f497
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265497792 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.2265497792
Directory /workspace/1.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.34920002
Short name T51
Test name
Test status
Simulation time 112888182 ps
CPU time 1.34 seconds
Started Mar 19 12:43:59 PM PDT 24
Finished Mar 19 12:44:01 PM PDT 24
Peak memory 200032 kb
Host smart-ef80a8c4-577f-44c4-9f27-aa1284b0b719
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34920002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err.34920002
Directory /workspace/1.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.3520683276
Short name T43
Test name
Test status
Simulation time 49793116 ps
CPU time 1.04 seconds
Started Mar 19 12:43:57 PM PDT 24
Finished Mar 19 12:43:59 PM PDT 24
Peak memory 196092 kb
Host smart-6a088248-72e2-4168-9952-96461cc3ade2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520683276 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.3520683276
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.3998702706
Short name T87
Test name
Test status
Simulation time 16586925 ps
CPU time 0.65 seconds
Started Mar 19 12:43:56 PM PDT 24
Finished Mar 19 12:43:56 PM PDT 24
Peak memory 195048 kb
Host smart-a0da732a-4196-4b2c-ac8a-690a0a2c8a12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998702706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.3998702706
Directory /workspace/10.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1081889287
Short name T930
Test name
Test status
Simulation time 76708816 ps
CPU time 0.75 seconds
Started Mar 19 12:43:48 PM PDT 24
Finished Mar 19 12:43:49 PM PDT 24
Peak memory 197000 kb
Host smart-87637ae0-4d2a-4914-b662-153b780a8790
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081889287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_s
ame_csr_outstanding.1081889287
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.3530321206
Short name T917
Test name
Test status
Simulation time 303258985 ps
CPU time 1.7 seconds
Started Mar 19 12:43:48 PM PDT 24
Finished Mar 19 12:43:50 PM PDT 24
Peak memory 200452 kb
Host smart-ddd9384d-baed-4546-8bcd-c74e19e8caab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530321206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.3530321206
Directory /workspace/10.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.3653009676
Short name T968
Test name
Test status
Simulation time 290585794 ps
CPU time 1.05 seconds
Started Mar 19 12:43:57 PM PDT 24
Finished Mar 19 12:43:58 PM PDT 24
Peak memory 195056 kb
Host smart-aad513d3-ca3a-4d4a-9aef-48fea3c29110
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653009676 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_er
r.3653009676
Directory /workspace/10.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1212582056
Short name T42
Test name
Test status
Simulation time 67481845 ps
CPU time 1.13 seconds
Started Mar 19 12:44:04 PM PDT 24
Finished Mar 19 12:44:05 PM PDT 24
Peak memory 197700 kb
Host smart-2b25f494-c3ce-4553-aa61-89519def9a56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212582056 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.1212582056
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.890901896
Short name T913
Test name
Test status
Simulation time 54386719 ps
CPU time 0.66 seconds
Started Mar 19 12:44:05 PM PDT 24
Finished Mar 19 12:44:05 PM PDT 24
Peak memory 197128 kb
Host smart-97a3e1ac-1848-4535-98b6-e84c8ecf2483
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890901896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.890901896
Directory /workspace/11.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.2066538724
Short name T955
Test name
Test status
Simulation time 55301891 ps
CPU time 0.65 seconds
Started Mar 19 12:44:06 PM PDT 24
Finished Mar 19 12:44:06 PM PDT 24
Peak memory 194928 kb
Host smart-6b64d75e-047f-4b2e-8b2e-211fd1526f37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066538724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.2066538724
Directory /workspace/11.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3451081513
Short name T89
Test name
Test status
Simulation time 79222053 ps
CPU time 0.93 seconds
Started Mar 19 12:43:56 PM PDT 24
Finished Mar 19 12:43:57 PM PDT 24
Peak memory 194892 kb
Host smart-5b3f1255-094a-4622-a261-6492ce230297
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451081513 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.3451081513
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.632806122
Short name T79
Test name
Test status
Simulation time 32495394 ps
CPU time 1.48 seconds
Started Mar 19 12:44:04 PM PDT 24
Finished Mar 19 12:44:06 PM PDT 24
Peak memory 196284 kb
Host smart-553f254c-5843-43a8-81f8-f456728cd789
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632806122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.632806122
Directory /workspace/11.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.41085717
Short name T922
Test name
Test status
Simulation time 100932815 ps
CPU time 1.18 seconds
Started Mar 19 12:44:06 PM PDT 24
Finished Mar 19 12:44:07 PM PDT 24
Peak memory 200120 kb
Host smart-5bde59cd-c490-4052-a8f5-d0aa4879bc25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41085717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_err.41085717
Directory /workspace/11.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.2655963878
Short name T961
Test name
Test status
Simulation time 71727077 ps
CPU time 0.86 seconds
Started Mar 19 12:44:04 PM PDT 24
Finished Mar 19 12:44:05 PM PDT 24
Peak memory 195020 kb
Host smart-30b3dda5-9d5c-4959-a549-8f930b4b41e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655963878 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.2655963878
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.1817276407
Short name T897
Test name
Test status
Simulation time 31638709 ps
CPU time 0.68 seconds
Started Mar 19 12:44:02 PM PDT 24
Finished Mar 19 12:44:04 PM PDT 24
Peak memory 197168 kb
Host smart-cfeae2ce-2e1c-41e4-9df6-ae43acb236bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817276407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.1817276407
Directory /workspace/12.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.2803376152
Short name T884
Test name
Test status
Simulation time 33680648 ps
CPU time 0.59 seconds
Started Mar 19 12:43:59 PM PDT 24
Finished Mar 19 12:44:01 PM PDT 24
Peak memory 194912 kb
Host smart-f04baabe-d1d2-4b87-a73c-7fa13854ff2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803376152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.2803376152
Directory /workspace/12.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.1602856983
Short name T88
Test name
Test status
Simulation time 23361045 ps
CPU time 0.92 seconds
Started Mar 19 12:43:59 PM PDT 24
Finished Mar 19 12:44:01 PM PDT 24
Peak memory 198156 kb
Host smart-6588b7cb-7884-4f06-a18f-8b24d8eb09e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602856983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.1602856983
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.3213003280
Short name T916
Test name
Test status
Simulation time 136913412 ps
CPU time 1.66 seconds
Started Mar 19 12:44:14 PM PDT 24
Finished Mar 19 12:44:17 PM PDT 24
Peak memory 196176 kb
Host smart-06749c1d-db14-4e44-9e4b-085254a5914d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213003280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.3213003280
Directory /workspace/12.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.2847805939
Short name T982
Test name
Test status
Simulation time 249912022 ps
CPU time 1.62 seconds
Started Mar 19 12:44:06 PM PDT 24
Finished Mar 19 12:44:08 PM PDT 24
Peak memory 195088 kb
Host smart-c0df219b-13d2-4eef-be40-05907d28fb20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847805939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.2847805939
Directory /workspace/12.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.287391597
Short name T969
Test name
Test status
Simulation time 90999641 ps
CPU time 0.83 seconds
Started Mar 19 12:44:01 PM PDT 24
Finished Mar 19 12:44:03 PM PDT 24
Peak memory 195032 kb
Host smart-c4dfb3b6-3222-4bf4-9de3-04f651c2d47e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287391597 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.287391597
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.2883449699
Short name T97
Test name
Test status
Simulation time 121478727 ps
CPU time 0.65 seconds
Started Mar 19 12:43:57 PM PDT 24
Finished Mar 19 12:43:58 PM PDT 24
Peak memory 197156 kb
Host smart-063a53c9-ce2b-47fc-8dea-23977edb72f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883449699 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.2883449699
Directory /workspace/13.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.553796432
Short name T956
Test name
Test status
Simulation time 40243109 ps
CPU time 0.89 seconds
Started Mar 19 12:43:54 PM PDT 24
Finished Mar 19 12:43:55 PM PDT 24
Peak memory 198284 kb
Host smart-12e6a471-b78a-4ec7-91f8-077c0b73427d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553796432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sa
me_csr_outstanding.553796432
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.1439961362
Short name T983
Test name
Test status
Simulation time 1064102215 ps
CPU time 1.94 seconds
Started Mar 19 12:44:00 PM PDT 24
Finished Mar 19 12:44:04 PM PDT 24
Peak memory 196064 kb
Host smart-6e51219e-3b8f-46fd-b955-99eddaceb50d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439961362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.1439961362
Directory /workspace/13.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3297170835
Short name T67
Test name
Test status
Simulation time 113377669 ps
CPU time 1.18 seconds
Started Mar 19 12:44:04 PM PDT 24
Finished Mar 19 12:44:06 PM PDT 24
Peak memory 200100 kb
Host smart-1f8f7a37-78c8-4b97-895c-66c331d9a692
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297170835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.3297170835
Directory /workspace/13.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1644309693
Short name T80
Test name
Test status
Simulation time 57552865 ps
CPU time 1.01 seconds
Started Mar 19 12:43:54 PM PDT 24
Finished Mar 19 12:43:55 PM PDT 24
Peak memory 195036 kb
Host smart-d5fad0cf-85f0-4637-95d6-7c14d0d5ee2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644309693 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.1644309693
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.414348606
Short name T92
Test name
Test status
Simulation time 38204607 ps
CPU time 0.6 seconds
Started Mar 19 12:44:05 PM PDT 24
Finished Mar 19 12:44:06 PM PDT 24
Peak memory 195052 kb
Host smart-6238f116-7181-4e5a-8125-643ae43e98e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414348606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.414348606
Directory /workspace/14.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.532435228
Short name T135
Test name
Test status
Simulation time 43074987 ps
CPU time 0.59 seconds
Started Mar 19 12:43:58 PM PDT 24
Finished Mar 19 12:43:59 PM PDT 24
Peak memory 194884 kb
Host smart-49823d12-e0f9-4e7d-b015-d6b910bbad2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532435228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.532435228
Directory /workspace/14.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.847564976
Short name T972
Test name
Test status
Simulation time 52935637 ps
CPU time 0.75 seconds
Started Mar 19 12:44:01 PM PDT 24
Finished Mar 19 12:44:03 PM PDT 24
Peak memory 194888 kb
Host smart-4aa1444d-ea88-4ca3-9213-6180b18f0fea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847564976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sa
me_csr_outstanding.847564976
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.1608620843
Short name T66
Test name
Test status
Simulation time 407709039 ps
CPU time 2.26 seconds
Started Mar 19 12:43:52 PM PDT 24
Finished Mar 19 12:43:54 PM PDT 24
Peak memory 196260 kb
Host smart-ec08b87d-4259-4655-b856-1ad91990c9e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608620843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.1608620843
Directory /workspace/14.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.3937517894
Short name T53
Test name
Test status
Simulation time 348904577 ps
CPU time 1.56 seconds
Started Mar 19 12:43:58 PM PDT 24
Finished Mar 19 12:43:59 PM PDT 24
Peak memory 200304 kb
Host smart-91da201b-0bff-499c-9f98-e533d6008832
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937517894 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_er
r.3937517894
Directory /workspace/14.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3514896721
Short name T986
Test name
Test status
Simulation time 38047475 ps
CPU time 0.89 seconds
Started Mar 19 12:44:05 PM PDT 24
Finished Mar 19 12:44:06 PM PDT 24
Peak memory 195036 kb
Host smart-c7e6110f-4578-41e1-836c-ce4536f25b61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514896721 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.3514896721
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.760116623
Short name T90
Test name
Test status
Simulation time 27966714 ps
CPU time 0.62 seconds
Started Mar 19 12:43:55 PM PDT 24
Finished Mar 19 12:43:56 PM PDT 24
Peak memory 194952 kb
Host smart-e49a2370-bddd-497d-888b-d1daf2701076
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760116623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.760116623
Directory /workspace/15.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.2125147184
Short name T949
Test name
Test status
Simulation time 46780125 ps
CPU time 0.59 seconds
Started Mar 19 12:44:11 PM PDT 24
Finished Mar 19 12:44:12 PM PDT 24
Peak memory 194900 kb
Host smart-7604ccb1-85b9-4154-a913-be92eaa52564
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125147184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.2125147184
Directory /workspace/15.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.4114244771
Short name T86
Test name
Test status
Simulation time 61434500 ps
CPU time 0.85 seconds
Started Mar 19 12:43:58 PM PDT 24
Finished Mar 19 12:43:59 PM PDT 24
Peak memory 198280 kb
Host smart-40624c98-5233-4bcc-a262-5eb98d7a4b47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114244771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s
ame_csr_outstanding.4114244771
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.952514757
Short name T931
Test name
Test status
Simulation time 65451302 ps
CPU time 1.4 seconds
Started Mar 19 12:43:56 PM PDT 24
Finished Mar 19 12:43:58 PM PDT 24
Peak memory 196072 kb
Host smart-3292897b-5169-4e13-8dc4-9cd7ac487350
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952514757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.952514757
Directory /workspace/15.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.4219858597
Short name T125
Test name
Test status
Simulation time 130339737 ps
CPU time 1.16 seconds
Started Mar 19 12:43:57 PM PDT 24
Finished Mar 19 12:43:58 PM PDT 24
Peak memory 200144 kb
Host smart-510f0282-5173-4e72-b152-3ae7ec6e8ff2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219858597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.4219858597
Directory /workspace/15.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.3969265155
Short name T962
Test name
Test status
Simulation time 88444544 ps
CPU time 1.2 seconds
Started Mar 19 12:43:58 PM PDT 24
Finished Mar 19 12:43:59 PM PDT 24
Peak memory 197428 kb
Host smart-c1075867-cf53-4eb3-9661-f7e449046ff5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969265155 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.3969265155
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.3793211471
Short name T935
Test name
Test status
Simulation time 16201840 ps
CPU time 0.63 seconds
Started Mar 19 12:43:56 PM PDT 24
Finished Mar 19 12:43:57 PM PDT 24
Peak memory 197256 kb
Host smart-0549b0c9-1bb2-472f-96ce-8e80b0c56e0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793211471 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.3793211471
Directory /workspace/16.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.547330227
Short name T886
Test name
Test status
Simulation time 54575913 ps
CPU time 0.6 seconds
Started Mar 19 12:43:59 PM PDT 24
Finished Mar 19 12:43:59 PM PDT 24
Peak memory 194840 kb
Host smart-a85016fc-8bbc-431e-96cf-775806cc0ef7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547330227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.547330227
Directory /workspace/16.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1052321211
Short name T84
Test name
Test status
Simulation time 74622556 ps
CPU time 0.92 seconds
Started Mar 19 12:43:54 PM PDT 24
Finished Mar 19 12:43:55 PM PDT 24
Peak memory 194892 kb
Host smart-5fb4caed-8a09-47e1-84de-03a7e2eea1ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052321211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s
ame_csr_outstanding.1052321211
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.2975364548
Short name T984
Test name
Test status
Simulation time 153328936 ps
CPU time 1.79 seconds
Started Mar 19 12:44:10 PM PDT 24
Finished Mar 19 12:44:12 PM PDT 24
Peak memory 196064 kb
Host smart-d2a6bd38-0bb3-4c4a-ba3b-363552b3fcfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975364548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.2975364548
Directory /workspace/16.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1681334584
Short name T928
Test name
Test status
Simulation time 57305627 ps
CPU time 0.83 seconds
Started Mar 19 12:44:07 PM PDT 24
Finished Mar 19 12:44:08 PM PDT 24
Peak memory 195020 kb
Host smart-6944917e-da33-4a08-a3e3-a04310cb3060
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681334584 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.1681334584
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.1902408327
Short name T901
Test name
Test status
Simulation time 27823198 ps
CPU time 0.61 seconds
Started Mar 19 12:44:08 PM PDT 24
Finished Mar 19 12:44:09 PM PDT 24
Peak memory 198176 kb
Host smart-6c7c718a-11c4-4e63-9c04-9e66c51fbb48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902408327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.1902408327
Directory /workspace/17.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.3436477806
Short name T48
Test name
Test status
Simulation time 42743121 ps
CPU time 0.61 seconds
Started Mar 19 12:43:54 PM PDT 24
Finished Mar 19 12:43:55 PM PDT 24
Peak memory 194876 kb
Host smart-4cbe9b35-7313-4808-9cb2-c8bc2457b5e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436477806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.3436477806
Directory /workspace/17.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.3513597295
Short name T915
Test name
Test status
Simulation time 56009680 ps
CPU time 0.91 seconds
Started Mar 19 12:43:53 PM PDT 24
Finished Mar 19 12:43:54 PM PDT 24
Peak memory 194888 kb
Host smart-3b5ea41b-005a-4865-8f51-19442587374b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513597295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s
ame_csr_outstanding.3513597295
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.1846575964
Short name T914
Test name
Test status
Simulation time 241573545 ps
CPU time 1.18 seconds
Started Mar 19 12:43:57 PM PDT 24
Finished Mar 19 12:43:58 PM PDT 24
Peak memory 195136 kb
Host smart-e08f8b6d-a72a-4d56-94e4-2c205f48ea78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846575964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.1846575964
Directory /workspace/17.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3637746796
Short name T959
Test name
Test status
Simulation time 206739749 ps
CPU time 1.6 seconds
Started Mar 19 12:44:07 PM PDT 24
Finished Mar 19 12:44:09 PM PDT 24
Peak memory 200188 kb
Host smart-b88839b5-273f-496b-942f-7eff6693cd68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637746796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_er
r.3637746796
Directory /workspace/17.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.2335033019
Short name T945
Test name
Test status
Simulation time 63667298 ps
CPU time 1.17 seconds
Started Mar 19 12:43:55 PM PDT 24
Finished Mar 19 12:43:56 PM PDT 24
Peak memory 196868 kb
Host smart-3df044e4-81e2-42b0-a1db-9b88fa5a08b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335033019 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.2335033019
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.3511002950
Short name T908
Test name
Test status
Simulation time 147698541 ps
CPU time 0.64 seconds
Started Mar 19 12:43:57 PM PDT 24
Finished Mar 19 12:43:58 PM PDT 24
Peak memory 194960 kb
Host smart-654351bc-c37a-4ac0-9c5f-dd7f1ab1e398
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511002950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.3511002950
Directory /workspace/18.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.1599142950
Short name T138
Test name
Test status
Simulation time 18256329 ps
CPU time 0.6 seconds
Started Mar 19 12:44:04 PM PDT 24
Finished Mar 19 12:44:05 PM PDT 24
Peak memory 194860 kb
Host smart-24cc1028-0039-45c8-9f7c-540bec7b4b2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599142950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.1599142950
Directory /workspace/18.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.3535968030
Short name T957
Test name
Test status
Simulation time 362825061 ps
CPU time 0.82 seconds
Started Mar 19 12:44:08 PM PDT 24
Finished Mar 19 12:44:09 PM PDT 24
Peak memory 198196 kb
Host smart-3252e8af-c695-468c-961d-1cbcc6486e2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535968030 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_s
ame_csr_outstanding.3535968030
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.4195028265
Short name T989
Test name
Test status
Simulation time 168508784 ps
CPU time 1.23 seconds
Started Mar 19 12:43:56 PM PDT 24
Finished Mar 19 12:43:57 PM PDT 24
Peak memory 196120 kb
Host smart-9ecdc11c-bb0d-487e-baa2-eefce1c74db5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195028265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.4195028265
Directory /workspace/18.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.1093860482
Short name T77
Test name
Test status
Simulation time 113099370 ps
CPU time 1.09 seconds
Started Mar 19 12:44:05 PM PDT 24
Finished Mar 19 12:44:06 PM PDT 24
Peak memory 200012 kb
Host smart-cdc437ec-af6a-4a08-b1ee-8227046e4210
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093860482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.1093860482
Directory /workspace/18.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.2463424902
Short name T940
Test name
Test status
Simulation time 54696349 ps
CPU time 0.89 seconds
Started Mar 19 12:44:07 PM PDT 24
Finished Mar 19 12:44:14 PM PDT 24
Peak memory 195036 kb
Host smart-b3cb6cab-ab39-4594-ac3f-09c9737403b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463424902 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.2463424902
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.4179429401
Short name T101
Test name
Test status
Simulation time 18165476 ps
CPU time 0.66 seconds
Started Mar 19 12:44:10 PM PDT 24
Finished Mar 19 12:44:11 PM PDT 24
Peak memory 194980 kb
Host smart-c1061acf-6bbf-4865-8697-b4453b67ea1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179429401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.4179429401
Directory /workspace/19.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.711521255
Short name T971
Test name
Test status
Simulation time 19765713 ps
CPU time 0.61 seconds
Started Mar 19 12:43:55 PM PDT 24
Finished Mar 19 12:43:56 PM PDT 24
Peak memory 194884 kb
Host smart-ace5e2ee-3130-499b-aae9-855805839979
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711521255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.711521255
Directory /workspace/19.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.3260810986
Short name T936
Test name
Test status
Simulation time 257305447 ps
CPU time 0.93 seconds
Started Mar 19 12:44:00 PM PDT 24
Finished Mar 19 12:44:01 PM PDT 24
Peak memory 194888 kb
Host smart-aa806c93-a6ec-415e-a641-1f755fd77851
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260810986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s
ame_csr_outstanding.3260810986
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.2502937127
Short name T965
Test name
Test status
Simulation time 201762926 ps
CPU time 1.43 seconds
Started Mar 19 12:44:00 PM PDT 24
Finished Mar 19 12:44:02 PM PDT 24
Peak memory 195252 kb
Host smart-d9f9f432-9fa5-4298-ac83-41dc5e0cf19b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502937127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.2502937127
Directory /workspace/19.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.1632917490
Short name T942
Test name
Test status
Simulation time 210651836 ps
CPU time 1.74 seconds
Started Mar 19 12:44:03 PM PDT 24
Finished Mar 19 12:44:05 PM PDT 24
Peak memory 200208 kb
Host smart-3db70f21-3552-4735-a70b-6cb2520f148a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632917490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.1632917490
Directory /workspace/19.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.1365340821
Short name T950
Test name
Test status
Simulation time 123781049 ps
CPU time 1.89 seconds
Started Mar 19 12:44:01 PM PDT 24
Finished Mar 19 12:44:03 PM PDT 24
Peak memory 195000 kb
Host smart-16f042db-aaeb-45a4-9c85-9a6925889ef1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365340821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.1
365340821
Directory /workspace/2.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2409040781
Short name T988
Test name
Test status
Simulation time 75431617 ps
CPU time 0.69 seconds
Started Mar 19 12:43:48 PM PDT 24
Finished Mar 19 12:43:50 PM PDT 24
Peak memory 198108 kb
Host smart-43d90b2a-bdd6-48b9-ab12-b541dbb83b73
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409040781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.2
409040781
Directory /workspace/2.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.4183552379
Short name T906
Test name
Test status
Simulation time 62379550 ps
CPU time 0.85 seconds
Started Mar 19 12:43:52 PM PDT 24
Finished Mar 19 12:43:53 PM PDT 24
Peak memory 195000 kb
Host smart-340f4428-4e09-4e12-8d99-0bcc9fa186b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183552379 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.4183552379
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.3339536581
Short name T98
Test name
Test status
Simulation time 51531692 ps
CPU time 0.64 seconds
Started Mar 19 12:43:43 PM PDT 24
Finished Mar 19 12:43:44 PM PDT 24
Peak memory 197420 kb
Host smart-6cbd498c-a31a-4e41-86ed-ca247dc7b325
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339536581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.3339536581
Directory /workspace/2.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.4056665076
Short name T907
Test name
Test status
Simulation time 20575163 ps
CPU time 0.63 seconds
Started Mar 19 12:43:42 PM PDT 24
Finished Mar 19 12:43:43 PM PDT 24
Peak memory 194876 kb
Host smart-ad93f264-b332-4496-a8cd-a4223c82caae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056665076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.4056665076
Directory /workspace/2.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.625910128
Short name T941
Test name
Test status
Simulation time 34325654 ps
CPU time 0.89 seconds
Started Mar 19 12:44:15 PM PDT 24
Finished Mar 19 12:44:16 PM PDT 24
Peak memory 198196 kb
Host smart-46bcdf9e-62ab-4753-99d7-f7aebe24e21a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625910128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sam
e_csr_outstanding.625910128
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.3614436913
Short name T938
Test name
Test status
Simulation time 181149053 ps
CPU time 1.67 seconds
Started Mar 19 12:43:45 PM PDT 24
Finished Mar 19 12:43:47 PM PDT 24
Peak memory 196080 kb
Host smart-9d78c15e-3f57-4d5e-a1dd-641d854025ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614436913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.3614436913
Directory /workspace/2.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.3284984199
Short name T932
Test name
Test status
Simulation time 20881846 ps
CPU time 0.61 seconds
Started Mar 19 12:43:59 PM PDT 24
Finished Mar 19 12:44:01 PM PDT 24
Peak memory 194920 kb
Host smart-cc742e65-b224-4148-a16c-9d735e2a671a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284984199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.3284984199
Directory /workspace/20.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.3032935602
Short name T898
Test name
Test status
Simulation time 23084611 ps
CPU time 0.63 seconds
Started Mar 19 12:44:12 PM PDT 24
Finished Mar 19 12:44:13 PM PDT 24
Peak memory 194864 kb
Host smart-048314a9-bb99-4a3f-9f2d-bacc5a052fa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032935602 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.3032935602
Directory /workspace/21.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.1716170443
Short name T893
Test name
Test status
Simulation time 17135495 ps
CPU time 0.65 seconds
Started Mar 19 12:44:02 PM PDT 24
Finished Mar 19 12:44:03 PM PDT 24
Peak memory 194888 kb
Host smart-5b2cf239-d10e-46e8-ba7d-bd6af37da4c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716170443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.1716170443
Directory /workspace/22.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.1988422420
Short name T883
Test name
Test status
Simulation time 23952153 ps
CPU time 0.59 seconds
Started Mar 19 12:43:59 PM PDT 24
Finished Mar 19 12:44:01 PM PDT 24
Peak memory 194884 kb
Host smart-cfbd5726-c0ca-45d1-8e26-34a53f80c50f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988422420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.1988422420
Directory /workspace/23.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.3646180044
Short name T923
Test name
Test status
Simulation time 47538507 ps
CPU time 0.61 seconds
Started Mar 19 12:44:00 PM PDT 24
Finished Mar 19 12:44:02 PM PDT 24
Peak memory 194876 kb
Host smart-801d18fb-5760-4bcc-a022-e2c4ade4216c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646180044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.3646180044
Directory /workspace/24.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.3837414220
Short name T892
Test name
Test status
Simulation time 50128596 ps
CPU time 0.61 seconds
Started Mar 19 12:44:00 PM PDT 24
Finished Mar 19 12:44:01 PM PDT 24
Peak memory 194860 kb
Host smart-f889211e-5c52-476b-af7c-1841379fdc1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837414220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.3837414220
Directory /workspace/25.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.1767314475
Short name T924
Test name
Test status
Simulation time 42534998 ps
CPU time 0.61 seconds
Started Mar 19 12:44:00 PM PDT 24
Finished Mar 19 12:44:02 PM PDT 24
Peak memory 194876 kb
Host smart-7ac0ead9-b046-4141-886c-d4aba5b3d4de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767314475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.1767314475
Directory /workspace/26.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.731849859
Short name T980
Test name
Test status
Simulation time 28028984 ps
CPU time 0.63 seconds
Started Mar 19 12:44:05 PM PDT 24
Finished Mar 19 12:44:06 PM PDT 24
Peak memory 194916 kb
Host smart-c6bfd9a5-20d6-4cec-90b6-844b0efc7e9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731849859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.731849859
Directory /workspace/27.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.761107500
Short name T943
Test name
Test status
Simulation time 31637564 ps
CPU time 0.6 seconds
Started Mar 19 12:44:00 PM PDT 24
Finished Mar 19 12:44:01 PM PDT 24
Peak memory 194884 kb
Host smart-9987cd15-7142-4bdd-93b8-4c2141f613b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761107500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.761107500
Directory /workspace/28.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.247788500
Short name T911
Test name
Test status
Simulation time 18732662 ps
CPU time 0.66 seconds
Started Mar 19 12:44:16 PM PDT 24
Finished Mar 19 12:44:16 PM PDT 24
Peak memory 194936 kb
Host smart-abc0d235-f76e-49b8-b4dc-a7bc32b0b3a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247788500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.247788500
Directory /workspace/29.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.2707733069
Short name T95
Test name
Test status
Simulation time 147345869 ps
CPU time 0.98 seconds
Started Mar 19 12:43:50 PM PDT 24
Finished Mar 19 12:43:51 PM PDT 24
Peak memory 194860 kb
Host smart-6a5ea333-9e65-4932-b839-dcb79bb4c48c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707733069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.2
707733069
Directory /workspace/3.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.2664966115
Short name T102
Test name
Test status
Simulation time 504344947 ps
CPU time 1.88 seconds
Started Mar 19 12:43:56 PM PDT 24
Finished Mar 19 12:43:58 PM PDT 24
Peak memory 195008 kb
Host smart-110e8784-f304-493b-aebf-16d388638e82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664966115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.2
664966115
Directory /workspace/3.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2495107276
Short name T94
Test name
Test status
Simulation time 35719611 ps
CPU time 0.67 seconds
Started Mar 19 12:43:48 PM PDT 24
Finished Mar 19 12:43:49 PM PDT 24
Peak memory 196116 kb
Host smart-d088328b-1409-474f-802e-e92f5471039b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495107276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.2
495107276
Directory /workspace/3.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.4175584603
Short name T78
Test name
Test status
Simulation time 70741292 ps
CPU time 0.96 seconds
Started Mar 19 12:43:48 PM PDT 24
Finished Mar 19 12:43:50 PM PDT 24
Peak memory 195120 kb
Host smart-83112e59-5281-4caf-b660-0c95d98fdbee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175584603 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.4175584603
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.516437534
Short name T99
Test name
Test status
Simulation time 25160750 ps
CPU time 0.68 seconds
Started Mar 19 12:43:56 PM PDT 24
Finished Mar 19 12:43:57 PM PDT 24
Peak memory 194992 kb
Host smart-780aa8bf-652e-48ef-b3a5-e2e29f24f069
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516437534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.516437534
Directory /workspace/3.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.2068504841
Short name T919
Test name
Test status
Simulation time 43458365 ps
CPU time 0.59 seconds
Started Mar 19 12:44:04 PM PDT 24
Finished Mar 19 12:44:04 PM PDT 24
Peak memory 194848 kb
Host smart-8fd5f7a6-f118-4988-9948-e698c7090267
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068504841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.2068504841
Directory /workspace/3.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.633110439
Short name T946
Test name
Test status
Simulation time 61144329 ps
CPU time 0.83 seconds
Started Mar 19 12:43:48 PM PDT 24
Finished Mar 19 12:43:50 PM PDT 24
Peak memory 198208 kb
Host smart-dfc3f47e-6f73-40d4-8a33-844eb93196c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633110439 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sam
e_csr_outstanding.633110439
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.1177448650
Short name T905
Test name
Test status
Simulation time 478465990 ps
CPU time 2.3 seconds
Started Mar 19 12:44:03 PM PDT 24
Finished Mar 19 12:44:06 PM PDT 24
Peak memory 196140 kb
Host smart-cfa45bfd-e244-431b-af37-e67384904d3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177448650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.1177448650
Directory /workspace/3.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.3971318588
Short name T126
Test name
Test status
Simulation time 208511000 ps
CPU time 1.77 seconds
Started Mar 19 12:43:52 PM PDT 24
Finished Mar 19 12:43:54 PM PDT 24
Peak memory 200288 kb
Host smart-18ebd897-cd13-4f9e-9cf0-a52dc0d2f14d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971318588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.3971318588
Directory /workspace/3.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.1249642182
Short name T918
Test name
Test status
Simulation time 16646604 ps
CPU time 0.62 seconds
Started Mar 19 12:43:59 PM PDT 24
Finished Mar 19 12:44:01 PM PDT 24
Peak memory 194860 kb
Host smart-4b55607b-aa6f-4ebb-8038-76ba655e448e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249642182 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.1249642182
Directory /workspace/30.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.34747244
Short name T900
Test name
Test status
Simulation time 22468134 ps
CPU time 0.66 seconds
Started Mar 19 12:44:05 PM PDT 24
Finished Mar 19 12:44:05 PM PDT 24
Peak memory 194880 kb
Host smart-4e450e98-ead3-49b4-be87-5de496b35df3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34747244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.34747244
Directory /workspace/31.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.1942526284
Short name T947
Test name
Test status
Simulation time 17929426 ps
CPU time 0.7 seconds
Started Mar 19 12:44:00 PM PDT 24
Finished Mar 19 12:44:02 PM PDT 24
Peak memory 194884 kb
Host smart-ed3356fd-fa3e-4d7e-b104-131c53d6d4f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942526284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.1942526284
Directory /workspace/32.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.4208542094
Short name T888
Test name
Test status
Simulation time 36186737 ps
CPU time 0.66 seconds
Started Mar 19 12:44:11 PM PDT 24
Finished Mar 19 12:44:12 PM PDT 24
Peak memory 194928 kb
Host smart-461d99a7-06a3-4428-9462-d29482003707
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208542094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.4208542094
Directory /workspace/33.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.1971177498
Short name T925
Test name
Test status
Simulation time 17997810 ps
CPU time 0.63 seconds
Started Mar 19 12:44:05 PM PDT 24
Finished Mar 19 12:44:06 PM PDT 24
Peak memory 194924 kb
Host smart-efb3c3e5-f2c3-4d23-8ebb-1726784bc379
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971177498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.1971177498
Directory /workspace/34.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.1657144198
Short name T929
Test name
Test status
Simulation time 55667123 ps
CPU time 0.57 seconds
Started Mar 19 12:44:01 PM PDT 24
Finished Mar 19 12:44:03 PM PDT 24
Peak memory 194820 kb
Host smart-e41a3dfd-dea9-4719-bfb8-514409104153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657144198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.1657144198
Directory /workspace/35.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.10972723
Short name T934
Test name
Test status
Simulation time 23321302 ps
CPU time 0.61 seconds
Started Mar 19 12:43:59 PM PDT 24
Finished Mar 19 12:44:01 PM PDT 24
Peak memory 194924 kb
Host smart-0d0fb9fe-eeb4-4e2b-b726-a690cf282cc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10972723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.10972723
Directory /workspace/36.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.2559122889
Short name T954
Test name
Test status
Simulation time 42270353 ps
CPU time 0.58 seconds
Started Mar 19 12:44:02 PM PDT 24
Finished Mar 19 12:44:03 PM PDT 24
Peak memory 194884 kb
Host smart-6d6c6dff-655d-4fae-af1c-bfdf8c50dfe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559122889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.2559122889
Directory /workspace/37.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.2965874585
Short name T891
Test name
Test status
Simulation time 40900329 ps
CPU time 0.59 seconds
Started Mar 19 12:44:00 PM PDT 24
Finished Mar 19 12:44:02 PM PDT 24
Peak memory 194868 kb
Host smart-955f6e8a-4bfb-468b-a47b-75ab8ba45943
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965874585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.2965874585
Directory /workspace/38.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2273603383
Short name T890
Test name
Test status
Simulation time 93747357 ps
CPU time 0.61 seconds
Started Mar 19 12:44:05 PM PDT 24
Finished Mar 19 12:44:06 PM PDT 24
Peak memory 194896 kb
Host smart-b5930cff-773c-4a23-922f-a8402bd9a6bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273603383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.2273603383
Directory /workspace/39.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.54737714
Short name T977
Test name
Test status
Simulation time 27236276 ps
CPU time 1.03 seconds
Started Mar 19 12:43:47 PM PDT 24
Finished Mar 19 12:43:49 PM PDT 24
Peak memory 194888 kb
Host smart-9153adc5-7c86-41f3-a138-299227241481
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54737714 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.54737714
Directory /workspace/4.pwrmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.1282540872
Short name T96
Test name
Test status
Simulation time 275063034 ps
CPU time 2.7 seconds
Started Mar 19 12:43:54 PM PDT 24
Finished Mar 19 12:43:58 PM PDT 24
Peak memory 195080 kb
Host smart-0a64d7d1-eac8-445f-9c3d-1791e706d411
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282540872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.1
282540872
Directory /workspace/4.pwrmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.1291650570
Short name T55
Test name
Test status
Simulation time 126921847 ps
CPU time 0.68 seconds
Started Mar 19 12:43:58 PM PDT 24
Finished Mar 19 12:43:59 PM PDT 24
Peak memory 197152 kb
Host smart-f1067114-0576-4c19-9c76-e8ed681c15e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291650570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.1
291650570
Directory /workspace/4.pwrmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1010845457
Short name T65
Test name
Test status
Simulation time 57000422 ps
CPU time 0.91 seconds
Started Mar 19 12:44:09 PM PDT 24
Finished Mar 19 12:44:10 PM PDT 24
Peak memory 195060 kb
Host smart-662bfbea-1508-459b-9836-efe3b0bc5823
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010845457 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.1010845457
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.3290680888
Short name T910
Test name
Test status
Simulation time 56355868 ps
CPU time 0.67 seconds
Started Mar 19 12:43:57 PM PDT 24
Finished Mar 19 12:43:57 PM PDT 24
Peak memory 197124 kb
Host smart-fbdbdd00-c5d7-4663-bd52-ffc2623ddf27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290680888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.3290680888
Directory /workspace/4.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.984453672
Short name T139
Test name
Test status
Simulation time 33296541 ps
CPU time 0.6 seconds
Started Mar 19 12:43:57 PM PDT 24
Finished Mar 19 12:43:58 PM PDT 24
Peak memory 194908 kb
Host smart-e330370c-765a-4359-9bd0-c2810d961dbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984453672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.984453672
Directory /workspace/4.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3737849005
Short name T933
Test name
Test status
Simulation time 108506005 ps
CPU time 0.85 seconds
Started Mar 19 12:43:48 PM PDT 24
Finished Mar 19 12:43:49 PM PDT 24
Peak memory 198144 kb
Host smart-01c16630-e2fc-4134-bedd-b88f798622c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737849005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.3737849005
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.1381062344
Short name T979
Test name
Test status
Simulation time 42824214 ps
CPU time 1.86 seconds
Started Mar 19 12:44:01 PM PDT 24
Finished Mar 19 12:44:04 PM PDT 24
Peak memory 196040 kb
Host smart-8485334e-2555-4ab6-b420-b69bbc2f9dc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381062344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.1381062344
Directory /workspace/4.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2126116364
Short name T57
Test name
Test status
Simulation time 341522516 ps
CPU time 1.54 seconds
Started Mar 19 12:43:50 PM PDT 24
Finished Mar 19 12:43:52 PM PDT 24
Peak memory 200320 kb
Host smart-c1407aeb-32f7-48e6-bf24-2a1105a31c6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126116364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err
.2126116364
Directory /workspace/4.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.2965669166
Short name T895
Test name
Test status
Simulation time 24167913 ps
CPU time 0.63 seconds
Started Mar 19 12:43:59 PM PDT 24
Finished Mar 19 12:44:01 PM PDT 24
Peak memory 194960 kb
Host smart-4bcb09e0-8ec0-4794-8b19-eb4b9f724e16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965669166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.2965669166
Directory /workspace/40.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.4202529449
Short name T49
Test name
Test status
Simulation time 34507074 ps
CPU time 0.63 seconds
Started Mar 19 12:43:59 PM PDT 24
Finished Mar 19 12:44:01 PM PDT 24
Peak memory 194900 kb
Host smart-8424ddd1-c76c-421e-a4ab-1fb4099cdfb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202529449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.4202529449
Directory /workspace/41.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.1339263916
Short name T973
Test name
Test status
Simulation time 50779031 ps
CPU time 0.61 seconds
Started Mar 19 12:44:08 PM PDT 24
Finished Mar 19 12:44:09 PM PDT 24
Peak memory 194824 kb
Host smart-fd87908c-8aad-41ee-81b6-2b610af1ceaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339263916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.1339263916
Directory /workspace/42.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.3999148132
Short name T885
Test name
Test status
Simulation time 22013914 ps
CPU time 0.62 seconds
Started Mar 19 12:44:01 PM PDT 24
Finished Mar 19 12:44:03 PM PDT 24
Peak memory 194812 kb
Host smart-96e74832-cd04-490c-9e73-72be6be93352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999148132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.3999148132
Directory /workspace/43.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.2856744696
Short name T887
Test name
Test status
Simulation time 83790072 ps
CPU time 0.62 seconds
Started Mar 19 12:44:10 PM PDT 24
Finished Mar 19 12:44:10 PM PDT 24
Peak memory 194872 kb
Host smart-c6dca0e4-2b03-4d76-adc9-b59819caa431
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856744696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.2856744696
Directory /workspace/44.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.309557372
Short name T889
Test name
Test status
Simulation time 20468605 ps
CPU time 0.63 seconds
Started Mar 19 12:44:06 PM PDT 24
Finished Mar 19 12:44:06 PM PDT 24
Peak memory 194924 kb
Host smart-d5aea42e-8c6d-4f01-9c4d-9a57bfd88017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309557372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.309557372
Directory /workspace/45.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.3226487081
Short name T136
Test name
Test status
Simulation time 33708890 ps
CPU time 0.58 seconds
Started Mar 19 12:44:02 PM PDT 24
Finished Mar 19 12:44:03 PM PDT 24
Peak memory 194884 kb
Host smart-5fea73c7-7f54-440a-8f76-1fa5989c4fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226487081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.3226487081
Directory /workspace/46.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1239789424
Short name T899
Test name
Test status
Simulation time 18450867 ps
CPU time 0.62 seconds
Started Mar 19 12:44:10 PM PDT 24
Finished Mar 19 12:44:10 PM PDT 24
Peak memory 194860 kb
Host smart-f3b6a0ab-f7c1-448f-a775-54bc9fc02855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239789424 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.1239789424
Directory /workspace/47.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.4205189248
Short name T958
Test name
Test status
Simulation time 50456527 ps
CPU time 0.59 seconds
Started Mar 19 12:43:58 PM PDT 24
Finished Mar 19 12:43:59 PM PDT 24
Peak memory 194916 kb
Host smart-9abd63a1-1f80-4b8a-8104-1f769e794c21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205189248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.4205189248
Directory /workspace/48.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.1562203431
Short name T967
Test name
Test status
Simulation time 41551059 ps
CPU time 0.6 seconds
Started Mar 19 12:44:08 PM PDT 24
Finished Mar 19 12:44:08 PM PDT 24
Peak memory 194900 kb
Host smart-ec236e4c-7b09-42a1-a599-8ed0794c2945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562203431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.1562203431
Directory /workspace/49.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3083333658
Short name T944
Test name
Test status
Simulation time 312411244 ps
CPU time 1.14 seconds
Started Mar 19 12:43:58 PM PDT 24
Finished Mar 19 12:44:00 PM PDT 24
Peak memory 197028 kb
Host smart-89f8a8ce-22f2-409f-84a3-b7fd95c82779
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083333658 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.3083333658
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.3798484137
Short name T50
Test name
Test status
Simulation time 18010317 ps
CPU time 0.65 seconds
Started Mar 19 12:43:55 PM PDT 24
Finished Mar 19 12:43:56 PM PDT 24
Peak memory 195000 kb
Host smart-4bf1d79a-6d2a-45d3-81ce-058a042041d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798484137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.3798484137
Directory /workspace/5.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.1972711014
Short name T926
Test name
Test status
Simulation time 54845671 ps
CPU time 0.62 seconds
Started Mar 19 12:43:54 PM PDT 24
Finished Mar 19 12:43:54 PM PDT 24
Peak memory 194836 kb
Host smart-1ec5e0b0-5d8c-40d7-8d46-ea0c9d09615a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972711014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.1972711014
Directory /workspace/5.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.985190640
Short name T978
Test name
Test status
Simulation time 130090834 ps
CPU time 0.7 seconds
Started Mar 19 12:43:58 PM PDT 24
Finished Mar 19 12:44:01 PM PDT 24
Peak memory 194888 kb
Host smart-59b2991b-ce79-465d-a54e-511290a4a785
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985190640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sam
e_csr_outstanding.985190640
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.608248072
Short name T951
Test name
Test status
Simulation time 54968127 ps
CPU time 0.76 seconds
Started Mar 19 12:43:59 PM PDT 24
Finished Mar 19 12:44:01 PM PDT 24
Peak memory 195116 kb
Host smart-1321f238-a561-4f13-82b0-ac61403c74b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608248072 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.608248072
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.3669260860
Short name T963
Test name
Test status
Simulation time 110451706 ps
CPU time 0.65 seconds
Started Mar 19 12:43:57 PM PDT 24
Finished Mar 19 12:43:58 PM PDT 24
Peak memory 194992 kb
Host smart-2ac3e463-e14c-459d-810e-9f2599b6c821
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669260860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.3669260860
Directory /workspace/6.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.578694158
Short name T981
Test name
Test status
Simulation time 43053446 ps
CPU time 0.57 seconds
Started Mar 19 12:43:46 PM PDT 24
Finished Mar 19 12:43:47 PM PDT 24
Peak memory 194920 kb
Host smart-bb59d3cb-9a69-499f-b476-ab463fce5692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578694158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.578694158
Directory /workspace/6.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1599956879
Short name T46
Test name
Test status
Simulation time 45280165 ps
CPU time 0.75 seconds
Started Mar 19 12:43:48 PM PDT 24
Finished Mar 19 12:43:49 PM PDT 24
Peak memory 197020 kb
Host smart-cba0517d-3cb0-4421-a987-f659ce489b81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599956879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa
me_csr_outstanding.1599956879
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.732378058
Short name T985
Test name
Test status
Simulation time 102315797 ps
CPU time 1.28 seconds
Started Mar 19 12:43:50 PM PDT 24
Finished Mar 19 12:43:52 PM PDT 24
Peak memory 196124 kb
Host smart-d895e163-c576-403f-be64-d1cf88f0378f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732378058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.732378058
Directory /workspace/6.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.3837977417
Short name T937
Test name
Test status
Simulation time 189395365 ps
CPU time 1.09 seconds
Started Mar 19 12:43:52 PM PDT 24
Finished Mar 19 12:43:53 PM PDT 24
Peak memory 200280 kb
Host smart-c8f8b06b-c173-4db4-a9aa-cfbd95c6ff95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837977417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.3837977417
Directory /workspace/6.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.1107828275
Short name T966
Test name
Test status
Simulation time 66599185 ps
CPU time 0.73 seconds
Started Mar 19 12:43:51 PM PDT 24
Finished Mar 19 12:43:51 PM PDT 24
Peak memory 195032 kb
Host smart-db5599cc-ebe4-4e62-a5e3-dd705896e7d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107828275 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.1107828275
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.127158953
Short name T921
Test name
Test status
Simulation time 39348911 ps
CPU time 0.59 seconds
Started Mar 19 12:43:48 PM PDT 24
Finished Mar 19 12:43:49 PM PDT 24
Peak memory 194920 kb
Host smart-40af04f5-adbf-4648-bce6-a996e74041dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127158953 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.127158953
Directory /workspace/7.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.53497118
Short name T912
Test name
Test status
Simulation time 17009658 ps
CPU time 0.59 seconds
Started Mar 19 12:43:47 PM PDT 24
Finished Mar 19 12:43:48 PM PDT 24
Peak memory 194896 kb
Host smart-d1144119-9e96-465c-9ca8-6193fe141e46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53497118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.53497118
Directory /workspace/7.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1013680206
Short name T970
Test name
Test status
Simulation time 45862819 ps
CPU time 0.87 seconds
Started Mar 19 12:43:46 PM PDT 24
Finished Mar 19 12:43:48 PM PDT 24
Peak memory 194884 kb
Host smart-bec2319b-f64d-44b0-9b93-d42e3e81b967
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013680206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa
me_csr_outstanding.1013680206
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.2192276824
Short name T56
Test name
Test status
Simulation time 167961043 ps
CPU time 2.25 seconds
Started Mar 19 12:43:58 PM PDT 24
Finished Mar 19 12:44:00 PM PDT 24
Peak memory 197372 kb
Host smart-509cfa83-d4ea-4bab-986a-f2f54011e869
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192276824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.2192276824
Directory /workspace/7.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.1870705692
Short name T37
Test name
Test status
Simulation time 117605233 ps
CPU time 1.06 seconds
Started Mar 19 12:43:52 PM PDT 24
Finished Mar 19 12:43:53 PM PDT 24
Peak memory 200092 kb
Host smart-15c1fde4-6653-4be7-b5ab-cd8cff95ac93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870705692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.1870705692
Directory /workspace/7.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2899253695
Short name T987
Test name
Test status
Simulation time 73739181 ps
CPU time 1.09 seconds
Started Mar 19 12:43:51 PM PDT 24
Finished Mar 19 12:43:52 PM PDT 24
Peak memory 196324 kb
Host smart-9685b71d-8d24-4d58-8ca7-bcb225bf1d95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899253695 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.2899253695
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.4021053157
Short name T903
Test name
Test status
Simulation time 18725413 ps
CPU time 0.69 seconds
Started Mar 19 12:43:48 PM PDT 24
Finished Mar 19 12:43:49 PM PDT 24
Peak memory 196264 kb
Host smart-8f1de587-e57b-4763-8d32-864c8b679a43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021053157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.4021053157
Directory /workspace/8.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.1177544634
Short name T882
Test name
Test status
Simulation time 33693444 ps
CPU time 0.6 seconds
Started Mar 19 12:44:01 PM PDT 24
Finished Mar 19 12:44:03 PM PDT 24
Peak memory 194844 kb
Host smart-44899ba8-5e8f-4981-b7eb-0329cb42e96f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177544634 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.1177544634
Directory /workspace/8.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.2367222549
Short name T974
Test name
Test status
Simulation time 23618003 ps
CPU time 0.74 seconds
Started Mar 19 12:43:57 PM PDT 24
Finished Mar 19 12:43:58 PM PDT 24
Peak memory 197284 kb
Host smart-8d7aa741-6af6-4096-869f-854a058ebc50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367222549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sa
me_csr_outstanding.2367222549
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.736110344
Short name T991
Test name
Test status
Simulation time 28116364 ps
CPU time 1.22 seconds
Started Mar 19 12:43:47 PM PDT 24
Finished Mar 19 12:43:49 PM PDT 24
Peak memory 195240 kb
Host smart-1bdc347f-9de5-4daf-8fea-4893fd205edd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736110344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.736110344
Directory /workspace/8.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.472605567
Short name T902
Test name
Test status
Simulation time 125811148 ps
CPU time 1.07 seconds
Started Mar 19 12:43:57 PM PDT 24
Finished Mar 19 12:43:59 PM PDT 24
Peak memory 200140 kb
Host smart-e7260b23-e8dd-4c3b-8629-f20324578347
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472605567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err.
472605567
Directory /workspace/8.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3355657544
Short name T939
Test name
Test status
Simulation time 46455972 ps
CPU time 0.7 seconds
Started Mar 19 12:43:48 PM PDT 24
Finished Mar 19 12:43:49 PM PDT 24
Peak memory 199096 kb
Host smart-5b7b9d1d-cd15-477c-a339-a2824b9b40cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355657544 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.3355657544
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.2727178681
Short name T964
Test name
Test status
Simulation time 22591355 ps
CPU time 0.67 seconds
Started Mar 19 12:43:51 PM PDT 24
Finished Mar 19 12:43:52 PM PDT 24
Peak memory 196152 kb
Host smart-d5afad77-f9a0-491d-b562-500aa7849530
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727178681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.2727178681
Directory /workspace/9.pwrmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.2178568651
Short name T137
Test name
Test status
Simulation time 18227541 ps
CPU time 0.62 seconds
Started Mar 19 12:43:47 PM PDT 24
Finished Mar 19 12:43:48 PM PDT 24
Peak memory 194884 kb
Host smart-ac1ae72a-68b6-409e-8ab9-f68be95d612d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178568651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.2178568651
Directory /workspace/9.pwrmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.469065196
Short name T976
Test name
Test status
Simulation time 63640659 ps
CPU time 0.9 seconds
Started Mar 19 12:43:49 PM PDT 24
Finished Mar 19 12:43:50 PM PDT 24
Peak memory 198220 kb
Host smart-8f552794-373a-43d8-945b-07164aa18d6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469065196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sam
e_csr_outstanding.469065196
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.2866358939
Short name T41
Test name
Test status
Simulation time 52240256 ps
CPU time 1.35 seconds
Started Mar 19 12:43:50 PM PDT 24
Finished Mar 19 12:43:51 PM PDT 24
Peak memory 195208 kb
Host smart-6a3c45b3-bb32-43ef-ba98-191e27bc8518
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866358939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.2866358939
Directory /workspace/9.pwrmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.1431254788
Short name T948
Test name
Test status
Simulation time 253852842 ps
CPU time 1.55 seconds
Started Mar 19 12:43:57 PM PDT 24
Finished Mar 19 12:43:59 PM PDT 24
Peak memory 200316 kb
Host smart-63186452-9634-45d3-acba-a852992df0c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431254788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err
.1431254788
Directory /workspace/9.pwrmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.2308527692
Short name T373
Test name
Test status
Simulation time 18871524 ps
CPU time 0.62 seconds
Started Mar 19 03:06:27 PM PDT 24
Finished Mar 19 03:06:27 PM PDT 24
Peak memory 197472 kb
Host smart-fda287c8-17ea-4a14-9d58-34209b511e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308527692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.2308527692
Directory /workspace/0.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.186246698
Short name T115
Test name
Test status
Simulation time 65813742 ps
CPU time 0.76 seconds
Started Mar 19 03:06:08 PM PDT 24
Finished Mar 19 03:06:09 PM PDT 24
Peak memory 198528 kb
Host smart-9af4fe6b-8afc-473e-8e96-71627dccb7a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186246698 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disab
le_rom_integrity_check.186246698
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.1581845636
Short name T357
Test name
Test status
Simulation time 29767102 ps
CPU time 0.67 seconds
Started Mar 19 03:06:04 PM PDT 24
Finished Mar 19 03:06:04 PM PDT 24
Peak memory 197440 kb
Host smart-60ff4573-3a93-484d-a476-d9ecba91a595
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581845636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.1581845636
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.539972070
Short name T436
Test name
Test status
Simulation time 313314284 ps
CPU time 0.97 seconds
Started Mar 19 03:06:07 PM PDT 24
Finished Mar 19 03:06:08 PM PDT 24
Peak memory 197540 kb
Host smart-42a80659-5b15-4840-8dd3-55b1c7117246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539972070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.539972070
Directory /workspace/0.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/0.pwrmgr_glitch.3658146088
Short name T689
Test name
Test status
Simulation time 48305489 ps
CPU time 0.6 seconds
Started Mar 19 03:06:12 PM PDT 24
Finished Mar 19 03:06:13 PM PDT 24
Peak memory 197512 kb
Host smart-51e49283-12b9-4b05-84d9-9c7ae8a88e09
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658146088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.3658146088
Directory /workspace/0.pwrmgr_glitch/latest

Test location /workspace/coverage/default/0.pwrmgr_global_esc.3468465893
Short name T144
Test name
Test status
Simulation time 59019170 ps
CPU time 0.63 seconds
Started Mar 19 03:06:20 PM PDT 24
Finished Mar 19 03:06:21 PM PDT 24
Peak memory 197512 kb
Host smart-f3e9f444-8c34-4ea5-94a4-fc33170e06d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468465893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.3468465893
Directory /workspace/0.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.2933383018
Short name T482
Test name
Test status
Simulation time 136902971 ps
CPU time 0.66 seconds
Started Mar 19 03:06:09 PM PDT 24
Finished Mar 19 03:06:10 PM PDT 24
Peak memory 200800 kb
Host smart-42275856-e06d-4890-be98-806de9ec38eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933383018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invali
d.2933383018
Directory /workspace/0.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_reset.2256968484
Short name T872
Test name
Test status
Simulation time 83960790 ps
CPU time 0.82 seconds
Started Mar 19 03:06:03 PM PDT 24
Finished Mar 19 03:06:04 PM PDT 24
Peak memory 198624 kb
Host smart-b04d7fae-07b2-4b67-b61a-fbb7c1e5a889
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256968484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.2256968484
Directory /workspace/0.pwrmgr_reset/latest

Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.2875362589
Short name T437
Test name
Test status
Simulation time 164264727 ps
CPU time 0.85 seconds
Started Mar 19 03:06:20 PM PDT 24
Finished Mar 19 03:06:21 PM PDT 24
Peak memory 208872 kb
Host smart-34be431f-fa4d-41ab-aaae-e29530e38db4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875362589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.2875362589
Directory /workspace/0.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.1462730603
Short name T643
Test name
Test status
Simulation time 203622080 ps
CPU time 0.84 seconds
Started Mar 19 03:06:27 PM PDT 24
Finished Mar 19 03:06:28 PM PDT 24
Peak memory 199172 kb
Host smart-5785e3ae-0a72-4156-9d5a-adbddaeee913
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462730603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_c
m_ctrl_config_regwen.1462730603
Directory /workspace/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2911863097
Short name T414
Test name
Test status
Simulation time 818564234 ps
CPU time 3.08 seconds
Started Mar 19 03:06:14 PM PDT 24
Finished Mar 19 03:06:17 PM PDT 24
Peak memory 200656 kb
Host smart-e50231db-f97b-490b-9507-b7ae8d22195f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911863097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2911863097
Directory /workspace/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.762510539
Short name T172
Test name
Test status
Simulation time 823153929 ps
CPU time 2.53 seconds
Started Mar 19 03:06:16 PM PDT 24
Finished Mar 19 03:06:19 PM PDT 24
Peak memory 200612 kb
Host smart-179d0a34-9a22-42ef-987e-1e176df86bd8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762510539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.762510539
Directory /workspace/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2641481654
Short name T766
Test name
Test status
Simulation time 146554434 ps
CPU time 0.85 seconds
Started Mar 19 03:06:04 PM PDT 24
Finished Mar 19 03:06:05 PM PDT 24
Peak memory 198508 kb
Host smart-2a8546ae-ba28-4c51-8a09-2e5501ba06e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641481654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2641481654
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/0.pwrmgr_smoke.4140283568
Short name T347
Test name
Test status
Simulation time 28703454 ps
CPU time 0.72 seconds
Started Mar 19 03:06:14 PM PDT 24
Finished Mar 19 03:06:21 PM PDT 24
Peak memory 198716 kb
Host smart-20c6f432-8b38-43af-9059-fb138cb1a85a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140283568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.4140283568
Directory /workspace/0.pwrmgr_smoke/latest

Test location /workspace/coverage/default/0.pwrmgr_stress_all.3170768983
Short name T842
Test name
Test status
Simulation time 276456125 ps
CPU time 1.38 seconds
Started Mar 19 03:06:09 PM PDT 24
Finished Mar 19 03:06:11 PM PDT 24
Peak memory 200580 kb
Host smart-7ea91c89-1b56-428f-bf29-ba3ad0badb3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170768983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.3170768983
Directory /workspace/0.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/0.pwrmgr_wakeup_reset.4161526148
Short name T162
Test name
Test status
Simulation time 106881529 ps
CPU time 0.91 seconds
Started Mar 19 03:06:08 PM PDT 24
Finished Mar 19 03:06:09 PM PDT 24
Peak memory 198712 kb
Host smart-c8040fb3-5d70-489e-9040-c9601149d4c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161526148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.4161526148
Directory /workspace/0.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.483339091
Short name T878
Test name
Test status
Simulation time 22495913 ps
CPU time 0.66 seconds
Started Mar 19 03:06:20 PM PDT 24
Finished Mar 19 03:06:21 PM PDT 24
Peak memory 197952 kb
Host smart-fdbcac17-8d90-4c7e-9067-22dfee815e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483339091 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.483339091
Directory /workspace/1.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.2583705147
Short name T845
Test name
Test status
Simulation time 29560324 ps
CPU time 0.63 seconds
Started Mar 19 03:06:26 PM PDT 24
Finished Mar 19 03:06:27 PM PDT 24
Peak memory 196764 kb
Host smart-90533686-ae52-4841-a63d-262da410c6c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583705147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_
malfunc.2583705147
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.2529648367
Short name T504
Test name
Test status
Simulation time 161223883 ps
CPU time 1 seconds
Started Mar 19 03:06:10 PM PDT 24
Finished Mar 19 03:06:21 PM PDT 24
Peak memory 197668 kb
Host smart-e396a555-5209-4643-9290-16683740bcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529648367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.2529648367
Directory /workspace/1.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/1.pwrmgr_glitch.4016052791
Short name T457
Test name
Test status
Simulation time 79468300 ps
CPU time 0.62 seconds
Started Mar 19 03:06:03 PM PDT 24
Finished Mar 19 03:06:04 PM PDT 24
Peak memory 197564 kb
Host smart-9a66ed58-26bc-486b-a468-d525d725f316
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016052791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.4016052791
Directory /workspace/1.pwrmgr_glitch/latest

Test location /workspace/coverage/default/1.pwrmgr_global_esc.4072549104
Short name T399
Test name
Test status
Simulation time 34434357 ps
CPU time 0.61 seconds
Started Mar 19 03:06:29 PM PDT 24
Finished Mar 19 03:06:30 PM PDT 24
Peak memory 197508 kb
Host smart-a2ad985a-06a9-4f97-92ba-78666158f12c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072549104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.4072549104
Directory /workspace/1.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.1987519895
Short name T830
Test name
Test status
Simulation time 69778917 ps
CPU time 0.7 seconds
Started Mar 19 03:06:07 PM PDT 24
Finished Mar 19 03:06:08 PM PDT 24
Peak memory 200812 kb
Host smart-d518a884-0496-495f-87d7-0edff8674a1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987519895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.1987519895
Directory /workspace/1.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.2611298231
Short name T63
Test name
Test status
Simulation time 314317246 ps
CPU time 0.8 seconds
Started Mar 19 03:06:14 PM PDT 24
Finished Mar 19 03:06:15 PM PDT 24
Peak memory 197944 kb
Host smart-7f4de99f-9f7b-4fca-b269-611de2b5dfe5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611298231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wa
keup_race.2611298231
Directory /workspace/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/1.pwrmgr_reset.2594866933
Short name T716
Test name
Test status
Simulation time 133838520 ps
CPU time 0.82 seconds
Started Mar 19 03:06:36 PM PDT 24
Finished Mar 19 03:06:37 PM PDT 24
Peak memory 198092 kb
Host smart-18664e11-95fd-4b2c-ae1a-6b9c676c5274
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594866933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.2594866933
Directory /workspace/1.pwrmgr_reset/latest

Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.2015277964
Short name T498
Test name
Test status
Simulation time 169446633 ps
CPU time 0.76 seconds
Started Mar 19 03:06:17 PM PDT 24
Finished Mar 19 03:06:18 PM PDT 24
Peak memory 208892 kb
Host smart-6d779d6e-e4db-4ea7-ac73-7b9850b609a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015277964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.2015277964
Directory /workspace/1.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm.2924153563
Short name T24
Test name
Test status
Simulation time 663762766 ps
CPU time 1.86 seconds
Started Mar 19 03:06:31 PM PDT 24
Finished Mar 19 03:06:33 PM PDT 24
Peak memory 217548 kb
Host smart-651ea8ac-fd1e-4efd-96f2-9d2b395407ec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924153563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.2924153563
Directory /workspace/1.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2899305134
Short name T496
Test name
Test status
Simulation time 834136008 ps
CPU time 2.31 seconds
Started Mar 19 03:06:14 PM PDT 24
Finished Mar 19 03:06:17 PM PDT 24
Peak memory 200476 kb
Host smart-f6cd6f7f-589b-4117-97c0-e4788df01a03
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899305134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2899305134
Directory /workspace/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3465032450
Short name T585
Test name
Test status
Simulation time 1722138334 ps
CPU time 1.87 seconds
Started Mar 19 03:06:27 PM PDT 24
Finished Mar 19 03:06:29 PM PDT 24
Peak memory 200644 kb
Host smart-cca0ace9-11a2-4f1c-941e-0ba0f35d2ef4
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465032450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3465032450
Directory /workspace/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.2284539046
Short name T216
Test name
Test status
Simulation time 166291070 ps
CPU time 0.87 seconds
Started Mar 19 03:06:06 PM PDT 24
Finished Mar 19 03:06:06 PM PDT 24
Peak memory 198740 kb
Host smart-cb50727e-1409-417c-8dca-af3c752a7f08
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284539046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2284539046
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/1.pwrmgr_smoke.1767479947
Short name T857
Test name
Test status
Simulation time 32615565 ps
CPU time 0.67 seconds
Started Mar 19 03:06:18 PM PDT 24
Finished Mar 19 03:06:19 PM PDT 24
Peak memory 198744 kb
Host smart-57dc5d96-cdf2-42c0-bc39-93859b8d1905
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767479947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.1767479947
Directory /workspace/1.pwrmgr_smoke/latest

Test location /workspace/coverage/default/1.pwrmgr_stress_all.2891072821
Short name T837
Test name
Test status
Simulation time 1663675386 ps
CPU time 3.87 seconds
Started Mar 19 03:06:15 PM PDT 24
Finished Mar 19 03:06:19 PM PDT 24
Peak memory 200628 kb
Host smart-81439bd8-3d2b-4f7e-94ba-a9cc9069b7e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891072821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.2891072821
Directory /workspace/1.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup.423620144
Short name T265
Test name
Test status
Simulation time 229334269 ps
CPU time 0.9 seconds
Started Mar 19 03:06:08 PM PDT 24
Finished Mar 19 03:06:09 PM PDT 24
Peak memory 197924 kb
Host smart-41cb31b4-aa1a-48e7-ab22-3333c7f8ae91
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423620144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.423620144
Directory /workspace/1.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/1.pwrmgr_wakeup_reset.3886370916
Short name T835
Test name
Test status
Simulation time 447317853 ps
CPU time 1.15 seconds
Started Mar 19 03:06:04 PM PDT 24
Finished Mar 19 03:06:05 PM PDT 24
Peak memory 200580 kb
Host smart-3cd64689-a67c-45fb-ab15-8242113870c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886370916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.3886370916
Directory /workspace/1.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.2976089642
Short name T729
Test name
Test status
Simulation time 52321051 ps
CPU time 0.67 seconds
Started Mar 19 03:06:43 PM PDT 24
Finished Mar 19 03:06:44 PM PDT 24
Peak memory 197972 kb
Host smart-47961e28-eab8-47a5-bed3-2ee743b7b1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976089642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.2976089642
Directory /workspace/10.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.2483858392
Short name T402
Test name
Test status
Simulation time 88172383 ps
CPU time 0.74 seconds
Started Mar 19 03:06:42 PM PDT 24
Finished Mar 19 03:06:43 PM PDT 24
Peak memory 198572 kb
Host smart-85241476-ba3a-493c-804f-b4b1a84f226e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483858392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.2483858392
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.3440994050
Short name T376
Test name
Test status
Simulation time 31384663 ps
CPU time 0.68 seconds
Started Mar 19 03:06:53 PM PDT 24
Finished Mar 19 03:06:54 PM PDT 24
Peak memory 197496 kb
Host smart-dfbea6c9-c9c8-4e79-8cf3-950f46551357
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440994050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.3440994050
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.544713335
Short name T678
Test name
Test status
Simulation time 344827217 ps
CPU time 0.95 seconds
Started Mar 19 03:06:48 PM PDT 24
Finished Mar 19 03:06:50 PM PDT 24
Peak memory 197532 kb
Host smart-d3a6d698-73a6-400c-abb9-b1929d8f57d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544713335 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.544713335
Directory /workspace/10.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/10.pwrmgr_glitch.4116057201
Short name T739
Test name
Test status
Simulation time 60711884 ps
CPU time 0.6 seconds
Started Mar 19 03:06:48 PM PDT 24
Finished Mar 19 03:06:50 PM PDT 24
Peak memory 197512 kb
Host smart-6237fb25-3842-447e-837d-e152633bd8aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116057201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.4116057201
Directory /workspace/10.pwrmgr_glitch/latest

Test location /workspace/coverage/default/10.pwrmgr_global_esc.3705487893
Short name T267
Test name
Test status
Simulation time 45451513 ps
CPU time 0.68 seconds
Started Mar 19 03:06:36 PM PDT 24
Finished Mar 19 03:06:37 PM PDT 24
Peak memory 197816 kb
Host smart-63c19cca-4fee-41e3-b02f-7155d7dbb17a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705487893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.3705487893
Directory /workspace/10.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.1055920944
Short name T262
Test name
Test status
Simulation time 53307606 ps
CPU time 0.68 seconds
Started Mar 19 03:06:51 PM PDT 24
Finished Mar 19 03:06:52 PM PDT 24
Peak memory 200808 kb
Host smart-ce00f8f8-71a4-4924-9ebf-23665c5bbd9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055920944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_inval
id.1055920944
Directory /workspace/10.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_reset.2457552880
Short name T501
Test name
Test status
Simulation time 73105523 ps
CPU time 0.7 seconds
Started Mar 19 03:06:48 PM PDT 24
Finished Mar 19 03:06:49 PM PDT 24
Peak memory 198548 kb
Host smart-a28905b2-da13-42b1-aaaf-522a68fba625
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457552880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.2457552880
Directory /workspace/10.pwrmgr_reset/latest

Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.1114001558
Short name T681
Test name
Test status
Simulation time 100272994 ps
CPU time 1.07 seconds
Started Mar 19 03:06:46 PM PDT 24
Finished Mar 19 03:06:48 PM PDT 24
Peak memory 208960 kb
Host smart-67903624-4c87-4cb8-971e-ea8b161272c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114001558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.1114001558
Directory /workspace/10.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.3213352462
Short name T725
Test name
Test status
Simulation time 428761582 ps
CPU time 0.88 seconds
Started Mar 19 03:06:46 PM PDT 24
Finished Mar 19 03:06:48 PM PDT 24
Peak memory 199364 kb
Host smart-a7107611-17c5-4107-8550-ed56e274b46f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213352462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_
cm_ctrl_config_regwen.3213352462
Directory /workspace/10.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3782873396
Short name T680
Test name
Test status
Simulation time 739306494 ps
CPU time 3.02 seconds
Started Mar 19 03:06:37 PM PDT 24
Finished Mar 19 03:06:40 PM PDT 24
Peak memory 200600 kb
Host smart-48d860e8-535f-4b80-801d-17563cc5eda1
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782873396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3782873396
Directory /workspace/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3751902124
Short name T219
Test name
Test status
Simulation time 1044779282 ps
CPU time 2.6 seconds
Started Mar 19 03:06:45 PM PDT 24
Finished Mar 19 03:06:48 PM PDT 24
Peak memory 200572 kb
Host smart-b0120d70-530c-4e99-80d4-1b2966ba2f6d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751902124 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3751902124
Directory /workspace/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.384449314
Short name T649
Test name
Test status
Simulation time 51502113 ps
CPU time 0.88 seconds
Started Mar 19 03:06:44 PM PDT 24
Finished Mar 19 03:06:46 PM PDT 24
Peak memory 198816 kb
Host smart-5df8b8ba-3c2f-42d9-a798-00a94519e90d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384449314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig_
mubi.384449314
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/10.pwrmgr_smoke.2822803467
Short name T386
Test name
Test status
Simulation time 29871920 ps
CPU time 0.7 seconds
Started Mar 19 03:06:49 PM PDT 24
Finished Mar 19 03:06:50 PM PDT 24
Peak memory 197988 kb
Host smart-ed56b5bc-db23-4e5d-ba3a-dd7b427eec38
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822803467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.2822803467
Directory /workspace/10.pwrmgr_smoke/latest

Test location /workspace/coverage/default/10.pwrmgr_stress_all.300761015
Short name T307
Test name
Test status
Simulation time 3515299002 ps
CPU time 1.91 seconds
Started Mar 19 03:06:50 PM PDT 24
Finished Mar 19 03:06:52 PM PDT 24
Peak memory 200720 kb
Host smart-cd334f0c-0f90-412f-92a4-c3b7d3d1c88a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300761015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.300761015
Directory /workspace/10.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/10.pwrmgr_wakeup_reset.2929890727
Short name T746
Test name
Test status
Simulation time 433503684 ps
CPU time 1.12 seconds
Started Mar 19 03:06:40 PM PDT 24
Finished Mar 19 03:06:41 PM PDT 24
Peak memory 200548 kb
Host smart-1d1fe3c2-ebfa-42e3-a2d2-21ce326c9018
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929890727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.2929890727
Directory /workspace/10.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.27466088
Short name T813
Test name
Test status
Simulation time 35391433 ps
CPU time 0.83 seconds
Started Mar 19 03:06:55 PM PDT 24
Finished Mar 19 03:06:56 PM PDT 24
Peak memory 199324 kb
Host smart-ffb83a5c-cad0-4864-9038-413ab5283ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27466088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.27466088
Directory /workspace/11.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.3414468459
Short name T133
Test name
Test status
Simulation time 63231581 ps
CPU time 0.75 seconds
Started Mar 19 03:06:56 PM PDT 24
Finished Mar 19 03:06:57 PM PDT 24
Peak memory 198568 kb
Host smart-dda88dfc-9c1a-4756-81ad-5b8032506910
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414468459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_dis
able_rom_integrity_check.3414468459
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.938207777
Short name T506
Test name
Test status
Simulation time 160533603 ps
CPU time 0.96 seconds
Started Mar 19 03:06:46 PM PDT 24
Finished Mar 19 03:06:48 PM PDT 24
Peak memory 197532 kb
Host smart-ad632161-3770-494f-9d6f-2322251899bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938207777 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.938207777
Directory /workspace/11.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/11.pwrmgr_glitch.327068467
Short name T502
Test name
Test status
Simulation time 65499121 ps
CPU time 0.69 seconds
Started Mar 19 03:06:59 PM PDT 24
Finished Mar 19 03:07:00 PM PDT 24
Peak memory 196756 kb
Host smart-fcc942ce-3506-47bf-86b8-f52d43308ee7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327068467 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.327068467
Directory /workspace/11.pwrmgr_glitch/latest

Test location /workspace/coverage/default/11.pwrmgr_global_esc.1172327643
Short name T541
Test name
Test status
Simulation time 63386197 ps
CPU time 0.65 seconds
Started Mar 19 03:06:48 PM PDT 24
Finished Mar 19 03:06:49 PM PDT 24
Peak memory 197512 kb
Host smart-b27c2c0e-3323-4821-9675-f4ab57fd25bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172327643 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.1172327643
Directory /workspace/11.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.3294903521
Short name T856
Test name
Test status
Simulation time 45770605 ps
CPU time 0.71 seconds
Started Mar 19 03:06:54 PM PDT 24
Finished Mar 19 03:06:55 PM PDT 24
Peak memory 200628 kb
Host smart-1f964d30-03f5-4db4-8776-0d6aae0ec88b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294903521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_inval
id.3294903521
Directory /workspace/11.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_reset.2108753673
Short name T332
Test name
Test status
Simulation time 33747156 ps
CPU time 0.68 seconds
Started Mar 19 03:06:44 PM PDT 24
Finished Mar 19 03:06:44 PM PDT 24
Peak memory 197896 kb
Host smart-9e514613-fb69-4c8b-bef1-0be17c700713
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108753673 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.2108753673
Directory /workspace/11.pwrmgr_reset/latest

Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.2397383417
Short name T701
Test name
Test status
Simulation time 184061174 ps
CPU time 0.89 seconds
Started Mar 19 03:06:46 PM PDT 24
Finished Mar 19 03:06:48 PM PDT 24
Peak memory 208856 kb
Host smart-7c69c34b-d9fd-453f-be96-1522b7f62483
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397383417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.2397383417
Directory /workspace/11.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3159659197
Short name T603
Test name
Test status
Simulation time 795646719 ps
CPU time 3 seconds
Started Mar 19 03:06:47 PM PDT 24
Finished Mar 19 03:06:50 PM PDT 24
Peak memory 200660 kb
Host smart-b34a7eb3-8aa2-4736-815b-0cedd27ab0e6
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159659197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3159659197
Directory /workspace/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2717957224
Short name T163
Test name
Test status
Simulation time 1083784496 ps
CPU time 2.55 seconds
Started Mar 19 03:07:04 PM PDT 24
Finished Mar 19 03:07:12 PM PDT 24
Peak memory 200716 kb
Host smart-0bebb600-df3f-41cc-906f-e58748588142
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717957224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2717957224
Directory /workspace/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.2981178312
Short name T220
Test name
Test status
Simulation time 144183895 ps
CPU time 0.87 seconds
Started Mar 19 03:06:50 PM PDT 24
Finished Mar 19 03:06:51 PM PDT 24
Peak memory 198668 kb
Host smart-f7597b37-4043-4be9-824e-addaeb1023e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981178312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2981178312
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/11.pwrmgr_smoke.3863334628
Short name T535
Test name
Test status
Simulation time 30246972 ps
CPU time 0.67 seconds
Started Mar 19 03:06:39 PM PDT 24
Finished Mar 19 03:06:40 PM PDT 24
Peak memory 198724 kb
Host smart-0d4e5c2c-76a7-44b0-a274-1cbca3327aa7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863334628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.3863334628
Directory /workspace/11.pwrmgr_smoke/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup.1396330825
Short name T602
Test name
Test status
Simulation time 216011061 ps
CPU time 0.85 seconds
Started Mar 19 03:06:48 PM PDT 24
Finished Mar 19 03:06:50 PM PDT 24
Peak memory 198980 kb
Host smart-9bb49fb0-9ee1-4756-a18e-0d9120864b2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396330825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.1396330825
Directory /workspace/11.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/11.pwrmgr_wakeup_reset.888110073
Short name T581
Test name
Test status
Simulation time 224849078 ps
CPU time 1.15 seconds
Started Mar 19 03:06:48 PM PDT 24
Finished Mar 19 03:06:50 PM PDT 24
Peak memory 199324 kb
Host smart-334ad387-bec1-4e61-beb2-ddb41f9c5fcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888110073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.888110073
Directory /workspace/11.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.2756716478
Short name T213
Test name
Test status
Simulation time 37475484 ps
CPU time 0.64 seconds
Started Mar 19 03:06:47 PM PDT 24
Finished Mar 19 03:06:48 PM PDT 24
Peak memory 197980 kb
Host smart-ed0f9782-b685-490d-96e0-28622fdc4ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756716478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.2756716478
Directory /workspace/12.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.4085675374
Short name T454
Test name
Test status
Simulation time 79908156 ps
CPU time 0.68 seconds
Started Mar 19 03:06:56 PM PDT 24
Finished Mar 19 03:06:58 PM PDT 24
Peak memory 198184 kb
Host smart-c2cc8c1a-94e0-4fdf-96c5-116221a2b25d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085675374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.4085675374
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.1723998539
Short name T690
Test name
Test status
Simulation time 30993263 ps
CPU time 0.62 seconds
Started Mar 19 03:06:43 PM PDT 24
Finished Mar 19 03:06:44 PM PDT 24
Peak memory 197432 kb
Host smart-d178535f-d2f4-4ed1-960d-d3cc4cac8556
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723998539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.1723998539
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.2960328024
Short name T876
Test name
Test status
Simulation time 320008122 ps
CPU time 0.93 seconds
Started Mar 19 03:06:50 PM PDT 24
Finished Mar 19 03:06:52 PM PDT 24
Peak memory 197472 kb
Host smart-0f86b195-40b3-4bee-90ce-117ccc2ad09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960328024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.2960328024
Directory /workspace/12.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/12.pwrmgr_global_esc.1486109841
Short name T255
Test name
Test status
Simulation time 21844940 ps
CPU time 0.61 seconds
Started Mar 19 03:06:50 PM PDT 24
Finished Mar 19 03:06:51 PM PDT 24
Peak memory 197456 kb
Host smart-597b8be0-3e42-439a-a9bf-16b1def7b156
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486109841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.1486109841
Directory /workspace/12.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.3811822151
Short name T362
Test name
Test status
Simulation time 43071110 ps
CPU time 0.73 seconds
Started Mar 19 03:06:48 PM PDT 24
Finished Mar 19 03:06:49 PM PDT 24
Peak memory 200820 kb
Host smart-fffa90e5-f26c-4258-a7ff-cccaa9176f33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811822151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.3811822151
Directory /workspace/12.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_lowpower_wakeup_race.1501050560
Short name T62
Test name
Test status
Simulation time 120119958 ps
CPU time 0.76 seconds
Started Mar 19 03:06:45 PM PDT 24
Finished Mar 19 03:06:46 PM PDT 24
Peak memory 197880 kb
Host smart-4463ac7c-1fce-4ba1-bec3-2bdf1939c7fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501050560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_w
akeup_race.1501050560
Directory /workspace/12.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/12.pwrmgr_reset.2737678383
Short name T339
Test name
Test status
Simulation time 56546721 ps
CPU time 0.73 seconds
Started Mar 19 03:06:52 PM PDT 24
Finished Mar 19 03:06:53 PM PDT 24
Peak memory 198512 kb
Host smart-cfb794fc-b870-4003-8704-92ca20128b3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737678383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.2737678383
Directory /workspace/12.pwrmgr_reset/latest

Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.4073511927
Short name T617
Test name
Test status
Simulation time 121587869 ps
CPU time 0.83 seconds
Started Mar 19 03:06:45 PM PDT 24
Finished Mar 19 03:06:46 PM PDT 24
Peak memory 208884 kb
Host smart-c0f14fc7-24ec-4ebb-9a2f-61a17eca846e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073511927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.4073511927
Directory /workspace/12.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.4063031946
Short name T867
Test name
Test status
Simulation time 59950085 ps
CPU time 0.82 seconds
Started Mar 19 03:06:38 PM PDT 24
Finished Mar 19 03:06:39 PM PDT 24
Peak memory 198524 kb
Host smart-f9d69ba9-cfff-488c-9a25-2b563df42310
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063031946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_
cm_ctrl_config_regwen.4063031946
Directory /workspace/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2507801947
Short name T495
Test name
Test status
Simulation time 1174017726 ps
CPU time 2.23 seconds
Started Mar 19 03:06:52 PM PDT 24
Finished Mar 19 03:06:55 PM PDT 24
Peak memory 200588 kb
Host smart-97ffa491-1da7-4d11-a55f-c00e1e099946
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507801947 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2507801947
Directory /workspace/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2330394602
Short name T178
Test name
Test status
Simulation time 1141559912 ps
CPU time 2.25 seconds
Started Mar 19 03:06:57 PM PDT 24
Finished Mar 19 03:07:00 PM PDT 24
Peak memory 200612 kb
Host smart-45fe3973-f94d-4a00-b8ef-358092acc0de
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330394602 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2330394602
Directory /workspace/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.1777406564
Short name T549
Test name
Test status
Simulation time 162833677 ps
CPU time 0.87 seconds
Started Mar 19 03:06:44 PM PDT 24
Finished Mar 19 03:06:46 PM PDT 24
Peak memory 198588 kb
Host smart-cf367fa4-cd79-4eb6-ab56-2e53a4668af2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777406564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1777406564
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/12.pwrmgr_smoke.1996806984
Short name T235
Test name
Test status
Simulation time 51176305 ps
CPU time 0.64 seconds
Started Mar 19 03:06:53 PM PDT 24
Finished Mar 19 03:06:54 PM PDT 24
Peak memory 198736 kb
Host smart-0ff6390d-830b-4f70-93d1-5652613f95ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996806984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.1996806984
Directory /workspace/12.pwrmgr_smoke/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup.3045215849
Short name T459
Test name
Test status
Simulation time 364391242 ps
CPU time 0.92 seconds
Started Mar 19 03:06:56 PM PDT 24
Finished Mar 19 03:06:59 PM PDT 24
Peak memory 198944 kb
Host smart-b8b62786-f8c7-45ce-a8e8-ce8d74b21144
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045215849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.3045215849
Directory /workspace/12.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/12.pwrmgr_wakeup_reset.3041006743
Short name T859
Test name
Test status
Simulation time 106084249 ps
CPU time 0.95 seconds
Started Mar 19 03:06:47 PM PDT 24
Finished Mar 19 03:06:48 PM PDT 24
Peak memory 198576 kb
Host smart-e6debdd6-e18d-447b-b25e-ca61cbd12b6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041006743 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.3041006743
Directory /workspace/12.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.2847136417
Short name T790
Test name
Test status
Simulation time 33332421 ps
CPU time 0.72 seconds
Started Mar 19 03:06:52 PM PDT 24
Finished Mar 19 03:06:53 PM PDT 24
Peak memory 197964 kb
Host smart-92ff463b-7599-4bae-91dc-5c956431541f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847136417 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.2847136417
Directory /workspace/13.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.1211761263
Short name T531
Test name
Test status
Simulation time 40065249 ps
CPU time 0.61 seconds
Started Mar 19 03:06:51 PM PDT 24
Finished Mar 19 03:06:52 PM PDT 24
Peak memory 197472 kb
Host smart-4841a919-f68f-4084-816a-e64c34ee8abb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211761263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst
_malfunc.1211761263
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.3063191693
Short name T562
Test name
Test status
Simulation time 639509241 ps
CPU time 0.95 seconds
Started Mar 19 03:06:50 PM PDT 24
Finished Mar 19 03:06:51 PM PDT 24
Peak memory 197848 kb
Host smart-3861433a-57dc-4e10-87e7-529ddf916124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063191693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.3063191693
Directory /workspace/13.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/13.pwrmgr_glitch.2627917048
Short name T350
Test name
Test status
Simulation time 45766302 ps
CPU time 0.6 seconds
Started Mar 19 03:06:58 PM PDT 24
Finished Mar 19 03:06:59 PM PDT 24
Peak memory 197508 kb
Host smart-cb185ec5-a5a8-4504-bab5-a77b0fced78c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627917048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.2627917048
Directory /workspace/13.pwrmgr_glitch/latest

Test location /workspace/coverage/default/13.pwrmgr_global_esc.3133898503
Short name T146
Test name
Test status
Simulation time 223925323 ps
CPU time 0.62 seconds
Started Mar 19 03:06:47 PM PDT 24
Finished Mar 19 03:06:48 PM PDT 24
Peak memory 197484 kb
Host smart-a3bf9d6b-13fc-4496-8eba-0d09ebc4ed34
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133898503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.3133898503
Directory /workspace/13.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.2907790660
Short name T794
Test name
Test status
Simulation time 45338714 ps
CPU time 0.72 seconds
Started Mar 19 03:06:55 PM PDT 24
Finished Mar 19 03:06:56 PM PDT 24
Peak memory 200796 kb
Host smart-c19f4e48-df9d-4d72-8335-c256cbcd1dce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907790660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.2907790660
Directory /workspace/13.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_lowpower_wakeup_race.2410779125
Short name T440
Test name
Test status
Simulation time 199704159 ps
CPU time 0.94 seconds
Started Mar 19 03:06:53 PM PDT 24
Finished Mar 19 03:06:54 PM PDT 24
Peak memory 199116 kb
Host smart-8de3cc78-d2d0-455b-8c3b-60d620b454bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410779125 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_w
akeup_race.2410779125
Directory /workspace/13.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/13.pwrmgr_reset.4194128899
Short name T855
Test name
Test status
Simulation time 62807609 ps
CPU time 0.89 seconds
Started Mar 19 03:06:47 PM PDT 24
Finished Mar 19 03:06:49 PM PDT 24
Peak memory 199308 kb
Host smart-54eef79a-7ced-4f08-96c1-f0595db813f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194128899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.4194128899
Directory /workspace/13.pwrmgr_reset/latest

Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.2499013501
Short name T782
Test name
Test status
Simulation time 96624868 ps
CPU time 1.01 seconds
Started Mar 19 03:06:52 PM PDT 24
Finished Mar 19 03:06:54 PM PDT 24
Peak memory 208912 kb
Host smart-ecf0d958-448c-4099-bab4-0f2481abd999
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499013501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.2499013501
Directory /workspace/13.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.1301613557
Short name T591
Test name
Test status
Simulation time 355338460 ps
CPU time 1.09 seconds
Started Mar 19 03:06:52 PM PDT 24
Finished Mar 19 03:06:54 PM PDT 24
Peak memory 200352 kb
Host smart-21583f0c-602f-44ea-bf99-c55bdd3cd994
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301613557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_
cm_ctrl_config_regwen.1301613557
Directory /workspace/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2397938108
Short name T547
Test name
Test status
Simulation time 840146002 ps
CPU time 2.46 seconds
Started Mar 19 03:06:56 PM PDT 24
Finished Mar 19 03:07:00 PM PDT 24
Peak memory 200664 kb
Host smart-842fca45-17d4-43ce-9fd3-6c7b3d436729
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397938108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2397938108
Directory /workspace/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.635854552
Short name T580
Test name
Test status
Simulation time 848082388 ps
CPU time 2.53 seconds
Started Mar 19 03:06:49 PM PDT 24
Finished Mar 19 03:06:53 PM PDT 24
Peak memory 200632 kb
Host smart-1e27ea16-7820-4e3b-9a39-c417de727265
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635854552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.635854552
Directory /workspace/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.4189617827
Short name T771
Test name
Test status
Simulation time 170189773 ps
CPU time 0.89 seconds
Started Mar 19 03:06:49 PM PDT 24
Finished Mar 19 03:06:50 PM PDT 24
Peak memory 198768 kb
Host smart-c197d536-6823-43fb-8a13-0fd5c8a72cb7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189617827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4189617827
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/13.pwrmgr_smoke.2432443774
Short name T155
Test name
Test status
Simulation time 48835570 ps
CPU time 0.63 seconds
Started Mar 19 03:06:48 PM PDT 24
Finished Mar 19 03:06:54 PM PDT 24
Peak memory 198764 kb
Host smart-0cb715f1-6091-4e0d-ae45-ac986ad06c90
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432443774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.2432443774
Directory /workspace/13.pwrmgr_smoke/latest

Test location /workspace/coverage/default/13.pwrmgr_stress_all.3806231037
Short name T461
Test name
Test status
Simulation time 2186467962 ps
CPU time 2.96 seconds
Started Mar 19 03:06:41 PM PDT 24
Finished Mar 19 03:06:44 PM PDT 24
Peak memory 200696 kb
Host smart-70f25df3-24cc-4846-8580-d7aee58d32e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806231037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.3806231037
Directory /workspace/13.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/13.pwrmgr_wakeup_reset.1428563957
Short name T658
Test name
Test status
Simulation time 177446375 ps
CPU time 0.81 seconds
Started Mar 19 03:06:50 PM PDT 24
Finished Mar 19 03:06:51 PM PDT 24
Peak memory 198564 kb
Host smart-be56e116-ab4b-45d8-9934-7d0dc7ec45d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428563957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.1428563957
Directory /workspace/13.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.1194651745
Short name T423
Test name
Test status
Simulation time 20950040 ps
CPU time 0.7 seconds
Started Mar 19 03:06:47 PM PDT 24
Finished Mar 19 03:06:49 PM PDT 24
Peak memory 197956 kb
Host smart-396c1bc1-be52-48fb-877d-325ee1c80b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194651745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.1194651745
Directory /workspace/14.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.3875718038
Short name T132
Test name
Test status
Simulation time 49192840 ps
CPU time 0.79 seconds
Started Mar 19 03:06:58 PM PDT 24
Finished Mar 19 03:06:59 PM PDT 24
Peak memory 198584 kb
Host smart-5941ab23-ff7f-413c-874c-7e603d9f06c9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875718038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.3875718038
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.3245877887
Short name T298
Test name
Test status
Simulation time 71110581 ps
CPU time 0.58 seconds
Started Mar 19 03:06:55 PM PDT 24
Finished Mar 19 03:06:56 PM PDT 24
Peak memory 196772 kb
Host smart-a3714064-a25f-47c0-bda1-1fd1db607d72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245877887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.3245877887
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.309623995
Short name T785
Test name
Test status
Simulation time 163349112 ps
CPU time 1.03 seconds
Started Mar 19 03:06:57 PM PDT 24
Finished Mar 19 03:06:59 PM PDT 24
Peak memory 197836 kb
Host smart-e7ba00eb-a197-481a-b793-2fd629d2bdd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309623995 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.309623995
Directory /workspace/14.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/14.pwrmgr_glitch.1823709349
Short name T578
Test name
Test status
Simulation time 108025561 ps
CPU time 0.62 seconds
Started Mar 19 03:06:48 PM PDT 24
Finished Mar 19 03:06:49 PM PDT 24
Peak memory 197480 kb
Host smart-a41b9948-9f12-4008-8d73-04345a18e4b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823709349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.1823709349
Directory /workspace/14.pwrmgr_glitch/latest

Test location /workspace/coverage/default/14.pwrmgr_global_esc.3923930852
Short name T438
Test name
Test status
Simulation time 60120498 ps
CPU time 0.62 seconds
Started Mar 19 03:06:49 PM PDT 24
Finished Mar 19 03:06:50 PM PDT 24
Peak memory 197556 kb
Host smart-f3b21b6d-b3d5-4afd-a7a5-5663e7fe7f98
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923930852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.3923930852
Directory /workspace/14.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.79036857
Short name T317
Test name
Test status
Simulation time 46088635 ps
CPU time 0.72 seconds
Started Mar 19 03:07:01 PM PDT 24
Finished Mar 19 03:07:02 PM PDT 24
Peak memory 200756 kb
Host smart-ef0b95ac-2941-4537-9cbe-9fd06a8f160c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79036857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_invalid
.79036857
Directory /workspace/14.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_lowpower_wakeup_race.524605806
Short name T874
Test name
Test status
Simulation time 353408140 ps
CPU time 1.08 seconds
Started Mar 19 03:07:09 PM PDT 24
Finished Mar 19 03:07:10 PM PDT 24
Peak memory 199000 kb
Host smart-3a0cf310-87d1-44b5-b5ab-f8ff29d7fe2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524605806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_wa
keup_race.524605806
Directory /workspace/14.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/14.pwrmgr_reset.3265120317
Short name T552
Test name
Test status
Simulation time 86363992 ps
CPU time 1.06 seconds
Started Mar 19 03:06:55 PM PDT 24
Finished Mar 19 03:06:56 PM PDT 24
Peak memory 199248 kb
Host smart-63fdd613-df88-47f7-bc64-f80edf5369dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265120317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.3265120317
Directory /workspace/14.pwrmgr_reset/latest

Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.1835804359
Short name T615
Test name
Test status
Simulation time 110160215 ps
CPU time 0.88 seconds
Started Mar 19 03:07:01 PM PDT 24
Finished Mar 19 03:07:03 PM PDT 24
Peak memory 208892 kb
Host smart-e3f47f0d-8da6-4db5-89f4-e8f9d171452a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835804359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.1835804359
Directory /workspace/14.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.3465455211
Short name T863
Test name
Test status
Simulation time 44324637 ps
CPU time 0.66 seconds
Started Mar 19 03:06:58 PM PDT 24
Finished Mar 19 03:06:59 PM PDT 24
Peak memory 198496 kb
Host smart-90f2e7e3-3912-4b7a-93a9-a98cbe388a9d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465455211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_
cm_ctrl_config_regwen.3465455211
Directory /workspace/14.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.951392273
Short name T792
Test name
Test status
Simulation time 834289397 ps
CPU time 3.07 seconds
Started Mar 19 03:07:03 PM PDT 24
Finished Mar 19 03:07:06 PM PDT 24
Peak memory 200636 kb
Host smart-816d45a9-64cc-4997-8f59-32dd02cfffb1
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951392273 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.951392273
Directory /workspace/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4293423167
Short name T542
Test name
Test status
Simulation time 1294441050 ps
CPU time 2.41 seconds
Started Mar 19 03:06:56 PM PDT 24
Finished Mar 19 03:06:58 PM PDT 24
Peak memory 200552 kb
Host smart-49276333-7665-4568-ac9a-8de979a890ed
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293423167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4293423167
Directory /workspace/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.2884657888
Short name T687
Test name
Test status
Simulation time 111555716 ps
CPU time 0.92 seconds
Started Mar 19 03:06:49 PM PDT 24
Finished Mar 19 03:06:51 PM PDT 24
Peak memory 198592 kb
Host smart-9a5b9a50-52e9-4e6d-a032-ffbfbbed5126
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884657888 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2884657888
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/14.pwrmgr_smoke.2872305603
Short name T607
Test name
Test status
Simulation time 60817305 ps
CPU time 0.65 seconds
Started Mar 19 03:06:46 PM PDT 24
Finished Mar 19 03:06:48 PM PDT 24
Peak memory 197820 kb
Host smart-b5be7297-61e7-4f8c-86ce-8b5a10156c6e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872305603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.2872305603
Directory /workspace/14.pwrmgr_smoke/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup.1453062970
Short name T877
Test name
Test status
Simulation time 28885201 ps
CPU time 0.66 seconds
Started Mar 19 03:07:04 PM PDT 24
Finished Mar 19 03:07:04 PM PDT 24
Peak memory 197660 kb
Host smart-ea3436ac-b114-4d59-9017-ff4fc948ae63
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453062970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.1453062970
Directory /workspace/14.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/14.pwrmgr_wakeup_reset.2124824618
Short name T304
Test name
Test status
Simulation time 130054778 ps
CPU time 0.84 seconds
Started Mar 19 03:06:57 PM PDT 24
Finished Mar 19 03:06:58 PM PDT 24
Peak memory 198740 kb
Host smart-642d7c48-868e-4589-a8ee-a3163f0285c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124824618 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.2124824618
Directory /workspace/14.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.1236317734
Short name T210
Test name
Test status
Simulation time 69726347 ps
CPU time 0.73 seconds
Started Mar 19 03:06:58 PM PDT 24
Finished Mar 19 03:06:59 PM PDT 24
Peak memory 198108 kb
Host smart-183a9bef-7712-4117-a6f6-f562ccca7167
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236317734 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.1236317734
Directory /workspace/15.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.3990279768
Short name T337
Test name
Test status
Simulation time 65090495 ps
CPU time 0.84 seconds
Started Mar 19 03:06:56 PM PDT 24
Finished Mar 19 03:06:56 PM PDT 24
Peak memory 198556 kb
Host smart-b10ea55e-402f-4794-9700-e7a0fcae2dcd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990279768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_dis
able_rom_integrity_check.3990279768
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.2934028654
Short name T691
Test name
Test status
Simulation time 38121879 ps
CPU time 0.61 seconds
Started Mar 19 03:07:05 PM PDT 24
Finished Mar 19 03:07:06 PM PDT 24
Peak memory 197268 kb
Host smart-10894093-784b-4a18-a0b0-7a840fb53d5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934028654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.2934028654
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.1381360516
Short name T751
Test name
Test status
Simulation time 169161951 ps
CPU time 0.94 seconds
Started Mar 19 03:06:58 PM PDT 24
Finished Mar 19 03:06:59 PM PDT 24
Peak memory 197380 kb
Host smart-bbaf5461-06ff-42bd-8435-23ce7ef02be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381360516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.1381360516
Directory /workspace/15.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/15.pwrmgr_glitch.947194798
Short name T660
Test name
Test status
Simulation time 53964839 ps
CPU time 0.58 seconds
Started Mar 19 03:06:57 PM PDT 24
Finished Mar 19 03:06:58 PM PDT 24
Peak memory 196768 kb
Host smart-7968e52d-2d09-41ea-9393-70a704a9d309
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947194798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.947194798
Directory /workspace/15.pwrmgr_glitch/latest

Test location /workspace/coverage/default/15.pwrmgr_global_esc.1992560652
Short name T875
Test name
Test status
Simulation time 49071506 ps
CPU time 0.65 seconds
Started Mar 19 03:07:05 PM PDT 24
Finished Mar 19 03:07:05 PM PDT 24
Peak memory 197840 kb
Host smart-51ff05fa-f292-4573-8185-9d3e12b064d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992560652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.1992560652
Directory /workspace/15.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.2778049464
Short name T444
Test name
Test status
Simulation time 87570159 ps
CPU time 0.72 seconds
Started Mar 19 03:06:55 PM PDT 24
Finished Mar 19 03:06:56 PM PDT 24
Peak memory 200788 kb
Host smart-f73ac175-49f0-402e-89ec-1359a78a486f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778049464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.2778049464
Directory /workspace/15.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_reset.2803988559
Short name T351
Test name
Test status
Simulation time 85691130 ps
CPU time 0.84 seconds
Started Mar 19 03:07:09 PM PDT 24
Finished Mar 19 03:07:10 PM PDT 24
Peak memory 198516 kb
Host smart-2817c8cb-b1a6-4d3d-9ca4-993942ed3da6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803988559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.2803988559
Directory /workspace/15.pwrmgr_reset/latest

Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.652629325
Short name T864
Test name
Test status
Simulation time 98709678 ps
CPU time 0.87 seconds
Started Mar 19 03:06:48 PM PDT 24
Finished Mar 19 03:06:50 PM PDT 24
Peak memory 208892 kb
Host smart-7cc595fc-de53-4c89-aa14-a58c0ff0644f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652629325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.652629325
Directory /workspace/15.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2510518659
Short name T123
Test name
Test status
Simulation time 816111886 ps
CPU time 2.78 seconds
Started Mar 19 03:06:58 PM PDT 24
Finished Mar 19 03:07:01 PM PDT 24
Peak memory 200660 kb
Host smart-4fd438b0-b014-4cf2-89d7-038774b4b871
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510518659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2510518659
Directory /workspace/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.297356367
Short name T732
Test name
Test status
Simulation time 1308286132 ps
CPU time 2.29 seconds
Started Mar 19 03:06:52 PM PDT 24
Finished Mar 19 03:06:54 PM PDT 24
Peak memory 200656 kb
Host smart-a1f51386-b463-4752-9456-fbbc3333d2f8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297356367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.297356367
Directory /workspace/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.2414864359
Short name T428
Test name
Test status
Simulation time 66568943 ps
CPU time 0.94 seconds
Started Mar 19 03:06:54 PM PDT 24
Finished Mar 19 03:06:55 PM PDT 24
Peak memory 198676 kb
Host smart-8472a94b-2bfe-43d0-8e99-d07d079968e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414864359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2414864359
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/15.pwrmgr_smoke.1269394905
Short name T180
Test name
Test status
Simulation time 31678192 ps
CPU time 0.68 seconds
Started Mar 19 03:06:54 PM PDT 24
Finished Mar 19 03:06:56 PM PDT 24
Peak memory 198036 kb
Host smart-45fd3961-fcaa-4317-8576-122ebc25e723
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269394905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.1269394905
Directory /workspace/15.pwrmgr_smoke/latest

Test location /workspace/coverage/default/15.pwrmgr_stress_all.2257271268
Short name T200
Test name
Test status
Simulation time 436400083 ps
CPU time 1.12 seconds
Started Mar 19 03:06:55 PM PDT 24
Finished Mar 19 03:06:56 PM PDT 24
Peak memory 200452 kb
Host smart-b7907516-bc19-45d2-b0e1-6f4f5b5eadd2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257271268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.2257271268
Directory /workspace/15.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/15.pwrmgr_wakeup_reset.2073308475
Short name T801
Test name
Test status
Simulation time 65665722 ps
CPU time 0.85 seconds
Started Mar 19 03:06:58 PM PDT 24
Finished Mar 19 03:06:59 PM PDT 24
Peak memory 198720 kb
Host smart-6a8e8276-a1f9-4ccb-a7ae-6d44929a76ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073308475 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.2073308475
Directory /workspace/15.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.2628257677
Short name T198
Test name
Test status
Simulation time 65995068 ps
CPU time 0.71 seconds
Started Mar 19 03:07:16 PM PDT 24
Finished Mar 19 03:07:17 PM PDT 24
Peak memory 197992 kb
Host smart-15587554-4e12-4a4b-8184-df3e8c690893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628257677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.2628257677
Directory /workspace/16.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.1326541453
Short name T601
Test name
Test status
Simulation time 64646377 ps
CPU time 0.85 seconds
Started Mar 19 03:06:52 PM PDT 24
Finished Mar 19 03:06:53 PM PDT 24
Peak memory 198520 kb
Host smart-7bf15806-cda8-46e5-b847-30cf50a69e1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326541453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_dis
able_rom_integrity_check.1326541453
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.3542179521
Short name T308
Test name
Test status
Simulation time 29585116 ps
CPU time 0.63 seconds
Started Mar 19 03:07:02 PM PDT 24
Finished Mar 19 03:07:03 PM PDT 24
Peak memory 197456 kb
Host smart-1b4386b8-8ed1-4075-85f3-54475b18c9a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542179521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.3542179521
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.550889553
Short name T398
Test name
Test status
Simulation time 309673270 ps
CPU time 0.95 seconds
Started Mar 19 03:06:57 PM PDT 24
Finished Mar 19 03:06:59 PM PDT 24
Peak memory 197808 kb
Host smart-065355fa-f8fd-4ade-82c6-78cd2f94c24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550889553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.550889553
Directory /workspace/16.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/16.pwrmgr_glitch.1929452554
Short name T879
Test name
Test status
Simulation time 31849687 ps
CPU time 0.63 seconds
Started Mar 19 03:06:53 PM PDT 24
Finished Mar 19 03:06:54 PM PDT 24
Peak memory 197524 kb
Host smart-b5dbdb78-7f74-44c6-a16f-ecb2c080a804
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929452554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.1929452554
Directory /workspace/16.pwrmgr_glitch/latest

Test location /workspace/coverage/default/16.pwrmgr_global_esc.260522738
Short name T420
Test name
Test status
Simulation time 82354551 ps
CPU time 0.59 seconds
Started Mar 19 03:06:55 PM PDT 24
Finished Mar 19 03:06:56 PM PDT 24
Peak memory 197804 kb
Host smart-70c9fbdd-404c-4987-bea8-d3ae52a8ac43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260522738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.260522738
Directory /workspace/16.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.1134554672
Short name T710
Test name
Test status
Simulation time 74534108 ps
CPU time 0.68 seconds
Started Mar 19 03:07:00 PM PDT 24
Finished Mar 19 03:07:01 PM PDT 24
Peak memory 200788 kb
Host smart-dfe91c5b-2a0a-4701-ae23-4072f36d24e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134554672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.1134554672
Directory /workspace/16.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_reset.3487073928
Short name T604
Test name
Test status
Simulation time 39001316 ps
CPU time 0.72 seconds
Started Mar 19 03:06:52 PM PDT 24
Finished Mar 19 03:06:53 PM PDT 24
Peak memory 198544 kb
Host smart-0b09014d-a2e2-4e7b-813a-5d162528a755
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487073928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.3487073928
Directory /workspace/16.pwrmgr_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.2750096153
Short name T653
Test name
Test status
Simulation time 237091776 ps
CPU time 0.76 seconds
Started Mar 19 03:07:03 PM PDT 24
Finished Mar 19 03:07:04 PM PDT 24
Peak memory 208896 kb
Host smart-cbf5ae91-a404-4c94-9166-c7a85aaaf391
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750096153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.2750096153
Directory /workspace/16.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.657352184
Short name T611
Test name
Test status
Simulation time 45678795 ps
CPU time 0.7 seconds
Started Mar 19 03:07:03 PM PDT 24
Finished Mar 19 03:07:03 PM PDT 24
Peak memory 198840 kb
Host smart-66b67479-a2ef-435e-878f-573781285d36
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657352184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_c
m_ctrl_config_regwen.657352184
Directory /workspace/16.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3270427181
Short name T800
Test name
Test status
Simulation time 1092640181 ps
CPU time 2.38 seconds
Started Mar 19 03:06:58 PM PDT 24
Finished Mar 19 03:07:00 PM PDT 24
Peak memory 200508 kb
Host smart-154d7481-eb21-49fc-bd6c-55563c896ad3
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270427181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3270427181
Directory /workspace/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.21593768
Short name T632
Test name
Test status
Simulation time 956195282 ps
CPU time 2.31 seconds
Started Mar 19 03:07:02 PM PDT 24
Finished Mar 19 03:07:04 PM PDT 24
Peak memory 200556 kb
Host smart-a29c28c7-4d96-4da2-8028-d941854170a0
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21593768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.21593768
Directory /workspace/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.3938847855
Short name T673
Test name
Test status
Simulation time 94310620 ps
CPU time 0.81 seconds
Started Mar 19 03:07:08 PM PDT 24
Finished Mar 19 03:07:10 PM PDT 24
Peak memory 198784 kb
Host smart-af3b0f20-17ac-43e7-99f0-5c5a2a39578a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938847855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3938847855
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/16.pwrmgr_smoke.1528884954
Short name T484
Test name
Test status
Simulation time 53161168 ps
CPU time 0.65 seconds
Started Mar 19 03:06:52 PM PDT 24
Finished Mar 19 03:06:53 PM PDT 24
Peak memory 198740 kb
Host smart-5acb6329-bb25-4c36-a43d-9001fe321082
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528884954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.1528884954
Directory /workspace/16.pwrmgr_smoke/latest

Test location /workspace/coverage/default/16.pwrmgr_stress_all.3021993307
Short name T584
Test name
Test status
Simulation time 1220464842 ps
CPU time 1.26 seconds
Started Mar 19 03:06:58 PM PDT 24
Finished Mar 19 03:07:00 PM PDT 24
Peak memory 200660 kb
Host smart-64d44b01-84a3-417f-bc5c-27eec9f630d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021993307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.3021993307
Directory /workspace/16.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/16.pwrmgr_stress_all_with_rand_reset.451410245
Short name T19
Test name
Test status
Simulation time 42240713536 ps
CPU time 25.85 seconds
Started Mar 19 03:06:53 PM PDT 24
Finished Mar 19 03:07:19 PM PDT 24
Peak memory 200864 kb
Host smart-5845d742-4e24-46d8-a571-00385895fb7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451410245 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all_with_rand_reset.451410245
Directory /workspace/16.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.pwrmgr_wakeup_reset.3653977206
Short name T231
Test name
Test status
Simulation time 479695071 ps
CPU time 1.13 seconds
Started Mar 19 03:06:50 PM PDT 24
Finished Mar 19 03:06:52 PM PDT 24
Peak memory 200464 kb
Host smart-afc3bcf6-45ae-4fc7-9f19-a7eaf54bbc6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653977206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.3653977206
Directory /workspace/16.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.2374189100
Short name T497
Test name
Test status
Simulation time 94227737 ps
CPU time 0.7 seconds
Started Mar 19 03:06:52 PM PDT 24
Finished Mar 19 03:06:53 PM PDT 24
Peak memory 198064 kb
Host smart-4f5a6e94-04f7-4f37-83b0-fee1417abf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374189100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.2374189100
Directory /workspace/17.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.1539234094
Short name T358
Test name
Test status
Simulation time 48215423 ps
CPU time 0.8 seconds
Started Mar 19 03:07:09 PM PDT 24
Finished Mar 19 03:07:10 PM PDT 24
Peak memory 198604 kb
Host smart-66e8cc03-0d93-4d0f-84e3-90038dfc7989
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539234094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_dis
able_rom_integrity_check.1539234094
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.2742673712
Short name T474
Test name
Test status
Simulation time 32380250 ps
CPU time 0.6 seconds
Started Mar 19 03:07:13 PM PDT 24
Finished Mar 19 03:07:14 PM PDT 24
Peak memory 197456 kb
Host smart-65455b66-0f6c-4ca7-8789-87e374431a10
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742673712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst
_malfunc.2742673712
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.606317779
Short name T733
Test name
Test status
Simulation time 635700132 ps
CPU time 0.94 seconds
Started Mar 19 03:06:57 PM PDT 24
Finished Mar 19 03:06:59 PM PDT 24
Peak memory 197532 kb
Host smart-b09497d9-702a-48f7-800c-bf0dc68bf98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606317779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.606317779
Directory /workspace/17.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/17.pwrmgr_glitch.3857494415
Short name T707
Test name
Test status
Simulation time 46518287 ps
CPU time 0.6 seconds
Started Mar 19 03:07:01 PM PDT 24
Finished Mar 19 03:07:02 PM PDT 24
Peak memory 197560 kb
Host smart-03930dd7-6060-431d-ac14-44d78c7aad4f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857494415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.3857494415
Directory /workspace/17.pwrmgr_glitch/latest

Test location /workspace/coverage/default/17.pwrmgr_global_esc.1128726751
Short name T659
Test name
Test status
Simulation time 28791268 ps
CPU time 0.66 seconds
Started Mar 19 03:07:17 PM PDT 24
Finished Mar 19 03:07:17 PM PDT 24
Peak memory 197540 kb
Host smart-8cee0438-9e3e-44e5-87e4-4f545c3cd1f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128726751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.1128726751
Directory /workspace/17.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.3408563735
Short name T141
Test name
Test status
Simulation time 72404658 ps
CPU time 0.66 seconds
Started Mar 19 03:07:21 PM PDT 24
Finished Mar 19 03:07:22 PM PDT 24
Peak memory 200816 kb
Host smart-52bf2642-1227-4423-bc62-46e36945be2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408563735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.3408563735
Directory /workspace/17.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_reset.4050559780
Short name T597
Test name
Test status
Simulation time 25447035 ps
CPU time 0.69 seconds
Started Mar 19 03:06:59 PM PDT 24
Finished Mar 19 03:07:00 PM PDT 24
Peak memory 198608 kb
Host smart-61dfc61b-ece7-42c1-8ff5-4df0e1ed9a25
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050559780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.4050559780
Directory /workspace/17.pwrmgr_reset/latest

Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.1288250678
Short name T264
Test name
Test status
Simulation time 118025810 ps
CPU time 0.97 seconds
Started Mar 19 03:07:01 PM PDT 24
Finished Mar 19 03:07:03 PM PDT 24
Peak memory 208876 kb
Host smart-02fb4a2a-3d08-4620-acd4-f390e3a00233
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288250678 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.1288250678
Directory /workspace/17.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1611640427
Short name T201
Test name
Test status
Simulation time 932610518 ps
CPU time 2.53 seconds
Started Mar 19 03:06:59 PM PDT 24
Finished Mar 19 03:07:02 PM PDT 24
Peak memory 200568 kb
Host smart-6529e0d9-ee8c-41ea-8509-797c4565cc79
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611640427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1611640427
Directory /workspace/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3495672071
Short name T583
Test name
Test status
Simulation time 912999632 ps
CPU time 3.06 seconds
Started Mar 19 03:06:54 PM PDT 24
Finished Mar 19 03:06:57 PM PDT 24
Peak memory 200624 kb
Host smart-3cc9e173-ed78-4a25-9ee6-1007da9f4138
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495672071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3495672071
Directory /workspace/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.236437476
Short name T642
Test name
Test status
Simulation time 53473856 ps
CPU time 0.9 seconds
Started Mar 19 03:06:56 PM PDT 24
Finished Mar 19 03:06:58 PM PDT 24
Peak memory 198804 kb
Host smart-aba9b6d2-152b-4305-baf5-0fca9b2c0577
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236437476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig_
mubi.236437476
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/17.pwrmgr_smoke.3928635546
Short name T340
Test name
Test status
Simulation time 31333648 ps
CPU time 0.71 seconds
Started Mar 19 03:06:55 PM PDT 24
Finished Mar 19 03:06:56 PM PDT 24
Peak memory 198748 kb
Host smart-210fa7fd-5a96-4e7d-8a37-a9fa31f448aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928635546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.3928635546
Directory /workspace/17.pwrmgr_smoke/latest

Test location /workspace/coverage/default/17.pwrmgr_stress_all.1869317627
Short name T759
Test name
Test status
Simulation time 3425066320 ps
CPU time 3.34 seconds
Started Mar 19 03:06:55 PM PDT 24
Finished Mar 19 03:06:59 PM PDT 24
Peak memory 200796 kb
Host smart-2af5cbb4-6234-4db8-bb0e-3e64bca0e766
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869317627 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.1869317627
Directory /workspace/17.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup.1155667911
Short name T271
Test name
Test status
Simulation time 339857102 ps
CPU time 0.82 seconds
Started Mar 19 03:06:53 PM PDT 24
Finished Mar 19 03:06:54 PM PDT 24
Peak memory 199008 kb
Host smart-99b93f99-db7e-4a87-a13b-22d1fd191fed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155667911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.1155667911
Directory /workspace/17.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/17.pwrmgr_wakeup_reset.2279714026
Short name T217
Test name
Test status
Simulation time 108594807 ps
CPU time 0.84 seconds
Started Mar 19 03:06:55 PM PDT 24
Finished Mar 19 03:06:56 PM PDT 24
Peak memory 198744 kb
Host smart-5aaa9bfa-b676-4e42-b494-301e0fd7716b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279714026 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.2279714026
Directory /workspace/17.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.4265863531
Short name T523
Test name
Test status
Simulation time 37281822 ps
CPU time 0.81 seconds
Started Mar 19 03:07:02 PM PDT 24
Finished Mar 19 03:07:03 PM PDT 24
Peak memory 198012 kb
Host smart-f95fb5f5-f945-4a98-88d0-56917692dd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265863531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.4265863531
Directory /workspace/18.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.1605331787
Short name T372
Test name
Test status
Simulation time 53716569 ps
CPU time 0.7 seconds
Started Mar 19 03:06:57 PM PDT 24
Finished Mar 19 03:06:58 PM PDT 24
Peak memory 198612 kb
Host smart-37473510-9f27-4b98-aafb-01c12530e2d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605331787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.1605331787
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.4271515554
Short name T283
Test name
Test status
Simulation time 29544913 ps
CPU time 0.64 seconds
Started Mar 19 03:06:58 PM PDT 24
Finished Mar 19 03:06:59 PM PDT 24
Peak memory 197468 kb
Host smart-51b6ce05-e233-4ab1-8416-4255095412d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271515554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst
_malfunc.4271515554
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.4070303997
Short name T781
Test name
Test status
Simulation time 944335052 ps
CPU time 0.92 seconds
Started Mar 19 03:06:57 PM PDT 24
Finished Mar 19 03:06:58 PM PDT 24
Peak memory 197536 kb
Host smart-b84c924b-0ace-4978-bfce-2ae0a044df31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070303997 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.4070303997
Directory /workspace/18.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/18.pwrmgr_glitch.3738811089
Short name T434
Test name
Test status
Simulation time 36216468 ps
CPU time 0.63 seconds
Started Mar 19 03:06:54 PM PDT 24
Finished Mar 19 03:06:54 PM PDT 24
Peak memory 197492 kb
Host smart-55a2de3b-b701-4980-ada9-68f59997972e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738811089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.3738811089
Directory /workspace/18.pwrmgr_glitch/latest

Test location /workspace/coverage/default/18.pwrmgr_global_esc.301769630
Short name T179
Test name
Test status
Simulation time 55744853 ps
CPU time 0.66 seconds
Started Mar 19 03:06:58 PM PDT 24
Finished Mar 19 03:06:59 PM PDT 24
Peak memory 197816 kb
Host smart-9d6cd282-f77a-4e4d-9e05-1e74c9525f76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301769630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.301769630
Directory /workspace/18.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.2465263025
Short name T629
Test name
Test status
Simulation time 64106061 ps
CPU time 0.68 seconds
Started Mar 19 03:06:54 PM PDT 24
Finished Mar 19 03:06:55 PM PDT 24
Peak memory 200824 kb
Host smart-4e8acd0e-3862-4d13-bc7f-68192fdfbb14
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465263025 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_inval
id.2465263025
Directory /workspace/18.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_lowpower_wakeup_race.1153327420
Short name T738
Test name
Test status
Simulation time 69978150 ps
CPU time 0.71 seconds
Started Mar 19 03:06:58 PM PDT 24
Finished Mar 19 03:06:59 PM PDT 24
Peak memory 197572 kb
Host smart-1e53c5a7-6998-439c-8544-a4fd610d9c8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153327420 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_w
akeup_race.1153327420
Directory /workspace/18.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/18.pwrmgr_reset.3895860195
Short name T113
Test name
Test status
Simulation time 146960924 ps
CPU time 0.71 seconds
Started Mar 19 03:06:54 PM PDT 24
Finished Mar 19 03:06:55 PM PDT 24
Peak memory 198588 kb
Host smart-1b0a639f-b595-4c74-94ec-db7fda3a84dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895860195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.3895860195
Directory /workspace/18.pwrmgr_reset/latest

Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.2730561274
Short name T238
Test name
Test status
Simulation time 162412966 ps
CPU time 0.8 seconds
Started Mar 19 03:06:55 PM PDT 24
Finished Mar 19 03:06:56 PM PDT 24
Peak memory 208908 kb
Host smart-7177915c-7bc9-4a57-96b4-84e026c3f383
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730561274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.2730561274
Directory /workspace/18.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.2694415681
Short name T389
Test name
Test status
Simulation time 134998839 ps
CPU time 0.77 seconds
Started Mar 19 03:07:06 PM PDT 24
Finished Mar 19 03:07:10 PM PDT 24
Peak memory 198504 kb
Host smart-99fd59f2-e261-454e-8528-3e791b90ef39
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694415681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_
cm_ctrl_config_regwen.2694415681
Directory /workspace/18.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2019499438
Short name T572
Test name
Test status
Simulation time 1105512034 ps
CPU time 2.19 seconds
Started Mar 19 03:07:09 PM PDT 24
Finished Mar 19 03:07:11 PM PDT 24
Peak memory 200464 kb
Host smart-83177a19-5e95-472f-9d22-2308c4c1aae1
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019499438 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2019499438
Directory /workspace/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1461139887
Short name T824
Test name
Test status
Simulation time 904909856 ps
CPU time 3.3 seconds
Started Mar 19 03:06:57 PM PDT 24
Finished Mar 19 03:07:01 PM PDT 24
Peak memory 200596 kb
Host smart-fe4cb0a9-636c-4bca-9f78-f4e59cf6024b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461139887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1461139887
Directory /workspace/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.1757240742
Short name T353
Test name
Test status
Simulation time 130246005 ps
CPU time 0.84 seconds
Started Mar 19 03:06:57 PM PDT 24
Finished Mar 19 03:06:58 PM PDT 24
Peak memory 198788 kb
Host smart-95415645-1dc5-47bb-b181-eaf5d01ee6fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757240742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1757240742
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/18.pwrmgr_smoke.93464379
Short name T529
Test name
Test status
Simulation time 29441038 ps
CPU time 0.72 seconds
Started Mar 19 03:07:22 PM PDT 24
Finished Mar 19 03:07:23 PM PDT 24
Peak memory 198744 kb
Host smart-21fbe177-6f8c-493e-b8c7-301114fc51e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93464379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.93464379
Directory /workspace/18.pwrmgr_smoke/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup.3420163854
Short name T818
Test name
Test status
Simulation time 82107176 ps
CPU time 0.67 seconds
Started Mar 19 03:07:09 PM PDT 24
Finished Mar 19 03:07:10 PM PDT 24
Peak memory 197640 kb
Host smart-b8712391-c35c-4ef7-9b86-0aed61d4d07b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420163854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.3420163854
Directory /workspace/18.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/18.pwrmgr_wakeup_reset.4170752497
Short name T503
Test name
Test status
Simulation time 82456108 ps
CPU time 0.67 seconds
Started Mar 19 03:06:57 PM PDT 24
Finished Mar 19 03:06:58 PM PDT 24
Peak memory 198724 kb
Host smart-a882a9f6-a37f-4ccd-bf0f-c7a2e8de4bc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170752497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.4170752497
Directory /workspace/18.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.610987260
Short name T164
Test name
Test status
Simulation time 171672790 ps
CPU time 0.76 seconds
Started Mar 19 03:06:58 PM PDT 24
Finished Mar 19 03:06:59 PM PDT 24
Peak memory 197988 kb
Host smart-f8418b13-a91a-4eb2-bb26-0182636b9fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610987260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.610987260
Directory /workspace/19.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.733953746
Short name T564
Test name
Test status
Simulation time 215435749 ps
CPU time 0.66 seconds
Started Mar 19 03:07:04 PM PDT 24
Finished Mar 19 03:07:05 PM PDT 24
Peak memory 198012 kb
Host smart-216457a3-c27b-4171-b9a2-dffed041debf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733953746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_disa
ble_rom_integrity_check.733953746
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.2927131136
Short name T711
Test name
Test status
Simulation time 57387495 ps
CPU time 0.61 seconds
Started Mar 19 03:07:00 PM PDT 24
Finished Mar 19 03:07:01 PM PDT 24
Peak memory 197460 kb
Host smart-c87b3340-32da-4388-b265-a4fa6b4c18b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927131136 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.2927131136
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.360136559
Short name T269
Test name
Test status
Simulation time 166523051 ps
CPU time 0.95 seconds
Started Mar 19 03:06:52 PM PDT 24
Finished Mar 19 03:06:53 PM PDT 24
Peak memory 197540 kb
Host smart-c96d9a57-eb69-4fc1-a5ac-8a723c0c57c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360136559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.360136559
Directory /workspace/19.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/19.pwrmgr_glitch.3886673297
Short name T669
Test name
Test status
Simulation time 24180395 ps
CPU time 0.63 seconds
Started Mar 19 03:07:12 PM PDT 24
Finished Mar 19 03:07:12 PM PDT 24
Peak memory 196848 kb
Host smart-020d1214-310a-4703-81ef-68446719a553
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886673297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.3886673297
Directory /workspace/19.pwrmgr_glitch/latest

Test location /workspace/coverage/default/19.pwrmgr_global_esc.1316289508
Short name T247
Test name
Test status
Simulation time 124506301 ps
CPU time 0.62 seconds
Started Mar 19 03:07:06 PM PDT 24
Finished Mar 19 03:07:07 PM PDT 24
Peak memory 197848 kb
Host smart-996f4e0e-ff0b-4947-929d-e810e67e7bac
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316289508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.1316289508
Directory /workspace/19.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.3059466364
Short name T839
Test name
Test status
Simulation time 41915735 ps
CPU time 0.73 seconds
Started Mar 19 03:06:58 PM PDT 24
Finished Mar 19 03:06:59 PM PDT 24
Peak memory 200836 kb
Host smart-6363eeea-7a59-4609-a891-b28857fb8b0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059466364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.3059466364
Directory /workspace/19.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_lowpower_wakeup_race.2604395071
Short name T435
Test name
Test status
Simulation time 60474495 ps
CPU time 0.66 seconds
Started Mar 19 03:06:55 PM PDT 24
Finished Mar 19 03:06:56 PM PDT 24
Peak memory 198520 kb
Host smart-750d63f7-653f-4b59-b293-701fc9642da9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604395071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_w
akeup_race.2604395071
Directory /workspace/19.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/19.pwrmgr_reset.1531353970
Short name T647
Test name
Test status
Simulation time 91326863 ps
CPU time 0.82 seconds
Started Mar 19 03:07:05 PM PDT 24
Finished Mar 19 03:07:06 PM PDT 24
Peak memory 199112 kb
Host smart-c173c1ec-bf4f-4752-a1e8-ef5ca0ddf7fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531353970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.1531353970
Directory /workspace/19.pwrmgr_reset/latest

Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.1936905094
Short name T74
Test name
Test status
Simulation time 154974921 ps
CPU time 0.85 seconds
Started Mar 19 03:06:56 PM PDT 24
Finished Mar 19 03:06:58 PM PDT 24
Peak memory 208956 kb
Host smart-5cf14e0b-0fed-43d5-bf7a-3f777deefcd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936905094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.1936905094
Directory /workspace/19.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.3089344161
Short name T44
Test name
Test status
Simulation time 30778122 ps
CPU time 0.66 seconds
Started Mar 19 03:07:04 PM PDT 24
Finished Mar 19 03:07:04 PM PDT 24
Peak memory 198448 kb
Host smart-31e7aa70-ff65-4d2d-b015-50b36f95cc09
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089344161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_
cm_ctrl_config_regwen.3089344161
Directory /workspace/19.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1891166012
Short name T737
Test name
Test status
Simulation time 814683233 ps
CPU time 2.91 seconds
Started Mar 19 03:07:06 PM PDT 24
Finished Mar 19 03:07:09 PM PDT 24
Peak memory 200616 kb
Host smart-bca1af5d-8343-4a34-b714-d9004dd37e06
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891166012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1891166012
Directory /workspace/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3920481111
Short name T648
Test name
Test status
Simulation time 899700906 ps
CPU time 3.31 seconds
Started Mar 19 03:06:52 PM PDT 24
Finished Mar 19 03:06:56 PM PDT 24
Peak memory 200512 kb
Host smart-72670054-24e7-49ac-8de3-67990a8abf21
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920481111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3920481111
Directory /workspace/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.1638828675
Short name T555
Test name
Test status
Simulation time 67465079 ps
CPU time 0.95 seconds
Started Mar 19 03:06:57 PM PDT 24
Finished Mar 19 03:06:59 PM PDT 24
Peak memory 198600 kb
Host smart-07a92b0c-5b8e-4f6b-a8d2-38cb904a4cab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638828675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1638828675
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/19.pwrmgr_smoke.3898608206
Short name T342
Test name
Test status
Simulation time 41216855 ps
CPU time 0.67 seconds
Started Mar 19 03:07:00 PM PDT 24
Finished Mar 19 03:07:01 PM PDT 24
Peak memory 198720 kb
Host smart-087b85c8-06c0-4407-9534-d7c97b2c0fb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898608206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.3898608206
Directory /workspace/19.pwrmgr_smoke/latest

Test location /workspace/coverage/default/19.pwrmgr_stress_all.3601398360
Short name T401
Test name
Test status
Simulation time 5893710975 ps
CPU time 3.87 seconds
Started Mar 19 03:07:22 PM PDT 24
Finished Mar 19 03:07:26 PM PDT 24
Peak memory 200748 kb
Host smart-21ab0274-aa48-4fd8-b2b4-f318800cd065
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601398360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all.3601398360
Directory /workspace/19.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup.410786474
Short name T712
Test name
Test status
Simulation time 198806687 ps
CPU time 0.87 seconds
Started Mar 19 03:07:04 PM PDT 24
Finished Mar 19 03:07:05 PM PDT 24
Peak memory 197936 kb
Host smart-5ca8cb4c-f669-458a-bbc7-c9d3f9088e49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410786474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.410786474
Directory /workspace/19.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/19.pwrmgr_wakeup_reset.1129259669
Short name T374
Test name
Test status
Simulation time 359989433 ps
CPU time 1.21 seconds
Started Mar 19 03:06:54 PM PDT 24
Finished Mar 19 03:06:55 PM PDT 24
Peak memory 200496 kb
Host smart-773eb90f-15b8-4bda-9f00-5fc9d1dac44a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129259669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.1129259669
Directory /workspace/19.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.1970475826
Short name T796
Test name
Test status
Simulation time 16875215 ps
CPU time 0.63 seconds
Started Mar 19 03:06:19 PM PDT 24
Finished Mar 19 03:06:20 PM PDT 24
Peak memory 197464 kb
Host smart-801b1c0f-ed1c-4dbe-99d1-145f08932b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970475826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.1970475826
Directory /workspace/2.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.3829072982
Short name T728
Test name
Test status
Simulation time 63217440 ps
CPU time 0.67 seconds
Started Mar 19 03:06:05 PM PDT 24
Finished Mar 19 03:06:06 PM PDT 24
Peak memory 197920 kb
Host smart-4a542a48-4330-4738-9dd5-a2f4f68da460
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829072982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.3829072982
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.3031948594
Short name T664
Test name
Test status
Simulation time 27468819 ps
CPU time 0.61 seconds
Started Mar 19 03:06:21 PM PDT 24
Finished Mar 19 03:06:22 PM PDT 24
Peak memory 196764 kb
Host smart-f0690415-4464-4184-9dc2-d4421cedf75c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031948594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_
malfunc.3031948594
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.1347780553
Short name T288
Test name
Test status
Simulation time 159210883 ps
CPU time 0.92 seconds
Started Mar 19 03:06:16 PM PDT 24
Finished Mar 19 03:06:17 PM PDT 24
Peak memory 197552 kb
Host smart-368952ab-a2b9-4b60-a5c8-79c0b1c1a77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347780553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.1347780553
Directory /workspace/2.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/2.pwrmgr_glitch.2692975772
Short name T445
Test name
Test status
Simulation time 30372197 ps
CPU time 0.64 seconds
Started Mar 19 03:06:08 PM PDT 24
Finished Mar 19 03:06:09 PM PDT 24
Peak memory 197556 kb
Host smart-8aa56759-7ba0-4c88-a2dd-58a4bf848587
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692975772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.2692975772
Directory /workspace/2.pwrmgr_glitch/latest

Test location /workspace/coverage/default/2.pwrmgr_global_esc.1105325361
Short name T557
Test name
Test status
Simulation time 34621182 ps
CPU time 0.6 seconds
Started Mar 19 03:06:05 PM PDT 24
Finished Mar 19 03:06:06 PM PDT 24
Peak memory 197528 kb
Host smart-1f4fffbe-9098-4648-b400-7cdc4f12b282
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105325361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.1105325361
Directory /workspace/2.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.3812191551
Short name T70
Test name
Test status
Simulation time 43664369 ps
CPU time 0.67 seconds
Started Mar 19 03:06:12 PM PDT 24
Finished Mar 19 03:06:13 PM PDT 24
Peak memory 200824 kb
Host smart-fbab08e1-b5ad-4339-90a3-78677763d5a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812191551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.3812191551
Directory /workspace/2.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_reset.972616806
Short name T391
Test name
Test status
Simulation time 69973655 ps
CPU time 0.75 seconds
Started Mar 19 03:06:14 PM PDT 24
Finished Mar 19 03:06:15 PM PDT 24
Peak memory 198048 kb
Host smart-1e366608-92ea-42c5-81f2-9af16fe2aeda
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972616806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.972616806
Directory /workspace/2.pwrmgr_reset/latest

Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.3210133807
Short name T367
Test name
Test status
Simulation time 165687053 ps
CPU time 0.8 seconds
Started Mar 19 03:06:24 PM PDT 24
Finished Mar 19 03:06:25 PM PDT 24
Peak memory 208920 kb
Host smart-5da2a699-0ca0-444a-8b3d-763be7567db3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210133807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.3210133807
Directory /workspace/2.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm.1886571234
Short name T5
Test name
Test status
Simulation time 318063803 ps
CPU time 1.39 seconds
Started Mar 19 03:06:10 PM PDT 24
Finished Mar 19 03:06:11 PM PDT 24
Peak memory 217344 kb
Host smart-1013f17b-8622-48f7-b501-631ce9820860
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886571234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.1886571234
Directory /workspace/2.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1911052355
Short name T197
Test name
Test status
Simulation time 1297872335 ps
CPU time 2.29 seconds
Started Mar 19 03:06:07 PM PDT 24
Finished Mar 19 03:06:10 PM PDT 24
Peak memory 200644 kb
Host smart-1923f3b2-b4a3-4b7f-af0a-cd9178a70a12
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911052355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1911052355
Directory /workspace/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2937464042
Short name T695
Test name
Test status
Simulation time 1000538840 ps
CPU time 3.03 seconds
Started Mar 19 03:06:25 PM PDT 24
Finished Mar 19 03:06:28 PM PDT 24
Peak memory 200660 kb
Host smart-bc6e29ab-9662-42d7-9fe0-74698ff6a8f8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937464042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2937464042
Directory /workspace/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.196026443
Short name T749
Test name
Test status
Simulation time 164270137 ps
CPU time 0.89 seconds
Started Mar 19 03:06:05 PM PDT 24
Finished Mar 19 03:06:06 PM PDT 24
Peak memory 198668 kb
Host smart-9b1e6390-93b1-4fee-9c5a-893ce261da68
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196026443 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.196026443
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/2.pwrmgr_smoke.2504964645
Short name T606
Test name
Test status
Simulation time 61794473 ps
CPU time 0.65 seconds
Started Mar 19 03:06:11 PM PDT 24
Finished Mar 19 03:06:12 PM PDT 24
Peak memory 198708 kb
Host smart-fbc359eb-4c3a-4108-b624-4ff46a0880a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504964645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.2504964645
Directory /workspace/2.pwrmgr_smoke/latest

Test location /workspace/coverage/default/2.pwrmgr_wakeup_reset.110772249
Short name T734
Test name
Test status
Simulation time 812747746 ps
CPU time 1.08 seconds
Started Mar 19 03:06:08 PM PDT 24
Finished Mar 19 03:06:10 PM PDT 24
Peak memory 200468 kb
Host smart-ae107699-6f86-47ae-972e-3723a078ed62
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110772249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.110772249
Directory /workspace/2.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.2092026202
Short name T356
Test name
Test status
Simulation time 151073911 ps
CPU time 0.69 seconds
Started Mar 19 03:06:58 PM PDT 24
Finished Mar 19 03:06:59 PM PDT 24
Peak memory 198028 kb
Host smart-f1c7af54-2628-4f5f-9ac0-99e084ada1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092026202 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.2092026202
Directory /workspace/20.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.2028599823
Short name T854
Test name
Test status
Simulation time 56350369 ps
CPU time 0.78 seconds
Started Mar 19 03:07:15 PM PDT 24
Finished Mar 19 03:07:16 PM PDT 24
Peak memory 198028 kb
Host smart-f60222fd-d8a7-4d13-a308-8ddd335f6755
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028599823 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_dis
able_rom_integrity_check.2028599823
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.1940476954
Short name T530
Test name
Test status
Simulation time 35065605 ps
CPU time 0.63 seconds
Started Mar 19 03:07:25 PM PDT 24
Finished Mar 19 03:07:26 PM PDT 24
Peak memory 196752 kb
Host smart-07651b03-b61f-4a09-a662-055a614ca744
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940476954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.1940476954
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.465963474
Short name T279
Test name
Test status
Simulation time 886918491 ps
CPU time 1 seconds
Started Mar 19 03:07:11 PM PDT 24
Finished Mar 19 03:07:12 PM PDT 24
Peak memory 197508 kb
Host smart-91826eac-9d04-489a-91b6-ad52a778122e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465963474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.465963474
Directory /workspace/20.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/20.pwrmgr_glitch.278378754
Short name T16
Test name
Test status
Simulation time 189193138 ps
CPU time 0.59 seconds
Started Mar 19 03:07:09 PM PDT 24
Finished Mar 19 03:07:10 PM PDT 24
Peak memory 197532 kb
Host smart-6ab10aa0-4314-4f47-b39a-d4d05fa93c61
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278378754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.278378754
Directory /workspace/20.pwrmgr_glitch/latest

Test location /workspace/coverage/default/20.pwrmgr_global_esc.993011729
Short name T366
Test name
Test status
Simulation time 69102087 ps
CPU time 0.56 seconds
Started Mar 19 03:07:10 PM PDT 24
Finished Mar 19 03:07:10 PM PDT 24
Peak memory 197452 kb
Host smart-77eb2151-50d2-4301-90ef-94a185a75201
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993011729 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.993011729
Directory /workspace/20.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.1575271619
Short name T822
Test name
Test status
Simulation time 77829736 ps
CPU time 0.7 seconds
Started Mar 19 03:07:19 PM PDT 24
Finished Mar 19 03:07:21 PM PDT 24
Peak memory 200824 kb
Host smart-4dd0e565-4cc4-4532-8288-0775607b8231
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575271619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.1575271619
Directory /workspace/20.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_reset.464231284
Short name T143
Test name
Test status
Simulation time 84413505 ps
CPU time 0.73 seconds
Started Mar 19 03:06:53 PM PDT 24
Finished Mar 19 03:06:54 PM PDT 24
Peak memory 198500 kb
Host smart-40dd379a-8005-499a-9b3b-63d5099e5a46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464231284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.464231284
Directory /workspace/20.pwrmgr_reset/latest

Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.1711194958
Short name T415
Test name
Test status
Simulation time 124104400 ps
CPU time 0.86 seconds
Started Mar 19 03:07:23 PM PDT 24
Finished Mar 19 03:07:23 PM PDT 24
Peak memory 208892 kb
Host smart-a6b2c8d7-4b8c-43cb-926c-9c70a306f717
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711194958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.1711194958
Directory /workspace/20.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.70233798
Short name T192
Test name
Test status
Simulation time 126618278 ps
CPU time 0.69 seconds
Started Mar 19 03:07:15 PM PDT 24
Finished Mar 19 03:07:16 PM PDT 24
Peak memory 198096 kb
Host smart-990660d3-0c9b-4e3f-9e5f-c8c2ea5ea5f2
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70233798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_co
nfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm
_ctrl_config_regwen.70233798
Directory /workspace/20.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2450473859
Short name T424
Test name
Test status
Simulation time 1302374509 ps
CPU time 2.29 seconds
Started Mar 19 03:07:14 PM PDT 24
Finished Mar 19 03:07:16 PM PDT 24
Peak memory 200580 kb
Host smart-bc172712-d224-47f9-96ff-fb413c9d6ec1
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450473859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2450473859
Directory /workspace/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1376536256
Short name T698
Test name
Test status
Simulation time 1360673578 ps
CPU time 2.23 seconds
Started Mar 19 03:07:28 PM PDT 24
Finished Mar 19 03:07:30 PM PDT 24
Peak memory 200660 kb
Host smart-b47453dc-6fc8-4f5b-80fe-276c637ad658
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376536256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1376536256
Directory /workspace/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.1921546608
Short name T511
Test name
Test status
Simulation time 72930318 ps
CPU time 0.93 seconds
Started Mar 19 03:07:22 PM PDT 24
Finished Mar 19 03:07:23 PM PDT 24
Peak memory 198684 kb
Host smart-1bff9b66-2cc4-454f-a1d5-a05f728156b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921546608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1921546608
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/20.pwrmgr_smoke.3869909876
Short name T881
Test name
Test status
Simulation time 32765277 ps
CPU time 0.7 seconds
Started Mar 19 03:07:01 PM PDT 24
Finished Mar 19 03:07:02 PM PDT 24
Peak memory 198728 kb
Host smart-d39191dc-65b1-46ae-bd3e-c1890e1b5a51
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869909876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.3869909876
Directory /workspace/20.pwrmgr_smoke/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup.292703245
Short name T844
Test name
Test status
Simulation time 60472235 ps
CPU time 0.66 seconds
Started Mar 19 03:07:11 PM PDT 24
Finished Mar 19 03:07:11 PM PDT 24
Peak memory 197884 kb
Host smart-15afcff1-2f6a-4691-bed1-7add4c223088
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292703245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.292703245
Directory /workspace/20.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/20.pwrmgr_wakeup_reset.3043971899
Short name T226
Test name
Test status
Simulation time 537274741 ps
CPU time 0.97 seconds
Started Mar 19 03:06:53 PM PDT 24
Finished Mar 19 03:06:55 PM PDT 24
Peak memory 199688 kb
Host smart-76c36f89-5892-4552-bece-bbe90e8eb877
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043971899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.3043971899
Directory /workspace/20.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.996551858
Short name T183
Test name
Test status
Simulation time 47741523 ps
CPU time 0.68 seconds
Started Mar 19 03:07:15 PM PDT 24
Finished Mar 19 03:07:21 PM PDT 24
Peak memory 197956 kb
Host smart-ccec7a5b-176e-4018-87d8-01e4b2586f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996551858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.996551858
Directory /workspace/21.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.2065600546
Short name T646
Test name
Test status
Simulation time 63585176 ps
CPU time 0.8 seconds
Started Mar 19 03:07:13 PM PDT 24
Finished Mar 19 03:07:14 PM PDT 24
Peak memory 198556 kb
Host smart-e8dc3110-1d32-44bc-a36b-c22f0b9d2620
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065600546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_dis
able_rom_integrity_check.2065600546
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.2433099825
Short name T840
Test name
Test status
Simulation time 29890787 ps
CPU time 0.66 seconds
Started Mar 19 03:07:29 PM PDT 24
Finished Mar 19 03:07:30 PM PDT 24
Peak memory 196772 kb
Host smart-af01aff6-6926-4a2b-bc1e-ccbc94773338
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433099825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst
_malfunc.2433099825
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.2080493215
Short name T412
Test name
Test status
Simulation time 275318394 ps
CPU time 1.02 seconds
Started Mar 19 03:07:06 PM PDT 24
Finished Mar 19 03:07:07 PM PDT 24
Peak memory 197492 kb
Host smart-ef7144f5-39ae-4735-a21e-13fc370e9237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080493215 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.2080493215
Directory /workspace/21.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/21.pwrmgr_glitch.3463969452
Short name T672
Test name
Test status
Simulation time 83838463 ps
CPU time 0.62 seconds
Started Mar 19 03:07:35 PM PDT 24
Finished Mar 19 03:07:36 PM PDT 24
Peak memory 197524 kb
Host smart-c89bf9e5-fa84-49d0-97fb-e473cc9ed3dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463969452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.3463969452
Directory /workspace/21.pwrmgr_glitch/latest

Test location /workspace/coverage/default/21.pwrmgr_global_esc.1204778555
Short name T849
Test name
Test status
Simulation time 31848473 ps
CPU time 0.6 seconds
Started Mar 19 03:07:19 PM PDT 24
Finished Mar 19 03:07:21 PM PDT 24
Peak memory 197540 kb
Host smart-c6eef2b2-0eb5-4fff-b347-1398db91480e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204778555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.1204778555
Directory /workspace/21.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.1416080880
Short name T223
Test name
Test status
Simulation time 44817667 ps
CPU time 0.76 seconds
Started Mar 19 03:07:15 PM PDT 24
Finished Mar 19 03:07:16 PM PDT 24
Peak memory 200788 kb
Host smart-6882d862-9775-4304-8566-55b123c7ee46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416080880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_inval
id.1416080880
Directory /workspace/21.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_reset.564882100
Short name T666
Test name
Test status
Simulation time 67725329 ps
CPU time 0.74 seconds
Started Mar 19 03:07:09 PM PDT 24
Finished Mar 19 03:07:10 PM PDT 24
Peak memory 198536 kb
Host smart-e0d87b91-50a2-4948-b3e5-e9c33588432c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564882100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.564882100
Directory /workspace/21.pwrmgr_reset/latest

Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.2498512643
Short name T34
Test name
Test status
Simulation time 122588227 ps
CPU time 0.83 seconds
Started Mar 19 03:07:09 PM PDT 24
Finished Mar 19 03:07:10 PM PDT 24
Peak memory 208944 kb
Host smart-c957f4ee-087f-49b5-86b4-66a9256bb900
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498512643 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.2498512643
Directory /workspace/21.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.1241280543
Short name T305
Test name
Test status
Simulation time 104135752 ps
CPU time 0.77 seconds
Started Mar 19 03:07:10 PM PDT 24
Finished Mar 19 03:07:11 PM PDT 24
Peak memory 198220 kb
Host smart-f12dc5b3-c0de-4d97-8dde-4dda0d90ec0f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241280543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_
cm_ctrl_config_regwen.1241280543
Directory /workspace/21.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3963721307
Short name T234
Test name
Test status
Simulation time 836592629 ps
CPU time 2.8 seconds
Started Mar 19 03:07:34 PM PDT 24
Finished Mar 19 03:07:37 PM PDT 24
Peak memory 200588 kb
Host smart-c5b0e6e7-3153-4a3b-b431-594ae912aba8
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963721307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3963721307
Directory /workspace/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.444768301
Short name T587
Test name
Test status
Simulation time 1564281559 ps
CPU time 2.26 seconds
Started Mar 19 03:07:16 PM PDT 24
Finished Mar 19 03:07:19 PM PDT 24
Peak memory 200664 kb
Host smart-c204582e-c3de-407a-be89-1f0dcd04106a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444768301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.444768301
Directory /workspace/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.1412371317
Short name T425
Test name
Test status
Simulation time 376429931 ps
CPU time 0.83 seconds
Started Mar 19 03:07:25 PM PDT 24
Finished Mar 19 03:07:26 PM PDT 24
Peak memory 198960 kb
Host smart-1022feff-9332-475b-abd0-ceea200ef502
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412371317 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1412371317
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/21.pwrmgr_smoke.1088881006
Short name T773
Test name
Test status
Simulation time 37757294 ps
CPU time 0.65 seconds
Started Mar 19 03:07:35 PM PDT 24
Finished Mar 19 03:07:36 PM PDT 24
Peak memory 198736 kb
Host smart-1ca45117-f699-4935-9979-f15a944f1920
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088881006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.1088881006
Directory /workspace/21.pwrmgr_smoke/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup.983696150
Short name T677
Test name
Test status
Simulation time 169268230 ps
CPU time 0.81 seconds
Started Mar 19 03:07:18 PM PDT 24
Finished Mar 19 03:07:19 PM PDT 24
Peak memory 198504 kb
Host smart-c9493e88-2492-41d7-b205-5c23c101a74d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983696150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.983696150
Directory /workspace/21.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/21.pwrmgr_wakeup_reset.4122612981
Short name T515
Test name
Test status
Simulation time 71548099 ps
CPU time 0.67 seconds
Started Mar 19 03:07:16 PM PDT 24
Finished Mar 19 03:07:17 PM PDT 24
Peak memory 198716 kb
Host smart-dab5d208-74d8-433f-bf4f-ef57fbc03475
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122612981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.4122612981
Directory /workspace/21.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.1938713269
Short name T73
Test name
Test status
Simulation time 21773756 ps
CPU time 0.65 seconds
Started Mar 19 03:07:28 PM PDT 24
Finished Mar 19 03:07:29 PM PDT 24
Peak memory 197972 kb
Host smart-5ab5e3cd-8dae-4610-8386-4b9531fed858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938713269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.1938713269
Directory /workspace/22.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.4105015267
Short name T505
Test name
Test status
Simulation time 71179728 ps
CPU time 0.68 seconds
Started Mar 19 03:07:11 PM PDT 24
Finished Mar 19 03:07:12 PM PDT 24
Peak memory 198132 kb
Host smart-58227697-7e9f-4c26-af76-04fab92a624a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105015267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.4105015267
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.1004689413
Short name T175
Test name
Test status
Simulation time 36991053 ps
CPU time 0.59 seconds
Started Mar 19 03:07:23 PM PDT 24
Finished Mar 19 03:07:24 PM PDT 24
Peak memory 196768 kb
Host smart-31aed2bf-aba3-4c0c-a4c8-46d0fb1ecc4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004689413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.1004689413
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.2081737740
Short name T641
Test name
Test status
Simulation time 311064133 ps
CPU time 0.92 seconds
Started Mar 19 03:07:09 PM PDT 24
Finished Mar 19 03:07:10 PM PDT 24
Peak memory 197556 kb
Host smart-26889e5e-729d-4bea-a1b1-e2ef56d25190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081737740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.2081737740
Directory /workspace/22.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/22.pwrmgr_glitch.2785028263
Short name T724
Test name
Test status
Simulation time 31111413 ps
CPU time 0.64 seconds
Started Mar 19 03:07:11 PM PDT 24
Finished Mar 19 03:07:12 PM PDT 24
Peak memory 197576 kb
Host smart-5d0b8bba-b110-4589-9f0e-6561ad8a3964
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785028263 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.2785028263
Directory /workspace/22.pwrmgr_glitch/latest

Test location /workspace/coverage/default/22.pwrmgr_global_esc.919146808
Short name T833
Test name
Test status
Simulation time 95152986 ps
CPU time 0.61 seconds
Started Mar 19 03:07:02 PM PDT 24
Finished Mar 19 03:07:03 PM PDT 24
Peak memory 197508 kb
Host smart-16a78cfc-8709-437c-8f78-d41bd92d8ef3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919146808 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.919146808
Directory /workspace/22.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.3347028360
Short name T319
Test name
Test status
Simulation time 77752688 ps
CPU time 0.66 seconds
Started Mar 19 03:07:10 PM PDT 24
Finished Mar 19 03:07:10 PM PDT 24
Peak memory 200596 kb
Host smart-514195ae-f29c-4424-b253-b82b894f3f05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347028360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval
id.3347028360
Directory /workspace/22.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_lowpower_wakeup_race.2728281625
Short name T623
Test name
Test status
Simulation time 423197220 ps
CPU time 1.06 seconds
Started Mar 19 03:07:08 PM PDT 24
Finished Mar 19 03:07:10 PM PDT 24
Peak memory 199268 kb
Host smart-1439d034-cea2-4dcb-9dd3-c4c068765d5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728281625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_w
akeup_race.2728281625
Directory /workspace/22.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/22.pwrmgr_reset.2814641552
Short name T251
Test name
Test status
Simulation time 75974826 ps
CPU time 0.99 seconds
Started Mar 19 03:07:11 PM PDT 24
Finished Mar 19 03:07:12 PM PDT 24
Peak memory 199500 kb
Host smart-42f06709-58ee-4843-9244-c40243718475
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814641552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.2814641552
Directory /workspace/22.pwrmgr_reset/latest

Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.4114108604
Short name T807
Test name
Test status
Simulation time 111623409 ps
CPU time 1.11 seconds
Started Mar 19 03:07:25 PM PDT 24
Finished Mar 19 03:07:26 PM PDT 24
Peak memory 208888 kb
Host smart-ff81198b-bc69-4740-beca-7c938b74dd07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114108604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.4114108604
Directory /workspace/22.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.1904156670
Short name T740
Test name
Test status
Simulation time 383690103 ps
CPU time 0.96 seconds
Started Mar 19 03:07:18 PM PDT 24
Finished Mar 19 03:07:19 PM PDT 24
Peak memory 199536 kb
Host smart-62e4fb1a-edf2-4c23-b6f9-62935e7cc192
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904156670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_
cm_ctrl_config_regwen.1904156670
Directory /workspace/22.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.293484790
Short name T346
Test name
Test status
Simulation time 855400414 ps
CPU time 2.28 seconds
Started Mar 19 03:07:05 PM PDT 24
Finished Mar 19 03:07:07 PM PDT 24
Peak memory 200624 kb
Host smart-5a89a180-7b9c-4526-a863-5fa1d82ead04
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293484790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.293484790
Directory /workspace/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2987991345
Short name T106
Test name
Test status
Simulation time 1012352845 ps
CPU time 1.99 seconds
Started Mar 19 03:07:12 PM PDT 24
Finished Mar 19 03:07:14 PM PDT 24
Peak memory 200680 kb
Host smart-15a7b9ea-2ff9-458d-b6ab-ef5e6534ab0b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987991345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2987991345
Directory /workspace/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.1035031609
Short name T568
Test name
Test status
Simulation time 67627442 ps
CPU time 0.93 seconds
Started Mar 19 03:07:08 PM PDT 24
Finished Mar 19 03:07:10 PM PDT 24
Peak memory 198660 kb
Host smart-e6d20992-ffec-49b6-96a8-3374d302b585
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035031609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1035031609
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/22.pwrmgr_smoke.1625737188
Short name T679
Test name
Test status
Simulation time 68917462 ps
CPU time 0.62 seconds
Started Mar 19 03:07:10 PM PDT 24
Finished Mar 19 03:07:11 PM PDT 24
Peak memory 197872 kb
Host smart-450bf656-e105-4a61-8ef0-33847efd6f48
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625737188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.1625737188
Directory /workspace/22.pwrmgr_smoke/latest

Test location /workspace/coverage/default/22.pwrmgr_wakeup_reset.2937378884
Short name T76
Test name
Test status
Simulation time 206377214 ps
CPU time 0.86 seconds
Started Mar 19 03:07:21 PM PDT 24
Finished Mar 19 03:07:22 PM PDT 24
Peak memory 199676 kb
Host smart-0d9464a9-f6e5-4157-9d98-0ad00ad7eb51
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937378884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup_reset.2937378884
Directory /workspace/22.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.2652716814
Short name T467
Test name
Test status
Simulation time 81869475 ps
CPU time 0.73 seconds
Started Mar 19 03:07:12 PM PDT 24
Finished Mar 19 03:07:13 PM PDT 24
Peak memory 198160 kb
Host smart-47fc21ff-248d-47df-8e1f-679ee287a991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652716814 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.2652716814
Directory /workspace/23.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.4294170703
Short name T128
Test name
Test status
Simulation time 202431230 ps
CPU time 0.68 seconds
Started Mar 19 03:07:34 PM PDT 24
Finished Mar 19 03:07:35 PM PDT 24
Peak memory 197964 kb
Host smart-67af3cb1-8343-4c85-9864-098969754615
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294170703 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.4294170703
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.1933560400
Short name T463
Test name
Test status
Simulation time 41762689 ps
CPU time 0.6 seconds
Started Mar 19 03:07:21 PM PDT 24
Finished Mar 19 03:07:22 PM PDT 24
Peak memory 197492 kb
Host smart-077b9e31-4f8f-4788-af5b-b9ce6bdd6c40
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933560400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst
_malfunc.1933560400
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.3275548774
Short name T280
Test name
Test status
Simulation time 168308438 ps
CPU time 0.95 seconds
Started Mar 19 03:07:23 PM PDT 24
Finished Mar 19 03:07:24 PM PDT 24
Peak memory 197532 kb
Host smart-1c5b4fa8-451f-493c-b651-5ff0f44449dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275548774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.3275548774
Directory /workspace/23.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/23.pwrmgr_glitch.3488475490
Short name T829
Test name
Test status
Simulation time 55516131 ps
CPU time 0.7 seconds
Started Mar 19 03:07:32 PM PDT 24
Finished Mar 19 03:07:34 PM PDT 24
Peak memory 197492 kb
Host smart-3e5effa5-007b-4e71-b63a-8d3fae9e1217
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488475490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.3488475490
Directory /workspace/23.pwrmgr_glitch/latest

Test location /workspace/coverage/default/23.pwrmgr_global_esc.1460750482
Short name T755
Test name
Test status
Simulation time 26093138 ps
CPU time 0.61 seconds
Started Mar 19 03:07:21 PM PDT 24
Finished Mar 19 03:07:22 PM PDT 24
Peak memory 197528 kb
Host smart-4b5d5a41-69c2-476c-a7c1-e5f4a85be896
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460750482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.1460750482
Directory /workspace/23.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.1321635450
Short name T693
Test name
Test status
Simulation time 42339312 ps
CPU time 0.69 seconds
Started Mar 19 03:07:16 PM PDT 24
Finished Mar 19 03:07:17 PM PDT 24
Peak memory 200780 kb
Host smart-bb2cb904-d9cd-496e-805e-9149330e0015
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321635450 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.1321635450
Directory /workspace/23.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_lowpower_wakeup_race.1772727274
Short name T624
Test name
Test status
Simulation time 80836440 ps
CPU time 0.78 seconds
Started Mar 19 03:07:14 PM PDT 24
Finished Mar 19 03:07:15 PM PDT 24
Peak memory 197728 kb
Host smart-6e164a4b-19fa-4640-bcf0-9d7093699206
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772727274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_w
akeup_race.1772727274
Directory /workspace/23.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/23.pwrmgr_reset.4045644581
Short name T483
Test name
Test status
Simulation time 49503475 ps
CPU time 0.78 seconds
Started Mar 19 03:07:24 PM PDT 24
Finished Mar 19 03:07:25 PM PDT 24
Peak memory 198548 kb
Host smart-d47c0377-2e18-4c63-a727-37534a083ba2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045644581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.4045644581
Directory /workspace/23.pwrmgr_reset/latest

Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.576036432
Short name T533
Test name
Test status
Simulation time 105456300 ps
CPU time 1.07 seconds
Started Mar 19 03:07:25 PM PDT 24
Finished Mar 19 03:07:27 PM PDT 24
Peak memory 208900 kb
Host smart-98cbeb3e-8b2a-4a7e-96c7-2607a5fc8619
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576036432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.576036432
Directory /workspace/23.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3654017168
Short name T479
Test name
Test status
Simulation time 740449052 ps
CPU time 2.86 seconds
Started Mar 19 03:07:35 PM PDT 24
Finished Mar 19 03:07:38 PM PDT 24
Peak memory 200664 kb
Host smart-aa890bf7-f25b-4653-ac21-54020190ea92
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654017168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3654017168
Directory /workspace/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1365444199
Short name T348
Test name
Test status
Simulation time 903561947 ps
CPU time 2.46 seconds
Started Mar 19 03:07:12 PM PDT 24
Finished Mar 19 03:07:14 PM PDT 24
Peak memory 200564 kb
Host smart-02f294d3-3607-40eb-8772-eb88132d393c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365444199 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1365444199
Directory /workspace/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.1330164525
Short name T741
Test name
Test status
Simulation time 63178898 ps
CPU time 0.79 seconds
Started Mar 19 03:07:20 PM PDT 24
Finished Mar 19 03:07:21 PM PDT 24
Peak memory 198828 kb
Host smart-dda31002-3515-4e5b-a8b9-dabd818ad006
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330164525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1330164525
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/23.pwrmgr_smoke.1889618832
Short name T228
Test name
Test status
Simulation time 55364908 ps
CPU time 0.64 seconds
Started Mar 19 03:07:38 PM PDT 24
Finished Mar 19 03:07:39 PM PDT 24
Peak memory 198744 kb
Host smart-4e8c4d6d-e414-48cd-a547-fc1254f798cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889618832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.1889618832
Directory /workspace/23.pwrmgr_smoke/latest

Test location /workspace/coverage/default/23.pwrmgr_stress_all.1294537098
Short name T650
Test name
Test status
Simulation time 976013603 ps
CPU time 2.98 seconds
Started Mar 19 03:07:22 PM PDT 24
Finished Mar 19 03:07:25 PM PDT 24
Peak memory 200660 kb
Host smart-11de1390-c2fc-4035-b82b-78568d3bcb6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294537098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.1294537098
Directory /workspace/23.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup.2134760941
Short name T576
Test name
Test status
Simulation time 500894562 ps
CPU time 0.92 seconds
Started Mar 19 03:07:30 PM PDT 24
Finished Mar 19 03:07:31 PM PDT 24
Peak memory 199204 kb
Host smart-fd3a29d9-f442-451c-9247-3df94cf6bd30
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134760941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.2134760941
Directory /workspace/23.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/23.pwrmgr_wakeup_reset.3587778945
Short name T301
Test name
Test status
Simulation time 113714081 ps
CPU time 0.84 seconds
Started Mar 19 03:07:25 PM PDT 24
Finished Mar 19 03:07:26 PM PDT 24
Peak memory 198760 kb
Host smart-3d3f21ca-1c7d-4a89-9450-f6b107568c1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587778945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.3587778945
Directory /workspace/23.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.462704608
Short name T292
Test name
Test status
Simulation time 48456494 ps
CPU time 0.67 seconds
Started Mar 19 03:07:38 PM PDT 24
Finished Mar 19 03:07:38 PM PDT 24
Peak memory 197912 kb
Host smart-3c6d1f16-45e6-4797-91b0-dfbbf1a0d2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462704608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.462704608
Directory /workspace/24.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.576808813
Short name T686
Test name
Test status
Simulation time 54177924 ps
CPU time 0.76 seconds
Started Mar 19 03:07:16 PM PDT 24
Finished Mar 19 03:07:17 PM PDT 24
Peak memory 198560 kb
Host smart-a8869c79-0ced-4385-b8b4-19d8e46cd3dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576808813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_disa
ble_rom_integrity_check.576808813
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.2012243072
Short name T688
Test name
Test status
Simulation time 32316498 ps
CPU time 0.59 seconds
Started Mar 19 03:07:37 PM PDT 24
Finished Mar 19 03:07:38 PM PDT 24
Peak memory 196748 kb
Host smart-13d6f06f-27e8-45e1-a7f2-34ec3af205a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012243072 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.2012243072
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.3065514711
Short name T700
Test name
Test status
Simulation time 165723610 ps
CPU time 1.01 seconds
Started Mar 19 03:07:14 PM PDT 24
Finished Mar 19 03:07:15 PM PDT 24
Peak memory 197552 kb
Host smart-4db9d87e-1224-4862-b096-3c033fb646c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065514711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.3065514711
Directory /workspace/24.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/24.pwrmgr_glitch.326074524
Short name T670
Test name
Test status
Simulation time 34446037 ps
CPU time 0.63 seconds
Started Mar 19 03:07:14 PM PDT 24
Finished Mar 19 03:07:14 PM PDT 24
Peak memory 197452 kb
Host smart-a1de1a27-ffda-4a82-b71f-0bdf1c4c623d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326074524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.326074524
Directory /workspace/24.pwrmgr_glitch/latest

Test location /workspace/coverage/default/24.pwrmgr_global_esc.1187275462
Short name T239
Test name
Test status
Simulation time 41115010 ps
CPU time 0.66 seconds
Started Mar 19 03:07:25 PM PDT 24
Finished Mar 19 03:07:25 PM PDT 24
Peak memory 197552 kb
Host smart-9c07daa7-3071-4b36-92b5-786f23d99259
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187275462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.1187275462
Directory /workspace/24.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.2643165511
Short name T718
Test name
Test status
Simulation time 74802063 ps
CPU time 0.66 seconds
Started Mar 19 03:07:14 PM PDT 24
Finished Mar 19 03:07:15 PM PDT 24
Peak memory 200760 kb
Host smart-16c76a8c-cf6e-4102-99d2-6a13cefc6551
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643165511 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_inval
id.2643165511
Directory /workspace/24.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_reset.1844714442
Short name T28
Test name
Test status
Simulation time 94656324 ps
CPU time 0.92 seconds
Started Mar 19 03:07:30 PM PDT 24
Finished Mar 19 03:07:31 PM PDT 24
Peak memory 199236 kb
Host smart-f3d2baa0-b524-4259-a013-1a05e51e8c50
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844714442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.1844714442
Directory /workspace/24.pwrmgr_reset/latest

Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.2194667358
Short name T763
Test name
Test status
Simulation time 110495917 ps
CPU time 1.09 seconds
Started Mar 19 03:07:22 PM PDT 24
Finished Mar 19 03:07:23 PM PDT 24
Peak memory 208888 kb
Host smart-f7f941d3-80d2-4c80-9751-32426f782df5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194667358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.2194667358
Directory /workspace/24.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1372445793
Short name T293
Test name
Test status
Simulation time 786232281 ps
CPU time 2.98 seconds
Started Mar 19 03:07:24 PM PDT 24
Finished Mar 19 03:07:27 PM PDT 24
Peak memory 200596 kb
Host smart-aaab32d8-ca73-49fe-b224-9d9b3a5ccae2
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372445793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1372445793
Directory /workspace/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4271714225
Short name T233
Test name
Test status
Simulation time 1325914449 ps
CPU time 2.05 seconds
Started Mar 19 03:07:10 PM PDT 24
Finished Mar 19 03:07:13 PM PDT 24
Peak memory 200572 kb
Host smart-f6ee0636-01e7-4682-90d3-ec855540609a
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271714225 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4271714225
Directory /workspace/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.3544732626
Short name T282
Test name
Test status
Simulation time 95133102 ps
CPU time 0.82 seconds
Started Mar 19 03:07:26 PM PDT 24
Finished Mar 19 03:07:27 PM PDT 24
Peak memory 198504 kb
Host smart-1b2d3951-c5eb-48b8-a3a6-75682e53a449
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544732626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3544732626
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/24.pwrmgr_smoke.3172438086
Short name T662
Test name
Test status
Simulation time 29225284 ps
CPU time 0.7 seconds
Started Mar 19 03:07:27 PM PDT 24
Finished Mar 19 03:07:27 PM PDT 24
Peak memory 198760 kb
Host smart-b5743ff9-ad0e-4f27-a52d-b71c39474e62
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172438086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.3172438086
Directory /workspace/24.pwrmgr_smoke/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup.846633291
Short name T823
Test name
Test status
Simulation time 322164939 ps
CPU time 0.98 seconds
Started Mar 19 03:07:14 PM PDT 24
Finished Mar 19 03:07:15 PM PDT 24
Peak memory 199180 kb
Host smart-708cb5ec-8451-4106-aae6-7d4f863c2d5c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846633291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.846633291
Directory /workspace/24.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/24.pwrmgr_wakeup_reset.2825318192
Short name T64
Test name
Test status
Simulation time 158675099 ps
CPU time 0.99 seconds
Started Mar 19 03:07:14 PM PDT 24
Finished Mar 19 03:07:16 PM PDT 24
Peak memory 199640 kb
Host smart-486e8d1a-70fc-4d33-a3c8-7f02ec958770
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825318192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.2825318192
Directory /workspace/24.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.1331969958
Short name T685
Test name
Test status
Simulation time 33159352 ps
CPU time 0.65 seconds
Started Mar 19 03:07:19 PM PDT 24
Finished Mar 19 03:07:21 PM PDT 24
Peak memory 197948 kb
Host smart-b2ffe2a6-636c-4240-823c-f68d6eef1ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331969958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.1331969958
Directory /workspace/25.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.37607829
Short name T470
Test name
Test status
Simulation time 81621054 ps
CPU time 0.71 seconds
Started Mar 19 03:07:12 PM PDT 24
Finished Mar 19 03:07:12 PM PDT 24
Peak memory 198576 kb
Host smart-f16b7fc9-deb8-4ddb-b934-6c278cb5cad0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37607829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_disab
le_rom_integrity_check.37607829
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.3339628644
Short name T450
Test name
Test status
Simulation time 32220255 ps
CPU time 0.62 seconds
Started Mar 19 03:07:31 PM PDT 24
Finished Mar 19 03:07:31 PM PDT 24
Peak memory 197432 kb
Host smart-6268c3e6-e7bd-4e31-abfc-ef8b661c50ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339628644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst
_malfunc.3339628644
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.3897153723
Short name T596
Test name
Test status
Simulation time 167403457 ps
CPU time 1 seconds
Started Mar 19 03:07:26 PM PDT 24
Finished Mar 19 03:07:27 PM PDT 24
Peak memory 197844 kb
Host smart-a5674ef4-558a-46ac-88d8-37853a4e6171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897153723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.3897153723
Directory /workspace/25.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/25.pwrmgr_glitch.2636008647
Short name T286
Test name
Test status
Simulation time 75970179 ps
CPU time 0.61 seconds
Started Mar 19 03:07:30 PM PDT 24
Finished Mar 19 03:07:31 PM PDT 24
Peak memory 197504 kb
Host smart-de8e9313-2a27-4b35-b0c2-9c46511d354f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636008647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.2636008647
Directory /workspace/25.pwrmgr_glitch/latest

Test location /workspace/coverage/default/25.pwrmgr_global_esc.331007861
Short name T507
Test name
Test status
Simulation time 27049653 ps
CPU time 0.6 seconds
Started Mar 19 03:07:33 PM PDT 24
Finished Mar 19 03:07:34 PM PDT 24
Peak memory 197540 kb
Host smart-c9732102-1e22-4476-bc5e-18572931f526
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331007861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.331007861
Directory /workspace/25.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.1103960573
Short name T296
Test name
Test status
Simulation time 43510590 ps
CPU time 0.7 seconds
Started Mar 19 03:07:43 PM PDT 24
Finished Mar 19 03:07:44 PM PDT 24
Peak memory 200808 kb
Host smart-bd8d2865-c4b9-4d06-aab7-9ddc7184d2ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103960573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_inval
id.1103960573
Directory /workspace/25.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_reset.1072827857
Short name T570
Test name
Test status
Simulation time 37183404 ps
CPU time 0.74 seconds
Started Mar 19 03:07:27 PM PDT 24
Finished Mar 19 03:07:28 PM PDT 24
Peak memory 198596 kb
Host smart-16533fe8-1b73-4aab-8496-1a65d11fdb98
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072827857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.1072827857
Directory /workspace/25.pwrmgr_reset/latest

Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.3743392295
Short name T196
Test name
Test status
Simulation time 96483872 ps
CPU time 1.07 seconds
Started Mar 19 03:07:23 PM PDT 24
Finished Mar 19 03:07:24 PM PDT 24
Peak memory 208948 kb
Host smart-70e4b217-56c5-4600-afab-d436fe32f347
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743392295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.3743392295
Directory /workspace/25.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.2016471449
Short name T275
Test name
Test status
Simulation time 106151857 ps
CPU time 0.7 seconds
Started Mar 19 03:07:24 PM PDT 24
Finished Mar 19 03:07:24 PM PDT 24
Peak memory 198828 kb
Host smart-fb1a34be-b288-4845-8ab1-349262e0955c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016471449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_
cm_ctrl_config_regwen.2016471449
Directory /workspace/25.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1902180257
Short name T719
Test name
Test status
Simulation time 1409905072 ps
CPU time 2.16 seconds
Started Mar 19 03:07:24 PM PDT 24
Finished Mar 19 03:07:27 PM PDT 24
Peak memory 200640 kb
Host smart-878c77aa-b058-4d53-b9de-5797a9fa0b21
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902180257 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1902180257
Directory /workspace/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2299744938
Short name T312
Test name
Test status
Simulation time 2489528842 ps
CPU time 2.17 seconds
Started Mar 19 03:07:15 PM PDT 24
Finished Mar 19 03:07:17 PM PDT 24
Peak memory 200724 kb
Host smart-1d1d5874-83a7-4eaf-b944-737034387e13
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299744938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2299744938
Directory /workspace/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.1054441391
Short name T612
Test name
Test status
Simulation time 69425899 ps
CPU time 0.91 seconds
Started Mar 19 03:07:23 PM PDT 24
Finished Mar 19 03:07:24 PM PDT 24
Peak memory 198536 kb
Host smart-1062f92f-f11f-40a9-866b-54e09e800131
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054441391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1054441391
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/25.pwrmgr_smoke.4058682645
Short name T404
Test name
Test status
Simulation time 68675303 ps
CPU time 0.63 seconds
Started Mar 19 03:07:33 PM PDT 24
Finished Mar 19 03:07:34 PM PDT 24
Peak memory 197920 kb
Host smart-0e7e3e85-df21-48e9-9432-b6099606d258
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058682645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.4058682645
Directory /workspace/25.pwrmgr_smoke/latest

Test location /workspace/coverage/default/25.pwrmgr_stress_all.2278031245
Short name T517
Test name
Test status
Simulation time 2216648129 ps
CPU time 3.82 seconds
Started Mar 19 03:07:24 PM PDT 24
Finished Mar 19 03:07:28 PM PDT 24
Peak memory 200788 kb
Host smart-7203ab8e-deb2-4c5a-b210-5c4c6ddcfab9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278031245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.2278031245
Directory /workspace/25.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup.108455302
Short name T556
Test name
Test status
Simulation time 237200794 ps
CPU time 0.87 seconds
Started Mar 19 03:07:28 PM PDT 24
Finished Mar 19 03:07:29 PM PDT 24
Peak memory 199020 kb
Host smart-b52cefb7-3de6-4582-a207-74831138a001
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108455302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.108455302
Directory /workspace/25.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/25.pwrmgr_wakeup_reset.1299960227
Short name T336
Test name
Test status
Simulation time 266965517 ps
CPU time 0.93 seconds
Started Mar 19 03:07:20 PM PDT 24
Finished Mar 19 03:07:21 PM PDT 24
Peak memory 199616 kb
Host smart-aa5e1060-d834-465a-a0fa-4ace8f1c5763
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299960227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.1299960227
Directory /workspace/25.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.1803857542
Short name T526
Test name
Test status
Simulation time 29459803 ps
CPU time 0.74 seconds
Started Mar 19 03:07:39 PM PDT 24
Finished Mar 19 03:07:40 PM PDT 24
Peak memory 198236 kb
Host smart-a106208d-2c53-4d85-a746-df48ac0cedc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803857542 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.1803857542
Directory /workspace/26.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.2705355265
Short name T134
Test name
Test status
Simulation time 74632958 ps
CPU time 0.72 seconds
Started Mar 19 03:07:37 PM PDT 24
Finished Mar 19 03:07:38 PM PDT 24
Peak memory 198924 kb
Host smart-6ea13e06-ab48-4c44-af9b-9f45385e799d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705355265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.2705355265
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.1438132350
Short name T826
Test name
Test status
Simulation time 31564874 ps
CPU time 0.62 seconds
Started Mar 19 03:07:43 PM PDT 24
Finished Mar 19 03:07:44 PM PDT 24
Peak memory 196756 kb
Host smart-93e33df0-4ea2-4585-a940-8e64344bf3cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438132350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.1438132350
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.590278187
Short name T465
Test name
Test status
Simulation time 1386408454 ps
CPU time 0.95 seconds
Started Mar 19 03:07:41 PM PDT 24
Finished Mar 19 03:07:42 PM PDT 24
Peak memory 197512 kb
Host smart-1d806a1e-393d-449e-b1cd-eefaa039caa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590278187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.590278187
Directory /workspace/26.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/26.pwrmgr_glitch.1572667067
Short name T806
Test name
Test status
Simulation time 38971288 ps
CPU time 0.6 seconds
Started Mar 19 03:07:32 PM PDT 24
Finished Mar 19 03:07:34 PM PDT 24
Peak memory 196840 kb
Host smart-9cf0c86f-1c3a-4b9c-8407-5c0bf88c1292
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572667067 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.1572667067
Directory /workspace/26.pwrmgr_glitch/latest

Test location /workspace/coverage/default/26.pwrmgr_global_esc.2647677735
Short name T69
Test name
Test status
Simulation time 43655917 ps
CPU time 0.65 seconds
Started Mar 19 03:07:30 PM PDT 24
Finished Mar 19 03:07:31 PM PDT 24
Peak memory 197524 kb
Host smart-fbee1092-be82-4e96-862c-25104d448137
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647677735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.2647677735
Directory /workspace/26.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.2412576570
Short name T525
Test name
Test status
Simulation time 95397325 ps
CPU time 0.7 seconds
Started Mar 19 03:07:42 PM PDT 24
Finished Mar 19 03:07:44 PM PDT 24
Peak memory 200776 kb
Host smart-48b2cf22-dfbe-43cc-9f0a-d6e37812c17e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412576570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.2412576570
Directory /workspace/26.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_reset.615877292
Short name T206
Test name
Test status
Simulation time 41243623 ps
CPU time 0.68 seconds
Started Mar 19 03:07:36 PM PDT 24
Finished Mar 19 03:07:37 PM PDT 24
Peak memory 198576 kb
Host smart-10be347f-bb0d-4a07-954a-3c19f8fb1f4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615877292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.615877292
Directory /workspace/26.pwrmgr_reset/latest

Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.3312913181
Short name T705
Test name
Test status
Simulation time 123419438 ps
CPU time 0.97 seconds
Started Mar 19 03:07:41 PM PDT 24
Finished Mar 19 03:07:42 PM PDT 24
Peak memory 208864 kb
Host smart-13b58cb9-ec66-467b-b426-e81f81eccec3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312913181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.3312913181
Directory /workspace/26.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.3658895468
Short name T532
Test name
Test status
Simulation time 278306689 ps
CPU time 1.48 seconds
Started Mar 19 03:07:30 PM PDT 24
Finished Mar 19 03:07:32 PM PDT 24
Peak memory 200304 kb
Host smart-53a9dbeb-5deb-43fa-995d-e2a190fad29d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658895468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_
cm_ctrl_config_regwen.3658895468
Directory /workspace/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1872837448
Short name T232
Test name
Test status
Simulation time 869801237 ps
CPU time 2.89 seconds
Started Mar 19 03:07:40 PM PDT 24
Finished Mar 19 03:07:43 PM PDT 24
Peak memory 200396 kb
Host smart-710d04c8-c686-47dc-8f87-3385dd93f38e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872837448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1872837448
Directory /workspace/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.89827219
Short name T207
Test name
Test status
Simulation time 1084303280 ps
CPU time 2.12 seconds
Started Mar 19 03:07:36 PM PDT 24
Finished Mar 19 03:07:38 PM PDT 24
Peak memory 200628 kb
Host smart-2b6a033e-990a-4164-9736-442af17896f5
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89827219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.89827219
Directory /workspace/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.2477175198
Short name T273
Test name
Test status
Simulation time 74194433 ps
CPU time 0.95 seconds
Started Mar 19 03:07:24 PM PDT 24
Finished Mar 19 03:07:26 PM PDT 24
Peak memory 198512 kb
Host smart-c844fa56-da70-461b-92da-e60b1bbc859c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477175198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2477175198
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/26.pwrmgr_smoke.1349643649
Short name T638
Test name
Test status
Simulation time 90417393 ps
CPU time 0.63 seconds
Started Mar 19 03:07:39 PM PDT 24
Finished Mar 19 03:07:39 PM PDT 24
Peak memory 197980 kb
Host smart-af648cbc-b049-4fc3-8ca5-e89a7a569413
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349643649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.1349643649
Directory /workspace/26.pwrmgr_smoke/latest

Test location /workspace/coverage/default/26.pwrmgr_stress_all.2776755429
Short name T524
Test name
Test status
Simulation time 1896884631 ps
CPU time 3.11 seconds
Started Mar 19 03:07:36 PM PDT 24
Finished Mar 19 03:07:40 PM PDT 24
Peak memory 200676 kb
Host smart-c59c7112-e96b-4953-b1d7-6b1c9e88b1b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776755429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all.2776755429
Directory /workspace/26.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/26.pwrmgr_wakeup_reset.1708720861
Short name T448
Test name
Test status
Simulation time 283070808 ps
CPU time 1.01 seconds
Started Mar 19 03:07:29 PM PDT 24
Finished Mar 19 03:07:30 PM PDT 24
Peak memory 200512 kb
Host smart-2fa22d65-9bdc-4861-852e-e60f569439ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708720861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup_reset.1708720861
Directory /workspace/26.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.1119645416
Short name T593
Test name
Test status
Simulation time 68552864 ps
CPU time 0.64 seconds
Started Mar 19 03:07:28 PM PDT 24
Finished Mar 19 03:07:28 PM PDT 24
Peak memory 197896 kb
Host smart-aa099226-469d-4206-90bd-7ed126040278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119645416 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.1119645416
Directory /workspace/27.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.2797713661
Short name T21
Test name
Test status
Simulation time 77638071 ps
CPU time 0.69 seconds
Started Mar 19 03:07:43 PM PDT 24
Finished Mar 19 03:07:44 PM PDT 24
Peak memory 198596 kb
Host smart-88b4975d-43ee-403b-8a1c-62d796ff31e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797713661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_dis
able_rom_integrity_check.2797713661
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.2785119082
Short name T375
Test name
Test status
Simulation time 29143598 ps
CPU time 0.64 seconds
Started Mar 19 03:07:42 PM PDT 24
Finished Mar 19 03:07:43 PM PDT 24
Peak memory 196756 kb
Host smart-c8317783-7dc5-47e3-8d01-40cd794ff3e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785119082 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.2785119082
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.1338914807
Short name T182
Test name
Test status
Simulation time 835026044 ps
CPU time 0.99 seconds
Started Mar 19 03:07:38 PM PDT 24
Finished Mar 19 03:07:39 PM PDT 24
Peak memory 197828 kb
Host smart-d820b419-c120-4b91-9a00-4d5c1b3b6942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338914807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.1338914807
Directory /workspace/27.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/27.pwrmgr_glitch.809885342
Short name T762
Test name
Test status
Simulation time 40179890 ps
CPU time 0.68 seconds
Started Mar 19 03:07:41 PM PDT 24
Finished Mar 19 03:07:42 PM PDT 24
Peak memory 197408 kb
Host smart-c2cf282a-4412-4da4-af3a-6e1242f63a9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809885342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.809885342
Directory /workspace/27.pwrmgr_glitch/latest

Test location /workspace/coverage/default/27.pwrmgr_global_esc.3377729152
Short name T107
Test name
Test status
Simulation time 40730925 ps
CPU time 0.64 seconds
Started Mar 19 03:07:39 PM PDT 24
Finished Mar 19 03:07:40 PM PDT 24
Peak memory 197572 kb
Host smart-b3692090-bd7b-4e50-89ca-5a45d6b7ad41
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377729152 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.3377729152
Directory /workspace/27.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.211846779
Short name T706
Test name
Test status
Simulation time 74125292 ps
CPU time 0.63 seconds
Started Mar 19 03:07:25 PM PDT 24
Finished Mar 19 03:07:26 PM PDT 24
Peak memory 200784 kb
Host smart-a9dfd97b-a879-4215-ba46-fb308e0c26bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211846779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_invali
d.211846779
Directory /workspace/27.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_lowpower_wakeup_race.1746138692
Short name T352
Test name
Test status
Simulation time 105415550 ps
CPU time 0.84 seconds
Started Mar 19 03:07:38 PM PDT 24
Finished Mar 19 03:07:39 PM PDT 24
Peak memory 197808 kb
Host smart-729dd5b8-b8df-451e-b00d-e2a24d418511
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746138692 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_w
akeup_race.1746138692
Directory /workspace/27.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/27.pwrmgr_reset.986273076
Short name T809
Test name
Test status
Simulation time 94083053 ps
CPU time 0.96 seconds
Started Mar 19 03:07:45 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 198612 kb
Host smart-cdb3f1d0-e0d5-464a-9815-5189b9415800
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986273076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.986273076
Directory /workspace/27.pwrmgr_reset/latest

Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.1951145073
Short name T191
Test name
Test status
Simulation time 125668983 ps
CPU time 0.87 seconds
Started Mar 19 03:07:40 PM PDT 24
Finished Mar 19 03:07:40 PM PDT 24
Peak memory 208884 kb
Host smart-87593ac7-0130-4124-8c3a-732fed171e39
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951145073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.1951145073
Directory /workspace/27.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.339499265
Short name T610
Test name
Test status
Simulation time 143263570 ps
CPU time 0.64 seconds
Started Mar 19 03:07:44 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 198048 kb
Host smart-c1a0fa85-b8cf-4d6b-a17e-b28754a75987
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339499265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_c
m_ctrl_config_regwen.339499265
Directory /workspace/27.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2560886828
Short name T539
Test name
Test status
Simulation time 861050076 ps
CPU time 2.46 seconds
Started Mar 19 03:07:40 PM PDT 24
Finished Mar 19 03:07:42 PM PDT 24
Peak memory 200616 kb
Host smart-bf696969-9cf1-4144-8f30-4e7aa08bb97f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560886828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2560886828
Directory /workspace/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2964710813
Short name T522
Test name
Test status
Simulation time 884209340 ps
CPU time 3.3 seconds
Started Mar 19 03:07:36 PM PDT 24
Finished Mar 19 03:07:40 PM PDT 24
Peak memory 200636 kb
Host smart-ec91bd9f-f7ef-4bcd-bc37-b249c5152c6f
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964710813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2964710813
Directory /workspace/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.3695194412
Short name T315
Test name
Test status
Simulation time 97035127 ps
CPU time 0.9 seconds
Started Mar 19 03:07:45 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 198716 kb
Host smart-db5d8fcd-b86a-4504-a2b6-2a6084d43983
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695194412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3695194412
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/27.pwrmgr_smoke.3796859606
Short name T59
Test name
Test status
Simulation time 71482291 ps
CPU time 0.65 seconds
Started Mar 19 03:07:37 PM PDT 24
Finished Mar 19 03:07:38 PM PDT 24
Peak memory 197888 kb
Host smart-cf916cc4-1266-4c8a-999b-c5b42bf4c6d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796859606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.3796859606
Directory /workspace/27.pwrmgr_smoke/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup.504942265
Short name T778
Test name
Test status
Simulation time 340695033 ps
CPU time 0.86 seconds
Started Mar 19 03:07:36 PM PDT 24
Finished Mar 19 03:07:37 PM PDT 24
Peak memory 199068 kb
Host smart-d81a4280-d9eb-466a-a4fb-ac5cc9d33140
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504942265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.504942265
Directory /workspace/27.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/27.pwrmgr_wakeup_reset.3791078659
Short name T258
Test name
Test status
Simulation time 531686890 ps
CPU time 0.9 seconds
Started Mar 19 03:07:27 PM PDT 24
Finished Mar 19 03:07:28 PM PDT 24
Peak memory 199696 kb
Host smart-32d7f3ba-e173-46a8-b254-9da004b7236e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791078659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.3791078659
Directory /workspace/27.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.3956707844
Short name T717
Test name
Test status
Simulation time 56819543 ps
CPU time 0.79 seconds
Started Mar 19 03:07:30 PM PDT 24
Finished Mar 19 03:07:31 PM PDT 24
Peak memory 198008 kb
Host smart-8f6dd9e7-355a-4e0f-b0bd-6acb36f1871a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956707844 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.3956707844
Directory /workspace/28.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.716188435
Short name T571
Test name
Test status
Simulation time 210521688 ps
CPU time 0.72 seconds
Started Mar 19 03:07:26 PM PDT 24
Finished Mar 19 03:07:27 PM PDT 24
Peak memory 198628 kb
Host smart-520230ae-9100-464d-9293-2b5e662a79be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716188435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_disa
ble_rom_integrity_check.716188435
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.1050509587
Short name T432
Test name
Test status
Simulation time 54432202 ps
CPU time 0.6 seconds
Started Mar 19 03:07:35 PM PDT 24
Finished Mar 19 03:07:35 PM PDT 24
Peak memory 197500 kb
Host smart-a04c7a75-fe80-4b16-a95f-233aeb457ec4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050509587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.1050509587
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.3702170002
Short name T808
Test name
Test status
Simulation time 185889103 ps
CPU time 0.95 seconds
Started Mar 19 03:07:37 PM PDT 24
Finished Mar 19 03:07:38 PM PDT 24
Peak memory 197528 kb
Host smart-8510cd38-c3ac-4c58-b8c7-f6e060cecd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702170002 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.3702170002
Directory /workspace/28.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/28.pwrmgr_glitch.3769094115
Short name T329
Test name
Test status
Simulation time 84418720 ps
CPU time 0.59 seconds
Started Mar 19 03:07:38 PM PDT 24
Finished Mar 19 03:07:38 PM PDT 24
Peak memory 197540 kb
Host smart-7e2ac478-28e7-4e51-971c-f45dc6716ede
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769094115 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.3769094115
Directory /workspace/28.pwrmgr_glitch/latest

Test location /workspace/coverage/default/28.pwrmgr_global_esc.3032092150
Short name T458
Test name
Test status
Simulation time 367763485 ps
CPU time 0.65 seconds
Started Mar 19 03:07:48 PM PDT 24
Finished Mar 19 03:07:49 PM PDT 24
Peak memory 197832 kb
Host smart-49a4bbba-8cd9-45f8-acff-cec48c63b983
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032092150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.3032092150
Directory /workspace/28.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.607751693
Short name T26
Test name
Test status
Simulation time 42520952 ps
CPU time 0.76 seconds
Started Mar 19 03:07:37 PM PDT 24
Finished Mar 19 03:07:38 PM PDT 24
Peak memory 200616 kb
Host smart-76bdacc4-18f9-4aef-8fee-23e3029b1495
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607751693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_invali
d.607751693
Directory /workspace/28.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_lowpower_wakeup_race.2764864514
Short name T149
Test name
Test status
Simulation time 58654101 ps
CPU time 0.62 seconds
Started Mar 19 03:07:43 PM PDT 24
Finished Mar 19 03:07:44 PM PDT 24
Peak memory 197876 kb
Host smart-9c244dc0-cbf8-4071-9cee-968e53947f6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764864514 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_w
akeup_race.2764864514
Directory /workspace/28.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/28.pwrmgr_reset.3167638937
Short name T150
Test name
Test status
Simulation time 131093999 ps
CPU time 0.66 seconds
Started Mar 19 03:07:41 PM PDT 24
Finished Mar 19 03:07:41 PM PDT 24
Peak memory 198044 kb
Host smart-3901659f-153b-43ef-9b97-d257ef8e8184
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167638937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.3167638937
Directory /workspace/28.pwrmgr_reset/latest

Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.1925002148
Short name T254
Test name
Test status
Simulation time 105187255 ps
CPU time 0.88 seconds
Started Mar 19 03:07:41 PM PDT 24
Finished Mar 19 03:07:42 PM PDT 24
Peak memory 208856 kb
Host smart-4a3c788a-54c1-438d-a4df-8603dde19836
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925002148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.1925002148
Directory /workspace/28.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.1322292347
Short name T379
Test name
Test status
Simulation time 47653022 ps
CPU time 0.77 seconds
Started Mar 19 03:07:36 PM PDT 24
Finished Mar 19 03:07:37 PM PDT 24
Peak memory 198496 kb
Host smart-07f9f2ca-8d31-488c-b570-6a18a09e3431
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322292347 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_
cm_ctrl_config_regwen.1322292347
Directory /workspace/28.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1140356423
Short name T384
Test name
Test status
Simulation time 1447188231 ps
CPU time 1.98 seconds
Started Mar 19 03:07:33 PM PDT 24
Finished Mar 19 03:07:35 PM PDT 24
Peak memory 200692 kb
Host smart-171f2901-b856-49c1-96da-c1278cee456d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140356423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1140356423
Directory /workspace/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3744257718
Short name T577
Test name
Test status
Simulation time 884266649 ps
CPU time 3.25 seconds
Started Mar 19 03:07:33 PM PDT 24
Finished Mar 19 03:07:36 PM PDT 24
Peak memory 200640 kb
Host smart-cbdfbd4b-2bb6-4391-9475-40c9454bbbd9
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744257718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3744257718
Directory /workspace/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.2046539868
Short name T633
Test name
Test status
Simulation time 71296723 ps
CPU time 0.8 seconds
Started Mar 19 03:07:41 PM PDT 24
Finished Mar 19 03:07:41 PM PDT 24
Peak memory 198580 kb
Host smart-073f3d56-9ef0-492c-b95a-a4241eeec07d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046539868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2046539868
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/28.pwrmgr_smoke.2255475584
Short name T551
Test name
Test status
Simulation time 31694720 ps
CPU time 0.7 seconds
Started Mar 19 03:07:30 PM PDT 24
Finished Mar 19 03:07:31 PM PDT 24
Peak memory 198728 kb
Host smart-fef27009-79b0-4722-b2b0-1e4d13a284ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255475584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.2255475584
Directory /workspace/28.pwrmgr_smoke/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup.3763730058
Short name T61
Test name
Test status
Simulation time 161208349 ps
CPU time 0.73 seconds
Started Mar 19 03:07:44 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 197744 kb
Host smart-1cdb836c-68ae-4c50-b540-a1bbabf9c75b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763730058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.3763730058
Directory /workspace/28.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/28.pwrmgr_wakeup_reset.544762622
Short name T246
Test name
Test status
Simulation time 239595611 ps
CPU time 1.34 seconds
Started Mar 19 03:07:38 PM PDT 24
Finished Mar 19 03:07:39 PM PDT 24
Peak memory 199744 kb
Host smart-a710a171-0741-4e87-a5c3-5f281ad5ef99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544762622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.544762622
Directory /workspace/28.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.2820573163
Short name T661
Test name
Test status
Simulation time 51120596 ps
CPU time 0.64 seconds
Started Mar 19 03:07:32 PM PDT 24
Finished Mar 19 03:07:34 PM PDT 24
Peak memory 197928 kb
Host smart-20823c25-48bc-4c96-a0d5-562c6fdc1525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820573163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.2820573163
Directory /workspace/29.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.2109952976
Short name T548
Test name
Test status
Simulation time 54021512 ps
CPU time 0.79 seconds
Started Mar 19 03:07:39 PM PDT 24
Finished Mar 19 03:07:40 PM PDT 24
Peak memory 198616 kb
Host smart-5018df17-8b83-4643-a604-adcb5fd6b30b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109952976 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.2109952976
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.1262560628
Short name T488
Test name
Test status
Simulation time 37453263 ps
CPU time 0.6 seconds
Started Mar 19 03:07:30 PM PDT 24
Finished Mar 19 03:07:31 PM PDT 24
Peak memory 197444 kb
Host smart-a5b46364-261e-4dea-a125-3abb48a0e873
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262560628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst
_malfunc.1262560628
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.3524515651
Short name T380
Test name
Test status
Simulation time 1009583829 ps
CPU time 1.05 seconds
Started Mar 19 03:07:19 PM PDT 24
Finished Mar 19 03:07:21 PM PDT 24
Peak memory 197544 kb
Host smart-1e3b81ea-eb31-4b05-adeb-c14412a5f415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524515651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.3524515651
Directory /workspace/29.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/29.pwrmgr_glitch.651917203
Short name T7
Test name
Test status
Simulation time 84791024 ps
CPU time 0.64 seconds
Started Mar 19 03:07:39 PM PDT 24
Finished Mar 19 03:07:40 PM PDT 24
Peak memory 196812 kb
Host smart-19145c73-b1b3-4348-8598-8a2c8c1cf0cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651917203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.651917203
Directory /workspace/29.pwrmgr_glitch/latest

Test location /workspace/coverage/default/29.pwrmgr_global_esc.2757964560
Short name T620
Test name
Test status
Simulation time 67785344 ps
CPU time 0.61 seconds
Started Mar 19 03:07:43 PM PDT 24
Finished Mar 19 03:07:44 PM PDT 24
Peak memory 197536 kb
Host smart-dc5e3f97-5fdd-436a-a836-fc13aafcf2e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757964560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.2757964560
Directory /workspace/29.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.725416233
Short name T692
Test name
Test status
Simulation time 42595573 ps
CPU time 0.74 seconds
Started Mar 19 03:07:41 PM PDT 24
Finished Mar 19 03:07:42 PM PDT 24
Peak memory 200768 kb
Host smart-dfaf2ea4-a64e-4d68-93b7-b7d691bfd575
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725416233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_invali
d.725416233
Directory /workspace/29.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_lowpower_wakeup_race.1762085787
Short name T481
Test name
Test status
Simulation time 185539440 ps
CPU time 1.04 seconds
Started Mar 19 03:07:47 PM PDT 24
Finished Mar 19 03:07:48 PM PDT 24
Peak memory 198980 kb
Host smart-83928ceb-8e14-4810-9fee-0527d9eda2d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762085787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_w
akeup_race.1762085787
Directory /workspace/29.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/29.pwrmgr_reset.3871744440
Short name T322
Test name
Test status
Simulation time 103905149 ps
CPU time 0.93 seconds
Started Mar 19 03:07:38 PM PDT 24
Finished Mar 19 03:07:39 PM PDT 24
Peak memory 199144 kb
Host smart-36536d71-7a9c-4abf-98e2-c473def0c594
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871744440 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.3871744440
Directory /workspace/29.pwrmgr_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.3658987760
Short name T820
Test name
Test status
Simulation time 263936795 ps
CPU time 0.8 seconds
Started Mar 19 03:07:27 PM PDT 24
Finished Mar 19 03:07:28 PM PDT 24
Peak memory 208952 kb
Host smart-dfb87fb5-0385-481a-9eb6-6a989441ac8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658987760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.3658987760
Directory /workspace/29.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.1733438489
Short name T565
Test name
Test status
Simulation time 36044781 ps
CPU time 0.67 seconds
Started Mar 19 03:07:29 PM PDT 24
Finished Mar 19 03:07:30 PM PDT 24
Peak memory 197952 kb
Host smart-38efda86-47c4-42e9-9527-eacce587dcfc
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733438489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_
cm_ctrl_config_regwen.1733438489
Directory /workspace/29.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1804003130
Short name T828
Test name
Test status
Simulation time 1056196378 ps
CPU time 2.46 seconds
Started Mar 19 03:07:43 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 200560 kb
Host smart-2e8069cb-7380-49e7-8ecf-413869bf7248
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804003130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1804003130
Directory /workspace/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2582818072
Short name T861
Test name
Test status
Simulation time 872894254 ps
CPU time 3.31 seconds
Started Mar 19 03:07:43 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 200544 kb
Host smart-bfc24b14-cb28-48ce-be1b-66f51cb5d0e2
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582818072 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2582818072
Directory /workspace/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.4013532146
Short name T618
Test name
Test status
Simulation time 74636478 ps
CPU time 0.94 seconds
Started Mar 19 03:07:47 PM PDT 24
Finished Mar 19 03:07:48 PM PDT 24
Peak memory 199012 kb
Host smart-29f42d32-ccda-472d-a719-5107da15b598
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013532146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4013532146
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/29.pwrmgr_smoke.4276061638
Short name T387
Test name
Test status
Simulation time 54477105 ps
CPU time 0.65 seconds
Started Mar 19 03:07:38 PM PDT 24
Finished Mar 19 03:07:38 PM PDT 24
Peak memory 197884 kb
Host smart-59d9a54d-c579-477e-b735-213fdf19bcee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276061638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.4276061638
Directory /workspace/29.pwrmgr_smoke/latest

Test location /workspace/coverage/default/29.pwrmgr_stress_all.4026382710
Short name T462
Test name
Test status
Simulation time 2888968218 ps
CPU time 3.42 seconds
Started Mar 19 03:07:53 PM PDT 24
Finished Mar 19 03:07:56 PM PDT 24
Peak memory 200732 kb
Host smart-4debdae7-ab96-4f2b-af9d-ce5e93caf989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026382710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.4026382710
Directory /workspace/29.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/29.pwrmgr_stress_all_with_rand_reset.2102109197
Short name T20
Test name
Test status
Simulation time 8971570321 ps
CPU time 5.06 seconds
Started Mar 19 03:07:30 PM PDT 24
Finished Mar 19 03:07:35 PM PDT 24
Peak memory 200916 kb
Host smart-5e4b1955-16b4-4783-840e-6cdbbcf40721
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102109197 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all_with_rand_reset.2102109197
Directory /workspace/29.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup.605159288
Short name T140
Test name
Test status
Simulation time 96908002 ps
CPU time 0.91 seconds
Started Mar 19 03:07:36 PM PDT 24
Finished Mar 19 03:07:37 PM PDT 24
Peak memory 198476 kb
Host smart-ae0f32fb-61ed-444d-b9aa-e0c6919bae56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605159288 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.605159288
Directory /workspace/29.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/29.pwrmgr_wakeup_reset.2106278557
Short name T798
Test name
Test status
Simulation time 307942300 ps
CPU time 1.11 seconds
Started Mar 19 03:07:40 PM PDT 24
Finished Mar 19 03:07:42 PM PDT 24
Peak memory 199464 kb
Host smart-593eb398-a9ca-4d9b-923e-28f81dee7716
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106278557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.2106278557
Directory /workspace/29.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.1002467883
Short name T422
Test name
Test status
Simulation time 33627393 ps
CPU time 0.73 seconds
Started Mar 19 03:06:15 PM PDT 24
Finished Mar 19 03:06:16 PM PDT 24
Peak memory 197964 kb
Host smart-a6f2ff43-e58e-435b-bbc2-a648677b4905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002467883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.1002467883
Directory /workspace/3.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.3484611330
Short name T536
Test name
Test status
Simulation time 72818839 ps
CPU time 0.71 seconds
Started Mar 19 03:06:09 PM PDT 24
Finished Mar 19 03:06:10 PM PDT 24
Peak memory 198560 kb
Host smart-6b47486f-18eb-47c8-bdbf-ed67ee680a81
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484611330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disa
ble_rom_integrity_check.3484611330
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.3504725593
Short name T363
Test name
Test status
Simulation time 42714111 ps
CPU time 0.64 seconds
Started Mar 19 03:06:22 PM PDT 24
Finished Mar 19 03:06:24 PM PDT 24
Peak memory 197456 kb
Host smart-ef31aebc-b4f3-4f37-9488-2a2fbe99cc6c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504725593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.3504725593
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.1214974938
Short name T713
Test name
Test status
Simulation time 172129744 ps
CPU time 0.94 seconds
Started Mar 19 03:06:10 PM PDT 24
Finished Mar 19 03:06:11 PM PDT 24
Peak memory 197520 kb
Host smart-dc3279ef-cbb7-41c8-b760-5b8c7956e210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214974938 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.1214974938
Directory /workspace/3.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/3.pwrmgr_glitch.198517338
Short name T671
Test name
Test status
Simulation time 46185715 ps
CPU time 0.65 seconds
Started Mar 19 03:06:25 PM PDT 24
Finished Mar 19 03:06:26 PM PDT 24
Peak memory 196760 kb
Host smart-e96c4a98-0321-4137-acff-9fd8808add22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198517338 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.198517338
Directory /workspace/3.pwrmgr_glitch/latest

Test location /workspace/coverage/default/3.pwrmgr_global_esc.2136770453
Short name T838
Test name
Test status
Simulation time 48711720 ps
CPU time 0.64 seconds
Started Mar 19 03:06:19 PM PDT 24
Finished Mar 19 03:06:21 PM PDT 24
Peak memory 197532 kb
Host smart-df53dbc3-3918-48c2-9c2e-0e435a0d26cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136770453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.2136770453
Directory /workspace/3.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.1228326934
Short name T405
Test name
Test status
Simulation time 45683395 ps
CPU time 0.74 seconds
Started Mar 19 03:06:19 PM PDT 24
Finished Mar 19 03:06:21 PM PDT 24
Peak memory 200760 kb
Host smart-24b5308a-5d4d-4298-91b7-5301ac0c3fd3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228326934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.1228326934
Directory /workspace/3.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_lowpower_wakeup_race.3090345711
Short name T761
Test name
Test status
Simulation time 73505743 ps
CPU time 0.75 seconds
Started Mar 19 03:06:14 PM PDT 24
Finished Mar 19 03:06:15 PM PDT 24
Peak memory 197540 kb
Host smart-5526223b-fe9c-4184-998a-cfb9368a55a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090345711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wa
keup_race.3090345711
Directory /workspace/3.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/3.pwrmgr_reset.238540429
Short name T614
Test name
Test status
Simulation time 107081873 ps
CPU time 0.78 seconds
Started Mar 19 03:06:17 PM PDT 24
Finished Mar 19 03:06:18 PM PDT 24
Peak memory 198540 kb
Host smart-ee861a34-f6d2-4db9-8f16-8a6600c0c354
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238540429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.238540429
Directory /workspace/3.pwrmgr_reset/latest

Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.1836913147
Short name T569
Test name
Test status
Simulation time 172032179 ps
CPU time 0.76 seconds
Started Mar 19 03:06:21 PM PDT 24
Finished Mar 19 03:06:23 PM PDT 24
Peak memory 208972 kb
Host smart-1f16a433-ff15-45bb-a416-699f1dca6a0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836913147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.1836913147
Directory /workspace/3.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm.4179540267
Short name T23
Test name
Test status
Simulation time 581639503 ps
CPU time 1.92 seconds
Started Mar 19 03:06:14 PM PDT 24
Finished Mar 19 03:06:16 PM PDT 24
Peak memory 218392 kb
Host smart-ef8cf053-2623-4d59-ac4c-e2f46a400107
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179540267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.4179540267
Directory /workspace/3.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.1212830932
Short name T613
Test name
Test status
Simulation time 135546203 ps
CPU time 1.08 seconds
Started Mar 19 03:06:34 PM PDT 24
Finished Mar 19 03:06:35 PM PDT 24
Peak memory 199648 kb
Host smart-5524d179-e466-40a0-bce7-3021f6025d99
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212830932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_c
m_ctrl_config_regwen.1212830932
Directory /workspace/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1187962650
Short name T704
Test name
Test status
Simulation time 1032075928 ps
CPU time 2.38 seconds
Started Mar 19 03:06:06 PM PDT 24
Finished Mar 19 03:06:08 PM PDT 24
Peak memory 200464 kb
Host smart-3a10d971-c488-4d0b-8f88-79d47f968b23
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187962650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1187962650
Directory /workspace/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3929075657
Short name T429
Test name
Test status
Simulation time 1181806041 ps
CPU time 2 seconds
Started Mar 19 03:06:20 PM PDT 24
Finished Mar 19 03:06:23 PM PDT 24
Peak memory 200696 kb
Host smart-a37f409a-a5ee-45a4-b262-e1ffa6f39ab6
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929075657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3929075657
Directory /workspace/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.3826354015
Short name T300
Test name
Test status
Simulation time 138110853 ps
CPU time 0.85 seconds
Started Mar 19 03:06:14 PM PDT 24
Finished Mar 19 03:06:15 PM PDT 24
Peak memory 199076 kb
Host smart-6fe7a032-2a82-4f20-a84a-652c3b03c07e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826354015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3826354015
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/3.pwrmgr_smoke.128083025
Short name T324
Test name
Test status
Simulation time 36845034 ps
CPU time 0.64 seconds
Started Mar 19 03:06:08 PM PDT 24
Finished Mar 19 03:06:09 PM PDT 24
Peak memory 197896 kb
Host smart-89e91db1-d69c-48a8-ada9-3395251b35fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128083025 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.128083025
Directory /workspace/3.pwrmgr_smoke/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup.2936745913
Short name T722
Test name
Test status
Simulation time 384331421 ps
CPU time 0.85 seconds
Started Mar 19 03:06:15 PM PDT 24
Finished Mar 19 03:06:16 PM PDT 24
Peak memory 198952 kb
Host smart-20815172-c75b-49fd-a4e7-07e21ec39788
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936745913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.2936745913
Directory /workspace/3.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/3.pwrmgr_wakeup_reset.3482892848
Short name T609
Test name
Test status
Simulation time 277463442 ps
CPU time 1.32 seconds
Started Mar 19 03:06:08 PM PDT 24
Finished Mar 19 03:06:09 PM PDT 24
Peak memory 200584 kb
Host smart-f9e464b0-a6db-4c94-8509-34c51974d003
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482892848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.3482892848
Directory /workspace/3.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.1533157897
Short name T608
Test name
Test status
Simulation time 28619266 ps
CPU time 0.68 seconds
Started Mar 19 03:07:46 PM PDT 24
Finished Mar 19 03:07:47 PM PDT 24
Peak memory 197992 kb
Host smart-f3787cb5-4c78-4151-ae71-f3de9e8b4e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533157897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.1533157897
Directory /workspace/30.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.851574234
Short name T723
Test name
Test status
Simulation time 43680658 ps
CPU time 0.81 seconds
Started Mar 19 03:07:39 PM PDT 24
Finished Mar 19 03:07:40 PM PDT 24
Peak memory 198580 kb
Host smart-e66e006a-01e5-43a4-87c6-ca8657d3332c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851574234 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disa
ble_rom_integrity_check.851574234
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.3026432772
Short name T104
Test name
Test status
Simulation time 40020866 ps
CPU time 0.6 seconds
Started Mar 19 03:07:53 PM PDT 24
Finished Mar 19 03:07:54 PM PDT 24
Peak memory 197444 kb
Host smart-3f9e7403-733d-4a20-9e55-a4fe0b4538c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026432772 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.3026432772
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.523953101
Short name T582
Test name
Test status
Simulation time 308314833 ps
CPU time 0.94 seconds
Started Mar 19 03:07:45 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 197504 kb
Host smart-d927cc7f-2c23-405d-8577-c287c10bd352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523953101 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.523953101
Directory /workspace/30.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/30.pwrmgr_glitch.970812238
Short name T769
Test name
Test status
Simulation time 34711878 ps
CPU time 0.61 seconds
Started Mar 19 03:07:48 PM PDT 24
Finished Mar 19 03:07:49 PM PDT 24
Peak memory 196760 kb
Host smart-f9e1912d-aa7a-402a-a387-2aea498e7fe7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970812238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.970812238
Directory /workspace/30.pwrmgr_glitch/latest

Test location /workspace/coverage/default/30.pwrmgr_global_esc.3956635781
Short name T472
Test name
Test status
Simulation time 43708270 ps
CPU time 0.65 seconds
Started Mar 19 03:07:40 PM PDT 24
Finished Mar 19 03:07:40 PM PDT 24
Peak memory 197844 kb
Host smart-733fedfd-456b-4e66-bb1c-a21bf2dbcbde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956635781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.3956635781
Directory /workspace/30.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.1270381208
Short name T772
Test name
Test status
Simulation time 54421918 ps
CPU time 0.72 seconds
Started Mar 19 03:07:36 PM PDT 24
Finished Mar 19 03:07:37 PM PDT 24
Peak memory 200772 kb
Host smart-5bb1721b-818a-4e61-9484-2a1b644c6ff6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270381208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.1270381208
Directory /workspace/30.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_lowpower_wakeup_race.130384088
Short name T742
Test name
Test status
Simulation time 119458395 ps
CPU time 0.69 seconds
Started Mar 19 03:07:41 PM PDT 24
Finished Mar 19 03:07:42 PM PDT 24
Peak memory 197284 kb
Host smart-316b6cce-1c9b-4525-a142-daedaae7dda8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130384088 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_wa
keup_race.130384088
Directory /workspace/30.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/30.pwrmgr_reset.2690842804
Short name T795
Test name
Test status
Simulation time 121580897 ps
CPU time 0.86 seconds
Started Mar 19 03:07:44 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 199480 kb
Host smart-dbad77f4-ca62-40ca-b944-8c6dc059c85a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690842804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.2690842804
Directory /workspace/30.pwrmgr_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.2711153738
Short name T508
Test name
Test status
Simulation time 501768585 ps
CPU time 0.83 seconds
Started Mar 19 03:07:44 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 208944 kb
Host smart-d7ed46e6-31c8-41c6-89ab-69baf8956164
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711153738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.2711153738
Directory /workspace/30.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.1519304625
Short name T558
Test name
Test status
Simulation time 231486542 ps
CPU time 0.96 seconds
Started Mar 19 03:07:39 PM PDT 24
Finished Mar 19 03:07:40 PM PDT 24
Peak memory 199472 kb
Host smart-f8202744-9d5e-4688-ac8f-7cfff4363b09
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519304625 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_
cm_ctrl_config_regwen.1519304625
Directory /workspace/30.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.589147294
Short name T553
Test name
Test status
Simulation time 774442880 ps
CPU time 3 seconds
Started Mar 19 03:07:39 PM PDT 24
Finished Mar 19 03:07:42 PM PDT 24
Peak memory 200656 kb
Host smart-5694745e-83a5-42bd-ad0b-dabf8b954fa8
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589147294 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.589147294
Directory /workspace/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3212496393
Short name T544
Test name
Test status
Simulation time 1191404793 ps
CPU time 1.94 seconds
Started Mar 19 03:08:09 PM PDT 24
Finished Mar 19 03:08:11 PM PDT 24
Peak memory 200668 kb
Host smart-14896fb4-b3c2-49ad-bad1-17d1b6dd61be
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212496393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3212496393
Directory /workspace/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.3967646073
Short name T419
Test name
Test status
Simulation time 401919374 ps
CPU time 0.88 seconds
Started Mar 19 03:07:47 PM PDT 24
Finished Mar 19 03:07:48 PM PDT 24
Peak memory 198588 kb
Host smart-44acf49e-3607-4d95-83e7-8ca90b5af9e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967646073 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3967646073
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/30.pwrmgr_smoke.4247634050
Short name T665
Test name
Test status
Simulation time 32630547 ps
CPU time 0.72 seconds
Started Mar 19 03:07:41 PM PDT 24
Finished Mar 19 03:07:42 PM PDT 24
Peak memory 197880 kb
Host smart-68a99865-92a5-4651-9f26-170bdf10a39b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247634050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.4247634050
Directory /workspace/30.pwrmgr_smoke/latest

Test location /workspace/coverage/default/30.pwrmgr_stress_all_with_rand_reset.2615529799
Short name T103
Test name
Test status
Simulation time 35162916972 ps
CPU time 15.54 seconds
Started Mar 19 03:07:48 PM PDT 24
Finished Mar 19 03:08:04 PM PDT 24
Peak memory 200872 kb
Host smart-f8344c10-cad2-4153-856b-093b529f5236
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615529799 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all_with_rand_reset.2615529799
Directory /workspace/30.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup.2970536686
Short name T850
Test name
Test status
Simulation time 309490526 ps
CPU time 1.09 seconds
Started Mar 19 03:07:31 PM PDT 24
Finished Mar 19 03:07:32 PM PDT 24
Peak memory 198984 kb
Host smart-076df881-3c71-4a8a-9a87-64cfbe11d9af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970536686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup.2970536686
Directory /workspace/30.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/30.pwrmgr_wakeup_reset.4028707521
Short name T410
Test name
Test status
Simulation time 553867453 ps
CPU time 1.21 seconds
Started Mar 19 03:07:31 PM PDT 24
Finished Mar 19 03:07:32 PM PDT 24
Peak memory 200584 kb
Host smart-8797f68f-9aaa-42c6-a592-19f9efe0b37f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028707521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.4028707521
Directory /workspace/30.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.1919034079
Short name T161
Test name
Test status
Simulation time 20907857 ps
CPU time 0.7 seconds
Started Mar 19 03:07:54 PM PDT 24
Finished Mar 19 03:07:55 PM PDT 24
Peak memory 197972 kb
Host smart-a4a40821-0305-4189-8ed0-1d1d832382c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919034079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.1919034079
Directory /workspace/31.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.435899566
Short name T344
Test name
Test status
Simulation time 141937208 ps
CPU time 0.69 seconds
Started Mar 19 03:07:46 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 197960 kb
Host smart-1e3066f8-3410-47f6-9265-5dc65064536e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435899566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_disa
ble_rom_integrity_check.435899566
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.1925732174
Short name T272
Test name
Test status
Simulation time 28778286 ps
CPU time 0.63 seconds
Started Mar 19 03:07:57 PM PDT 24
Finished Mar 19 03:07:59 PM PDT 24
Peak memory 197440 kb
Host smart-e7c1e2ee-9ae9-4507-a2e6-ef0d1728ddfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925732174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.1925732174
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.2238973299
Short name T475
Test name
Test status
Simulation time 165411229 ps
CPU time 0.94 seconds
Started Mar 19 03:07:45 PM PDT 24
Finished Mar 19 03:07:47 PM PDT 24
Peak memory 197556 kb
Host smart-620fc5d0-b02b-41ca-998a-ea3cd3665175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238973299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.2238973299
Directory /workspace/31.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/31.pwrmgr_glitch.1248964547
Short name T652
Test name
Test status
Simulation time 34190302 ps
CPU time 0.62 seconds
Started Mar 19 03:07:38 PM PDT 24
Finished Mar 19 03:07:39 PM PDT 24
Peak memory 196780 kb
Host smart-f8d561a7-0eba-4b83-bb15-96b6aa4fb468
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248964547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.1248964547
Directory /workspace/31.pwrmgr_glitch/latest

Test location /workspace/coverage/default/31.pwrmgr_global_esc.3763415085
Short name T338
Test name
Test status
Simulation time 22296869 ps
CPU time 0.61 seconds
Started Mar 19 03:07:53 PM PDT 24
Finished Mar 19 03:07:54 PM PDT 24
Peak memory 197544 kb
Host smart-a628c0b1-db60-4f0d-947d-669f20b5f441
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763415085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.3763415085
Directory /workspace/31.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.578303167
Short name T841
Test name
Test status
Simulation time 84002328 ps
CPU time 0.65 seconds
Started Mar 19 03:07:43 PM PDT 24
Finished Mar 19 03:07:44 PM PDT 24
Peak memory 200780 kb
Host smart-2b4cf4a0-fa4c-4e0c-893d-6c83621c44e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578303167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_invali
d.578303167
Directory /workspace/31.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.4043517080
Short name T816
Test name
Test status
Simulation time 107071272 ps
CPU time 0.97 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 208964 kb
Host smart-2d634b4a-5a3d-4052-9e79-fe560ed8d9d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043517080 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.4043517080
Directory /workspace/31.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1312717212
Short name T592
Test name
Test status
Simulation time 743832437 ps
CPU time 3.03 seconds
Started Mar 19 03:07:53 PM PDT 24
Finished Mar 19 03:07:56 PM PDT 24
Peak memory 200636 kb
Host smart-ba5b11b3-07e8-4066-b263-2c0aed941dba
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312717212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1312717212
Directory /workspace/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2793768629
Short name T108
Test name
Test status
Simulation time 991986941 ps
CPU time 2.51 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:55 PM PDT 24
Peak memory 200356 kb
Host smart-8aff62bb-dc7e-4ef7-b2f2-80fd8716adc4
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793768629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2793768629
Directory /workspace/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.1565677408
Short name T793
Test name
Test status
Simulation time 92348967 ps
CPU time 0.82 seconds
Started Mar 19 03:08:02 PM PDT 24
Finished Mar 19 03:08:04 PM PDT 24
Peak memory 198572 kb
Host smart-a44b6976-5dc3-45b0-b13f-ee743c31b1e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565677408 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1565677408
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/31.pwrmgr_smoke.1703403043
Short name T621
Test name
Test status
Simulation time 73465134 ps
CPU time 0.65 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 197716 kb
Host smart-84ea9b6e-065d-4e9b-b627-211b7350c0a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703403043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.1703403043
Directory /workspace/31.pwrmgr_smoke/latest

Test location /workspace/coverage/default/31.pwrmgr_stress_all.3431373118
Short name T727
Test name
Test status
Simulation time 1171180102 ps
CPU time 2.36 seconds
Started Mar 19 03:07:43 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 200608 kb
Host smart-edd57c7b-0496-40c7-9515-939d692f9e26
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431373118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.3431373118
Directory /workspace/31.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup.3399435645
Short name T656
Test name
Test status
Simulation time 153531362 ps
CPU time 0.62 seconds
Started Mar 19 03:07:57 PM PDT 24
Finished Mar 19 03:07:58 PM PDT 24
Peak memory 197588 kb
Host smart-06461d11-6109-4d5b-81cc-797eb951cf11
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399435645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.3399435645
Directory /workspace/31.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/31.pwrmgr_wakeup_reset.1341811478
Short name T846
Test name
Test status
Simulation time 229362104 ps
CPU time 1.3 seconds
Started Mar 19 03:07:46 PM PDT 24
Finished Mar 19 03:07:48 PM PDT 24
Peak memory 200408 kb
Host smart-29c1a1c7-d76c-4427-88a0-caf4826e1eb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341811478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.1341811478
Directory /workspace/31.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.1333422556
Short name T334
Test name
Test status
Simulation time 25265789 ps
CPU time 0.67 seconds
Started Mar 19 03:07:46 PM PDT 24
Finished Mar 19 03:07:47 PM PDT 24
Peak memory 197956 kb
Host smart-7afff6b4-8c60-48f4-9492-0c372605c0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333422556 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.1333422556
Directory /workspace/32.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.234157738
Short name T118
Test name
Test status
Simulation time 70863968 ps
CPU time 0.67 seconds
Started Mar 19 03:07:45 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 197984 kb
Host smart-3be4b63b-d66d-4fb2-9c47-7c5efdf25a49
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234157738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_disa
ble_rom_integrity_check.234157738
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.417888393
Short name T222
Test name
Test status
Simulation time 40134281 ps
CPU time 0.59 seconds
Started Mar 19 03:07:52 PM PDT 24
Finished Mar 19 03:07:54 PM PDT 24
Peak memory 196732 kb
Host smart-1f83c958-c50e-4ed5-b1f6-95af36597936
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417888393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst_
malfunc.417888393
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.2606540878
Short name T815
Test name
Test status
Simulation time 159913391 ps
CPU time 0.98 seconds
Started Mar 19 03:07:45 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 197492 kb
Host smart-66ba3437-08cc-4de2-af65-dab7d4f838d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606540878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.2606540878
Directory /workspace/32.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/32.pwrmgr_glitch.1557519058
Short name T181
Test name
Test status
Simulation time 33197698 ps
CPU time 0.69 seconds
Started Mar 19 03:07:35 PM PDT 24
Finished Mar 19 03:07:36 PM PDT 24
Peak memory 197536 kb
Host smart-171388d3-6952-4909-9935-d3458b3086c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557519058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.1557519058
Directory /workspace/32.pwrmgr_glitch/latest

Test location /workspace/coverage/default/32.pwrmgr_global_esc.3309936589
Short name T377
Test name
Test status
Simulation time 25266074 ps
CPU time 0.6 seconds
Started Mar 19 03:07:55 PM PDT 24
Finished Mar 19 03:07:56 PM PDT 24
Peak memory 197512 kb
Host smart-f5367f11-9fca-4f1e-abaf-a0923676baf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309936589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.3309936589
Directory /workspace/32.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.2568301782
Short name T521
Test name
Test status
Simulation time 204298175 ps
CPU time 0.64 seconds
Started Mar 19 03:07:47 PM PDT 24
Finished Mar 19 03:07:47 PM PDT 24
Peak memory 200832 kb
Host smart-48c6c3ee-2b06-480a-9ff6-019bae2676a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568301782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_inval
id.2568301782
Directory /workspace/32.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_reset.2933562413
Short name T486
Test name
Test status
Simulation time 64100709 ps
CPU time 0.72 seconds
Started Mar 19 03:07:45 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 198548 kb
Host smart-6f353346-a285-4a94-8e05-59d1bcf40262
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933562413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.2933562413
Directory /workspace/32.pwrmgr_reset/latest

Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.479132940
Short name T668
Test name
Test status
Simulation time 115017504 ps
CPU time 0.95 seconds
Started Mar 19 03:07:42 PM PDT 24
Finished Mar 19 03:07:43 PM PDT 24
Peak memory 208864 kb
Host smart-7b7e9aae-05ca-4bb3-80d9-c0fddf417de1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479132940 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.479132940
Directory /workspace/32.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.3858691106
Short name T817
Test name
Test status
Simulation time 32719387 ps
CPU time 0.66 seconds
Started Mar 19 03:07:41 PM PDT 24
Finished Mar 19 03:07:41 PM PDT 24
Peak memory 198820 kb
Host smart-f0b96914-e903-473e-a6d5-8c478cfce451
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858691106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_
cm_ctrl_config_regwen.3858691106
Directory /workspace/32.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4169274898
Short name T122
Test name
Test status
Simulation time 769944137 ps
CPU time 2.96 seconds
Started Mar 19 03:07:40 PM PDT 24
Finished Mar 19 03:07:43 PM PDT 24
Peak memory 200488 kb
Host smart-0659b067-7afc-4940-ac07-7f731b0176fc
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169274898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4169274898
Directory /workspace/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3265151640
Short name T460
Test name
Test status
Simulation time 840616709 ps
CPU time 3.03 seconds
Started Mar 19 03:08:02 PM PDT 24
Finished Mar 19 03:08:06 PM PDT 24
Peak memory 200668 kb
Host smart-e263ea5a-9e41-4f31-a28b-e04f9548dcd4
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265151640 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3265151640
Directory /workspace/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2573852119
Short name T160
Test name
Test status
Simulation time 94051980 ps
CPU time 0.83 seconds
Started Mar 19 03:07:45 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 198820 kb
Host smart-2632d754-44cd-4ca3-8877-15309dfc761c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573852119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2573852119
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/32.pwrmgr_smoke.2461829943
Short name T589
Test name
Test status
Simulation time 132478257 ps
CPU time 0.66 seconds
Started Mar 19 03:07:42 PM PDT 24
Finished Mar 19 03:07:44 PM PDT 24
Peak memory 197920 kb
Host smart-e1dfc7b6-0cbb-4f27-b7ed-d035427482d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461829943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.2461829943
Directory /workspace/32.pwrmgr_smoke/latest

Test location /workspace/coverage/default/32.pwrmgr_wakeup_reset.3690979642
Short name T619
Test name
Test status
Simulation time 97477299 ps
CPU time 0.81 seconds
Started Mar 19 03:07:39 PM PDT 24
Finished Mar 19 03:07:40 PM PDT 24
Peak memory 198756 kb
Host smart-fcbb93ac-cc0e-4969-aa89-25de0c2d07b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690979642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.3690979642
Directory /workspace/32.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.354705618
Short name T663
Test name
Test status
Simulation time 52186522 ps
CPU time 0.63 seconds
Started Mar 19 03:07:44 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 197964 kb
Host smart-bccfb4b7-30e8-45ca-be59-96c310d45d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354705618 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.354705618
Directory /workspace/33.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.2382053559
Short name T343
Test name
Test status
Simulation time 221358045 ps
CPU time 0.69 seconds
Started Mar 19 03:07:41 PM PDT 24
Finished Mar 19 03:07:42 PM PDT 24
Peak memory 197680 kb
Host smart-55166963-bc82-434b-b7ad-569cd2a8f174
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382053559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.2382053559
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.3499755039
Short name T14
Test name
Test status
Simulation time 39544429 ps
CPU time 0.59 seconds
Started Mar 19 03:07:47 PM PDT 24
Finished Mar 19 03:07:49 PM PDT 24
Peak memory 196664 kb
Host smart-0f19f198-ccc1-47cd-b96a-76e73bff4aa3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499755039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.3499755039
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.3250771195
Short name T631
Test name
Test status
Simulation time 540889751 ps
CPU time 0.94 seconds
Started Mar 19 03:07:40 PM PDT 24
Finished Mar 19 03:07:41 PM PDT 24
Peak memory 197832 kb
Host smart-5f803c84-d26a-472a-ba14-4b9b4ee92864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250771195 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.3250771195
Directory /workspace/33.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/33.pwrmgr_glitch.2750595106
Short name T655
Test name
Test status
Simulation time 46835658 ps
CPU time 0.67 seconds
Started Mar 19 03:07:40 PM PDT 24
Finished Mar 19 03:07:41 PM PDT 24
Peak memory 197504 kb
Host smart-bcfb79cf-4455-4e93-afc4-31e865b3a5ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750595106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.2750595106
Directory /workspace/33.pwrmgr_glitch/latest

Test location /workspace/coverage/default/33.pwrmgr_global_esc.582161062
Short name T276
Test name
Test status
Simulation time 47421279 ps
CPU time 0.64 seconds
Started Mar 19 03:07:38 PM PDT 24
Finished Mar 19 03:07:39 PM PDT 24
Peak memory 197500 kb
Host smart-6abca16b-9fc9-4a88-9ce8-1a99cb4a168b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582161062 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.582161062
Directory /workspace/33.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.3222741909
Short name T259
Test name
Test status
Simulation time 81909536 ps
CPU time 0.68 seconds
Started Mar 19 03:07:47 PM PDT 24
Finished Mar 19 03:07:48 PM PDT 24
Peak memory 200776 kb
Host smart-d933a1cc-6044-4bc1-9251-579d8c441ae4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222741909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.3222741909
Directory /workspace/33.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_lowpower_wakeup_race.508849592
Short name T278
Test name
Test status
Simulation time 216157673 ps
CPU time 0.83 seconds
Started Mar 19 03:07:45 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 197952 kb
Host smart-59647c0d-5905-4424-990f-2320c78cb694
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508849592 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_wa
keup_race.508849592
Directory /workspace/33.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/33.pwrmgr_reset.2344939376
Short name T29
Test name
Test status
Simulation time 44664778 ps
CPU time 0.76 seconds
Started Mar 19 03:07:46 PM PDT 24
Finished Mar 19 03:07:48 PM PDT 24
Peak memory 198524 kb
Host smart-bbfd8704-bd08-4c0c-85ee-0ba9279b2112
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344939376 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.2344939376
Directory /workspace/33.pwrmgr_reset/latest

Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.2905342211
Short name T205
Test name
Test status
Simulation time 161428995 ps
CPU time 0.78 seconds
Started Mar 19 03:07:56 PM PDT 24
Finished Mar 19 03:07:57 PM PDT 24
Peak memory 208932 kb
Host smart-cb699023-607d-4d76-868b-bc1d07e6ee69
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905342211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.2905342211
Directory /workspace/33.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.333729189
Short name T266
Test name
Test status
Simulation time 354723630 ps
CPU time 1.12 seconds
Started Mar 19 03:07:56 PM PDT 24
Finished Mar 19 03:07:57 PM PDT 24
Peak memory 200216 kb
Host smart-50815797-9891-4b1c-9733-6f9f327ede77
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333729189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_c
m_ctrl_config_regwen.333729189
Directory /workspace/33.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2443009954
Short name T116
Test name
Test status
Simulation time 963561405 ps
CPU time 2.12 seconds
Started Mar 19 03:07:40 PM PDT 24
Finished Mar 19 03:07:42 PM PDT 24
Peak memory 200604 kb
Host smart-2440adc5-0499-4515-8cac-aa0e52db648b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443009954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2443009954
Directory /workspace/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.2592082973
Short name T563
Test name
Test status
Simulation time 54351899 ps
CPU time 0.84 seconds
Started Mar 19 03:07:46 PM PDT 24
Finished Mar 19 03:07:47 PM PDT 24
Peak memory 198940 kb
Host smart-cd22edd6-d3cb-481b-8da7-f14c9a1a9a22
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592082973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2592082973
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/33.pwrmgr_smoke.3176476683
Short name T224
Test name
Test status
Simulation time 60416351 ps
CPU time 0.65 seconds
Started Mar 19 03:07:38 PM PDT 24
Finished Mar 19 03:07:39 PM PDT 24
Peak memory 198752 kb
Host smart-eb7c3e50-9059-495c-83d4-06fafd99414d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176476683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.3176476683
Directory /workspace/33.pwrmgr_smoke/latest

Test location /workspace/coverage/default/33.pwrmgr_wakeup.4265261593
Short name T469
Test name
Test status
Simulation time 242757227 ps
CPU time 0.67 seconds
Started Mar 19 03:07:43 PM PDT 24
Finished Mar 19 03:07:44 PM PDT 24
Peak memory 197700 kb
Host smart-48145f05-b5d6-4e6d-816e-f6caaa53ea25
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265261593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.4265261593
Directory /workspace/33.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/33.pwrmgr_wakeup_reset.2647251899
Short name T682
Test name
Test status
Simulation time 496145270 ps
CPU time 1.2 seconds
Started Mar 19 03:07:47 PM PDT 24
Finished Mar 19 03:07:49 PM PDT 24
Peak memory 200484 kb
Host smart-7ff9aa10-5ca3-457f-8f9e-883b983c8496
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647251899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.2647251899
Directory /workspace/33.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.1789114038
Short name T799
Test name
Test status
Simulation time 227099616 ps
CPU time 0.78 seconds
Started Mar 19 03:07:40 PM PDT 24
Finished Mar 19 03:07:41 PM PDT 24
Peak memory 199280 kb
Host smart-0e0e51a5-2caf-4e47-b459-57fb34bf0639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789114038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.1789114038
Directory /workspace/34.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.353892053
Short name T489
Test name
Test status
Simulation time 77186328 ps
CPU time 0.7 seconds
Started Mar 19 03:08:02 PM PDT 24
Finished Mar 19 03:08:03 PM PDT 24
Peak memory 198064 kb
Host smart-931027bf-1cbb-4c95-bdf4-4bcde5c0f69f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353892053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_disa
ble_rom_integrity_check.353892053
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.3653893118
Short name T159
Test name
Test status
Simulation time 39866713 ps
CPU time 0.62 seconds
Started Mar 19 03:07:44 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 196732 kb
Host smart-f4a9dc05-819e-4adc-8822-8d9b0139e946
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653893118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.3653893118
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.3858925516
Short name T411
Test name
Test status
Simulation time 214996901 ps
CPU time 0.94 seconds
Started Mar 19 03:07:48 PM PDT 24
Finished Mar 19 03:07:49 PM PDT 24
Peak memory 197536 kb
Host smart-03da3486-8864-450a-821b-305dafb0d635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858925516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.3858925516
Directory /workspace/34.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/34.pwrmgr_glitch.338524140
Short name T455
Test name
Test status
Simulation time 58270994 ps
CPU time 0.63 seconds
Started Mar 19 03:07:46 PM PDT 24
Finished Mar 19 03:07:47 PM PDT 24
Peak memory 197484 kb
Host smart-220fa7c9-46ee-4d70-aca5-176bcf5fb831
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338524140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.338524140
Directory /workspace/34.pwrmgr_glitch/latest

Test location /workspace/coverage/default/34.pwrmgr_global_esc.3700146303
Short name T514
Test name
Test status
Simulation time 34326425 ps
CPU time 0.61 seconds
Started Mar 19 03:07:44 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 197804 kb
Host smart-51b01007-dcbd-4e82-8074-1f052908dc9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700146303 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.3700146303
Directory /workspace/34.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.849962244
Short name T236
Test name
Test status
Simulation time 41418924 ps
CPU time 0.73 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 200608 kb
Host smart-c9bd811d-b2c4-4fba-8afd-48d6b35b78cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849962244 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_invali
d.849962244
Directory /workspace/34.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_lowpower_wakeup_race.3285992615
Short name T645
Test name
Test status
Simulation time 168000361 ps
CPU time 0.84 seconds
Started Mar 19 03:07:43 PM PDT 24
Finished Mar 19 03:07:44 PM PDT 24
Peak memory 197968 kb
Host smart-6ee0adb2-e29f-4b8f-8ea9-170e62e51b67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285992615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_w
akeup_race.3285992615
Directory /workspace/34.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/34.pwrmgr_reset.421953204
Short name T392
Test name
Test status
Simulation time 144131011 ps
CPU time 0.81 seconds
Started Mar 19 03:07:41 PM PDT 24
Finished Mar 19 03:07:42 PM PDT 24
Peak memory 199312 kb
Host smart-c9368ba3-aa56-4f98-8aa9-83e2df009c2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421953204 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.421953204
Directory /workspace/34.pwrmgr_reset/latest

Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.774215851
Short name T309
Test name
Test status
Simulation time 171846814 ps
CPU time 0.78 seconds
Started Mar 19 03:08:02 PM PDT 24
Finished Mar 19 03:08:04 PM PDT 24
Peak memory 208932 kb
Host smart-9b5bdd4c-78fb-409c-8f29-9539b041a6fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774215851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.774215851
Directory /workspace/34.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.1915348469
Short name T860
Test name
Test status
Simulation time 59047719 ps
CPU time 0.79 seconds
Started Mar 19 03:07:48 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 198164 kb
Host smart-d411ad48-a061-4254-87a7-a16ea1d56ed5
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915348469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_
cm_ctrl_config_regwen.1915348469
Directory /workspace/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1996099552
Short name T699
Test name
Test status
Simulation time 683532640 ps
CPU time 3.16 seconds
Started Mar 19 03:07:53 PM PDT 24
Finished Mar 19 03:07:56 PM PDT 24
Peak memory 200452 kb
Host smart-f4f9e376-0348-4016-a229-3eaf8a986bf8
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996099552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1996099552
Directory /workspace/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1856255022
Short name T636
Test name
Test status
Simulation time 881555063 ps
CPU time 3.23 seconds
Started Mar 19 03:08:00 PM PDT 24
Finished Mar 19 03:08:04 PM PDT 24
Peak memory 200612 kb
Host smart-f6ddda20-0328-4677-9e6c-3da9f2f31158
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856255022 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1856255022
Directory /workspace/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.3250400399
Short name T274
Test name
Test status
Simulation time 53741561 ps
CPU time 0.92 seconds
Started Mar 19 03:07:51 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 199064 kb
Host smart-e6bb307a-7013-4ba8-b7d8-e162f2a2c44a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250400399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3250400399
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/34.pwrmgr_smoke.3938095105
Short name T261
Test name
Test status
Simulation time 46735556 ps
CPU time 0.62 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 198744 kb
Host smart-37810faa-b121-48ce-9d6e-93a7ec99eedc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938095105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.3938095105
Directory /workspace/34.pwrmgr_smoke/latest

Test location /workspace/coverage/default/34.pwrmgr_wakeup_reset.1924091492
Short name T25
Test name
Test status
Simulation time 106888425 ps
CPU time 0.87 seconds
Started Mar 19 03:08:03 PM PDT 24
Finished Mar 19 03:08:05 PM PDT 24
Peak memory 198496 kb
Host smart-8844d50c-b054-4be4-9d7c-bbe2191942b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924091492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.1924091492
Directory /workspace/34.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.2721364560
Short name T302
Test name
Test status
Simulation time 37204809 ps
CPU time 0.81 seconds
Started Mar 19 03:07:51 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 199136 kb
Host smart-b5ee7425-6a2b-407c-9b0f-2f4a5951e5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721364560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.2721364560
Directory /workspace/35.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.877993455
Short name T616
Test name
Test status
Simulation time 57400034 ps
CPU time 0.85 seconds
Started Mar 19 03:08:00 PM PDT 24
Finished Mar 19 03:08:02 PM PDT 24
Peak memory 198532 kb
Host smart-d71bc8a1-57c6-4b95-803c-080e18a9cee8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877993455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_disa
ble_rom_integrity_check.877993455
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.3078465403
Short name T145
Test name
Test status
Simulation time 29538742 ps
CPU time 0.64 seconds
Started Mar 19 03:07:52 PM PDT 24
Finished Mar 19 03:07:54 PM PDT 24
Peak memory 196768 kb
Host smart-75662371-e504-43f4-9286-361f2017f969
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078465403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst
_malfunc.3078465403
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.188043914
Short name T148
Test name
Test status
Simulation time 165980246 ps
CPU time 0.99 seconds
Started Mar 19 03:07:46 PM PDT 24
Finished Mar 19 03:07:48 PM PDT 24
Peak memory 197800 kb
Host smart-16d577f0-65ed-4122-902c-3a142a2f53c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188043914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.188043914
Directory /workspace/35.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/35.pwrmgr_glitch.2060761222
Short name T406
Test name
Test status
Simulation time 59874709 ps
CPU time 0.69 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 197472 kb
Host smart-ad9911d0-18fb-4d89-bc50-ef4f860eb380
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060761222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.2060761222
Directory /workspace/35.pwrmgr_glitch/latest

Test location /workspace/coverage/default/35.pwrmgr_global_esc.2170294396
Short name T268
Test name
Test status
Simulation time 125391231 ps
CPU time 0.65 seconds
Started Mar 19 03:07:53 PM PDT 24
Finished Mar 19 03:07:54 PM PDT 24
Peak memory 197368 kb
Host smart-0723a24e-292a-4263-98fe-e984fb3996e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170294396 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.2170294396
Directory /workspace/35.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.959764252
Short name T744
Test name
Test status
Simulation time 73672795 ps
CPU time 0.68 seconds
Started Mar 19 03:07:59 PM PDT 24
Finished Mar 19 03:08:00 PM PDT 24
Peak memory 200612 kb
Host smart-c13afeb6-f301-4ecb-b644-827ca21985ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959764252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_invali
d.959764252
Directory /workspace/35.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_lowpower_wakeup_race.4177013200
Short name T416
Test name
Test status
Simulation time 236359665 ps
CPU time 0.9 seconds
Started Mar 19 03:07:54 PM PDT 24
Finished Mar 19 03:07:55 PM PDT 24
Peak memory 198968 kb
Host smart-1af6a841-7fcc-4eba-85c0-c5bbc651c9d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177013200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_w
akeup_race.4177013200
Directory /workspace/35.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/35.pwrmgr_reset.3464907200
Short name T626
Test name
Test status
Simulation time 150411213 ps
CPU time 0.65 seconds
Started Mar 19 03:07:50 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 197972 kb
Host smart-96f1330c-2ea2-4a31-9a27-a52828d9b326
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464907200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.3464907200
Directory /workspace/35.pwrmgr_reset/latest

Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.2172763227
Short name T519
Test name
Test status
Simulation time 162367850 ps
CPU time 0.79 seconds
Started Mar 19 03:07:59 PM PDT 24
Finished Mar 19 03:08:00 PM PDT 24
Peak memory 200684 kb
Host smart-23f190d1-69e3-46c8-8815-424be632795d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172763227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.2172763227
Directory /workspace/35.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.684284967
Short name T242
Test name
Test status
Simulation time 790684704 ps
CPU time 3.07 seconds
Started Mar 19 03:07:51 PM PDT 24
Finished Mar 19 03:07:56 PM PDT 24
Peak memory 200440 kb
Host smart-f8320eaa-5504-4070-91e1-41b408e75012
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684284967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.684284967
Directory /workspace/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3295012166
Short name T328
Test name
Test status
Simulation time 882794097 ps
CPU time 3.15 seconds
Started Mar 19 03:07:48 PM PDT 24
Finished Mar 19 03:07:51 PM PDT 24
Peak memory 200376 kb
Host smart-c6961943-7c8b-4349-a8e6-e34b2b7ff98b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295012166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3295012166
Directory /workspace/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.58781986
Short name T730
Test name
Test status
Simulation time 69138570 ps
CPU time 0.95 seconds
Started Mar 19 03:07:53 PM PDT 24
Finished Mar 19 03:07:54 PM PDT 24
Peak memory 198516 kb
Host smart-16f0826c-3847-465a-94b7-275efcb6a675
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58781986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.58781986
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/35.pwrmgr_smoke.2117114943
Short name T851
Test name
Test status
Simulation time 39747334 ps
CPU time 0.71 seconds
Started Mar 19 03:07:46 PM PDT 24
Finished Mar 19 03:07:46 PM PDT 24
Peak memory 198764 kb
Host smart-9e6e3664-53a0-4792-9602-196bd823c1f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117114943 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.2117114943
Directory /workspace/35.pwrmgr_smoke/latest

Test location /workspace/coverage/default/35.pwrmgr_stress_all.1853702689
Short name T736
Test name
Test status
Simulation time 218073614 ps
CPU time 1.33 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:54 PM PDT 24
Peak memory 200416 kb
Host smart-72768add-0637-4887-902f-166f8c4fb852
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853702689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.1853702689
Directory /workspace/35.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup.2272293320
Short name T594
Test name
Test status
Simulation time 28056680 ps
CPU time 0.67 seconds
Started Mar 19 03:07:50 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 198528 kb
Host smart-4bc00940-5fc3-4573-bf93-6f0e78abb6d1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272293320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.2272293320
Directory /workspace/35.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/35.pwrmgr_wakeup_reset.2038641339
Short name T188
Test name
Test status
Simulation time 295268269 ps
CPU time 1.07 seconds
Started Mar 19 03:08:13 PM PDT 24
Finished Mar 19 03:08:14 PM PDT 24
Peak memory 199512 kb
Host smart-81c758b4-e5ed-4b4c-9f6b-aef725b02067
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038641339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.2038641339
Directory /workspace/35.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.2185150996
Short name T468
Test name
Test status
Simulation time 25227887 ps
CPU time 0.72 seconds
Started Mar 19 03:07:51 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 197988 kb
Host smart-22813f8c-24cf-4c87-9009-37f258b92100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185150996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.2185150996
Directory /workspace/36.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.796200378
Short name T119
Test name
Test status
Simulation time 66783389 ps
CPU time 0.68 seconds
Started Mar 19 03:07:59 PM PDT 24
Finished Mar 19 03:08:01 PM PDT 24
Peak memory 198516 kb
Host smart-99bd4250-7036-409e-a0fb-ab3b52e0f7bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796200378 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_disa
ble_rom_integrity_check.796200378
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.581516102
Short name T449
Test name
Test status
Simulation time 40638524 ps
CPU time 0.6 seconds
Started Mar 19 03:07:58 PM PDT 24
Finished Mar 19 03:07:59 PM PDT 24
Peak memory 196588 kb
Host smart-2385bdb8-6588-42cf-b9b0-8f4e0804a1b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581516102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst_
malfunc.581516102
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.351611453
Short name T485
Test name
Test status
Simulation time 627235797 ps
CPU time 0.92 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 197832 kb
Host smart-7e35f255-b3e6-4cfb-9358-1152ba29de81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351611453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.351611453
Directory /workspace/36.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/36.pwrmgr_glitch.3970545942
Short name T385
Test name
Test status
Simulation time 51115155 ps
CPU time 0.64 seconds
Started Mar 19 03:08:02 PM PDT 24
Finished Mar 19 03:08:03 PM PDT 24
Peak memory 197544 kb
Host smart-9e787e35-05d8-40ef-ab31-e9b061886c89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970545942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.3970545942
Directory /workspace/36.pwrmgr_glitch/latest

Test location /workspace/coverage/default/36.pwrmgr_global_esc.390471093
Short name T176
Test name
Test status
Simulation time 47775044 ps
CPU time 0.63 seconds
Started Mar 19 03:07:54 PM PDT 24
Finished Mar 19 03:07:55 PM PDT 24
Peak memory 197832 kb
Host smart-0f835f78-098d-46dc-a1e9-1453f062ad08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390471093 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.390471093
Directory /workspace/36.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.3935725920
Short name T595
Test name
Test status
Simulation time 71756805 ps
CPU time 0.72 seconds
Started Mar 19 03:07:58 PM PDT 24
Finished Mar 19 03:08:00 PM PDT 24
Peak memory 200804 kb
Host smart-f5c0cbcd-888c-41ba-b5c3-8dd3816fb058
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935725920 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.3935725920
Directory /workspace/36.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_reset.827177071
Short name T371
Test name
Test status
Simulation time 79257123 ps
CPU time 0.81 seconds
Started Mar 19 03:07:57 PM PDT 24
Finished Mar 19 03:07:59 PM PDT 24
Peak memory 198092 kb
Host smart-e1967913-c875-4014-918c-1ac82b288359
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827177071 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.827177071
Directory /workspace/36.pwrmgr_reset/latest

Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.4030865255
Short name T310
Test name
Test status
Simulation time 100609668 ps
CPU time 0.94 seconds
Started Mar 19 03:07:50 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 208944 kb
Host smart-690bd0fa-5a60-43fe-b174-738ad3343abb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030865255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.4030865255
Directory /workspace/36.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.2528011707
Short name T561
Test name
Test status
Simulation time 88640166 ps
CPU time 0.83 seconds
Started Mar 19 03:08:01 PM PDT 24
Finished Mar 19 03:08:02 PM PDT 24
Peak memory 198080 kb
Host smart-3d4a0809-eb56-45a6-be91-c645039d088d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528011707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_
cm_ctrl_config_regwen.2528011707
Directory /workspace/36.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.318013447
Short name T757
Test name
Test status
Simulation time 874553137 ps
CPU time 2.28 seconds
Started Mar 19 03:08:08 PM PDT 24
Finished Mar 19 03:08:11 PM PDT 24
Peak memory 200636 kb
Host smart-35abe667-eb06-4d4b-bc03-1976dfcacf0b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318013447 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.318013447
Directory /workspace/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2284001784
Short name T12
Test name
Test status
Simulation time 1918669633 ps
CPU time 1.77 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:54 PM PDT 24
Peak memory 200584 kb
Host smart-7f15d21d-cf5b-4a92-8525-86ea54787387
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284001784 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2284001784
Directory /workspace/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.655448996
Short name T750
Test name
Test status
Simulation time 70337503 ps
CPU time 0.83 seconds
Started Mar 19 03:07:54 PM PDT 24
Finished Mar 19 03:07:55 PM PDT 24
Peak memory 198708 kb
Host smart-6f808fb2-845f-4052-8d94-de53f484d486
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655448996 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig_
mubi.655448996
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/36.pwrmgr_smoke.2973521576
Short name T202
Test name
Test status
Simulation time 85182926 ps
CPU time 0.61 seconds
Started Mar 19 03:07:59 PM PDT 24
Finished Mar 19 03:08:00 PM PDT 24
Peak memory 198728 kb
Host smart-a8cf399b-2d7c-44fd-aaf2-d6ca09332254
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973521576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.2973521576
Directory /workspace/36.pwrmgr_smoke/latest

Test location /workspace/coverage/default/36.pwrmgr_stress_all.328321434
Short name T32
Test name
Test status
Simulation time 653059498 ps
CPU time 2.85 seconds
Started Mar 19 03:07:57 PM PDT 24
Finished Mar 19 03:08:06 PM PDT 24
Peak memory 200632 kb
Host smart-5f3d9004-e641-4d68-bc53-ca77c2f75ccc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328321434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.328321434
Directory /workspace/36.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup.1991772388
Short name T290
Test name
Test status
Simulation time 401794936 ps
CPU time 0.86 seconds
Started Mar 19 03:07:46 PM PDT 24
Finished Mar 19 03:07:48 PM PDT 24
Peak memory 198992 kb
Host smart-715052c5-9909-4d23-bfec-3c54bbb74d44
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991772388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.1991772388
Directory /workspace/36.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/36.pwrmgr_wakeup_reset.9370188
Short name T446
Test name
Test status
Simulation time 410815177 ps
CPU time 1.16 seconds
Started Mar 19 03:07:55 PM PDT 24
Finished Mar 19 03:07:57 PM PDT 24
Peak memory 200508 kb
Host smart-e553ca2b-e89c-4e64-849e-168ee4740dea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9370188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.9370188
Directory /workspace/36.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.3961905108
Short name T383
Test name
Test status
Simulation time 52448365 ps
CPU time 0.7 seconds
Started Mar 19 03:07:46 PM PDT 24
Finished Mar 19 03:07:47 PM PDT 24
Peak memory 198088 kb
Host smart-c47a470c-94a1-433c-86d7-59cfba944cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961905108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.3961905108
Directory /workspace/37.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.2212737508
Short name T131
Test name
Test status
Simulation time 66080617 ps
CPU time 0.84 seconds
Started Mar 19 03:07:51 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 198384 kb
Host smart-4a305eee-b726-451e-9ede-58fb5d28f78a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212737508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_dis
able_rom_integrity_check.2212737508
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.190633414
Short name T397
Test name
Test status
Simulation time 54406507 ps
CPU time 0.6 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 197388 kb
Host smart-92ce9d8b-7bf8-4dd2-9488-47cd4692865f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190633414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst_
malfunc.190633414
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.1309394374
Short name T2
Test name
Test status
Simulation time 411221658 ps
CPU time 0.96 seconds
Started Mar 19 03:07:50 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 197576 kb
Host smart-f8680df8-4a40-4a88-9870-7f90eb822af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309394374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.1309394374
Directory /workspace/37.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/37.pwrmgr_glitch.3628830316
Short name T71
Test name
Test status
Simulation time 25767499 ps
CPU time 0.62 seconds
Started Mar 19 03:07:57 PM PDT 24
Finished Mar 19 03:07:58 PM PDT 24
Peak memory 197532 kb
Host smart-6301fee8-b9a8-4348-8390-840b5bb1d128
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628830316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.3628830316
Directory /workspace/37.pwrmgr_glitch/latest

Test location /workspace/coverage/default/37.pwrmgr_global_esc.324368926
Short name T157
Test name
Test status
Simulation time 36131657 ps
CPU time 0.64 seconds
Started Mar 19 03:07:52 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 197512 kb
Host smart-5e0a76aa-6df5-4c99-9b41-3c68b0a01ce0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324368926 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.324368926
Directory /workspace/37.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.2751708507
Short name T230
Test name
Test status
Simulation time 39485588 ps
CPU time 0.73 seconds
Started Mar 19 03:07:53 PM PDT 24
Finished Mar 19 03:07:54 PM PDT 24
Peak memory 200824 kb
Host smart-0ceff740-f193-4ca2-aa06-cab54eac417d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751708507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_inval
id.2751708507
Directory /workspace/37.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_lowpower_wakeup_race.2096397200
Short name T788
Test name
Test status
Simulation time 751963666 ps
CPU time 0.93 seconds
Started Mar 19 03:08:01 PM PDT 24
Finished Mar 19 03:08:04 PM PDT 24
Peak memory 199204 kb
Host smart-37c9e8c6-2a93-4be2-8e53-e580195be992
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096397200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_w
akeup_race.2096397200
Directory /workspace/37.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/37.pwrmgr_reset.3251478615
Short name T427
Test name
Test status
Simulation time 110603715 ps
CPU time 0.74 seconds
Started Mar 19 03:08:13 PM PDT 24
Finished Mar 19 03:08:14 PM PDT 24
Peak memory 198096 kb
Host smart-cfe5eedf-5233-45a0-8775-2acf4da9b312
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251478615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.3251478615
Directory /workspace/37.pwrmgr_reset/latest

Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.503999833
Short name T709
Test name
Test status
Simulation time 113590276 ps
CPU time 0.95 seconds
Started Mar 19 03:07:56 PM PDT 24
Finished Mar 19 03:07:57 PM PDT 24
Peak memory 208884 kb
Host smart-798a93b1-845b-4b47-8100-38be1bac23ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503999833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.503999833
Directory /workspace/37.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.3780573083
Short name T289
Test name
Test status
Simulation time 347834436 ps
CPU time 1.28 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:54 PM PDT 24
Peak memory 200432 kb
Host smart-bb11df0f-8630-4510-bfce-d65b37e73d41
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780573083 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_
cm_ctrl_config_regwen.3780573083
Directory /workspace/37.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3008321766
Short name T60
Test name
Test status
Simulation time 1135515221 ps
CPU time 2.05 seconds
Started Mar 19 03:07:54 PM PDT 24
Finished Mar 19 03:07:56 PM PDT 24
Peak memory 200456 kb
Host smart-34704789-ec26-48d9-8be2-f8b77c8f94fe
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008321766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3008321766
Directory /workspace/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2395506804
Short name T834
Test name
Test status
Simulation time 1200341915 ps
CPU time 2.22 seconds
Started Mar 19 03:07:53 PM PDT 24
Finished Mar 19 03:07:55 PM PDT 24
Peak memory 200520 kb
Host smart-017e0195-b9d7-42f9-af95-d917244e3e42
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395506804 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2395506804
Directory /workspace/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.2005526796
Short name T783
Test name
Test status
Simulation time 54210571 ps
CPU time 0.87 seconds
Started Mar 19 03:07:48 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 198996 kb
Host smart-f3ae2c6a-6d9b-4f07-a92d-87c92c83478c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005526796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2005526796
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/37.pwrmgr_smoke.1609237848
Short name T58
Test name
Test status
Simulation time 45474555 ps
CPU time 0.65 seconds
Started Mar 19 03:07:48 PM PDT 24
Finished Mar 19 03:07:49 PM PDT 24
Peak memory 197860 kb
Host smart-469a0428-e8c2-43c7-a9f1-f23cb6aa1b41
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609237848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.1609237848
Directory /workspace/37.pwrmgr_smoke/latest

Test location /workspace/coverage/default/37.pwrmgr_wakeup_reset.3444613598
Short name T186
Test name
Test status
Simulation time 219337394 ps
CPU time 1.02 seconds
Started Mar 19 03:07:50 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 199584 kb
Host smart-7ecb1a48-0343-4574-9986-be34060a57c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444613598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.3444613598
Directory /workspace/37.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.3029366978
Short name T394
Test name
Test status
Simulation time 78599801 ps
CPU time 0.7 seconds
Started Mar 19 03:07:56 PM PDT 24
Finished Mar 19 03:07:57 PM PDT 24
Peak memory 198000 kb
Host smart-e160b063-42ef-4ed7-8e80-6fc61612102e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029366978 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.3029366978
Directory /workspace/38.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.293806009
Short name T499
Test name
Test status
Simulation time 64713357 ps
CPU time 0.66 seconds
Started Mar 19 03:07:50 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 197860 kb
Host smart-67cdbeb5-205c-458f-9615-0aed59523558
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293806009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_disa
ble_rom_integrity_check.293806009
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.1915130047
Short name T651
Test name
Test status
Simulation time 28731327 ps
CPU time 0.62 seconds
Started Mar 19 03:08:11 PM PDT 24
Finished Mar 19 03:08:12 PM PDT 24
Peak memory 197440 kb
Host smart-4fe72ddb-d958-4fc6-bbc1-5ce74831281a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915130047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.1915130047
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.1676569165
Short name T151
Test name
Test status
Simulation time 307523318 ps
CPU time 1 seconds
Started Mar 19 03:07:50 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 197844 kb
Host smart-39ad43f8-1b0b-445c-917b-c9ffef5c862c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676569165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.1676569165
Directory /workspace/38.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/38.pwrmgr_glitch.931166171
Short name T684
Test name
Test status
Simulation time 96874085 ps
CPU time 0.61 seconds
Started Mar 19 03:08:04 PM PDT 24
Finished Mar 19 03:08:05 PM PDT 24
Peak memory 196820 kb
Host smart-704a1163-9fd3-4a97-bfbe-7df7c895388e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931166171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.931166171
Directory /workspace/38.pwrmgr_glitch/latest

Test location /workspace/coverage/default/38.pwrmgr_global_esc.484336802
Short name T550
Test name
Test status
Simulation time 31176734 ps
CPU time 0.63 seconds
Started Mar 19 03:08:11 PM PDT 24
Finished Mar 19 03:08:11 PM PDT 24
Peak memory 197508 kb
Host smart-b2d3bdb7-874a-42d2-aa9d-c3b92fa58fb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484336802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.484336802
Directory /workspace/38.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.3113677418
Short name T870
Test name
Test status
Simulation time 269841625 ps
CPU time 0.67 seconds
Started Mar 19 03:07:53 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 200792 kb
Host smart-5b9bc3d4-e735-4f7a-8306-1a21732c29d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113677418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_inval
id.3113677418
Directory /workspace/38.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_reset.2615497238
Short name T721
Test name
Test status
Simulation time 43615981 ps
CPU time 0.77 seconds
Started Mar 19 03:08:04 PM PDT 24
Finished Mar 19 03:08:05 PM PDT 24
Peak memory 198592 kb
Host smart-eef20e0f-e280-4951-99e3-e7ced14d4cdb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615497238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.2615497238
Directory /workspace/38.pwrmgr_reset/latest

Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.3168422366
Short name T866
Test name
Test status
Simulation time 111766201 ps
CPU time 0.94 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 208896 kb
Host smart-6b0913d4-0e51-4660-ba9d-939de2a31722
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168422366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.3168422366
Directory /workspace/38.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3310211930
Short name T110
Test name
Test status
Simulation time 1629507765 ps
CPU time 2.09 seconds
Started Mar 19 03:07:51 PM PDT 24
Finished Mar 19 03:07:55 PM PDT 24
Peak memory 200664 kb
Host smart-c327e8c6-03de-479c-9e60-f313ec573cde
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310211930 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3310211930
Directory /workspace/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1242021231
Short name T476
Test name
Test status
Simulation time 717352051 ps
CPU time 2.83 seconds
Started Mar 19 03:08:04 PM PDT 24
Finished Mar 19 03:08:08 PM PDT 24
Peak memory 200484 kb
Host smart-c7f8352e-7138-431f-95c3-aecdd9c5a4d6
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242021231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1242021231
Directory /workspace/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.3284003576
Short name T421
Test name
Test status
Simulation time 88159889 ps
CPU time 0.81 seconds
Started Mar 19 03:07:48 PM PDT 24
Finished Mar 19 03:07:49 PM PDT 24
Peak memory 198800 kb
Host smart-4f769e95-69cb-4a51-b397-9b6d009ecdd0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284003576 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3284003576
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/38.pwrmgr_smoke.3582893708
Short name T359
Test name
Test status
Simulation time 53729137 ps
CPU time 0.62 seconds
Started Mar 19 03:07:51 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 198588 kb
Host smart-62a27e5f-3be1-45d5-ab9d-53fceb6886db
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582893708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.3582893708
Directory /workspace/38.pwrmgr_smoke/latest

Test location /workspace/coverage/default/38.pwrmgr_wakeup_reset.2705461139
Short name T520
Test name
Test status
Simulation time 346136561 ps
CPU time 1.55 seconds
Started Mar 19 03:07:47 PM PDT 24
Finished Mar 19 03:07:49 PM PDT 24
Peak memory 200632 kb
Host smart-df4457ae-9093-424c-8731-a4702bb58c06
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705461139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.2705461139
Directory /workspace/38.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.1421056613
Short name T203
Test name
Test status
Simulation time 25452232 ps
CPU time 0.74 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 198160 kb
Host smart-3c2c5033-b95f-4b0f-a9e1-8816f82a8476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421056613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.1421056613
Directory /workspace/39.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.128050767
Short name T345
Test name
Test status
Simulation time 51814793 ps
CPU time 0.79 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 198620 kb
Host smart-0dee24cf-b358-4b83-afc4-45a77693e721
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128050767 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_disa
ble_rom_integrity_check.128050767
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.3643810601
Short name T512
Test name
Test status
Simulation time 33046912 ps
CPU time 0.61 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 197464 kb
Host smart-6b64f38d-31ad-4e10-92cb-d2d962b57142
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643810601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst
_malfunc.3643810601
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.2278113087
Short name T185
Test name
Test status
Simulation time 609229838 ps
CPU time 0.93 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 197836 kb
Host smart-3d1c44c0-38e3-4fb2-926e-8dc859f266f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278113087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.2278113087
Directory /workspace/39.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/39.pwrmgr_glitch.1387019295
Short name T500
Test name
Test status
Simulation time 53168754 ps
CPU time 0.74 seconds
Started Mar 19 03:07:50 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 196868 kb
Host smart-ec7c5359-3e2c-4c4d-ad27-4c359391eba4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387019295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.1387019295
Directory /workspace/39.pwrmgr_glitch/latest

Test location /workspace/coverage/default/39.pwrmgr_global_esc.390883908
Short name T368
Test name
Test status
Simulation time 43482639 ps
CPU time 0.66 seconds
Started Mar 19 03:07:50 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 197844 kb
Host smart-b32d9d3f-6895-4a0e-8f85-b13c055e3797
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390883908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.390883908
Directory /workspace/39.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.3152954677
Short name T453
Test name
Test status
Simulation time 50273821 ps
CPU time 0.71 seconds
Started Mar 19 03:07:48 PM PDT 24
Finished Mar 19 03:07:49 PM PDT 24
Peak memory 200160 kb
Host smart-1ada6b45-df3b-43f0-b565-1ded0bce5e3f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152954677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.3152954677
Directory /workspace/39.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_lowpower_wakeup_race.2510927660
Short name T190
Test name
Test status
Simulation time 379233916 ps
CPU time 1 seconds
Started Mar 19 03:07:51 PM PDT 24
Finished Mar 19 03:07:54 PM PDT 24
Peak memory 199192 kb
Host smart-80174b43-a712-43ce-8739-ace0b823ae6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510927660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_w
akeup_race.2510927660
Directory /workspace/39.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/39.pwrmgr_reset.2566259672
Short name T199
Test name
Test status
Simulation time 125576560 ps
CPU time 0.79 seconds
Started Mar 19 03:07:56 PM PDT 24
Finished Mar 19 03:08:06 PM PDT 24
Peak memory 198468 kb
Host smart-dc0753a3-be6d-47b4-bf4c-ec285a9c0dcb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566259672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.2566259672
Directory /workspace/39.pwrmgr_reset/latest

Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.4184095273
Short name T194
Test name
Test status
Simulation time 107109146 ps
CPU time 1 seconds
Started Mar 19 03:08:02 PM PDT 24
Finished Mar 19 03:08:04 PM PDT 24
Peak memory 208896 kb
Host smart-f8a8b741-3cc7-4f04-ba68-96ff08c16c37
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184095273 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.4184095273
Directory /workspace/39.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.216680594
Short name T447
Test name
Test status
Simulation time 804060902 ps
CPU time 1.05 seconds
Started Mar 19 03:08:14 PM PDT 24
Finished Mar 19 03:08:16 PM PDT 24
Peak memory 200284 kb
Host smart-c2256cb5-9ade-4315-917e-f31088f483c8
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216680594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_c
m_ctrl_config_regwen.216680594
Directory /workspace/39.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.875392691
Short name T768
Test name
Test status
Simulation time 1010855410 ps
CPU time 2.49 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:55 PM PDT 24
Peak memory 200620 kb
Host smart-fdb09485-0919-4233-bab4-4e6abfb296a4
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875392691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.875392691
Directory /workspace/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.460654134
Short name T674
Test name
Test status
Simulation time 1025896187 ps
CPU time 2.04 seconds
Started Mar 19 03:07:45 PM PDT 24
Finished Mar 19 03:07:48 PM PDT 24
Peak memory 200568 kb
Host smart-3523362b-c61b-4730-8c5d-a10ff40b217b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460654134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.460654134
Directory /workspace/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.1886064466
Short name T426
Test name
Test status
Simulation time 87320769 ps
CPU time 0.89 seconds
Started Mar 19 03:08:06 PM PDT 24
Finished Mar 19 03:08:07 PM PDT 24
Peak memory 198584 kb
Host smart-d6d94e3e-a5b0-435a-96b0-233b88542cd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886064466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1886064466
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/39.pwrmgr_smoke.3122486892
Short name T291
Test name
Test status
Simulation time 29262151 ps
CPU time 0.68 seconds
Started Mar 19 03:07:46 PM PDT 24
Finished Mar 19 03:07:47 PM PDT 24
Peak memory 198760 kb
Host smart-a6dc3534-1ee8-4267-a15f-479a99da9f38
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122486892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.3122486892
Directory /workspace/39.pwrmgr_smoke/latest

Test location /workspace/coverage/default/39.pwrmgr_stress_all.2794409705
Short name T605
Test name
Test status
Simulation time 464598568 ps
CPU time 2.1 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:55 PM PDT 24
Peak memory 200660 kb
Host smart-02040af3-cada-420e-9dbe-ffc657016d22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794409705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all.2794409705
Directory /workspace/39.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/39.pwrmgr_wakeup_reset.2429337412
Short name T112
Test name
Test status
Simulation time 137674322 ps
CPU time 0.96 seconds
Started Mar 19 03:08:04 PM PDT 24
Finished Mar 19 03:08:06 PM PDT 24
Peak memory 198516 kb
Host smart-ac6f8827-13f4-43c0-8941-a7294918e880
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429337412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.2429337412
Directory /workspace/39.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.2800919318
Short name T628
Test name
Test status
Simulation time 180190118 ps
CPU time 0.74 seconds
Started Mar 19 03:06:38 PM PDT 24
Finished Mar 19 03:06:39 PM PDT 24
Peak memory 197972 kb
Host smart-20ef672a-1b4e-495e-b369-5de0b3217fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800919318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.2800919318
Directory /workspace/4.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.3311815496
Short name T400
Test name
Test status
Simulation time 56601500 ps
CPU time 0.7 seconds
Started Mar 19 03:06:27 PM PDT 24
Finished Mar 19 03:06:28 PM PDT 24
Peak memory 198596 kb
Host smart-ac4e1a83-6c0e-4b6c-b59c-50d36eba447e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311815496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disa
ble_rom_integrity_check.3311815496
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.2832035744
Short name T281
Test name
Test status
Simulation time 31620110 ps
CPU time 0.69 seconds
Started Mar 19 03:06:29 PM PDT 24
Finished Mar 19 03:06:30 PM PDT 24
Peak memory 196740 kb
Host smart-90a5d408-2c0d-40c3-a87e-c5fe88d032cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832035744 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_
malfunc.2832035744
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.414899473
Short name T250
Test name
Test status
Simulation time 631340431 ps
CPU time 0.99 seconds
Started Mar 19 03:06:48 PM PDT 24
Finished Mar 19 03:06:50 PM PDT 24
Peak memory 197516 kb
Host smart-9a83b3b8-8acf-4284-847b-60b356a583a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414899473 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.414899473
Directory /workspace/4.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/4.pwrmgr_glitch.228475644
Short name T600
Test name
Test status
Simulation time 33220992 ps
CPU time 0.59 seconds
Started Mar 19 03:06:33 PM PDT 24
Finished Mar 19 03:06:34 PM PDT 24
Peak memory 196864 kb
Host smart-77b26440-9bdd-4bde-9fa5-eecb9cfa8d4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228475644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.228475644
Directory /workspace/4.pwrmgr_glitch/latest

Test location /workspace/coverage/default/4.pwrmgr_global_esc.1128137462
Short name T323
Test name
Test status
Simulation time 25705427 ps
CPU time 0.61 seconds
Started Mar 19 03:06:27 PM PDT 24
Finished Mar 19 03:06:28 PM PDT 24
Peak memory 197540 kb
Host smart-045e1063-22ea-4bc0-956a-4db1c11bc56c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128137462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.1128137462
Directory /workspace/4.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.941755922
Short name T270
Test name
Test status
Simulation time 42173688 ps
CPU time 0.76 seconds
Started Mar 19 03:06:49 PM PDT 24
Finished Mar 19 03:06:50 PM PDT 24
Peak memory 200768 kb
Host smart-f58d103b-2442-46fe-81ec-c782ab811237
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941755922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invalid
.941755922
Directory /workspace/4.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_lowpower_wakeup_race.3719631205
Short name T714
Test name
Test status
Simulation time 134704903 ps
CPU time 0.75 seconds
Started Mar 19 03:06:10 PM PDT 24
Finished Mar 19 03:06:11 PM PDT 24
Peak memory 197752 kb
Host smart-7b5c4cd7-9c4f-433a-96be-c696b77f68e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719631205 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wa
keup_race.3719631205
Directory /workspace/4.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/4.pwrmgr_reset.494299866
Short name T393
Test name
Test status
Simulation time 74763562 ps
CPU time 0.74 seconds
Started Mar 19 03:06:21 PM PDT 24
Finished Mar 19 03:06:22 PM PDT 24
Peak memory 198636 kb
Host smart-26640d14-fbb0-40f4-8f2a-65bda4e90282
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494299866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.494299866
Directory /workspace/4.pwrmgr_reset/latest

Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.2770131411
Short name T173
Test name
Test status
Simulation time 204282836 ps
CPU time 0.75 seconds
Started Mar 19 03:06:24 PM PDT 24
Finished Mar 19 03:06:26 PM PDT 24
Peak memory 208832 kb
Host smart-127b4693-95e5-4edc-835c-43a384725ed6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770131411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.2770131411
Directory /workspace/4.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm.1062869911
Short name T4
Test name
Test status
Simulation time 665721537 ps
CPU time 2.25 seconds
Started Mar 19 03:06:27 PM PDT 24
Finished Mar 19 03:06:29 PM PDT 24
Peak memory 217236 kb
Host smart-2963c13a-91d8-4d0b-ab69-2cf5d2f22a9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062869911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.1062869911
Directory /workspace/4.pwrmgr_sec_cm/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.2650592702
Short name T715
Test name
Test status
Simulation time 65594766 ps
CPU time 0.76 seconds
Started Mar 19 03:06:40 PM PDT 24
Finished Mar 19 03:06:41 PM PDT 24
Peak memory 198496 kb
Host smart-a2729562-b4b8-4562-a046-a892500a5293
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650592702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_c
m_ctrl_config_regwen.2650592702
Directory /workspace/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.254407298
Short name T189
Test name
Test status
Simulation time 833291100 ps
CPU time 2.87 seconds
Started Mar 19 03:06:45 PM PDT 24
Finished Mar 19 03:06:48 PM PDT 24
Peak memory 200388 kb
Host smart-41d55fae-f97e-4284-b2fb-8ee8daaff1f7
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254407298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.254407298
Directory /workspace/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2463572933
Short name T409
Test name
Test status
Simulation time 922695631 ps
CPU time 2.45 seconds
Started Mar 19 03:06:35 PM PDT 24
Finished Mar 19 03:06:37 PM PDT 24
Peak memory 200624 kb
Host smart-5256ddb4-f9bf-4f86-8fe6-716605909680
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463572933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2463572933
Directory /workspace/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.4072651454
Short name T378
Test name
Test status
Simulation time 52096843 ps
CPU time 0.9 seconds
Started Mar 19 03:06:23 PM PDT 24
Finished Mar 19 03:06:24 PM PDT 24
Peak memory 199060 kb
Host smart-3fafed2d-8484-4a12-98ff-f5efebd1ce8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072651454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.4072651454
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/4.pwrmgr_smoke.544556309
Short name T598
Test name
Test status
Simulation time 39104334 ps
CPU time 0.63 seconds
Started Mar 19 03:06:13 PM PDT 24
Finished Mar 19 03:06:14 PM PDT 24
Peak memory 198760 kb
Host smart-eb020232-d2fc-4c91-8b58-822b3946520c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544556309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.544556309
Directory /workspace/4.pwrmgr_smoke/latest

Test location /workspace/coverage/default/4.pwrmgr_stress_all.3883695473
Short name T791
Test name
Test status
Simulation time 43590619 ps
CPU time 0.81 seconds
Started Mar 19 03:06:29 PM PDT 24
Finished Mar 19 03:06:30 PM PDT 24
Peak memory 198208 kb
Host smart-80b7580a-51da-4b0a-b8d4-8ad32c1b2fbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883695473 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.3883695473
Directory /workspace/4.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/4.pwrmgr_wakeup_reset.1841793431
Short name T452
Test name
Test status
Simulation time 249398461 ps
CPU time 0.92 seconds
Started Mar 19 03:06:36 PM PDT 24
Finished Mar 19 03:06:37 PM PDT 24
Peak memory 199324 kb
Host smart-62959ea3-6b84-4a9a-9cab-df33aaac3c8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841793431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.1841793431
Directory /workspace/4.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.4124498644
Short name T15
Test name
Test status
Simulation time 45811407 ps
CPU time 0.69 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 197928 kb
Host smart-969b8482-d2a5-4cf0-b2ec-ae9bc09c2e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124498644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.4124498644
Directory /workspace/40.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.1314455345
Short name T243
Test name
Test status
Simulation time 91951241 ps
CPU time 0.68 seconds
Started Mar 19 03:08:03 PM PDT 24
Finished Mar 19 03:08:04 PM PDT 24
Peak memory 198144 kb
Host smart-42812ef5-83d5-4e43-8585-61d5ac5d9c73
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314455345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.1314455345
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.1955810982
Short name T277
Test name
Test status
Simulation time 31486159 ps
CPU time 0.61 seconds
Started Mar 19 03:08:02 PM PDT 24
Finished Mar 19 03:08:04 PM PDT 24
Peak memory 197460 kb
Host smart-a8e878c0-82ad-4ee6-ad37-ce81bc5187be
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955810982 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst
_malfunc.1955810982
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.160144087
Short name T779
Test name
Test status
Simulation time 323883855 ps
CPU time 0.91 seconds
Started Mar 19 03:07:54 PM PDT 24
Finished Mar 19 03:07:55 PM PDT 24
Peak memory 197524 kb
Host smart-7107e2be-f943-4946-af42-e04167004dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160144087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.160144087
Directory /workspace/40.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/40.pwrmgr_glitch.3999574863
Short name T852
Test name
Test status
Simulation time 66961736 ps
CPU time 0.61 seconds
Started Mar 19 03:07:59 PM PDT 24
Finished Mar 19 03:08:00 PM PDT 24
Peak memory 197416 kb
Host smart-a266e264-c952-4ffd-979e-d49ff05c1b7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999574863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.3999574863
Directory /workspace/40.pwrmgr_glitch/latest

Test location /workspace/coverage/default/40.pwrmgr_global_esc.624112609
Short name T287
Test name
Test status
Simulation time 35225482 ps
CPU time 0.64 seconds
Started Mar 19 03:07:48 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 197508 kb
Host smart-028f7ce4-7229-48ac-9027-c06d9a2ec6c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624112609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.624112609
Directory /workspace/40.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.2082913228
Short name T777
Test name
Test status
Simulation time 44284146 ps
CPU time 0.74 seconds
Started Mar 19 03:08:19 PM PDT 24
Finished Mar 19 03:08:19 PM PDT 24
Peak memory 200756 kb
Host smart-d65050d7-be7c-44f7-9763-1092b582ce3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082913228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.2082913228
Directory /workspace/40.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_lowpower_wakeup_race.2906381793
Short name T694
Test name
Test status
Simulation time 29289440 ps
CPU time 0.67 seconds
Started Mar 19 03:08:01 PM PDT 24
Finished Mar 19 03:08:02 PM PDT 24
Peak memory 198456 kb
Host smart-a035f9c7-d18a-46c0-bdf9-d74a9aa8026e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906381793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_w
akeup_race.2906381793
Directory /workspace/40.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/40.pwrmgr_reset.799766606
Short name T316
Test name
Test status
Simulation time 380198018 ps
CPU time 0.79 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 198512 kb
Host smart-fea196c6-58c4-4ff6-9bb6-f73625ad86d5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799766606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.799766606
Directory /workspace/40.pwrmgr_reset/latest

Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.4286941648
Short name T105
Test name
Test status
Simulation time 206054374 ps
CPU time 0.82 seconds
Started Mar 19 03:08:01 PM PDT 24
Finished Mar 19 03:08:04 PM PDT 24
Peak memory 208892 kb
Host smart-19dc4d5d-c94c-40cd-937e-4e3dd9cf2f0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286941648 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.4286941648
Directory /workspace/40.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.2195220558
Short name T538
Test name
Test status
Simulation time 146532379 ps
CPU time 0.94 seconds
Started Mar 19 03:07:49 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 199168 kb
Host smart-fa70bce9-065e-48b8-87f5-0d64a4e951d1
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195220558 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_
cm_ctrl_config_regwen.2195220558
Directory /workspace/40.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4013842533
Short name T819
Test name
Test status
Simulation time 752512384 ps
CPU time 2.79 seconds
Started Mar 19 03:08:00 PM PDT 24
Finished Mar 19 03:08:03 PM PDT 24
Peak memory 200476 kb
Host smart-e0689444-8d6d-492a-8cfe-67833ec50224
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013842533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4013842533
Directory /workspace/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2519348143
Short name T152
Test name
Test status
Simulation time 841441152 ps
CPU time 3.51 seconds
Started Mar 19 03:07:52 PM PDT 24
Finished Mar 19 03:07:56 PM PDT 24
Peak memory 200700 kb
Host smart-1a812329-8bd3-42ac-b5ca-7cc2e1eb07ee
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519348143 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2519348143
Directory /workspace/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.1146643106
Short name T537
Test name
Test status
Simulation time 90853041 ps
CPU time 0.84 seconds
Started Mar 19 03:07:55 PM PDT 24
Finished Mar 19 03:07:56 PM PDT 24
Peak memory 198676 kb
Host smart-61e11237-6ccc-4375-8e0b-8e8fe62e7e67
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146643106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1146643106
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/40.pwrmgr_smoke.2432918000
Short name T676
Test name
Test status
Simulation time 132936537 ps
CPU time 0.63 seconds
Started Mar 19 03:07:58 PM PDT 24
Finished Mar 19 03:07:59 PM PDT 24
Peak memory 197968 kb
Host smart-3148f21c-504e-43c3-9961-a6c2d62e8485
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432918000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.2432918000
Directory /workspace/40.pwrmgr_smoke/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup.744725053
Short name T853
Test name
Test status
Simulation time 184905273 ps
CPU time 0.75 seconds
Started Mar 19 03:08:02 PM PDT 24
Finished Mar 19 03:08:04 PM PDT 24
Peak memory 197972 kb
Host smart-37b70eb0-aaca-45df-a0f9-f9bc925e33aa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744725053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.744725053
Directory /workspace/40.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/40.pwrmgr_wakeup_reset.1716183230
Short name T240
Test name
Test status
Simulation time 207606904 ps
CPU time 1.23 seconds
Started Mar 19 03:07:46 PM PDT 24
Finished Mar 19 03:07:47 PM PDT 24
Peak memory 199536 kb
Host smart-dc7bff50-a7d4-4bbf-942b-5a629dbf44e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716183230 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.1716183230
Directory /workspace/40.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.504748755
Short name T543
Test name
Test status
Simulation time 75422219 ps
CPU time 0.78 seconds
Started Mar 19 03:08:08 PM PDT 24
Finished Mar 19 03:08:08 PM PDT 24
Peak memory 199248 kb
Host smart-0d83fda9-f284-423e-8a33-0465e37bdf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504748755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.504748755
Directory /workspace/41.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.3094006315
Short name T129
Test name
Test status
Simulation time 90023158 ps
CPU time 0.71 seconds
Started Mar 19 03:08:11 PM PDT 24
Finished Mar 19 03:08:13 PM PDT 24
Peak memory 198544 kb
Host smart-d03219aa-2a84-4ad1-8273-990d3ad75715
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094006315 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.3094006315
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.3106830401
Short name T147
Test name
Test status
Simulation time 36733563 ps
CPU time 0.6 seconds
Started Mar 19 03:08:16 PM PDT 24
Finished Mar 19 03:08:17 PM PDT 24
Peak memory 197416 kb
Host smart-f25bc76b-17a6-47a6-abf6-6b27608ccac4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106830401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.3106830401
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.3205121293
Short name T170
Test name
Test status
Simulation time 329650884 ps
CPU time 0.95 seconds
Started Mar 19 03:08:10 PM PDT 24
Finished Mar 19 03:08:11 PM PDT 24
Peak memory 197544 kb
Host smart-c8cec386-6738-4b4e-8017-67385f5e2f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205121293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.3205121293
Directory /workspace/41.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/41.pwrmgr_glitch.445425413
Short name T430
Test name
Test status
Simulation time 47180670 ps
CPU time 0.6 seconds
Started Mar 19 03:08:17 PM PDT 24
Finished Mar 19 03:08:17 PM PDT 24
Peak memory 196780 kb
Host smart-cefc1667-8c42-4f8b-92be-6fa9055bb622
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445425413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.445425413
Directory /workspace/41.pwrmgr_glitch/latest

Test location /workspace/coverage/default/41.pwrmgr_global_esc.2420007853
Short name T297
Test name
Test status
Simulation time 43578897 ps
CPU time 0.57 seconds
Started Mar 19 03:07:53 PM PDT 24
Finished Mar 19 03:07:53 PM PDT 24
Peak memory 197552 kb
Host smart-797c7021-27af-4585-bc31-98972f5b2b25
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420007853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.2420007853
Directory /workspace/41.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.3276297902
Short name T318
Test name
Test status
Simulation time 54659125 ps
CPU time 0.68 seconds
Started Mar 19 03:08:29 PM PDT 24
Finished Mar 19 03:08:31 PM PDT 24
Peak memory 200788 kb
Host smart-aff2df53-ca8b-4023-909f-4abc0fe2132a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276297902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.3276297902
Directory /workspace/41.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_reset.1071755221
Short name T493
Test name
Test status
Simulation time 116722434 ps
CPU time 0.76 seconds
Started Mar 19 03:08:08 PM PDT 24
Finished Mar 19 03:08:09 PM PDT 24
Peak memory 198584 kb
Host smart-50faaf6c-4751-4bc6-9f77-8afa712731e6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071755221 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.1071755221
Directory /workspace/41.pwrmgr_reset/latest

Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.630870771
Short name T675
Test name
Test status
Simulation time 100589621 ps
CPU time 1.15 seconds
Started Mar 19 03:08:04 PM PDT 24
Finished Mar 19 03:08:06 PM PDT 24
Peak memory 208864 kb
Host smart-b4a48c82-b6f1-437c-914f-071e37d213f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630870771 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.630870771
Directory /workspace/41.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2063017100
Short name T370
Test name
Test status
Simulation time 1013977250 ps
CPU time 2.02 seconds
Started Mar 19 03:08:12 PM PDT 24
Finished Mar 19 03:08:15 PM PDT 24
Peak memory 200588 kb
Host smart-bbda7e48-a56c-4a32-8cd8-1b22a5c3fc7e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063017100 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2063017100
Directory /workspace/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2191748201
Short name T330
Test name
Test status
Simulation time 812913487 ps
CPU time 3.33 seconds
Started Mar 19 03:08:21 PM PDT 24
Finished Mar 19 03:08:24 PM PDT 24
Peak memory 200636 kb
Host smart-c5bc183a-7b82-4471-acff-6b20a372f0ba
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191748201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2191748201
Directory /workspace/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3573688534
Short name T227
Test name
Test status
Simulation time 52513466 ps
CPU time 0.91 seconds
Started Mar 19 03:08:16 PM PDT 24
Finished Mar 19 03:08:18 PM PDT 24
Peak memory 198796 kb
Host smart-5e4c5401-ac34-433c-ab1c-7efb2a74289b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573688534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3573688534
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/41.pwrmgr_smoke.3713806600
Short name T805
Test name
Test status
Simulation time 51273592 ps
CPU time 0.66 seconds
Started Mar 19 03:08:17 PM PDT 24
Finished Mar 19 03:08:18 PM PDT 24
Peak memory 198728 kb
Host smart-9aef6aa0-3cd5-4bd9-bbcf-36a6270ad845
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713806600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.3713806600
Directory /workspace/41.pwrmgr_smoke/latest

Test location /workspace/coverage/default/41.pwrmgr_stress_all.1979304146
Short name T832
Test name
Test status
Simulation time 852266366 ps
CPU time 2.16 seconds
Started Mar 19 03:08:18 PM PDT 24
Finished Mar 19 03:08:20 PM PDT 24
Peak memory 200656 kb
Host smart-4e063537-66d8-4290-ae3f-3d50a96f51bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979304146 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.1979304146
Directory /workspace/41.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup.3335287595
Short name T256
Test name
Test status
Simulation time 67649577 ps
CPU time 0.72 seconds
Started Mar 19 03:08:06 PM PDT 24
Finished Mar 19 03:08:07 PM PDT 24
Peak memory 197684 kb
Host smart-544c4560-054c-4934-a1f4-8f3c21035af5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335287595 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.3335287595
Directory /workspace/41.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/41.pwrmgr_wakeup_reset.3914807828
Short name T599
Test name
Test status
Simulation time 255026221 ps
CPU time 1.3 seconds
Started Mar 19 03:07:51 PM PDT 24
Finished Mar 19 03:07:54 PM PDT 24
Peak memory 199524 kb
Host smart-06f487b3-72df-4544-be7a-b291f4260986
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914807828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.3914807828
Directory /workspace/41.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.926155627
Short name T418
Test name
Test status
Simulation time 23844792 ps
CPU time 0.64 seconds
Started Mar 19 03:08:11 PM PDT 24
Finished Mar 19 03:08:12 PM PDT 24
Peak memory 197448 kb
Host smart-41995f66-4936-4665-bb6b-d42e08a2136d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926155627 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.926155627
Directory /workspace/42.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.3478098331
Short name T117
Test name
Test status
Simulation time 76149705 ps
CPU time 0.68 seconds
Started Mar 19 03:08:14 PM PDT 24
Finished Mar 19 03:08:15 PM PDT 24
Peak memory 197868 kb
Host smart-f3ee26b4-9f38-46ec-a634-6e1e816d0ea9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478098331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_dis
able_rom_integrity_check.3478098331
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.110519555
Short name T575
Test name
Test status
Simulation time 38599810 ps
CPU time 0.58 seconds
Started Mar 19 03:08:13 PM PDT 24
Finished Mar 19 03:08:14 PM PDT 24
Peak memory 196768 kb
Host smart-2d1ae72e-4f83-4d4c-a640-1b71ff0c309f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110519555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst_
malfunc.110519555
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.125583623
Short name T703
Test name
Test status
Simulation time 891431365 ps
CPU time 0.96 seconds
Started Mar 19 03:08:03 PM PDT 24
Finished Mar 19 03:08:05 PM PDT 24
Peak memory 197508 kb
Host smart-9ce38355-375e-4a1a-9688-9ec6ef8a62c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125583623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.125583623
Directory /workspace/42.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/42.pwrmgr_glitch.2683005178
Short name T333
Test name
Test status
Simulation time 115836140 ps
CPU time 0.65 seconds
Started Mar 19 03:08:15 PM PDT 24
Finished Mar 19 03:08:16 PM PDT 24
Peak memory 197564 kb
Host smart-300280af-4357-4364-9500-d5499c30ed01
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683005178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.2683005178
Directory /workspace/42.pwrmgr_glitch/latest

Test location /workspace/coverage/default/42.pwrmgr_global_esc.1160327608
Short name T30
Test name
Test status
Simulation time 42628868 ps
CPU time 0.71 seconds
Started Mar 19 03:08:20 PM PDT 24
Finished Mar 19 03:08:21 PM PDT 24
Peak memory 197516 kb
Host smart-2ed2ef73-11a6-4a76-8728-b0a65adb6654
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160327608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.1160327608
Directory /workspace/42.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.1404724238
Short name T260
Test name
Test status
Simulation time 71723506 ps
CPU time 0.68 seconds
Started Mar 19 03:08:00 PM PDT 24
Finished Mar 19 03:08:02 PM PDT 24
Peak memory 200748 kb
Host smart-c44b807f-bb38-47b0-96d1-b5e4c63e4db3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404724238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_inval
id.1404724238
Directory /workspace/42.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/42.pwrmgr_lowpower_wakeup_race.4097275382
Short name T313
Test name
Test status
Simulation time 36689180 ps
CPU time 0.7 seconds
Started Mar 19 03:08:13 PM PDT 24
Finished Mar 19 03:08:14 PM PDT 24
Peak memory 198488 kb
Host smart-ce037132-c92f-4dd1-9f40-d734b4dc5aac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097275382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_w
akeup_race.4097275382
Directory /workspace/42.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/42.pwrmgr_reset.2013115076
Short name T390
Test name
Test status
Simulation time 71174853 ps
CPU time 0.71 seconds
Started Mar 19 03:08:18 PM PDT 24
Finished Mar 19 03:08:19 PM PDT 24
Peak memory 198032 kb
Host smart-6dc00a7b-2069-431b-aaa9-b70d4633ca90
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013115076 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.2013115076
Directory /workspace/42.pwrmgr_reset/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.1784200085
Short name T245
Test name
Test status
Simulation time 516207085 ps
CPU time 0.96 seconds
Started Mar 19 03:08:09 PM PDT 24
Finished Mar 19 03:08:10 PM PDT 24
Peak memory 200272 kb
Host smart-e617b4af-d1bd-484a-bac5-bac882ac6a87
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784200085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_
cm_ctrl_config_regwen.1784200085
Directory /workspace/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2106284756
Short name T417
Test name
Test status
Simulation time 835298438 ps
CPU time 2.67 seconds
Started Mar 19 03:07:52 PM PDT 24
Finished Mar 19 03:07:56 PM PDT 24
Peak memory 200424 kb
Host smart-f71ad3e1-35d0-4711-aebd-192b73cc4aa7
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106284756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2106284756
Directory /workspace/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2783301700
Short name T413
Test name
Test status
Simulation time 869398396 ps
CPU time 3.27 seconds
Started Mar 19 03:08:19 PM PDT 24
Finished Mar 19 03:08:22 PM PDT 24
Peak memory 200668 kb
Host smart-642795f8-8418-4c60-95e5-b910b851837d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783301700 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2783301700
Directory /workspace/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.2222013112
Short name T814
Test name
Test status
Simulation time 51699340 ps
CPU time 0.87 seconds
Started Mar 19 03:08:22 PM PDT 24
Finished Mar 19 03:08:23 PM PDT 24
Peak memory 199004 kb
Host smart-93002e52-9ca5-4ea6-a51f-89a4fda318c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222013112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2222013112
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/42.pwrmgr_smoke.3657034738
Short name T644
Test name
Test status
Simulation time 36168105 ps
CPU time 0.62 seconds
Started Mar 19 03:08:07 PM PDT 24
Finished Mar 19 03:08:08 PM PDT 24
Peak memory 197804 kb
Host smart-45862649-4c5a-4489-a781-201905862b07
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657034738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.3657034738
Directory /workspace/42.pwrmgr_smoke/latest

Test location /workspace/coverage/default/42.pwrmgr_wakeup_reset.651915299
Short name T775
Test name
Test status
Simulation time 35585858 ps
CPU time 0.63 seconds
Started Mar 19 03:08:18 PM PDT 24
Finished Mar 19 03:08:19 PM PDT 24
Peak memory 197904 kb
Host smart-4295ef78-1ec4-4161-bc42-4e294c5f6300
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651915299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.651915299
Directory /workspace/42.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.174302523
Short name T31
Test name
Test status
Simulation time 67644866 ps
CPU time 0.8 seconds
Started Mar 19 03:08:03 PM PDT 24
Finished Mar 19 03:08:04 PM PDT 24
Peak memory 199304 kb
Host smart-bdb0bbc7-7427-42c8-809c-ff90187af4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174302523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.174302523
Directory /workspace/43.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.3450250421
Short name T355
Test name
Test status
Simulation time 68926546 ps
CPU time 0.74 seconds
Started Mar 19 03:08:18 PM PDT 24
Finished Mar 19 03:08:19 PM PDT 24
Peak memory 198504 kb
Host smart-ab21e168-849f-4977-ba8e-527d14f76a41
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450250421 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis
able_rom_integrity_check.3450250421
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.330450742
Short name T780
Test name
Test status
Simulation time 31959810 ps
CPU time 0.63 seconds
Started Mar 19 03:08:14 PM PDT 24
Finished Mar 19 03:08:15 PM PDT 24
Peak memory 197420 kb
Host smart-d0c7fec1-fc62-4807-af23-443447c3e5f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330450742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst_
malfunc.330450742
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.599302457
Short name T622
Test name
Test status
Simulation time 2136283713 ps
CPU time 0.96 seconds
Started Mar 19 03:08:19 PM PDT 24
Finished Mar 19 03:08:20 PM PDT 24
Peak memory 197524 kb
Host smart-195e9c51-fc99-49f4-bccf-4755664a4517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599302457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.599302457
Directory /workspace/43.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/43.pwrmgr_glitch.4198164325
Short name T215
Test name
Test status
Simulation time 41432474 ps
CPU time 0.64 seconds
Started Mar 19 03:08:01 PM PDT 24
Finished Mar 19 03:08:02 PM PDT 24
Peak memory 196624 kb
Host smart-9f764a6e-6d2b-4bca-bf31-bba5fe862ae8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198164325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.4198164325
Directory /workspace/43.pwrmgr_glitch/latest

Test location /workspace/coverage/default/43.pwrmgr_global_esc.955940604
Short name T566
Test name
Test status
Simulation time 42205547 ps
CPU time 0.74 seconds
Started Mar 19 03:08:16 PM PDT 24
Finished Mar 19 03:08:17 PM PDT 24
Peak memory 197820 kb
Host smart-9c8e0b35-2b43-46ba-acf7-5751e5599119
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955940604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.955940604
Directory /workspace/43.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.35614333
Short name T365
Test name
Test status
Simulation time 41571241 ps
CPU time 0.72 seconds
Started Mar 19 03:08:03 PM PDT 24
Finished Mar 19 03:08:05 PM PDT 24
Peak memory 200812 kb
Host smart-24ccb980-6a88-41ec-8c2d-f117629bfa3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35614333 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invali
d_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_invalid
.35614333
Directory /workspace/43.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_lowpower_wakeup_race.3118471470
Short name T720
Test name
Test status
Simulation time 300204815 ps
CPU time 0.98 seconds
Started Mar 19 03:08:17 PM PDT 24
Finished Mar 19 03:08:18 PM PDT 24
Peak memory 198896 kb
Host smart-8ffc395f-c0c0-458d-a2c2-1f04ad14d4b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118471470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_w
akeup_race.3118471470
Directory /workspace/43.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/43.pwrmgr_reset.621455341
Short name T166
Test name
Test status
Simulation time 90161150 ps
CPU time 0.73 seconds
Started Mar 19 03:08:24 PM PDT 24
Finished Mar 19 03:08:25 PM PDT 24
Peak memory 198532 kb
Host smart-180bae50-9179-4ff7-b184-2f3f6c77ebd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621455341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.621455341
Directory /workspace/43.pwrmgr_reset/latest

Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.1796174727
Short name T760
Test name
Test status
Simulation time 161102125 ps
CPU time 0.8 seconds
Started Mar 19 03:08:03 PM PDT 24
Finished Mar 19 03:08:04 PM PDT 24
Peak memory 208960 kb
Host smart-a19d1176-60ac-47b4-b3da-c3f4e793cf26
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796174727 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.1796174727
Directory /workspace/43.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.3561962094
Short name T45
Test name
Test status
Simulation time 36056653 ps
CPU time 0.77 seconds
Started Mar 19 03:08:18 PM PDT 24
Finished Mar 19 03:08:19 PM PDT 24
Peak memory 198760 kb
Host smart-a607ed2f-40b5-48e6-8dc3-635a2d7a6381
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561962094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_
cm_ctrl_config_regwen.3561962094
Directory /workspace/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.254120414
Short name T72
Test name
Test status
Simulation time 857225717 ps
CPU time 3.14 seconds
Started Mar 19 03:08:23 PM PDT 24
Finished Mar 19 03:08:32 PM PDT 24
Peak memory 200704 kb
Host smart-b089dc1f-fe49-401f-a2e9-837e2d78ae0b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254120414 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.254120414
Directory /workspace/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3220664897
Short name T382
Test name
Test status
Simulation time 1223415576 ps
CPU time 2.33 seconds
Started Mar 19 03:07:50 PM PDT 24
Finished Mar 19 03:07:55 PM PDT 24
Peak memory 200652 kb
Host smart-4178cdc3-a777-44f4-8e89-4ce79e2e3542
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220664897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3220664897
Directory /workspace/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.3637185497
Short name T211
Test name
Test status
Simulation time 66712664 ps
CPU time 0.94 seconds
Started Mar 19 03:08:01 PM PDT 24
Finished Mar 19 03:08:03 PM PDT 24
Peak memory 198992 kb
Host smart-4eec5119-de63-4ce1-acfe-a02a1a7078d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637185497 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3637185497
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/43.pwrmgr_smoke.2173358813
Short name T208
Test name
Test status
Simulation time 73317157 ps
CPU time 0.59 seconds
Started Mar 19 03:07:58 PM PDT 24
Finished Mar 19 03:08:00 PM PDT 24
Peak memory 197916 kb
Host smart-72cdb909-adef-47e3-938a-93bd50694a02
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173358813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.2173358813
Directory /workspace/43.pwrmgr_smoke/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup.3652794951
Short name T320
Test name
Test status
Simulation time 274012125 ps
CPU time 1.22 seconds
Started Mar 19 03:08:05 PM PDT 24
Finished Mar 19 03:08:07 PM PDT 24
Peak memory 199080 kb
Host smart-c1701b8c-58f9-4b2e-941e-efc5183ffd65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652794951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.3652794951
Directory /workspace/43.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/43.pwrmgr_wakeup_reset.1645675932
Short name T774
Test name
Test status
Simulation time 203879882 ps
CPU time 1.29 seconds
Started Mar 19 03:08:18 PM PDT 24
Finished Mar 19 03:08:20 PM PDT 24
Peak memory 199412 kb
Host smart-a5ed15e7-c92b-422b-9f75-c61b3c931f93
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645675932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.1645675932
Directory /workspace/43.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.2619628671
Short name T869
Test name
Test status
Simulation time 60421422 ps
CPU time 0.79 seconds
Started Mar 19 03:08:04 PM PDT 24
Finished Mar 19 03:08:05 PM PDT 24
Peak memory 199328 kb
Host smart-2a7ded05-001f-400e-9f99-612972b4b9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619628671 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.2619628671
Directory /workspace/44.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.1479607812
Short name T509
Test name
Test status
Simulation time 118074994 ps
CPU time 0.76 seconds
Started Mar 19 03:08:04 PM PDT 24
Finished Mar 19 03:08:06 PM PDT 24
Peak memory 198188 kb
Host smart-757ab509-61da-4eb8-a03e-2b4fecbc5389
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479607812 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_dis
able_rom_integrity_check.1479607812
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.3617608734
Short name T634
Test name
Test status
Simulation time 29662871 ps
CPU time 0.63 seconds
Started Mar 19 03:08:09 PM PDT 24
Finished Mar 19 03:08:10 PM PDT 24
Peak memory 197448 kb
Host smart-f4e3bc98-7da9-42d5-b2b6-7a4bd13b694a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617608734 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst
_malfunc.3617608734
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.2978688586
Short name T294
Test name
Test status
Simulation time 320626889 ps
CPU time 0.95 seconds
Started Mar 19 03:08:04 PM PDT 24
Finished Mar 19 03:08:06 PM PDT 24
Peak memory 197824 kb
Host smart-cac0e1cf-48e5-43cb-8eb5-ecd9700f2a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978688586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.2978688586
Directory /workspace/44.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/44.pwrmgr_glitch.773860337
Short name T868
Test name
Test status
Simulation time 29287078 ps
CPU time 0.57 seconds
Started Mar 19 03:08:10 PM PDT 24
Finished Mar 19 03:08:10 PM PDT 24
Peak memory 197540 kb
Host smart-912ec0a9-931c-404b-adc8-1083340b8cc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773860337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.773860337
Directory /workspace/44.pwrmgr_glitch/latest

Test location /workspace/coverage/default/44.pwrmgr_global_esc.1872497580
Short name T209
Test name
Test status
Simulation time 69983785 ps
CPU time 0.61 seconds
Started Mar 19 03:08:06 PM PDT 24
Finished Mar 19 03:08:07 PM PDT 24
Peak memory 197560 kb
Host smart-29da186a-0fb3-4926-8a97-d111fd53cf6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872497580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.1872497580
Directory /workspace/44.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/44.pwrmgr_reset.3867666532
Short name T369
Test name
Test status
Simulation time 80982369 ps
CPU time 1.04 seconds
Started Mar 19 03:08:13 PM PDT 24
Finished Mar 19 03:08:14 PM PDT 24
Peak memory 199396 kb
Host smart-5bdee68b-f83a-4a07-bc2a-bd4b59acf02d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867666532 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.3867666532
Directory /workspace/44.pwrmgr_reset/latest

Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.4117834109
Short name T764
Test name
Test status
Simulation time 104297446 ps
CPU time 0.96 seconds
Started Mar 19 03:08:02 PM PDT 24
Finished Mar 19 03:08:04 PM PDT 24
Peak memory 208936 kb
Host smart-a26a19b3-7812-4934-82a7-8b12ed981668
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117834109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.4117834109
Directory /workspace/44.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.2872966562
Short name T325
Test name
Test status
Simulation time 258680089 ps
CPU time 1.16 seconds
Started Mar 19 03:08:04 PM PDT 24
Finished Mar 19 03:08:05 PM PDT 24
Peak memory 200248 kb
Host smart-de025c7f-e43b-46a5-a74a-1548bd6dec11
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872966562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_
cm_ctrl_config_regwen.2872966562
Directory /workspace/44.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3586876927
Short name T540
Test name
Test status
Simulation time 1187440875 ps
CPU time 2.21 seconds
Started Mar 19 03:07:54 PM PDT 24
Finished Mar 19 03:07:56 PM PDT 24
Peak memory 200660 kb
Host smart-3976d59d-45de-4700-a432-88c5f4d57a9b
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586876927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3586876927
Directory /workspace/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3258977914
Short name T285
Test name
Test status
Simulation time 1230874807 ps
CPU time 1.84 seconds
Started Mar 19 03:07:58 PM PDT 24
Finished Mar 19 03:08:00 PM PDT 24
Peak memory 200348 kb
Host smart-b0623b2c-3699-43b9-80a5-94067fd2fda9
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258977914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3258977914
Directory /workspace/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.420697977
Short name T758
Test name
Test status
Simulation time 281068279 ps
CPU time 0.9 seconds
Started Mar 19 03:08:00 PM PDT 24
Finished Mar 19 03:08:02 PM PDT 24
Peak memory 198732 kb
Host smart-83ece962-e663-402c-a407-6007badd89ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420697977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig_
mubi.420697977
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/44.pwrmgr_smoke.4263186906
Short name T403
Test name
Test status
Simulation time 28525867 ps
CPU time 0.67 seconds
Started Mar 19 03:08:27 PM PDT 24
Finished Mar 19 03:08:28 PM PDT 24
Peak memory 197924 kb
Host smart-9900eec0-cdc8-4240-896e-a6022e61dc46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263186906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.4263186906
Directory /workspace/44.pwrmgr_smoke/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup.3445169704
Short name T492
Test name
Test status
Simulation time 116510384 ps
CPU time 0.91 seconds
Started Mar 19 03:08:17 PM PDT 24
Finished Mar 19 03:08:18 PM PDT 24
Peak memory 198492 kb
Host smart-6ec6d734-e8ab-429d-b027-c54a8b8c3291
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445169704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.3445169704
Directory /workspace/44.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/44.pwrmgr_wakeup_reset.4279967342
Short name T696
Test name
Test status
Simulation time 340213061 ps
CPU time 0.81 seconds
Started Mar 19 03:08:23 PM PDT 24
Finished Mar 19 03:08:24 PM PDT 24
Peak memory 198668 kb
Host smart-253a0f59-fec0-43ad-ac86-4c43023ddd96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279967342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.4279967342
Directory /workspace/44.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.2117610131
Short name T33
Test name
Test status
Simulation time 36826734 ps
CPU time 0.82 seconds
Started Mar 19 03:08:19 PM PDT 24
Finished Mar 19 03:08:20 PM PDT 24
Peak memory 199324 kb
Host smart-76e0fabe-15fe-492d-b80d-bba3d6239310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117610131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.2117610131
Directory /workspace/45.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.1810577554
Short name T579
Test name
Test status
Simulation time 77257115 ps
CPU time 0.76 seconds
Started Mar 19 03:08:27 PM PDT 24
Finished Mar 19 03:08:29 PM PDT 24
Peak memory 198100 kb
Host smart-724c7aa4-ffbd-4616-98ea-85308c2e8d3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810577554 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.1810577554
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.3943713008
Short name T490
Test name
Test status
Simulation time 40261088 ps
CPU time 0.61 seconds
Started Mar 19 03:08:16 PM PDT 24
Finished Mar 19 03:08:16 PM PDT 24
Peak memory 197472 kb
Host smart-7a920f56-43d9-4f27-a764-9c8750a5a9b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943713008 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.3943713008
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.2467358147
Short name T177
Test name
Test status
Simulation time 168303817 ps
CPU time 1.02 seconds
Started Mar 19 03:08:29 PM PDT 24
Finished Mar 19 03:08:32 PM PDT 24
Peak memory 197824 kb
Host smart-5c174f04-7d7a-4dc8-9a81-da282657d66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467358147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.2467358147
Directory /workspace/45.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/45.pwrmgr_glitch.2521683859
Short name T627
Test name
Test status
Simulation time 51173229 ps
CPU time 0.69 seconds
Started Mar 19 03:08:23 PM PDT 24
Finished Mar 19 03:08:24 PM PDT 24
Peak memory 197400 kb
Host smart-448b680d-275d-4450-b576-e292bbc20707
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521683859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.2521683859
Directory /workspace/45.pwrmgr_glitch/latest

Test location /workspace/coverage/default/45.pwrmgr_global_esc.2257283944
Short name T252
Test name
Test status
Simulation time 43816161 ps
CPU time 0.56 seconds
Started Mar 19 03:08:16 PM PDT 24
Finished Mar 19 03:08:17 PM PDT 24
Peak memory 197544 kb
Host smart-3ae6838e-b9d6-47da-b345-0c3891b43b9e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257283944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.2257283944
Directory /workspace/45.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.3147765220
Short name T637
Test name
Test status
Simulation time 74351289 ps
CPU time 0.65 seconds
Started Mar 19 03:08:38 PM PDT 24
Finished Mar 19 03:08:38 PM PDT 24
Peak memory 200788 kb
Host smart-4ed20b9c-5125-4607-ab6d-2ec07cbcb5c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147765220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.3147765220
Directory /workspace/45.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_lowpower_wakeup_race.1794525915
Short name T306
Test name
Test status
Simulation time 704927211 ps
CPU time 0.94 seconds
Started Mar 19 03:08:24 PM PDT 24
Finished Mar 19 03:08:25 PM PDT 24
Peak memory 199268 kb
Host smart-991297b5-5e62-4e8d-a1b0-bd4f4574fd41
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794525915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_w
akeup_race.1794525915
Directory /workspace/45.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/45.pwrmgr_reset.2031539850
Short name T11
Test name
Test status
Simulation time 80076420 ps
CPU time 1.06 seconds
Started Mar 19 03:08:18 PM PDT 24
Finished Mar 19 03:08:19 PM PDT 24
Peak memory 199496 kb
Host smart-4e356225-d2be-4873-95f1-8fb52c0d6514
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031539850 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.2031539850
Directory /workspace/45.pwrmgr_reset/latest

Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.244597716
Short name T803
Test name
Test status
Simulation time 242425608 ps
CPU time 0.9 seconds
Started Mar 19 03:08:18 PM PDT 24
Finished Mar 19 03:08:19 PM PDT 24
Peak memory 208972 kb
Host smart-d9fba576-bf1f-4aac-be4f-ffd6ee7281f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244597716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.244597716
Directory /workspace/45.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.3699664704
Short name T491
Test name
Test status
Simulation time 157443448 ps
CPU time 0.96 seconds
Started Mar 19 03:08:14 PM PDT 24
Finished Mar 19 03:08:15 PM PDT 24
Peak memory 199600 kb
Host smart-30715fe9-9e43-4354-a6e3-9b844d0db0f7
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699664704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_
cm_ctrl_config_regwen.3699664704
Directory /workspace/45.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.898536256
Short name T68
Test name
Test status
Simulation time 960516159 ps
CPU time 2.03 seconds
Started Mar 19 03:08:33 PM PDT 24
Finished Mar 19 03:08:36 PM PDT 24
Peak memory 200584 kb
Host smart-dbe42f75-e2cd-4970-a3db-aa09d4f8178c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898536256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.898536256
Directory /workspace/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2821801503
Short name T745
Test name
Test status
Simulation time 2798733625 ps
CPU time 2.09 seconds
Started Mar 19 03:08:25 PM PDT 24
Finished Mar 19 03:08:28 PM PDT 24
Peak memory 200696 kb
Host smart-b0983b98-0797-4417-a37a-bcadb61f7dc7
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821801503 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2821801503
Directory /workspace/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.3281270926
Short name T249
Test name
Test status
Simulation time 64948884 ps
CPU time 0.96 seconds
Started Mar 19 03:08:27 PM PDT 24
Finished Mar 19 03:08:30 PM PDT 24
Peak memory 198592 kb
Host smart-a36a24d5-4bbf-4450-8137-97b08d138f0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281270926 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3281270926
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/45.pwrmgr_smoke.2110682519
Short name T388
Test name
Test status
Simulation time 48978568 ps
CPU time 0.68 seconds
Started Mar 19 03:08:27 PM PDT 24
Finished Mar 19 03:08:29 PM PDT 24
Peak memory 197916 kb
Host smart-2e677b9d-75a0-4a12-bd07-add724c5fb9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110682519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.2110682519
Directory /workspace/45.pwrmgr_smoke/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup.142769626
Short name T871
Test name
Test status
Simulation time 242588322 ps
CPU time 0.79 seconds
Started Mar 19 03:08:14 PM PDT 24
Finished Mar 19 03:08:16 PM PDT 24
Peak memory 197608 kb
Host smart-84d7faea-84c1-4750-9cad-ce7490a1ac85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142769626 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup.142769626
Directory /workspace/45.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/45.pwrmgr_wakeup_reset.4123163134
Short name T784
Test name
Test status
Simulation time 286694551 ps
CPU time 1.61 seconds
Started Mar 19 03:08:24 PM PDT 24
Finished Mar 19 03:08:26 PM PDT 24
Peak memory 200536 kb
Host smart-19c489e9-0b1b-479e-bfac-89c0c2b239f7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123163134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.4123163134
Directory /workspace/45.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.7097407
Short name T114
Test name
Test status
Simulation time 61923628 ps
CPU time 0.8 seconds
Started Mar 19 03:08:30 PM PDT 24
Finished Mar 19 03:08:32 PM PDT 24
Peak memory 199264 kb
Host smart-57931350-d813-4c79-8142-f28b6d4e38bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7097407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.7097407
Directory /workspace/46.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.147987604
Short name T789
Test name
Test status
Simulation time 63180512 ps
CPU time 0.84 seconds
Started Mar 19 03:08:15 PM PDT 24
Finished Mar 19 03:08:16 PM PDT 24
Peak memory 198544 kb
Host smart-cf7160d6-2468-4b67-b73e-c212896d3f25
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147987604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disa
ble_rom_integrity_check.147987604
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.1754043712
Short name T241
Test name
Test status
Simulation time 34477383 ps
CPU time 0.61 seconds
Started Mar 19 03:08:23 PM PDT 24
Finished Mar 19 03:08:24 PM PDT 24
Peak memory 197468 kb
Host smart-928d0b55-6486-4024-a66d-46774559abc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754043712 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst
_malfunc.1754043712
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.1227861359
Short name T284
Test name
Test status
Simulation time 631952614 ps
CPU time 0.96 seconds
Started Mar 19 03:08:27 PM PDT 24
Finished Mar 19 03:08:29 PM PDT 24
Peak memory 197864 kb
Host smart-c64fd7d7-84bc-482b-ad87-8c555592dc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227861359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.1227861359
Directory /workspace/46.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/46.pwrmgr_glitch.2033306426
Short name T477
Test name
Test status
Simulation time 40443149 ps
CPU time 0.64 seconds
Started Mar 19 03:08:31 PM PDT 24
Finished Mar 19 03:08:32 PM PDT 24
Peak memory 197544 kb
Host smart-80745e18-4b7e-46a4-a617-0a638bcd222a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033306426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.2033306426
Directory /workspace/46.pwrmgr_glitch/latest

Test location /workspace/coverage/default/46.pwrmgr_global_esc.2304967653
Short name T702
Test name
Test status
Simulation time 94885219 ps
CPU time 0.64 seconds
Started Mar 19 03:08:07 PM PDT 24
Finished Mar 19 03:08:08 PM PDT 24
Peak memory 197544 kb
Host smart-12cd00fb-ac65-468e-93cf-0f731f245e9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304967653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.2304967653
Directory /workspace/46.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.2099530406
Short name T168
Test name
Test status
Simulation time 211331871 ps
CPU time 0.68 seconds
Started Mar 19 03:08:20 PM PDT 24
Finished Mar 19 03:08:20 PM PDT 24
Peak memory 200824 kb
Host smart-3a394c2d-65a6-4634-a587-9d3fdccb6dfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099530406 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_inval
id.2099530406
Directory /workspace/46.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_lowpower_wakeup_race.1844590343
Short name T214
Test name
Test status
Simulation time 214449816 ps
CPU time 0.81 seconds
Started Mar 19 03:08:33 PM PDT 24
Finished Mar 19 03:08:34 PM PDT 24
Peak memory 197948 kb
Host smart-d6b554b8-a0e2-4af3-84dd-d5645cb81f97
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844590343 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_w
akeup_race.1844590343
Directory /workspace/46.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/46.pwrmgr_reset.2589124167
Short name T169
Test name
Test status
Simulation time 45521392 ps
CPU time 0.73 seconds
Started Mar 19 03:08:26 PM PDT 24
Finished Mar 19 03:08:27 PM PDT 24
Peak memory 198560 kb
Host smart-b7777b4c-343c-45f0-80f4-abda50248d3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589124167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.2589124167
Directory /workspace/46.pwrmgr_reset/latest

Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.4048227101
Short name T743
Test name
Test status
Simulation time 108250331 ps
CPU time 0.9 seconds
Started Mar 19 03:08:16 PM PDT 24
Finished Mar 19 03:08:17 PM PDT 24
Peak memory 208864 kb
Host smart-a3eaa7ca-1ab8-4bb8-ba29-2740700686a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048227101 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.4048227101
Directory /workspace/46.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.4186703120
Short name T747
Test name
Test status
Simulation time 304404714 ps
CPU time 0.98 seconds
Started Mar 19 03:08:29 PM PDT 24
Finished Mar 19 03:08:32 PM PDT 24
Peak memory 199328 kb
Host smart-e2ddf0cc-3745-4089-9329-2bc445533a5d
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186703120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_
cm_ctrl_config_regwen.4186703120
Directory /workspace/46.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4104483660
Short name T184
Test name
Test status
Simulation time 1137107113 ps
CPU time 2.19 seconds
Started Mar 19 03:08:29 PM PDT 24
Finished Mar 19 03:08:33 PM PDT 24
Peak memory 200540 kb
Host smart-d49bdca3-2751-4fc5-aee8-d81f2338028c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104483660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4104483660
Directory /workspace/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1769514956
Short name T726
Test name
Test status
Simulation time 1301568218 ps
CPU time 2.2 seconds
Started Mar 19 03:08:35 PM PDT 24
Finished Mar 19 03:08:38 PM PDT 24
Peak memory 200640 kb
Host smart-3083c0ed-4576-4c30-9534-6afc47b0181b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769514956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1769514956
Directory /workspace/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.2864000941
Short name T836
Test name
Test status
Simulation time 117035260 ps
CPU time 0.88 seconds
Started Mar 19 03:08:17 PM PDT 24
Finished Mar 19 03:08:18 PM PDT 24
Peak memory 198820 kb
Host smart-e5b6da02-d962-4708-b3ef-2c7f16af5115
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864000941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2864000941
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/46.pwrmgr_smoke.595503802
Short name T654
Test name
Test status
Simulation time 38983183 ps
CPU time 0.67 seconds
Started Mar 19 03:08:17 PM PDT 24
Finished Mar 19 03:08:18 PM PDT 24
Peak memory 198756 kb
Host smart-4e2daaec-e6c4-47d1-88e4-672b8c7a41c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595503802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.595503802
Directory /workspace/46.pwrmgr_smoke/latest

Test location /workspace/coverage/default/46.pwrmgr_wakeup_reset.222063836
Short name T843
Test name
Test status
Simulation time 410537760 ps
CPU time 1.11 seconds
Started Mar 19 03:08:23 PM PDT 24
Finished Mar 19 03:08:24 PM PDT 24
Peak memory 200580 kb
Host smart-081f28f8-a9db-460a-82a9-9bed7dbc1a7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222063836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.222063836
Directory /workspace/46.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.2017971564
Short name T471
Test name
Test status
Simulation time 60362421 ps
CPU time 0.68 seconds
Started Mar 19 03:08:23 PM PDT 24
Finished Mar 19 03:08:24 PM PDT 24
Peak memory 197984 kb
Host smart-b1fa1f68-6b92-4b6f-913c-b1b1dcd04038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017971564 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.2017971564
Directory /workspace/47.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.3933368810
Short name T510
Test name
Test status
Simulation time 59338027 ps
CPU time 0.85 seconds
Started Mar 19 03:08:30 PM PDT 24
Finished Mar 19 03:08:32 PM PDT 24
Peak memory 198536 kb
Host smart-c8efa4d4-b11b-442c-a0a6-d2d8654c3dd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933368810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_dis
able_rom_integrity_check.3933368810
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.4231898211
Short name T810
Test name
Test status
Simulation time 48269767 ps
CPU time 0.58 seconds
Started Mar 19 03:08:12 PM PDT 24
Finished Mar 19 03:08:12 PM PDT 24
Peak memory 197452 kb
Host smart-1acd1c77-09e9-4c1b-bc86-64a95facca05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231898211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst
_malfunc.4231898211
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.816269353
Short name T527
Test name
Test status
Simulation time 166457488 ps
CPU time 0.98 seconds
Started Mar 19 03:08:27 PM PDT 24
Finished Mar 19 03:08:30 PM PDT 24
Peak memory 197804 kb
Host smart-9d0ca6ca-5020-4df9-be02-01d659d3a5b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816269353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.816269353
Directory /workspace/47.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/47.pwrmgr_glitch.384006165
Short name T204
Test name
Test status
Simulation time 53402207 ps
CPU time 0.67 seconds
Started Mar 19 03:08:27 PM PDT 24
Finished Mar 19 03:08:29 PM PDT 24
Peak memory 197488 kb
Host smart-8d7e723b-96c5-4d59-ba50-cf15a288e1ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384006165 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.384006165
Directory /workspace/47.pwrmgr_glitch/latest

Test location /workspace/coverage/default/47.pwrmgr_global_esc.3649277437
Short name T321
Test name
Test status
Simulation time 136622207 ps
CPU time 0.61 seconds
Started Mar 19 03:08:36 PM PDT 24
Finished Mar 19 03:08:37 PM PDT 24
Peak memory 197520 kb
Host smart-18d2dd36-b3ed-4933-8fa9-9a54ee3e66a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649277437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.3649277437
Directory /workspace/47.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.1757351878
Short name T635
Test name
Test status
Simulation time 56412950 ps
CPU time 0.69 seconds
Started Mar 19 03:08:19 PM PDT 24
Finished Mar 19 03:08:20 PM PDT 24
Peak memory 200832 kb
Host smart-777a3cfa-468f-443a-8217-3c370cd9dc93
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757351878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.1757351878
Directory /workspace/47.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_lowpower_wakeup_race.4088452706
Short name T349
Test name
Test status
Simulation time 252063949 ps
CPU time 0.83 seconds
Started Mar 19 03:08:22 PM PDT 24
Finished Mar 19 03:08:23 PM PDT 24
Peak memory 197952 kb
Host smart-5f116d62-542b-431f-be65-940ec1c76075
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088452706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_w
akeup_race.4088452706
Directory /workspace/47.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/47.pwrmgr_reset.267419314
Short name T174
Test name
Test status
Simulation time 135746318 ps
CPU time 0.68 seconds
Started Mar 19 03:08:28 PM PDT 24
Finished Mar 19 03:08:30 PM PDT 24
Peak memory 197996 kb
Host smart-f35eea94-791a-404f-8434-f4d180c51896
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267419314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.267419314
Directory /workspace/47.pwrmgr_reset/latest

Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.2047024831
Short name T574
Test name
Test status
Simulation time 91461552 ps
CPU time 1.11 seconds
Started Mar 19 03:08:22 PM PDT 24
Finished Mar 19 03:08:23 PM PDT 24
Peak memory 208940 kb
Host smart-79315196-6998-4073-b59e-10f1f7eac7a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047024831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.2047024831
Directory /workspace/47.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.797989169
Short name T335
Test name
Test status
Simulation time 1240724828 ps
CPU time 2.26 seconds
Started Mar 19 03:08:22 PM PDT 24
Finished Mar 19 03:08:25 PM PDT 24
Peak memory 200496 kb
Host smart-bce1e620-31a2-4877-83e4-7906854ec1cc
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797989169 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.797989169
Directory /workspace/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1930045399
Short name T873
Test name
Test status
Simulation time 902103436 ps
CPU time 3.18 seconds
Started Mar 19 03:08:09 PM PDT 24
Finished Mar 19 03:08:12 PM PDT 24
Peak memory 200600 kb
Host smart-b91eefdb-a240-4e1b-8885-ddfb0b89d6a8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930045399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1930045399
Directory /workspace/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.4273258868
Short name T154
Test name
Test status
Simulation time 74600591 ps
CPU time 0.91 seconds
Started Mar 19 03:08:19 PM PDT 24
Finished Mar 19 03:08:20 PM PDT 24
Peak memory 198624 kb
Host smart-87ef98cd-a97b-487f-a94e-6ae9478b93d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273258868 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4273258868
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/47.pwrmgr_smoke.1388526372
Short name T586
Test name
Test status
Simulation time 45186049 ps
CPU time 0.65 seconds
Started Mar 19 03:08:41 PM PDT 24
Finished Mar 19 03:08:42 PM PDT 24
Peak memory 198716 kb
Host smart-37d91c3e-cd11-4f22-b6b3-3c4f6891b4ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388526372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.1388526372
Directory /workspace/47.pwrmgr_smoke/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup.405355099
Short name T360
Test name
Test status
Simulation time 81640482 ps
CPU time 0.83 seconds
Started Mar 19 03:08:23 PM PDT 24
Finished Mar 19 03:08:24 PM PDT 24
Peak memory 197696 kb
Host smart-a5826b02-d546-47ee-a798-962fe9e095f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405355099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup.405355099
Directory /workspace/47.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/47.pwrmgr_wakeup_reset.223431829
Short name T639
Test name
Test status
Simulation time 353923154 ps
CPU time 1.25 seconds
Started Mar 19 03:08:15 PM PDT 24
Finished Mar 19 03:08:16 PM PDT 24
Peak memory 200600 kb
Host smart-0e874aa9-aad3-4242-b62e-bd9eb3913b5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223431829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.223431829
Directory /workspace/47.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.2833889615
Short name T880
Test name
Test status
Simulation time 21980174 ps
CPU time 0.65 seconds
Started Mar 19 03:08:22 PM PDT 24
Finished Mar 19 03:08:23 PM PDT 24
Peak memory 197940 kb
Host smart-c6886923-704d-455a-9409-a60000fa3d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833889615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.2833889615
Directory /workspace/48.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.1083657459
Short name T466
Test name
Test status
Simulation time 52993655 ps
CPU time 0.8 seconds
Started Mar 19 03:08:33 PM PDT 24
Finished Mar 19 03:08:34 PM PDT 24
Peak memory 198568 kb
Host smart-c535cc2e-31de-47f3-a8e7-d033cb243bce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083657459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.1083657459
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.3730672773
Short name T827
Test name
Test status
Simulation time 30902939 ps
CPU time 0.65 seconds
Started Mar 19 03:08:26 PM PDT 24
Finished Mar 19 03:08:27 PM PDT 24
Peak memory 197432 kb
Host smart-927e3c37-0fac-42fe-a721-a2f215fec5a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730672773 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst
_malfunc.3730672773
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.1077140105
Short name T776
Test name
Test status
Simulation time 639959018 ps
CPU time 1 seconds
Started Mar 19 03:08:35 PM PDT 24
Finished Mar 19 03:08:37 PM PDT 24
Peak memory 197804 kb
Host smart-f483a69f-6e09-46af-af57-b380132208b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077140105 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.1077140105
Directory /workspace/48.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/48.pwrmgr_glitch.1603456389
Short name T464
Test name
Test status
Simulation time 58287867 ps
CPU time 0.6 seconds
Started Mar 19 03:08:43 PM PDT 24
Finished Mar 19 03:08:43 PM PDT 24
Peak memory 197504 kb
Host smart-ee6cb062-6956-4ffe-b5cf-80104672409a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603456389 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.1603456389
Directory /workspace/48.pwrmgr_glitch/latest

Test location /workspace/coverage/default/48.pwrmgr_global_esc.4178309761
Short name T756
Test name
Test status
Simulation time 152673233 ps
CPU time 0.62 seconds
Started Mar 19 03:08:47 PM PDT 24
Finished Mar 19 03:08:48 PM PDT 24
Peak memory 197524 kb
Host smart-6774ba81-e81e-48c7-bb67-e8e326622c18
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178309761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.4178309761
Directory /workspace/48.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.2594384535
Short name T364
Test name
Test status
Simulation time 45976360 ps
CPU time 0.79 seconds
Started Mar 19 03:08:22 PM PDT 24
Finished Mar 19 03:08:24 PM PDT 24
Peak memory 200800 kb
Host smart-8be9e3c2-7519-44dd-8b56-b71eaf50a511
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594384535 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.2594384535
Directory /workspace/48.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_reset.2450288198
Short name T708
Test name
Test status
Simulation time 107211820 ps
CPU time 0.85 seconds
Started Mar 19 03:08:28 PM PDT 24
Finished Mar 19 03:08:30 PM PDT 24
Peak memory 199372 kb
Host smart-29182cb7-570c-417f-9667-0ec603b58f84
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450288198 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.2450288198
Directory /workspace/48.pwrmgr_reset/latest

Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.2250166807
Short name T407
Test name
Test status
Simulation time 106925311 ps
CPU time 1.05 seconds
Started Mar 19 03:08:29 PM PDT 24
Finished Mar 19 03:08:32 PM PDT 24
Peak memory 208880 kb
Host smart-e661845c-0297-4b8f-91ea-7e304d5e95ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250166807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.2250166807
Directory /workspace/48.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.886487737
Short name T534
Test name
Test status
Simulation time 898881749 ps
CPU time 2.27 seconds
Started Mar 19 03:08:23 PM PDT 24
Finished Mar 19 03:08:26 PM PDT 24
Peak memory 200604 kb
Host smart-1972e45a-09e9-4daf-88ce-0c96c41ca3dd
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886487737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.886487737
Directory /workspace/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.997887110
Short name T120
Test name
Test status
Simulation time 1034194809 ps
CPU time 2.1 seconds
Started Mar 19 03:08:25 PM PDT 24
Finished Mar 19 03:08:28 PM PDT 24
Peak memory 200632 kb
Host smart-086e3add-1a95-4d8f-b263-9123e2880074
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997887110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.997887110
Directory /workspace/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.2506268228
Short name T311
Test name
Test status
Simulation time 175361180 ps
CPU time 0.86 seconds
Started Mar 19 03:08:36 PM PDT 24
Finished Mar 19 03:08:37 PM PDT 24
Peak memory 198812 kb
Host smart-e97a1612-d8a1-432e-821d-b9092030840d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506268228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2506268228
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/48.pwrmgr_smoke.1236341318
Short name T158
Test name
Test status
Simulation time 55131457 ps
CPU time 0.62 seconds
Started Mar 19 03:08:23 PM PDT 24
Finished Mar 19 03:08:24 PM PDT 24
Peak memory 198724 kb
Host smart-4055f6c0-1e70-4adc-893a-2dd7fc54cec2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236341318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.1236341318
Directory /workspace/48.pwrmgr_smoke/latest

Test location /workspace/coverage/default/48.pwrmgr_stress_all.569455077
Short name T354
Test name
Test status
Simulation time 1312305953 ps
CPU time 2.92 seconds
Started Mar 19 03:08:38 PM PDT 24
Finished Mar 19 03:08:41 PM PDT 24
Peak memory 200692 kb
Host smart-15dc916e-acd9-48e4-add7-ec42ecfeb411
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569455077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all.569455077
Directory /workspace/48.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/48.pwrmgr_wakeup_reset.1382828060
Short name T559
Test name
Test status
Simulation time 172950105 ps
CPU time 1.13 seconds
Started Mar 19 03:08:14 PM PDT 24
Finished Mar 19 03:08:15 PM PDT 24
Peak memory 199472 kb
Host smart-0a13a5d8-22f5-4561-9600-de4222f2b2eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382828060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.1382828060
Directory /workspace/48.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.178967284
Short name T244
Test name
Test status
Simulation time 36415598 ps
CPU time 0.68 seconds
Started Mar 19 03:08:27 PM PDT 24
Finished Mar 19 03:08:28 PM PDT 24
Peak memory 197948 kb
Host smart-ece828ef-6140-4abb-8d46-d5e034039ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178967284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.178967284
Directory /workspace/49.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.124315168
Short name T697
Test name
Test status
Simulation time 58832680 ps
CPU time 0.8 seconds
Started Mar 19 03:08:33 PM PDT 24
Finished Mar 19 03:08:34 PM PDT 24
Peak memory 198596 kb
Host smart-d851b832-0e7c-4beb-acbe-447106196807
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124315168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_disa
ble_rom_integrity_check.124315168
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.3049873663
Short name T237
Test name
Test status
Simulation time 30692184 ps
CPU time 0.61 seconds
Started Mar 19 03:08:33 PM PDT 24
Finished Mar 19 03:08:34 PM PDT 24
Peak memory 197432 kb
Host smart-42d3646c-16d5-4d60-927d-731f2b8c77ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049873663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst
_malfunc.3049873663
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.1981810159
Short name T395
Test name
Test status
Simulation time 365535829 ps
CPU time 1.06 seconds
Started Mar 19 03:08:28 PM PDT 24
Finished Mar 19 03:08:30 PM PDT 24
Peak memory 197520 kb
Host smart-414646b0-5836-4b5d-b672-1b3d22ff4c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981810159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.1981810159
Directory /workspace/49.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/49.pwrmgr_glitch.2423463389
Short name T473
Test name
Test status
Simulation time 65470062 ps
CPU time 0.65 seconds
Started Mar 19 03:08:26 PM PDT 24
Finished Mar 19 03:08:27 PM PDT 24
Peak memory 196856 kb
Host smart-e569101f-3b9a-41d2-8e6f-62b2dbe25027
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423463389 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.2423463389
Directory /workspace/49.pwrmgr_glitch/latest

Test location /workspace/coverage/default/49.pwrmgr_global_esc.3884631188
Short name T573
Test name
Test status
Simulation time 25614995 ps
CPU time 0.62 seconds
Started Mar 19 03:08:32 PM PDT 24
Finished Mar 19 03:08:33 PM PDT 24
Peak memory 197524 kb
Host smart-440a139f-9124-4994-9303-311a0a928717
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884631188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.3884631188
Directory /workspace/49.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.1330156147
Short name T36
Test name
Test status
Simulation time 57936880 ps
CPU time 0.65 seconds
Started Mar 19 03:08:37 PM PDT 24
Finished Mar 19 03:08:38 PM PDT 24
Peak memory 200804 kb
Host smart-997a9cad-3deb-4c13-9f1f-45d57977c468
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330156147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.1330156147
Directory /workspace/49.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_reset.1833250895
Short name T848
Test name
Test status
Simulation time 99624447 ps
CPU time 0.81 seconds
Started Mar 19 03:08:24 PM PDT 24
Finished Mar 19 03:08:25 PM PDT 24
Peak memory 199376 kb
Host smart-3a2c39c6-2aec-4c5a-9ad3-9fee0b561849
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833250895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.1833250895
Directory /workspace/49.pwrmgr_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.288657319
Short name T802
Test name
Test status
Simulation time 122284373 ps
CPU time 0.89 seconds
Started Mar 19 03:08:28 PM PDT 24
Finished Mar 19 03:08:31 PM PDT 24
Peak memory 208896 kb
Host smart-04c3ef43-4dc5-452a-ae5a-a082cac1460e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288657319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.288657319
Directory /workspace/49.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1067523897
Short name T753
Test name
Test status
Simulation time 739842346 ps
CPU time 3 seconds
Started Mar 19 03:08:30 PM PDT 24
Finished Mar 19 03:08:34 PM PDT 24
Peak memory 200656 kb
Host smart-a944d208-a92a-44df-b489-ab4f77d3db3c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067523897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1067523897
Directory /workspace/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3566987349
Short name T121
Test name
Test status
Simulation time 730340424 ps
CPU time 2.97 seconds
Started Mar 19 03:08:24 PM PDT 24
Finished Mar 19 03:08:27 PM PDT 24
Peak memory 200588 kb
Host smart-b9e5d506-f7c5-474a-af80-74f8047ae744
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566987349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3566987349
Directory /workspace/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1970223243
Short name T528
Test name
Test status
Simulation time 133713601 ps
CPU time 0.86 seconds
Started Mar 19 03:08:31 PM PDT 24
Finished Mar 19 03:08:33 PM PDT 24
Peak memory 198968 kb
Host smart-276266a7-c0cd-4510-b3ad-ef0406330746
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970223243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1970223243
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/49.pwrmgr_smoke.2391262780
Short name T257
Test name
Test status
Simulation time 26341684 ps
CPU time 0.68 seconds
Started Mar 19 03:08:29 PM PDT 24
Finished Mar 19 03:08:32 PM PDT 24
Peak memory 198756 kb
Host smart-e39d82cb-a796-4b22-a5e0-df96de419cfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391262780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.2391262780
Directory /workspace/49.pwrmgr_smoke/latest

Test location /workspace/coverage/default/49.pwrmgr_stress_all.4167767344
Short name T735
Test name
Test status
Simulation time 4853784411 ps
CPU time 4.55 seconds
Started Mar 19 03:08:35 PM PDT 24
Finished Mar 19 03:08:40 PM PDT 24
Peak memory 200772 kb
Host smart-2508438c-cbd7-4c0c-8622-2c4414bbf036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167767344 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all.4167767344
Directory /workspace/49.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/49.pwrmgr_stress_all_with_rand_reset.626146432
Short name T54
Test name
Test status
Simulation time 21120921762 ps
CPU time 23.15 seconds
Started Mar 19 03:08:27 PM PDT 24
Finished Mar 19 03:08:51 PM PDT 24
Peak memory 200792 kb
Host smart-467daed8-6959-42cb-a897-9a7296da9527
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626146432 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all_with_rand_reset.626146432
Directory /workspace/49.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup.50537118
Short name T218
Test name
Test status
Simulation time 329080621 ps
CPU time 0.83 seconds
Started Mar 19 03:08:36 PM PDT 24
Finished Mar 19 03:08:37 PM PDT 24
Peak memory 198940 kb
Host smart-2fc62484-d615-4360-9986-0de83c5a650c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50537118 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.50537118
Directory /workspace/49.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/49.pwrmgr_wakeup_reset.501799470
Short name T167
Test name
Test status
Simulation time 367776227 ps
CPU time 1.06 seconds
Started Mar 19 03:08:33 PM PDT 24
Finished Mar 19 03:08:35 PM PDT 24
Peak memory 200512 kb
Host smart-a2aafada-4edf-4c3a-b329-c4b7b31ca1af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501799470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.501799470
Directory /workspace/49.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.1449227941
Short name T588
Test name
Test status
Simulation time 75663369 ps
CPU time 0.69 seconds
Started Mar 19 03:06:38 PM PDT 24
Finished Mar 19 03:06:39 PM PDT 24
Peak memory 198148 kb
Host smart-9e78d92e-dc0d-4bb0-aca8-4b6292661451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449227941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.1449227941
Directory /workspace/5.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.2958293716
Short name T494
Test name
Test status
Simulation time 52316665 ps
CPU time 0.8 seconds
Started Mar 19 03:06:31 PM PDT 24
Finished Mar 19 03:06:32 PM PDT 24
Peak memory 198608 kb
Host smart-5da91ff3-1f8d-41f4-ab93-1b05c2bf5d14
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958293716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.2958293716
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.2219237491
Short name T804
Test name
Test status
Simulation time 34307355 ps
CPU time 0.59 seconds
Started Mar 19 03:06:23 PM PDT 24
Finished Mar 19 03:06:24 PM PDT 24
Peak memory 196732 kb
Host smart-ecb2f1f3-681d-4966-8cf8-c733c0e97bf7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219237491 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_
malfunc.2219237491
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.625430437
Short name T229
Test name
Test status
Simulation time 603767044 ps
CPU time 1.01 seconds
Started Mar 19 03:06:39 PM PDT 24
Finished Mar 19 03:06:40 PM PDT 24
Peak memory 197828 kb
Host smart-09cec95c-dfd4-4b9e-96c4-415bafcb3bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625430437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.625430437
Directory /workspace/5.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/5.pwrmgr_glitch.3898275172
Short name T17
Test name
Test status
Simulation time 47131644 ps
CPU time 0.66 seconds
Started Mar 19 03:06:33 PM PDT 24
Finished Mar 19 03:06:34 PM PDT 24
Peak memory 197544 kb
Host smart-5d2785e2-67c2-4d1e-a02e-ddaf48ea26f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898275172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.3898275172
Directory /workspace/5.pwrmgr_glitch/latest

Test location /workspace/coverage/default/5.pwrmgr_global_esc.2342455690
Short name T396
Test name
Test status
Simulation time 63104495 ps
CPU time 0.6 seconds
Started Mar 19 03:06:33 PM PDT 24
Finished Mar 19 03:06:34 PM PDT 24
Peak memory 197504 kb
Host smart-1fc3d637-6e9a-4772-9c84-8cc0dec24c39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342455690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.2342455690
Directory /workspace/5.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.483663507
Short name T109
Test name
Test status
Simulation time 45847593 ps
CPU time 0.72 seconds
Started Mar 19 03:06:30 PM PDT 24
Finished Mar 19 03:06:32 PM PDT 24
Peak memory 200812 kb
Host smart-03aee9e2-2a29-46c6-a4a8-14cdfacedaeb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483663507 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invalid
.483663507
Directory /workspace/5.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_lowpower_wakeup_race.3893525939
Short name T787
Test name
Test status
Simulation time 54014097 ps
CPU time 0.82 seconds
Started Mar 19 03:06:41 PM PDT 24
Finished Mar 19 03:06:42 PM PDT 24
Peak memory 198544 kb
Host smart-2a5ea46e-e3b9-43a1-bba7-cbc3c9b16fc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893525939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wa
keup_race.3893525939
Directory /workspace/5.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/5.pwrmgr_reset.646690131
Short name T640
Test name
Test status
Simulation time 163864725 ps
CPU time 0.82 seconds
Started Mar 19 03:06:21 PM PDT 24
Finished Mar 19 03:06:22 PM PDT 24
Peak memory 199216 kb
Host smart-188ad127-25e4-4c75-b601-794d74e84a63
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646690131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.646690131
Directory /workspace/5.pwrmgr_reset/latest

Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.2460255656
Short name T299
Test name
Test status
Simulation time 119153804 ps
CPU time 0.93 seconds
Started Mar 19 03:06:40 PM PDT 24
Finished Mar 19 03:06:41 PM PDT 24
Peak memory 208860 kb
Host smart-38d539c1-6213-43e5-91ef-27af5217c31a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460255656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.2460255656
Directory /workspace/5.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.729393460
Short name T821
Test name
Test status
Simulation time 491272056 ps
CPU time 1.14 seconds
Started Mar 19 03:06:45 PM PDT 24
Finished Mar 19 03:06:46 PM PDT 24
Peak memory 200268 kb
Host smart-35391e7f-21fb-471d-ae1f-e86881910bef
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729393460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm
_ctrl_config_regwen.729393460
Directory /workspace/5.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1936239974
Short name T124
Test name
Test status
Simulation time 1820618351 ps
CPU time 2.22 seconds
Started Mar 19 03:06:40 PM PDT 24
Finished Mar 19 03:06:42 PM PDT 24
Peak memory 200528 kb
Host smart-85dbb570-ff53-4acd-83d4-840c7a07947f
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936239974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1936239974
Directory /workspace/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2432594465
Short name T326
Test name
Test status
Simulation time 1692434122 ps
CPU time 2 seconds
Started Mar 19 03:06:31 PM PDT 24
Finished Mar 19 03:06:33 PM PDT 24
Peak memory 200440 kb
Host smart-0210bc2f-fd83-4564-a9c8-24dd09d572fd
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432594465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2432594465
Directory /workspace/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3370022449
Short name T748
Test name
Test status
Simulation time 109789105 ps
CPU time 0.91 seconds
Started Mar 19 03:06:12 PM PDT 24
Finished Mar 19 03:06:13 PM PDT 24
Peak memory 198656 kb
Host smart-de2991a9-4586-4c3c-8627-7853511b44b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370022449 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3370022449
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/5.pwrmgr_smoke.2879610628
Short name T546
Test name
Test status
Simulation time 34373167 ps
CPU time 0.65 seconds
Started Mar 19 03:06:30 PM PDT 24
Finished Mar 19 03:06:31 PM PDT 24
Peak memory 197932 kb
Host smart-5d2890c4-2fee-4b67-aadf-b2d75090e2ec
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879610628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.2879610628
Directory /workspace/5.pwrmgr_smoke/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup.931252047
Short name T75
Test name
Test status
Simulation time 140356446 ps
CPU time 0.73 seconds
Started Mar 19 03:06:45 PM PDT 24
Finished Mar 19 03:06:46 PM PDT 24
Peak memory 197664 kb
Host smart-26754fa5-8d46-4278-b0ed-2c64ffb44961
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931252047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.931252047
Directory /workspace/5.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/5.pwrmgr_wakeup_reset.947571504
Short name T221
Test name
Test status
Simulation time 562092163 ps
CPU time 1.11 seconds
Started Mar 19 03:06:31 PM PDT 24
Finished Mar 19 03:06:32 PM PDT 24
Peak memory 200572 kb
Host smart-9aadbc1c-7981-4156-b68c-02128b08af76
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947571504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.947571504
Directory /workspace/5.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.948613510
Short name T554
Test name
Test status
Simulation time 68186878 ps
CPU time 0.84 seconds
Started Mar 19 03:06:38 PM PDT 24
Finished Mar 19 03:06:39 PM PDT 24
Peak memory 199300 kb
Host smart-e757ac86-846c-420e-8cf4-e335f878990a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948613510 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.948613510
Directory /workspace/6.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.38322072
Short name T331
Test name
Test status
Simulation time 34037152 ps
CPU time 0.62 seconds
Started Mar 19 03:06:38 PM PDT 24
Finished Mar 19 03:06:39 PM PDT 24
Peak memory 197424 kb
Host smart-0aa69c25-88d2-4191-99a5-635d648365fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38322072 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_mal
func_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_ma
lfunc.38322072
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.4094698750
Short name T13
Test name
Test status
Simulation time 631205894 ps
CPU time 1.03 seconds
Started Mar 19 03:06:22 PM PDT 24
Finished Mar 19 03:06:23 PM PDT 24
Peak memory 197532 kb
Host smart-a4a7422f-59f8-4116-94d5-b318d3262ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094698750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.4094698750
Directory /workspace/6.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/6.pwrmgr_glitch.388696770
Short name T487
Test name
Test status
Simulation time 52401974 ps
CPU time 0.61 seconds
Started Mar 19 03:06:24 PM PDT 24
Finished Mar 19 03:06:25 PM PDT 24
Peak memory 197504 kb
Host smart-823f7f59-e65f-45f6-9a8e-8c9b403a613e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388696770 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.388696770
Directory /workspace/6.pwrmgr_glitch/latest

Test location /workspace/coverage/default/6.pwrmgr_global_esc.1338045980
Short name T171
Test name
Test status
Simulation time 88444647 ps
CPU time 0.6 seconds
Started Mar 19 03:06:45 PM PDT 24
Finished Mar 19 03:06:46 PM PDT 24
Peak memory 197824 kb
Host smart-070a1856-10ea-4e6e-9243-1cac51fd06c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338045980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.1338045980
Directory /workspace/6.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.768539559
Short name T212
Test name
Test status
Simulation time 66657013 ps
CPU time 0.68 seconds
Started Mar 19 03:06:26 PM PDT 24
Finished Mar 19 03:06:27 PM PDT 24
Peak memory 200776 kb
Host smart-e697019c-e182-4a4b-ace8-5d2ee5bcfd29
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768539559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invalid
.768539559
Directory /workspace/6.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_lowpower_wakeup_race.3278418974
Short name T193
Test name
Test status
Simulation time 359219091 ps
CPU time 0.86 seconds
Started Mar 19 03:06:20 PM PDT 24
Finished Mar 19 03:06:21 PM PDT 24
Peak memory 199056 kb
Host smart-7c0f5cf5-d4ed-4737-82ab-bb6df470b29c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278418974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wa
keup_race.3278418974
Directory /workspace/6.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/6.pwrmgr_reset.613749578
Short name T752
Test name
Test status
Simulation time 45763780 ps
CPU time 0.8 seconds
Started Mar 19 03:06:40 PM PDT 24
Finished Mar 19 03:06:41 PM PDT 24
Peak memory 198044 kb
Host smart-1138fc2e-86ec-45ba-a8cb-4aa88b25326b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613749578 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.613749578
Directory /workspace/6.pwrmgr_reset/latest

Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.2036013107
Short name T630
Test name
Test status
Simulation time 166132442 ps
CPU time 0.84 seconds
Started Mar 19 03:06:30 PM PDT 24
Finished Mar 19 03:06:31 PM PDT 24
Peak memory 200712 kb
Host smart-cf9eafa0-842d-4356-8202-75871ef537e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036013107 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.2036013107
Directory /workspace/6.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.297078652
Short name T767
Test name
Test status
Simulation time 149274457 ps
CPU time 0.87 seconds
Started Mar 19 03:06:32 PM PDT 24
Finished Mar 19 03:06:33 PM PDT 24
Peak memory 199384 kb
Host smart-0ad2f10d-23b1-4e4c-acbe-b6e6937dda0a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297078652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm
_ctrl_config_regwen.297078652
Directory /workspace/6.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.453706265
Short name T451
Test name
Test status
Simulation time 1924920905 ps
CPU time 2.12 seconds
Started Mar 19 03:06:30 PM PDT 24
Finished Mar 19 03:06:33 PM PDT 24
Peak memory 200568 kb
Host smart-a96706c3-26c5-41d1-b5ef-053baac4c9f2
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453706265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.453706265
Directory /workspace/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3080382849
Short name T295
Test name
Test status
Simulation time 800152329 ps
CPU time 2.95 seconds
Started Mar 19 03:06:32 PM PDT 24
Finished Mar 19 03:06:35 PM PDT 24
Peak memory 200644 kb
Host smart-5164e298-2446-4f07-8c1b-cd975aaf1805
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080382849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3080382849
Directory /workspace/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.3768491135
Short name T153
Test name
Test status
Simulation time 52588746 ps
CPU time 0.9 seconds
Started Mar 19 03:06:43 PM PDT 24
Finished Mar 19 03:06:44 PM PDT 24
Peak memory 199044 kb
Host smart-67de0817-fcb9-42c9-aaed-9728eb785fad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768491135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3768491135
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/6.pwrmgr_smoke.2353942937
Short name T513
Test name
Test status
Simulation time 31498219 ps
CPU time 0.65 seconds
Started Mar 19 03:06:32 PM PDT 24
Finished Mar 19 03:06:32 PM PDT 24
Peak memory 198732 kb
Host smart-31530211-2b5e-41db-9e93-886636f4dc57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353942937 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.2353942937
Directory /workspace/6.pwrmgr_smoke/latest

Test location /workspace/coverage/default/6.pwrmgr_stress_all.3329157844
Short name T625
Test name
Test status
Simulation time 928709902 ps
CPU time 3.79 seconds
Started Mar 19 03:06:25 PM PDT 24
Finished Mar 19 03:06:29 PM PDT 24
Peak memory 200672 kb
Host smart-3f399573-a6ca-4989-921f-f4ca06a2b2da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329157844 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.3329157844
Directory /workspace/6.pwrmgr_stress_all/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup.2604335362
Short name T862
Test name
Test status
Simulation time 314550100 ps
CPU time 0.9 seconds
Started Mar 19 03:06:42 PM PDT 24
Finished Mar 19 03:06:43 PM PDT 24
Peak memory 199136 kb
Host smart-e41f818b-a868-429a-9278-0ee78da298a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604335362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.2604335362
Directory /workspace/6.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/6.pwrmgr_wakeup_reset.473409028
Short name T847
Test name
Test status
Simulation time 94929997 ps
CPU time 0.8 seconds
Started Mar 19 03:06:32 PM PDT 24
Finished Mar 19 03:06:33 PM PDT 24
Peak memory 198744 kb
Host smart-7743ef25-d337-4f49-8a26-4a358d76118a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473409028 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.473409028
Directory /workspace/6.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.4284747871
Short name T657
Test name
Test status
Simulation time 32122595 ps
CPU time 0.66 seconds
Started Mar 19 03:06:45 PM PDT 24
Finished Mar 19 03:06:46 PM PDT 24
Peak memory 197760 kb
Host smart-24053524-10a1-4491-9e17-257ce8061575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284747871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.4284747871
Directory /workspace/7.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.2121873768
Short name T439
Test name
Test status
Simulation time 55992150 ps
CPU time 0.85 seconds
Started Mar 19 03:06:39 PM PDT 24
Finished Mar 19 03:06:40 PM PDT 24
Peak memory 198556 kb
Host smart-aae50dfe-9d51-44db-b0d4-782830ae4dc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121873768 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disa
ble_rom_integrity_check.2121873768
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.2303047865
Short name T754
Test name
Test status
Simulation time 40599977 ps
CPU time 0.58 seconds
Started Mar 19 03:06:34 PM PDT 24
Finished Mar 19 03:06:35 PM PDT 24
Peak memory 197440 kb
Host smart-e243dc95-8b63-46e5-9421-fe22f357c16c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303047865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.2303047865
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.1406842258
Short name T560
Test name
Test status
Simulation time 162290282 ps
CPU time 0.98 seconds
Started Mar 19 03:06:39 PM PDT 24
Finished Mar 19 03:06:40 PM PDT 24
Peak memory 197840 kb
Host smart-32f14241-ff76-4b55-802a-8c10f01bf3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406842258 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.1406842258
Directory /workspace/7.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/7.pwrmgr_glitch.1870474341
Short name T456
Test name
Test status
Simulation time 43095479 ps
CPU time 0.7 seconds
Started Mar 19 03:06:43 PM PDT 24
Finished Mar 19 03:06:44 PM PDT 24
Peak memory 196816 kb
Host smart-1a77a477-6797-401a-bae6-d9c24bd7c533
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870474341 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.1870474341
Directory /workspace/7.pwrmgr_glitch/latest

Test location /workspace/coverage/default/7.pwrmgr_global_esc.4121021329
Short name T443
Test name
Test status
Simulation time 215653553 ps
CPU time 0.6 seconds
Started Mar 19 03:06:39 PM PDT 24
Finished Mar 19 03:06:40 PM PDT 24
Peak memory 197528 kb
Host smart-52dd46ba-647f-4383-9a6b-33c871973b9c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121021329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.4121021329
Directory /workspace/7.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.1089952227
Short name T441
Test name
Test status
Simulation time 52275411 ps
CPU time 0.68 seconds
Started Mar 19 03:06:38 PM PDT 24
Finished Mar 19 03:06:39 PM PDT 24
Peak memory 200792 kb
Host smart-9acb3040-369d-4d51-9852-1b314e9bed97
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089952227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.1089952227
Directory /workspace/7.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_lowpower_wakeup_race.1182490435
Short name T667
Test name
Test status
Simulation time 154723488 ps
CPU time 0.77 seconds
Started Mar 19 03:06:30 PM PDT 24
Finished Mar 19 03:06:32 PM PDT 24
Peak memory 197764 kb
Host smart-7a2f3c91-51e2-4ba7-a67a-03c94c1d1eb0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182490435 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wa
keup_race.1182490435
Directory /workspace/7.pwrmgr_lowpower_wakeup_race/latest

Test location /workspace/coverage/default/7.pwrmgr_reset.931222463
Short name T797
Test name
Test status
Simulation time 97559500 ps
CPU time 0.76 seconds
Started Mar 19 03:06:12 PM PDT 24
Finished Mar 19 03:06:13 PM PDT 24
Peak memory 198208 kb
Host smart-37857ece-9bd5-4e70-9914-71d29b32d6f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931222463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.931222463
Directory /workspace/7.pwrmgr_reset/latest

Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.163313638
Short name T27
Test name
Test status
Simulation time 272241610 ps
CPU time 0.85 seconds
Started Mar 19 03:06:41 PM PDT 24
Finished Mar 19 03:06:42 PM PDT 24
Peak memory 208964 kb
Host smart-03c4cde5-0b08-47c9-a53a-de2a512c74cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163313638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.163313638
Directory /workspace/7.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2153774637
Short name T225
Test name
Test status
Simulation time 733814672 ps
CPU time 2.67 seconds
Started Mar 19 03:06:40 PM PDT 24
Finished Mar 19 03:06:43 PM PDT 24
Peak memory 200564 kb
Host smart-01dd9957-9d22-496f-91f9-db2a36cae541
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153774637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2153774637
Directory /workspace/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.221953723
Short name T858
Test name
Test status
Simulation time 981048378 ps
CPU time 2 seconds
Started Mar 19 03:06:50 PM PDT 24
Finished Mar 19 03:06:52 PM PDT 24
Peak memory 200572 kb
Host smart-da94a05a-65fd-4fd2-b796-d2bf3a08f22d
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221953723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.221953723
Directory /workspace/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.420549232
Short name T111
Test name
Test status
Simulation time 76027793 ps
CPU time 0.99 seconds
Started Mar 19 03:06:20 PM PDT 24
Finished Mar 19 03:06:22 PM PDT 24
Peak memory 198764 kb
Host smart-eda723f7-8fb9-475c-b208-c10e4c2e6f1b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420549232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.420549232
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/7.pwrmgr_smoke.2536604337
Short name T516
Test name
Test status
Simulation time 31406950 ps
CPU time 0.65 seconds
Started Mar 19 03:06:17 PM PDT 24
Finished Mar 19 03:06:18 PM PDT 24
Peak memory 198692 kb
Host smart-64f400be-3d5e-4a07-bbe4-e4dd7c7e6e87
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536604337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.2536604337
Directory /workspace/7.pwrmgr_smoke/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup.2813970599
Short name T361
Test name
Test status
Simulation time 40419771 ps
CPU time 0.69 seconds
Started Mar 19 03:06:28 PM PDT 24
Finished Mar 19 03:06:29 PM PDT 24
Peak memory 197676 kb
Host smart-50dd2294-300d-496f-bd2a-03a8df15b7d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813970599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.2813970599
Directory /workspace/7.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/7.pwrmgr_wakeup_reset.2642721213
Short name T478
Test name
Test status
Simulation time 300907067 ps
CPU time 1.36 seconds
Started Mar 19 03:06:35 PM PDT 24
Finished Mar 19 03:06:37 PM PDT 24
Peak memory 199516 kb
Host smart-56a3efda-bc40-4d73-a380-e0bdfc644bb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642721213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.2642721213
Directory /workspace/7.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.132645011
Short name T187
Test name
Test status
Simulation time 26668578 ps
CPU time 0.74 seconds
Started Mar 19 03:06:50 PM PDT 24
Finished Mar 19 03:06:51 PM PDT 24
Peak memory 198020 kb
Host smart-bebbf2d9-8838-4c81-a00a-957e9bcc26b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132645011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.132645011
Directory /workspace/8.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.2004799912
Short name T770
Test name
Test status
Simulation time 74474271 ps
CPU time 0.69 seconds
Started Mar 19 03:06:38 PM PDT 24
Finished Mar 19 03:06:39 PM PDT 24
Peak memory 198524 kb
Host smart-3a070372-21c2-49c0-8eb9-94d93a80236d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004799912 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disa
ble_rom_integrity_check.2004799912
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.2155327852
Short name T683
Test name
Test status
Simulation time 50194310 ps
CPU time 0.6 seconds
Started Mar 19 03:06:37 PM PDT 24
Finished Mar 19 03:06:38 PM PDT 24
Peak memory 197480 kb
Host smart-b93ff24f-c4cc-4425-9b70-41d513e8e16c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155327852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_
malfunc.2155327852
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.3765314366
Short name T731
Test name
Test status
Simulation time 159393989 ps
CPU time 0.98 seconds
Started Mar 19 03:06:43 PM PDT 24
Finished Mar 19 03:06:44 PM PDT 24
Peak memory 197608 kb
Host smart-7a3cc3ad-889c-4d49-9df8-781dacf68036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765314366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.3765314366
Directory /workspace/8.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/8.pwrmgr_glitch.3826394571
Short name T590
Test name
Test status
Simulation time 52486240 ps
CPU time 0.67 seconds
Started Mar 19 03:06:39 PM PDT 24
Finished Mar 19 03:06:40 PM PDT 24
Peak memory 196744 kb
Host smart-4d599c88-8930-4652-9965-8d8f987540d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826394571 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.3826394571
Directory /workspace/8.pwrmgr_glitch/latest

Test location /workspace/coverage/default/8.pwrmgr_global_esc.2819975287
Short name T195
Test name
Test status
Simulation time 42123349 ps
CPU time 0.68 seconds
Started Mar 19 03:06:24 PM PDT 24
Finished Mar 19 03:06:25 PM PDT 24
Peak memory 197532 kb
Host smart-c661df4b-055f-4893-ab89-7276453fa94d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819975287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.2819975287
Directory /workspace/8.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.556461340
Short name T831
Test name
Test status
Simulation time 42079247 ps
CPU time 0.68 seconds
Started Mar 19 03:06:49 PM PDT 24
Finished Mar 19 03:06:50 PM PDT 24
Peak memory 200804 kb
Host smart-1372bc65-d492-4a52-8348-e6cd3bf9e7ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556461340 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invalid
.556461340
Directory /workspace/8.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_reset.1185678537
Short name T825
Test name
Test status
Simulation time 68747372 ps
CPU time 0.98 seconds
Started Mar 19 03:06:47 PM PDT 24
Finished Mar 19 03:06:49 PM PDT 24
Peak memory 199196 kb
Host smart-82c05223-fc1e-4a66-a40e-fedafe9538d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185678537 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.1185678537
Directory /workspace/8.pwrmgr_reset/latest

Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.2109610593
Short name T253
Test name
Test status
Simulation time 123902129 ps
CPU time 0.86 seconds
Started Mar 19 03:06:45 PM PDT 24
Finished Mar 19 03:06:46 PM PDT 24
Peak memory 208952 kb
Host smart-452514bb-629a-4d10-a571-008c9ce521ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109610593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.2109610593
Directory /workspace/8.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2662905582
Short name T480
Test name
Test status
Simulation time 947100585 ps
CPU time 2.62 seconds
Started Mar 19 03:06:46 PM PDT 24
Finished Mar 19 03:06:50 PM PDT 24
Peak memory 200596 kb
Host smart-97c89f50-d322-4f59-9dc6-6eadcbe1ec1e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662905582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2662905582
Directory /workspace/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3129705020
Short name T341
Test name
Test status
Simulation time 1367201346 ps
CPU time 1.97 seconds
Started Mar 19 03:06:48 PM PDT 24
Finished Mar 19 03:06:50 PM PDT 24
Peak memory 200588 kb
Host smart-3117cd46-1115-463b-abe6-af89b9e62a06
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129705020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3129705020
Directory /workspace/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.2700683451
Short name T327
Test name
Test status
Simulation time 146952682 ps
CPU time 0.88 seconds
Started Mar 19 03:06:46 PM PDT 24
Finished Mar 19 03:06:48 PM PDT 24
Peak memory 198660 kb
Host smart-c9f67839-9ba4-4667-84aa-19e23229414c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700683451 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2700683451
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/8.pwrmgr_smoke.1271360094
Short name T786
Test name
Test status
Simulation time 36111312 ps
CPU time 0.65 seconds
Started Mar 19 03:06:46 PM PDT 24
Finished Mar 19 03:06:48 PM PDT 24
Peak memory 197864 kb
Host smart-499f42ff-04d0-4082-96e1-d998251a38c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271360094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.1271360094
Directory /workspace/8.pwrmgr_smoke/latest

Test location /workspace/coverage/default/8.pwrmgr_wakeup_reset.2340289949
Short name T165
Test name
Test status
Simulation time 257520416 ps
CPU time 0.87 seconds
Started Mar 19 03:06:31 PM PDT 24
Finished Mar 19 03:06:32 PM PDT 24
Peak memory 199280 kb
Host smart-eef90462-9c99-4b54-ad5f-3dd6e8d75d4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340289949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.2340289949
Directory /workspace/8.pwrmgr_wakeup_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.3293568819
Short name T545
Test name
Test status
Simulation time 44981750 ps
CPU time 0.72 seconds
Started Mar 19 03:06:49 PM PDT 24
Finished Mar 19 03:06:51 PM PDT 24
Peak memory 198052 kb
Host smart-35c8158a-993c-4386-a4b6-bd972289595c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293568819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.3293568819
Directory /workspace/9.pwrmgr_aborted_low_power/latest

Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.3404779321
Short name T811
Test name
Test status
Simulation time 77505705 ps
CPU time 0.71 seconds
Started Mar 19 03:06:37 PM PDT 24
Finished Mar 19 03:06:37 PM PDT 24
Peak memory 197892 kb
Host smart-9ea96b07-c420-4de8-bc7a-990a2b97b944
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404779321 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disa
ble_rom_integrity_check.3404779321
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.1451936148
Short name T314
Test name
Test status
Simulation time 30352568 ps
CPU time 0.63 seconds
Started Mar 19 03:06:38 PM PDT 24
Finished Mar 19 03:06:39 PM PDT 24
Peak memory 197436 kb
Host smart-4d19bfd2-3d70-4562-9fcd-dca5ba20a77b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451936148 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.1451936148
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.1217710304
Short name T263
Test name
Test status
Simulation time 1512828341 ps
CPU time 0.96 seconds
Started Mar 19 03:06:38 PM PDT 24
Finished Mar 19 03:06:39 PM PDT 24
Peak memory 197556 kb
Host smart-696f3aa8-bb44-40ef-b092-34d3f533b5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217710304 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.1217710304
Directory /workspace/9.pwrmgr_escalation_timeout/latest

Test location /workspace/coverage/default/9.pwrmgr_glitch.283881043
Short name T433
Test name
Test status
Simulation time 23253825 ps
CPU time 0.62 seconds
Started Mar 19 03:06:43 PM PDT 24
Finished Mar 19 03:06:44 PM PDT 24
Peak memory 197376 kb
Host smart-2cf6cc16-10e1-4723-b56c-9ae14391a416
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283881043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.283881043
Directory /workspace/9.pwrmgr_glitch/latest

Test location /workspace/coverage/default/9.pwrmgr_global_esc.1582910999
Short name T381
Test name
Test status
Simulation time 24053745 ps
CPU time 0.61 seconds
Started Mar 19 03:06:47 PM PDT 24
Finished Mar 19 03:06:48 PM PDT 24
Peak memory 197532 kb
Host smart-934bcade-e025-4b58-a63b-de0c5c63958d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582910999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.1582910999
Directory /workspace/9.pwrmgr_global_esc/latest

Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.2951521590
Short name T142
Test name
Test status
Simulation time 42846240 ps
CPU time 0.78 seconds
Started Mar 19 03:06:48 PM PDT 24
Finished Mar 19 03:06:50 PM PDT 24
Peak memory 200780 kb
Host smart-4e505ddf-48f8-41b4-93b6-e49766e9771a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951521590 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.2951521590
Directory /workspace/9.pwrmgr_lowpower_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_reset.201993384
Short name T765
Test name
Test status
Simulation time 60055982 ps
CPU time 0.92 seconds
Started Mar 19 03:06:50 PM PDT 24
Finished Mar 19 03:06:51 PM PDT 24
Peak memory 199088 kb
Host smart-34828d2a-c830-47b1-8e7f-ea755331010f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201993384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.201993384
Directory /workspace/9.pwrmgr_reset/latest

Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.1845126696
Short name T518
Test name
Test status
Simulation time 99178491 ps
CPU time 0.93 seconds
Started Mar 19 03:06:48 PM PDT 24
Finished Mar 19 03:06:50 PM PDT 24
Peak memory 200756 kb
Host smart-71c9ce83-2de1-4f27-8d22-10d1d4aae439
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845126696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.1845126696
Directory /workspace/9.pwrmgr_reset_invalid/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3461294297
Short name T812
Test name
Test status
Simulation time 942942421 ps
CPU time 2.63 seconds
Started Mar 19 03:06:47 PM PDT 24
Finished Mar 19 03:06:50 PM PDT 24
Peak memory 200608 kb
Host smart-f408570a-584a-42e3-a0b2-21849ab7aba9
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461294297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3461294297
Directory /workspace/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.364665284
Short name T248
Test name
Test status
Simulation time 1015251742 ps
CPU time 2.51 seconds
Started Mar 19 03:06:34 PM PDT 24
Finished Mar 19 03:06:36 PM PDT 24
Peak memory 200680 kb
Host smart-e458a0c9-fbdc-4eaf-bd5e-3274ec15eb58
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364665284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.364665284
Directory /workspace/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1819729188
Short name T442
Test name
Test status
Simulation time 138647864 ps
CPU time 0.83 seconds
Started Mar 19 03:06:39 PM PDT 24
Finished Mar 19 03:06:40 PM PDT 24
Peak memory 198528 kb
Host smart-f42fc2dc-ffb3-4f51-9018-b84b2e4690b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819729188 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1819729188
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspace/coverage/default/9.pwrmgr_smoke.2076309637
Short name T567
Test name
Test status
Simulation time 28637313 ps
CPU time 0.67 seconds
Started Mar 19 03:06:42 PM PDT 24
Finished Mar 19 03:06:44 PM PDT 24
Peak memory 197908 kb
Host smart-e7f5327c-1a06-41f3-bafc-abf6f93c8ff3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076309637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.2076309637
Directory /workspace/9.pwrmgr_smoke/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup.2278105559
Short name T865
Test name
Test status
Simulation time 269223795 ps
CPU time 0.77 seconds
Started Mar 19 03:06:37 PM PDT 24
Finished Mar 19 03:06:38 PM PDT 24
Peak memory 197696 kb
Host smart-77a83c62-02d6-4286-876b-8dfaa1cf756c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278105559 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.2278105559
Directory /workspace/9.pwrmgr_wakeup/latest

Test location /workspace/coverage/default/9.pwrmgr_wakeup_reset.362254622
Short name T408
Test name
Test status
Simulation time 58905575 ps
CPU time 0.74 seconds
Started Mar 19 03:06:38 PM PDT 24
Finished Mar 19 03:06:39 PM PDT 24
Peak memory 198756 kb
Host smart-f91ea6b3-bb24-41bd-9704-513a4ba1b0ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362254622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.362254622
Directory /workspace/9.pwrmgr_wakeup_reset/latest
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