Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30830

1

T3

10

T6

8

T7

1

auto[1]

29251

1

T3

6

T6

13

T7

5

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30911

1

T3

12

T6

13

T7

6

auto[1]

29170

1

T3

4

T6

8

T28

5

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29197

1

T3

4

T6

14

T7

5

auto[1]

30884

1

T3

12

T6

7

T7

1

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34182

1

T3

8

T6

16

T7

4

auto[1]

25899

1

T3

8

T6

5

T7

2

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29421

1

T3

10

T6

6

T7

3

auto[1]

30660

1

T3

6

T6

15

T7

3

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30365

1

T3

8

T6

14

T7

5

auto[1]

29716

1

T3

8

T6

7

T7

1

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1042

1

T6

1

T12

3

T29

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

788

1

T12

3

T29

1

T30

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1070

1

T12

2

T29

2

T14

5

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

813

1

T29

2

T14

5

T32

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1003

1

T6

1

T12

3

T14

14

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

724

1

T12

3

T14

12

T77

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1747

1

T3

1

T6

1

T7

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1471

1

T3

1

T12

2

T31

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1096

1

T14

13

T32

3

T23

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

802

1

T14

13

T32

3

T23

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1088

1

T3

2

T12

2

T14

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

832

1

T3

2

T14

4

T23

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1022

1

T6

1

T14

8

T32

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

763

1

T14

8

T32

2

T77

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1064

1

T3

1

T6

1

T12

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

787

1

T3

1

T12

2

T31

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1050

1

T3

1

T6

1

T12

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

774

1

T3

1

T12

3

T14

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1039

1

T12

2

T14

5

T32

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

785

1

T12

2

T14

5

T32

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

989

1

T6

1

T12

2

T29

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

751

1

T12

1

T29

1

T14

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1027

1

T6

1

T12

2

T29

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

792

1

T12

1

T29

1

T31

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1039

1

T12

4

T31

1

T14

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

788

1

T12

3

T31

1

T14

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1070

1

T12

7

T31

1

T14

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

813

1

T12

4

T31

1

T14

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1059

1

T12

4

T14

6

T32

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

810

1

T12

2

T14

5

T32

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1100

1

T12

3

T14

12

T15

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

832

1

T12

2

T14

10

T15

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1024

1

T6

1

T7

1

T8

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

755

1

T7

1

T8

1

T29

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1055

1

T3

1

T6

1

T28

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

807

1

T3

1

T12

4

T29

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1025

1

T6

2

T7

1

T12

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

785

1

T6

2

T7

1

T12

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1080

1

T12

3

T29

1

T14

6

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

813

1

T12

1

T29

1

T14

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1063

1

T3

1

T7

1

T12

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

804

1

T3

1

T12

4

T14

11

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1021

1

T12

1

T29

1

T31

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

794

1

T12

1

T29

1

T31

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1065

1

T6

1

T12

1

T29

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

788

1

T6

1

T12

1

T29

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1084

1

T12

2

T29

1

T31

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

836

1

T12

2

T29

1

T31

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1071

1

T28

1

T12

1

T14

10

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

803

1

T28

1

T12

1

T14

8

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

962

1

T6

1

T12

3

T14

9

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

713

1

T6

1

T12

1

T14

9

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1017

1

T12

1

T14

7

T23

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

738

1

T14

7

T23

3

T15

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1050

1

T3

1

T12

2

T29

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

802

1

T3

1

T29

1

T31

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1076

1

T28

2

T12

3

T29

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

795

1

T28

1

T12

3

T29

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1009

1

T12

2

T29

1

T30

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

780

1

T12

2

T29

1

T14

10

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1079

1

T6

1

T12

1

T29

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

809

1

T6

1

T12

1

T29

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

996

1

T6

1

T12

2

T31

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

752

1

T12

2

T31

1

T14

6