Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 98.23 96.58 99.44 96.00 96.37 100.00 99.02


Total test records in report: 1110
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T806 /workspace/coverage/default/42.pwrmgr_smoke.4056770128 Mar 24 01:12:10 PM PDT 24 Mar 24 01:12:12 PM PDT 24 57510948 ps
T807 /workspace/coverage/default/11.pwrmgr_stress_all.2532930880 Mar 24 01:10:43 PM PDT 24 Mar 24 01:10:44 PM PDT 24 312155977 ps
T808 /workspace/coverage/default/18.pwrmgr_lowpower_invalid.3318937012 Mar 24 01:11:05 PM PDT 24 Mar 24 01:11:06 PM PDT 24 77887706 ps
T809 /workspace/coverage/default/9.pwrmgr_lowpower_invalid.1600070978 Mar 24 01:10:36 PM PDT 24 Mar 24 01:10:36 PM PDT 24 85042828 ps
T810 /workspace/coverage/default/30.pwrmgr_escalation_timeout.265372072 Mar 24 01:11:34 PM PDT 24 Mar 24 01:11:35 PM PDT 24 164434431 ps
T811 /workspace/coverage/default/6.pwrmgr_stress_all.3818387733 Mar 24 01:10:27 PM PDT 24 Mar 24 01:10:31 PM PDT 24 1059225876 ps
T812 /workspace/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2665669405 Mar 24 01:11:28 PM PDT 24 Mar 24 01:11:31 PM PDT 24 1181026966 ps
T813 /workspace/coverage/default/41.pwrmgr_lowpower_wakeup_race.3581536183 Mar 24 01:12:00 PM PDT 24 Mar 24 01:12:01 PM PDT 24 72345610 ps
T814 /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.1951165791 Mar 24 01:10:06 PM PDT 24 Mar 24 01:10:07 PM PDT 24 36637125 ps
T815 /workspace/coverage/default/42.pwrmgr_global_esc.139158629 Mar 24 01:12:06 PM PDT 24 Mar 24 01:12:07 PM PDT 24 106656731 ps
T816 /workspace/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1825567843 Mar 24 01:10:35 PM PDT 24 Mar 24 01:10:38 PM PDT 24 1173046786 ps
T817 /workspace/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1962066560 Mar 24 01:12:02 PM PDT 24 Mar 24 01:12:05 PM PDT 24 1173017747 ps
T818 /workspace/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1983465063 Mar 24 01:11:49 PM PDT 24 Mar 24 01:11:52 PM PDT 24 1421356091 ps
T819 /workspace/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3915731050 Mar 24 01:10:40 PM PDT 24 Mar 24 01:10:41 PM PDT 24 91277973 ps
T820 /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.3206881336 Mar 24 01:10:03 PM PDT 24 Mar 24 01:10:05 PM PDT 24 108283054 ps
T821 /workspace/coverage/default/34.pwrmgr_stress_all.3776410484 Mar 24 01:11:57 PM PDT 24 Mar 24 01:11:59 PM PDT 24 460717916 ps
T822 /workspace/coverage/default/41.pwrmgr_stress_all_with_rand_reset.2724962326 Mar 24 01:12:03 PM PDT 24 Mar 24 01:12:34 PM PDT 24 8449525612 ps
T823 /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.1276263740 Mar 24 01:11:27 PM PDT 24 Mar 24 01:11:28 PM PDT 24 132331745 ps
T824 /workspace/coverage/default/25.pwrmgr_stress_all_with_rand_reset.117359726 Mar 24 01:11:24 PM PDT 24 Mar 24 01:11:37 PM PDT 24 7319199054 ps
T825 /workspace/coverage/default/25.pwrmgr_reset.3145452979 Mar 24 01:11:17 PM PDT 24 Mar 24 01:11:17 PM PDT 24 108402743 ps
T826 /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.994968046 Mar 24 01:10:35 PM PDT 24 Mar 24 01:10:36 PM PDT 24 68248218 ps
T827 /workspace/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4220088721 Mar 24 01:11:45 PM PDT 24 Mar 24 01:11:47 PM PDT 24 1211425933 ps
T828 /workspace/coverage/default/19.pwrmgr_aborted_low_power.2894385208 Mar 24 01:11:07 PM PDT 24 Mar 24 01:11:08 PM PDT 24 56577976 ps
T829 /workspace/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.8635940 Mar 24 01:12:16 PM PDT 24 Mar 24 01:12:18 PM PDT 24 1032635437 ps
T830 /workspace/coverage/default/6.pwrmgr_aborted_low_power.455043859 Mar 24 01:10:22 PM PDT 24 Mar 24 01:10:23 PM PDT 24 84699042 ps
T831 /workspace/coverage/default/3.pwrmgr_wakeup_reset.2647327511 Mar 24 01:10:13 PM PDT 24 Mar 24 01:10:14 PM PDT 24 216434480 ps
T832 /workspace/coverage/default/12.pwrmgr_glitch.4112687834 Mar 24 01:10:44 PM PDT 24 Mar 24 01:10:45 PM PDT 24 68001988 ps
T833 /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.2157002236 Mar 24 01:10:38 PM PDT 24 Mar 24 01:10:39 PM PDT 24 30214678 ps
T834 /workspace/coverage/default/20.pwrmgr_escalation_timeout.1173009538 Mar 24 01:11:11 PM PDT 24 Mar 24 01:11:13 PM PDT 24 313153305 ps
T835 /workspace/coverage/default/8.pwrmgr_glitch.3424857963 Mar 24 01:10:38 PM PDT 24 Mar 24 01:10:39 PM PDT 24 52463557 ps
T836 /workspace/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.4024056700 Mar 24 01:11:09 PM PDT 24 Mar 24 01:11:11 PM PDT 24 187717163 ps
T837 /workspace/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3451821275 Mar 24 01:11:54 PM PDT 24 Mar 24 01:11:56 PM PDT 24 2160537439 ps
T838 /workspace/coverage/default/16.pwrmgr_escalation_timeout.4142713320 Mar 24 01:11:02 PM PDT 24 Mar 24 01:11:03 PM PDT 24 640829028 ps
T839 /workspace/coverage/default/34.pwrmgr_escalation_timeout.2363084497 Mar 24 01:11:50 PM PDT 24 Mar 24 01:11:52 PM PDT 24 166797752 ps
T840 /workspace/coverage/default/34.pwrmgr_global_esc.620142908 Mar 24 01:11:55 PM PDT 24 Mar 24 01:11:56 PM PDT 24 109506095 ps
T841 /workspace/coverage/default/29.pwrmgr_global_esc.1224549380 Mar 24 01:11:31 PM PDT 24 Mar 24 01:11:32 PM PDT 24 30376822 ps
T842 /workspace/coverage/default/34.pwrmgr_lowpower_wakeup_race.660832030 Mar 24 01:11:57 PM PDT 24 Mar 24 01:11:58 PM PDT 24 116586808 ps
T843 /workspace/coverage/default/41.pwrmgr_wakeup_reset.3160161194 Mar 24 01:12:03 PM PDT 24 Mar 24 01:12:04 PM PDT 24 291855998 ps
T58 /workspace/coverage/default/21.pwrmgr_stress_all_with_rand_reset.1531199589 Mar 24 01:11:13 PM PDT 24 Mar 24 01:11:33 PM PDT 24 11882958217 ps
T844 /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.861315030 Mar 24 01:12:00 PM PDT 24 Mar 24 01:12:00 PM PDT 24 38588859 ps
T845 /workspace/coverage/default/15.pwrmgr_wakeup_reset.640141146 Mar 24 01:10:52 PM PDT 24 Mar 24 01:10:53 PM PDT 24 155502235 ps
T846 /workspace/coverage/default/40.pwrmgr_reset.1262265443 Mar 24 01:12:09 PM PDT 24 Mar 24 01:12:10 PM PDT 24 172076633 ps
T847 /workspace/coverage/default/0.pwrmgr_reset_invalid.2158562082 Mar 24 01:10:00 PM PDT 24 Mar 24 01:10:01 PM PDT 24 96594329 ps
T848 /workspace/coverage/default/6.pwrmgr_wakeup_reset.234505670 Mar 24 01:10:31 PM PDT 24 Mar 24 01:10:33 PM PDT 24 393913883 ps
T849 /workspace/coverage/default/45.pwrmgr_stress_all.2262212387 Mar 24 01:12:10 PM PDT 24 Mar 24 01:12:15 PM PDT 24 1239354987 ps
T850 /workspace/coverage/default/21.pwrmgr_lowpower_invalid.3248173005 Mar 24 01:11:13 PM PDT 24 Mar 24 01:11:14 PM PDT 24 84578450 ps
T851 /workspace/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1172453555 Mar 24 01:10:02 PM PDT 24 Mar 24 01:10:05 PM PDT 24 884529019 ps
T852 /workspace/coverage/default/38.pwrmgr_wakeup.688167326 Mar 24 01:11:56 PM PDT 24 Mar 24 01:11:57 PM PDT 24 535083151 ps
T853 /workspace/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.144523656 Mar 24 01:11:23 PM PDT 24 Mar 24 01:11:25 PM PDT 24 425225876 ps
T854 /workspace/coverage/default/21.pwrmgr_wakeup.705735316 Mar 24 01:11:11 PM PDT 24 Mar 24 01:11:12 PM PDT 24 66847396 ps
T143 /workspace/coverage/default/10.pwrmgr_stress_all_with_rand_reset.3482667998 Mar 24 01:10:42 PM PDT 24 Mar 24 01:10:55 PM PDT 24 8921039690 ps
T855 /workspace/coverage/default/23.pwrmgr_wakeup_reset.1846444397 Mar 24 01:11:13 PM PDT 24 Mar 24 01:11:15 PM PDT 24 236127729 ps
T856 /workspace/coverage/default/38.pwrmgr_smoke.2813362360 Mar 24 01:11:55 PM PDT 24 Mar 24 01:11:56 PM PDT 24 42819250 ps
T857 /workspace/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.663409023 Mar 24 01:10:26 PM PDT 24 Mar 24 01:10:29 PM PDT 24 1384341477 ps
T858 /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.3119637838 Mar 24 01:12:04 PM PDT 24 Mar 24 01:12:05 PM PDT 24 31458509 ps
T859 /workspace/coverage/default/13.pwrmgr_stress_all.1961568964 Mar 24 01:10:49 PM PDT 24 Mar 24 01:10:54 PM PDT 24 1573080624 ps
T860 /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.2544875728 Mar 24 01:12:19 PM PDT 24 Mar 24 01:12:20 PM PDT 24 84626461 ps
T861 /workspace/coverage/default/43.pwrmgr_glitch.2490572431 Mar 24 01:12:04 PM PDT 24 Mar 24 01:12:05 PM PDT 24 50904764 ps
T862 /workspace/coverage/default/16.pwrmgr_smoke.2417335367 Mar 24 01:10:55 PM PDT 24 Mar 24 01:10:56 PM PDT 24 29253690 ps
T863 /workspace/coverage/default/49.pwrmgr_lowpower_invalid.1349175104 Mar 24 01:12:30 PM PDT 24 Mar 24 01:12:31 PM PDT 24 44964706 ps
T864 /workspace/coverage/default/32.pwrmgr_lowpower_invalid.284439914 Mar 24 01:11:47 PM PDT 24 Mar 24 01:11:47 PM PDT 24 84475911 ps
T865 /workspace/coverage/default/17.pwrmgr_reset_invalid.909360568 Mar 24 01:11:02 PM PDT 24 Mar 24 01:11:03 PM PDT 24 97840265 ps
T866 /workspace/coverage/default/14.pwrmgr_aborted_low_power.823843509 Mar 24 01:10:50 PM PDT 24 Mar 24 01:10:51 PM PDT 24 73606038 ps
T867 /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.2474400846 Mar 24 01:10:49 PM PDT 24 Mar 24 01:10:50 PM PDT 24 171388994 ps
T868 /workspace/coverage/default/44.pwrmgr_stress_all.676324863 Mar 24 01:12:18 PM PDT 24 Mar 24 01:12:20 PM PDT 24 2614972225 ps
T869 /workspace/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1367722873 Mar 24 01:11:32 PM PDT 24 Mar 24 01:11:34 PM PDT 24 849202735 ps
T870 /workspace/coverage/default/31.pwrmgr_aborted_low_power.1089666651 Mar 24 01:11:55 PM PDT 24 Mar 24 01:11:56 PM PDT 24 42190388 ps
T871 /workspace/coverage/default/35.pwrmgr_reset_invalid.2089946807 Mar 24 01:11:46 PM PDT 24 Mar 24 01:11:48 PM PDT 24 99059047 ps
T872 /workspace/coverage/default/17.pwrmgr_stress_all.2371637171 Mar 24 01:11:02 PM PDT 24 Mar 24 01:11:08 PM PDT 24 1350492166 ps
T873 /workspace/coverage/default/9.pwrmgr_global_esc.3978667480 Mar 24 01:10:40 PM PDT 24 Mar 24 01:10:41 PM PDT 24 241827130 ps
T874 /workspace/coverage/default/37.pwrmgr_reset.1584227886 Mar 24 01:11:57 PM PDT 24 Mar 24 01:11:58 PM PDT 24 128212136 ps
T875 /workspace/coverage/default/43.pwrmgr_global_esc.2850163041 Mar 24 01:12:13 PM PDT 24 Mar 24 01:12:14 PM PDT 24 111544974 ps
T876 /workspace/coverage/default/12.pwrmgr_reset.2152613698 Mar 24 01:10:41 PM PDT 24 Mar 24 01:10:43 PM PDT 24 91575352 ps
T877 /workspace/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.937032660 Mar 24 01:12:42 PM PDT 24 Mar 24 01:12:45 PM PDT 24 757267722 ps
T878 /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.3762403245 Mar 24 01:12:13 PM PDT 24 Mar 24 01:12:14 PM PDT 24 67236085 ps
T879 /workspace/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1797312097 Mar 24 01:11:01 PM PDT 24 Mar 24 01:11:03 PM PDT 24 1389683836 ps
T880 /workspace/coverage/default/16.pwrmgr_reset_invalid.3028989649 Mar 24 01:11:00 PM PDT 24 Mar 24 01:11:01 PM PDT 24 105843811 ps
T881 /workspace/coverage/default/19.pwrmgr_escalation_timeout.1030627938 Mar 24 01:11:09 PM PDT 24 Mar 24 01:11:10 PM PDT 24 168843612 ps
T882 /workspace/coverage/default/46.pwrmgr_wakeup.2360251208 Mar 24 01:12:25 PM PDT 24 Mar 24 01:12:26 PM PDT 24 336680757 ps
T883 /workspace/coverage/default/28.pwrmgr_glitch.4026609270 Mar 24 01:11:35 PM PDT 24 Mar 24 01:11:36 PM PDT 24 62758980 ps
T884 /workspace/coverage/default/15.pwrmgr_lowpower_wakeup_race.1575604982 Mar 24 01:10:48 PM PDT 24 Mar 24 01:10:49 PM PDT 24 90880065 ps
T885 /workspace/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.1234916152 Mar 24 01:11:48 PM PDT 24 Mar 24 01:11:50 PM PDT 24 267658454 ps
T886 /workspace/coverage/default/4.pwrmgr_global_esc.3060588033 Mar 24 01:10:21 PM PDT 24 Mar 24 01:10:22 PM PDT 24 155314587 ps
T887 /workspace/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.911963319 Mar 24 01:11:46 PM PDT 24 Mar 24 01:11:49 PM PDT 24 694470523 ps
T888 /workspace/coverage/default/3.pwrmgr_global_esc.3440236015 Mar 24 01:10:08 PM PDT 24 Mar 24 01:10:09 PM PDT 24 35621703 ps
T889 /workspace/coverage/default/27.pwrmgr_smoke.1448862844 Mar 24 01:11:26 PM PDT 24 Mar 24 01:11:27 PM PDT 24 39251118 ps
T890 /workspace/coverage/default/40.pwrmgr_wakeup.43171514 Mar 24 01:11:59 PM PDT 24 Mar 24 01:12:00 PM PDT 24 188561363 ps
T891 /workspace/coverage/default/31.pwrmgr_smoke.19911599 Mar 24 01:11:48 PM PDT 24 Mar 24 01:11:49 PM PDT 24 66638315 ps
T892 /workspace/coverage/default/6.pwrmgr_escalation_timeout.3392527220 Mar 24 01:10:27 PM PDT 24 Mar 24 01:10:29 PM PDT 24 165150374 ps
T893 /workspace/coverage/default/38.pwrmgr_reset_invalid.3482245380 Mar 24 01:11:57 PM PDT 24 Mar 24 01:11:59 PM PDT 24 104632696 ps
T894 /workspace/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4089322158 Mar 24 01:10:49 PM PDT 24 Mar 24 01:10:52 PM PDT 24 805384988 ps
T895 /workspace/coverage/default/43.pwrmgr_reset_invalid.2352472418 Mar 24 01:12:13 PM PDT 24 Mar 24 01:12:19 PM PDT 24 149885999 ps
T896 /workspace/coverage/default/44.pwrmgr_lowpower_wakeup_race.21857619 Mar 24 01:12:13 PM PDT 24 Mar 24 01:12:14 PM PDT 24 80315361 ps
T897 /workspace/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2387922605 Mar 24 01:11:21 PM PDT 24 Mar 24 01:11:24 PM PDT 24 1603718027 ps
T898 /workspace/coverage/default/8.pwrmgr_global_esc.2265156315 Mar 24 01:10:33 PM PDT 24 Mar 24 01:10:34 PM PDT 24 74389921 ps
T899 /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.2635983485 Mar 24 01:11:32 PM PDT 24 Mar 24 01:11:33 PM PDT 24 29986442 ps
T900 /workspace/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2580638110 Mar 24 01:11:16 PM PDT 24 Mar 24 01:11:18 PM PDT 24 1637634081 ps
T901 /workspace/coverage/default/19.pwrmgr_stress_all.587210993 Mar 24 01:11:04 PM PDT 24 Mar 24 01:11:05 PM PDT 24 34118890 ps
T902 /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.1177267027 Mar 24 01:10:24 PM PDT 24 Mar 24 01:10:25 PM PDT 24 170595857 ps
T903 /workspace/coverage/default/4.pwrmgr_wakeup.212153494 Mar 24 01:10:15 PM PDT 24 Mar 24 01:10:16 PM PDT 24 341287803 ps
T904 /workspace/coverage/default/3.pwrmgr_stress_all.1115164390 Mar 24 01:10:17 PM PDT 24 Mar 24 01:10:21 PM PDT 24 1601619205 ps
T905 /workspace/coverage/default/5.pwrmgr_stress_all_with_rand_reset.3164928860 Mar 24 01:10:27 PM PDT 24 Mar 24 01:10:36 PM PDT 24 2330416027 ps
T906 /workspace/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.278175849 Mar 24 01:11:59 PM PDT 24 Mar 24 01:12:00 PM PDT 24 93745621 ps
T907 /workspace/coverage/default/3.pwrmgr_lowpower_wakeup_race.4108215921 Mar 24 01:10:12 PM PDT 24 Mar 24 01:10:14 PM PDT 24 217668750 ps
T908 /workspace/coverage/default/11.pwrmgr_smoke.1049397880 Mar 24 01:10:38 PM PDT 24 Mar 24 01:10:39 PM PDT 24 35988365 ps
T909 /workspace/coverage/default/0.pwrmgr_reset.1624478767 Mar 24 01:09:57 PM PDT 24 Mar 24 01:09:58 PM PDT 24 184469546 ps
T910 /workspace/coverage/default/39.pwrmgr_smoke.4094903877 Mar 24 01:11:59 PM PDT 24 Mar 24 01:12:00 PM PDT 24 86642475 ps
T911 /workspace/coverage/default/2.pwrmgr_reset_invalid.1823222754 Mar 24 01:10:16 PM PDT 24 Mar 24 01:10:18 PM PDT 24 158023990 ps
T912 /workspace/coverage/default/6.pwrmgr_lowpower_invalid.2793043182 Mar 24 01:10:27 PM PDT 24 Mar 24 01:10:28 PM PDT 24 41875119 ps
T913 /workspace/coverage/default/25.pwrmgr_smoke.902167194 Mar 24 01:11:26 PM PDT 24 Mar 24 01:11:26 PM PDT 24 62502450 ps
T914 /workspace/coverage/default/4.pwrmgr_reset_invalid.1216160624 Mar 24 01:10:24 PM PDT 24 Mar 24 01:10:25 PM PDT 24 107768035 ps
T915 /workspace/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1458914867 Mar 24 01:12:00 PM PDT 24 Mar 24 01:12:03 PM PDT 24 971120389 ps
T916 /workspace/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2179162155 Mar 24 01:10:37 PM PDT 24 Mar 24 01:10:41 PM PDT 24 900409071 ps
T917 /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.4056476682 Mar 24 01:12:13 PM PDT 24 Mar 24 01:12:15 PM PDT 24 144101667 ps
T918 /workspace/coverage/default/12.pwrmgr_wakeup_reset.589629974 Mar 24 01:10:44 PM PDT 24 Mar 24 01:10:45 PM PDT 24 218044218 ps
T919 /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.551206744 Mar 24 01:12:08 PM PDT 24 Mar 24 01:12:10 PM PDT 24 68331759 ps
T920 /workspace/coverage/default/37.pwrmgr_smoke.2148647762 Mar 24 01:12:00 PM PDT 24 Mar 24 01:12:01 PM PDT 24 139766656 ps
T921 /workspace/coverage/default/30.pwrmgr_wakeup_reset.223701448 Mar 24 01:11:35 PM PDT 24 Mar 24 01:11:37 PM PDT 24 139322877 ps
T922 /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.2720963391 Mar 24 01:11:10 PM PDT 24 Mar 24 01:11:11 PM PDT 24 29837371 ps
T923 /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.2055461033 Mar 24 01:11:27 PM PDT 24 Mar 24 01:11:28 PM PDT 24 82083398 ps
T924 /workspace/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3535172456 Mar 24 01:11:27 PM PDT 24 Mar 24 01:11:30 PM PDT 24 763564265 ps
T925 /workspace/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.1264862945 Mar 24 01:12:50 PM PDT 24 Mar 24 01:12:51 PM PDT 24 309090948 ps
T926 /workspace/coverage/default/39.pwrmgr_reset.2220345098 Mar 24 01:12:03 PM PDT 24 Mar 24 01:12:04 PM PDT 24 86661482 ps
T927 /workspace/coverage/default/2.pwrmgr_escalation_timeout.4046785657 Mar 24 01:10:09 PM PDT 24 Mar 24 01:10:10 PM PDT 24 792308812 ps
T26 /workspace/coverage/default/2.pwrmgr_sec_cm.3884481238 Mar 24 01:10:12 PM PDT 24 Mar 24 01:10:15 PM PDT 24 690368810 ps
T928 /workspace/coverage/default/0.pwrmgr_stress_all.1175232163 Mar 24 01:09:59 PM PDT 24 Mar 24 01:10:01 PM PDT 24 397859553 ps
T929 /workspace/coverage/default/1.pwrmgr_lowpower_invalid.2246107515 Mar 24 01:10:07 PM PDT 24 Mar 24 01:10:08 PM PDT 24 83621478 ps
T930 /workspace/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3958440057 Mar 24 01:12:00 PM PDT 24 Mar 24 01:12:03 PM PDT 24 898756813 ps
T931 /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.2635668525 Mar 24 01:11:52 PM PDT 24 Mar 24 01:11:53 PM PDT 24 76167755 ps
T932 /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.4154841414 Mar 24 01:10:10 PM PDT 24 Mar 24 01:10:11 PM PDT 24 51318061 ps
T933 /workspace/coverage/default/37.pwrmgr_wakeup_reset.3726264306 Mar 24 01:12:03 PM PDT 24 Mar 24 01:12:05 PM PDT 24 419754434 ps
T934 /workspace/coverage/default/43.pwrmgr_reset.3307518121 Mar 24 01:12:13 PM PDT 24 Mar 24 01:12:14 PM PDT 24 198797476 ps
T935 /workspace/coverage/default/19.pwrmgr_lowpower_invalid.237887332 Mar 24 01:11:04 PM PDT 24 Mar 24 01:11:05 PM PDT 24 108033867 ps
T936 /workspace/coverage/default/42.pwrmgr_lowpower_invalid.2453226477 Mar 24 01:12:10 PM PDT 24 Mar 24 01:12:11 PM PDT 24 72403218 ps
T937 /workspace/coverage/default/8.pwrmgr_wakeup.2305044916 Mar 24 01:10:37 PM PDT 24 Mar 24 01:10:38 PM PDT 24 139824395 ps
T938 /workspace/coverage/default/7.pwrmgr_smoke.3391328883 Mar 24 01:10:26 PM PDT 24 Mar 24 01:10:26 PM PDT 24 67316917 ps
T939 /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.1516203445 Mar 24 01:10:25 PM PDT 24 Mar 24 01:10:26 PM PDT 24 61495686 ps
T940 /workspace/coverage/default/14.pwrmgr_wakeup.2385438794 Mar 24 01:10:47 PM PDT 24 Mar 24 01:10:48 PM PDT 24 114070129 ps
T941 /workspace/coverage/default/10.pwrmgr_reset.4095440983 Mar 24 01:10:39 PM PDT 24 Mar 24 01:10:41 PM PDT 24 156663366 ps
T942 /workspace/coverage/default/26.pwrmgr_smoke.1562533922 Mar 24 01:11:22 PM PDT 24 Mar 24 01:11:23 PM PDT 24 61317181 ps
T943 /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.155918249 Mar 24 01:10:05 PM PDT 24 Mar 24 01:10:06 PM PDT 24 54792092 ps
T944 /workspace/coverage/default/47.pwrmgr_smoke.2323490224 Mar 24 01:12:16 PM PDT 24 Mar 24 01:12:17 PM PDT 24 56130288 ps
T945 /workspace/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1586158994 Mar 24 01:11:10 PM PDT 24 Mar 24 01:11:13 PM PDT 24 1015272844 ps
T946 /workspace/coverage/default/2.pwrmgr_global_esc.502925812 Mar 24 01:10:05 PM PDT 24 Mar 24 01:10:06 PM PDT 24 24475164 ps
T947 /workspace/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.2889789444 Mar 24 01:11:55 PM PDT 24 Mar 24 01:11:57 PM PDT 24 728196315 ps
T948 /workspace/coverage/default/3.pwrmgr_escalation_timeout.1307168402 Mar 24 01:10:13 PM PDT 24 Mar 24 01:10:14 PM PDT 24 315882762 ps
T949 /workspace/coverage/default/1.pwrmgr_stress_all.2425623247 Mar 24 01:10:08 PM PDT 24 Mar 24 01:10:10 PM PDT 24 522440703 ps
T950 /workspace/coverage/default/42.pwrmgr_stress_all.1840933815 Mar 24 01:12:07 PM PDT 24 Mar 24 01:12:10 PM PDT 24 979302136 ps
T951 /workspace/coverage/default/12.pwrmgr_lowpower_wakeup_race.670513277 Mar 24 01:10:44 PM PDT 24 Mar 24 01:10:45 PM PDT 24 313818379 ps
T952 /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.603294173 Mar 24 01:11:07 PM PDT 24 Mar 24 01:11:09 PM PDT 24 75270423 ps
T953 /workspace/coverage/default/43.pwrmgr_lowpower_wakeup_race.1783532451 Mar 24 01:12:07 PM PDT 24 Mar 24 01:12:09 PM PDT 24 214145259 ps
T954 /workspace/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2387965318 Mar 24 01:12:09 PM PDT 24 Mar 24 01:12:13 PM PDT 24 1018572542 ps
T955 /workspace/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.800457902 Mar 24 01:10:24 PM PDT 24 Mar 24 01:10:27 PM PDT 24 861378748 ps
T956 /workspace/coverage/default/34.pwrmgr_glitch.1407264593 Mar 24 01:11:49 PM PDT 24 Mar 24 01:11:50 PM PDT 24 43077783 ps
T957 /workspace/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.1405020328 Mar 24 01:12:20 PM PDT 24 Mar 24 01:12:21 PM PDT 24 439040207 ps
T958 /workspace/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3997474607 Mar 24 01:11:51 PM PDT 24 Mar 24 01:11:54 PM PDT 24 942380860 ps
T959 /workspace/coverage/default/29.pwrmgr_reset_invalid.3126963971 Mar 24 01:11:27 PM PDT 24 Mar 24 01:11:28 PM PDT 24 110719009 ps
T960 /workspace/coverage/default/34.pwrmgr_stress_all_with_rand_reset.1364173670 Mar 24 01:11:58 PM PDT 24 Mar 24 01:12:06 PM PDT 24 5727208567 ps
T961 /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.1210137098 Mar 24 01:12:26 PM PDT 24 Mar 24 01:12:27 PM PDT 24 97890199 ps
T962 /workspace/coverage/default/39.pwrmgr_stress_all_with_rand_reset.1871152955 Mar 24 01:11:59 PM PDT 24 Mar 24 01:12:12 PM PDT 24 6711034666 ps
T963 /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.1814294208 Mar 24 01:11:13 PM PDT 24 Mar 24 01:11:14 PM PDT 24 60746728 ps
T964 /workspace/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.3779233135 Mar 24 01:12:21 PM PDT 24 Mar 24 01:12:22 PM PDT 24 61278843 ps
T965 /workspace/coverage/default/49.pwrmgr_lowpower_wakeup_race.1272162526 Mar 24 01:12:27 PM PDT 24 Mar 24 01:12:28 PM PDT 24 393932104 ps
T966 /workspace/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.2434838951 Mar 24 01:11:57 PM PDT 24 Mar 24 01:11:57 PM PDT 24 117528133 ps
T967 /workspace/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2298387182 Mar 24 01:12:10 PM PDT 24 Mar 24 01:12:18 PM PDT 24 1038583236 ps
T968 /workspace/coverage/default/27.pwrmgr_global_esc.1766297776 Mar 24 01:11:22 PM PDT 24 Mar 24 01:11:22 PM PDT 24 45852802 ps
T969 /workspace/coverage/default/6.pwrmgr_wakeup.2017085376 Mar 24 01:10:32 PM PDT 24 Mar 24 01:10:33 PM PDT 24 256825465 ps
T970 /workspace/coverage/default/39.pwrmgr_wakeup_reset.927004403 Mar 24 01:11:57 PM PDT 24 Mar 24 01:11:58 PM PDT 24 159109450 ps
T971 /workspace/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.942695913 Mar 24 01:10:49 PM PDT 24 Mar 24 01:10:52 PM PDT 24 1399389465 ps
T972 /workspace/coverage/default/23.pwrmgr_wakeup.950783356 Mar 24 01:11:20 PM PDT 24 Mar 24 01:11:21 PM PDT 24 203336879 ps
T973 /workspace/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1632122148 Mar 24 01:11:08 PM PDT 24 Mar 24 01:11:11 PM PDT 24 1286075351 ps
T974 /workspace/coverage/default/20.pwrmgr_stress_all_with_rand_reset.368344031 Mar 24 01:11:12 PM PDT 24 Mar 24 01:11:29 PM PDT 24 35431708244 ps
T975 /workspace/coverage/default/6.pwrmgr_stress_all_with_rand_reset.3204853683 Mar 24 01:10:27 PM PDT 24 Mar 24 01:11:01 PM PDT 24 10918416901 ps
T976 /workspace/coverage/default/17.pwrmgr_wakeup_reset.1127817260 Mar 24 01:11:03 PM PDT 24 Mar 24 01:11:04 PM PDT 24 430422011 ps
T977 /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.452474428 Mar 24 01:12:00 PM PDT 24 Mar 24 01:12:01 PM PDT 24 175035595 ps
T978 /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.1026557557 Mar 24 01:11:13 PM PDT 24 Mar 24 01:11:14 PM PDT 24 84259516 ps
T979 /workspace/coverage/default/28.pwrmgr_stress_all.402593228 Mar 24 01:11:31 PM PDT 24 Mar 24 01:11:35 PM PDT 24 911458874 ps
T980 /workspace/coverage/default/39.pwrmgr_wakeup.314819628 Mar 24 01:12:00 PM PDT 24 Mar 24 01:12:01 PM PDT 24 77027816 ps
T981 /workspace/coverage/default/6.pwrmgr_lowpower_wakeup_race.1867137485 Mar 24 01:10:25 PM PDT 24 Mar 24 01:10:26 PM PDT 24 64650112 ps
T982 /workspace/coverage/default/10.pwrmgr_global_esc.3137960866 Mar 24 01:10:40 PM PDT 24 Mar 24 01:10:41 PM PDT 24 102697499 ps
T27 /workspace/coverage/default/3.pwrmgr_sec_cm.1058438103 Mar 24 01:10:16 PM PDT 24 Mar 24 01:10:18 PM PDT 24 322611450 ps
T983 /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.3562267585 Mar 24 01:11:36 PM PDT 24 Mar 24 01:11:37 PM PDT 24 96370772 ps
T984 /workspace/coverage/default/47.pwrmgr_lowpower_invalid.117697962 Mar 24 01:12:22 PM PDT 24 Mar 24 01:12:23 PM PDT 24 247133222 ps
T985 /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.3857780766 Mar 24 01:11:20 PM PDT 24 Mar 24 01:11:21 PM PDT 24 32704995 ps
T986 /workspace/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.512429602 Mar 24 01:11:19 PM PDT 24 Mar 24 01:11:22 PM PDT 24 800770641 ps
T987 /workspace/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.3250702180 Mar 24 01:11:28 PM PDT 24 Mar 24 01:11:29 PM PDT 24 98736543 ps
T988 /workspace/coverage/default/44.pwrmgr_glitch.1109260052 Mar 24 01:12:14 PM PDT 24 Mar 24 01:12:14 PM PDT 24 73835560 ps
T989 /workspace/coverage/default/9.pwrmgr_reset_invalid.1148174722 Mar 24 01:10:37 PM PDT 24 Mar 24 01:10:39 PM PDT 24 170636480 ps
T990 /workspace/coverage/default/43.pwrmgr_escalation_timeout.1570802084 Mar 24 01:12:04 PM PDT 24 Mar 24 01:12:05 PM PDT 24 630851338 ps
T991 /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.1190768101 Mar 24 01:11:31 PM PDT 24 Mar 24 01:11:32 PM PDT 24 69451431 ps
T992 /workspace/coverage/default/39.pwrmgr_escalation_timeout.1575422495 Mar 24 01:12:01 PM PDT 24 Mar 24 01:12:02 PM PDT 24 168193016 ps
T993 /workspace/coverage/default/25.pwrmgr_stress_all.3255921444 Mar 24 01:11:23 PM PDT 24 Mar 24 01:11:27 PM PDT 24 1104897708 ps
T994 /workspace/coverage/default/39.pwrmgr_reset_invalid.3028676312 Mar 24 01:11:59 PM PDT 24 Mar 24 01:12:00 PM PDT 24 243398096 ps
T995 /workspace/coverage/default/7.pwrmgr_reset.4081909056 Mar 24 01:10:28 PM PDT 24 Mar 24 01:10:29 PM PDT 24 32768006 ps
T996 /workspace/coverage/default/29.pwrmgr_escalation_timeout.2446074669 Mar 24 01:11:31 PM PDT 24 Mar 24 01:11:32 PM PDT 24 162305459 ps
T47 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.1907574423 Mar 24 12:33:31 PM PDT 24 Mar 24 12:33:33 PM PDT 24 119979479 ps
T61 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.1511702128 Mar 24 12:34:10 PM PDT 24 Mar 24 12:34:10 PM PDT 24 22094953 ps
T62 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.2281444207 Mar 24 12:34:24 PM PDT 24 Mar 24 12:34:25 PM PDT 24 30736199 ps
T63 /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.3287499285 Mar 24 12:34:14 PM PDT 24 Mar 24 12:34:15 PM PDT 24 20569388 ps
T162 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.4217872636 Mar 24 12:34:25 PM PDT 24 Mar 24 12:34:27 PM PDT 24 19298693 ps
T48 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.4160941356 Mar 24 12:34:04 PM PDT 24 Mar 24 12:34:05 PM PDT 24 101444202 ps
T161 /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.2294583008 Mar 24 12:34:17 PM PDT 24 Mar 24 12:34:18 PM PDT 24 19040304 ps
T56 /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.691704104 Mar 24 12:33:46 PM PDT 24 Mar 24 12:33:46 PM PDT 24 65117770 ps
T65 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.7955562 Mar 24 12:34:11 PM PDT 24 Mar 24 12:34:17 PM PDT 24 50248309 ps
T57 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.1936981181 Mar 24 12:34:20 PM PDT 24 Mar 24 12:34:20 PM PDT 24 71139732 ps
T116 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2064052252 Mar 24 12:34:21 PM PDT 24 Mar 24 12:34:22 PM PDT 24 125865649 ps
T163 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.2325747783 Mar 24 12:34:10 PM PDT 24 Mar 24 12:34:11 PM PDT 24 35296414 ps
T49 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.3720101460 Mar 24 12:34:04 PM PDT 24 Mar 24 12:34:05 PM PDT 24 30245141 ps
T64 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.3737685923 Mar 24 12:34:06 PM PDT 24 Mar 24 12:34:07 PM PDT 24 119066613 ps
T69 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1855192982 Mar 24 12:33:55 PM PDT 24 Mar 24 12:33:56 PM PDT 24 53252763 ps
T997 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.92751824 Mar 24 12:34:24 PM PDT 24 Mar 24 12:34:25 PM PDT 24 63845484 ps
T164 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.2797436563 Mar 24 12:34:09 PM PDT 24 Mar 24 12:34:10 PM PDT 24 39325593 ps
T50 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.3260763989 Mar 24 12:33:47 PM PDT 24 Mar 24 12:33:48 PM PDT 24 127893357 ps
T165 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3566588125 Mar 24 12:33:49 PM PDT 24 Mar 24 12:33:50 PM PDT 24 157499348 ps
T998 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.4002396323 Mar 24 12:34:04 PM PDT 24 Mar 24 12:34:04 PM PDT 24 17633742 ps
T59 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.2428980034 Mar 24 12:34:25 PM PDT 24 Mar 24 12:34:28 PM PDT 24 87862677 ps
T166 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.3309206527 Mar 24 12:34:05 PM PDT 24 Mar 24 12:34:06 PM PDT 24 105149699 ps
T999 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.577520085 Mar 24 12:33:48 PM PDT 24 Mar 24 12:33:48 PM PDT 24 28093532 ps
T132 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.4031020931 Mar 24 12:34:35 PM PDT 24 Mar 24 12:34:36 PM PDT 24 103883965 ps
T74 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3773819540 Mar 24 12:34:19 PM PDT 24 Mar 24 12:34:20 PM PDT 24 47490819 ps
T117 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.1658812842 Mar 24 12:34:15 PM PDT 24 Mar 24 12:34:16 PM PDT 24 31481446 ps
T114 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.2894524890 Mar 24 12:34:10 PM PDT 24 Mar 24 12:34:11 PM PDT 24 20467728 ps
T68 /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.2395691840 Mar 24 12:34:10 PM PDT 24 Mar 24 12:34:13 PM PDT 24 975056805 ps
T51 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.3081063765 Mar 24 12:34:03 PM PDT 24 Mar 24 12:34:04 PM PDT 24 117008319 ps
T70 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.2147627474 Mar 24 12:34:10 PM PDT 24 Mar 24 12:34:11 PM PDT 24 53798597 ps
T60 /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.138390745 Mar 24 12:34:11 PM PDT 24 Mar 24 12:34:13 PM PDT 24 123611331 ps
T104 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.1528324152 Mar 24 12:34:11 PM PDT 24 Mar 24 12:34:11 PM PDT 24 42081373 ps
T1000 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.3507055812 Mar 24 12:34:11 PM PDT 24 Mar 24 12:34:12 PM PDT 24 19625685 ps
T1001 /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.207105237 Mar 24 12:34:25 PM PDT 24 Mar 24 12:34:28 PM PDT 24 25249258 ps
T118 /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3248346279 Mar 24 12:34:10 PM PDT 24 Mar 24 12:34:11 PM PDT 24 21575821 ps
T1002 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.1421772794 Mar 24 12:33:47 PM PDT 24 Mar 24 12:33:48 PM PDT 24 38900878 ps
T71 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.2482552836 Mar 24 12:34:10 PM PDT 24 Mar 24 12:34:12 PM PDT 24 99078416 ps
T1003 /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.618433829 Mar 24 12:34:19 PM PDT 24 Mar 24 12:34:19 PM PDT 24 24169707 ps
T1004 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.3455865566 Mar 24 12:34:12 PM PDT 24 Mar 24 12:34:12 PM PDT 24 36063755 ps
T119 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.1597919380 Mar 24 12:34:06 PM PDT 24 Mar 24 12:34:07 PM PDT 24 144946692 ps
T1005 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.3022427850 Mar 24 12:34:11 PM PDT 24 Mar 24 12:34:13 PM PDT 24 154285336 ps
T1006 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.430363962 Mar 24 12:34:14 PM PDT 24 Mar 24 12:34:15 PM PDT 24 24955983 ps
T1007 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.3839073838 Mar 24 12:34:24 PM PDT 24 Mar 24 12:34:26 PM PDT 24 125805862 ps
T1008 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.3162442981 Mar 24 12:34:03 PM PDT 24 Mar 24 12:34:04 PM PDT 24 49202651 ps
T1009 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.3096523271 Mar 24 12:34:11 PM PDT 24 Mar 24 12:34:12 PM PDT 24 139962355 ps
T1010 /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.1096198012 Mar 24 12:34:22 PM PDT 24 Mar 24 12:34:23 PM PDT 24 45569196 ps
T66 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.343431080 Mar 24 12:34:21 PM PDT 24 Mar 24 12:34:23 PM PDT 24 185776040 ps
T133 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.951230507 Mar 24 12:34:31 PM PDT 24 Mar 24 12:34:32 PM PDT 24 96396202 ps
T1011 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.4026895441 Mar 24 12:34:12 PM PDT 24 Mar 24 12:34:16 PM PDT 24 420693227 ps
T134 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.2257190906 Mar 24 12:33:58 PM PDT 24 Mar 24 12:33:59 PM PDT 24 60179765 ps
T1012 /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.2933597376 Mar 24 12:34:02 PM PDT 24 Mar 24 12:34:02 PM PDT 24 20582293 ps
T1013 /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.2973414661 Mar 24 12:34:10 PM PDT 24 Mar 24 12:34:11 PM PDT 24 40796074 ps
T1014 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.360023988 Mar 24 12:34:22 PM PDT 24 Mar 24 12:34:23 PM PDT 24 131048648 ps
T105 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.3687257141 Mar 24 12:33:51 PM PDT 24 Mar 24 12:33:52 PM PDT 24 70832536 ps
T1015 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.373729098 Mar 24 12:34:05 PM PDT 24 Mar 24 12:34:06 PM PDT 24 109315246 ps
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