Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31302 1 T2 38 T4 19 T5 2
auto[1] 30208 1 T1 2 T2 26 T4 23


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31261 1 T1 2 T2 34 T4 18
auto[1] 30249 1 T2 30 T4 24 T8 521


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 30253 1 T2 26 T4 17 T8 547
auto[1] 31257 1 T1 2 T2 38 T4 25


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 35101 1 T1 1 T2 32 T4 33
auto[1] 26409 1 T1 1 T2 32 T4 9


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29678 1 T2 30 T4 25 T8 508
auto[1] 31832 1 T1 2 T2 34 T4 17


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31511 1 T1 2 T2 30 T4 18
auto[1] 29999 1 T2 34 T4 24 T8 484


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1122 1 T4 1 T8 18 T9 4
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 837 1 T8 14 T9 2 T13 7
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1000 1 T2 2 T4 3 T8 20
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 735 1 T2 2 T8 18 T13 9
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1046 1 T2 3 T8 27 T9 2
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 778 1 T2 3 T8 19 T13 19
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1731 1 T2 2 T5 1 T8 31
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1475 1 T2 2 T5 1 T8 29
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1072 1 T8 14 T9 1 T13 14
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 817 1 T8 13 T13 14 T27 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 1040 1 T2 2 T8 14 T9 2
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 793 1 T2 2 T8 12 T9 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1073 1 T4 1 T8 16 T9 2
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 801 1 T8 13 T9 2 T13 10
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1086 1 T2 1 T8 19 T9 3
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 813 1 T2 1 T8 13 T9 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1145 1 T2 2 T4 1 T8 26
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 850 1 T2 2 T8 20 T13 11
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 1028 1 T2 2 T8 12 T9 4
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 777 1 T2 2 T8 10 T9 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1086 1 T4 1 T8 16 T13 12
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 840 1 T4 1 T8 13 T13 11
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1128 1 T8 32 T9 2 T13 16
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 863 1 T8 23 T13 15 T27 3
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1058 1 T2 2 T8 19 T9 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 807 1 T2 2 T8 18 T9 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1032 1 T2 2 T4 5 T8 14
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 774 1 T2 2 T4 1 T8 11
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1077 1 T2 1 T4 3 T8 21
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 800 1 T2 1 T4 2 T8 19
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1039 1 T8 14 T9 2 T13 15
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 779 1 T8 11 T9 1 T13 14
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 1079 1 T8 17 T9 1 T13 10
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 777 1 T8 14 T13 8 T29 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 1022 1 T4 1 T8 20 T9 2
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 747 1 T8 16 T9 1 T13 8
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1089 1 T2 1 T4 2 T8 23
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 814 1 T2 1 T8 22 T13 16
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1074 1 T1 1 T2 2 T4 2
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 813 1 T1 1 T2 2 T4 2
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1039 1 T8 22 T13 8 T27 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 756 1 T8 18 T13 7 T27 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1112 1 T2 1 T4 4 T8 13
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 814 1 T2 1 T4 1 T8 9
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1137 1 T2 1 T8 20 T9 1
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 852 1 T2 1 T8 14 T25 2
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1096 1 T2 2 T4 1 T8 17
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 821 1 T2 2 T8 13 T13 12
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1056 1 T4 1 T8 14 T9 5
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 765 1 T8 11 T9 4 T13 8
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1068 1 T2 1 T4 1 T8 19
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 793 1 T2 1 T4 1 T8 17
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1097 1 T4 1 T8 15 T9 4
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 816 1 T8 13 T9 1 T13 16
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 1179 1 T8 19 T9 2 T25 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 881 1 T8 17 T9 1 T13 15
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 1083 1 T2 1 T4 2 T8 14
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 822 1 T2 1 T4 1 T8 12
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1063 1 T4 2 T8 22 T9 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 795 1 T8 17 T13 14 T27 2
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1071 1 T2 2 T8 18 T9 2
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 791 1 T2 2 T8 14 T13 14
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 1073 1 T2 2 T4 1 T8 12
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 813 1 T2 2 T8 8 T9 1

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