Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29756

1

T6

48

T7

6

T13

2

auto[1]

28519

1

T6

52

T7

6

T14

8

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29557

1

T6

46

T7

8

T13

2

auto[1]

28718

1

T6

54

T7

4

T14

4

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28532

1

T6

52

T7

6

T14

10

auto[1]

29743

1

T6

48

T7

6

T13

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33089

1

T6

50

T7

12

T13

1

auto[1]

25186

1

T6

50

T13

1

T14

7

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28766

1

T6

56

T7

6

T14

6

auto[1]

29509

1

T6

44

T7

6

T13

2

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29736

1

T6

44

T7

7

T13

2

auto[1]

28539

1

T6

56

T7

5

T14

8

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1059

1

T6

1

T7

1

T25

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

790

1

T6

1

T25

2

T15

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1017

1

T6

2

T25

3

T78

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

789

1

T6

2

T25

3

T78

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

972

1

T6

2

T7

1

T14

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

731

1

T6

2

T14

1

T25

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1667

1

T7

1

T13

1

T25

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1415

1

T13

1

T25

4

T78

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1002

1

T6

1

T25

2

T40

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

758

1

T6

1

T25

2

T40

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1002

1

T7

1

T25

2

T40

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

758

1

T25

2

T40

1

T79

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1005

1

T6

1

T40

1

T78

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

766

1

T6

1

T40

1

T78

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1035

1

T6

1

T25

6

T40

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

765

1

T6

1

T25

6

T40

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1028

1

T6

2

T14

1

T25

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

786

1

T6

2

T14

1

T25

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1017

1

T6

1

T25

1

T78

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

793

1

T6

1

T25

1

T78

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1021

1

T6

2

T25

1

T40

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

772

1

T6

2

T25

1

T40

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

979

1

T6

2

T79

3

T15

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

732

1

T6

2

T79

3

T15

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

975

1

T6

3

T7

1

T79

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

741

1

T6

3

T79

2

T15

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1029

1

T14

1

T78

1

T42

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

771

1

T14

1

T78

1

T42

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1026

1

T6

4

T25

1

T79

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

801

1

T6

4

T25

1

T79

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1010

1

T6

2

T7

1

T25

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

744

1

T6

2

T25

2

T42

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

997

1

T7

1

T50

1

T79

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

754

1

T50

1

T79

1

T15

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

989

1

T6

3

T25

1

T78

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

748

1

T6

3

T25

1

T78

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1016

1

T7

1

T14

1

T25

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

784

1

T14

1

T25

2

T40

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1007

1

T78

2

T15

2

T81

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

745

1

T78

2

T15

2

T81

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1014

1

T6

1

T14

1

T25

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

764

1

T6

1

T14

1

T25

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

978

1

T6

5

T25

3

T42

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

735

1

T6

5

T25

3

T15

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

987

1

T6

2

T14

1

T25

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

718

1

T6

2

T14

1

T25

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1009

1

T6

4

T7

2

T14

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

781

1

T6

4

T14

1

T78

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1048

1

T6

5

T7

1

T25

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

777

1

T6

5

T25

5

T79

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1058

1

T6

1

T7

1

T25

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

812

1

T6

1

T25

2

T79

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

978

1

T25

3

T78

1

T50

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

732

1

T25

3

T78

1

T79

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

980

1

T6

1

T79

1

T15

7

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

743

1

T6

1

T79

1

T15

7

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1079

1

T6

2

T40

1

T79

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

787

1

T6

2

T40

1

T79

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1081

1

T6

1

T25

2

T78

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

830

1

T6

1

T25

2

T78

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1047

1

T25

2

T78

1

T50

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

817

1

T25

2

T78

1

T50

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

977

1

T6

1

T40

1

T79

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

747

1

T6

1

T40

1

T79

4