Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29895 1 T2 2 T3 49 T6 16
auto[1] 28651 1 T2 4 T3 47 T6 14


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29902 1 T2 3 T3 34 T6 14
auto[1] 28644 1 T2 3 T3 62 T6 16


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29016 1 T2 2 T3 50 T6 14
auto[1] 29530 1 T2 4 T3 46 T6 16


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 33298 1 T2 5 T3 80 T6 15
auto[1] 25248 1 T2 1 T3 16 T6 15


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28552 1 T2 5 T3 45 T6 20
auto[1] 29994 1 T2 1 T3 51 T6 10


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29962 1 T2 2 T3 52 T6 14
auto[1] 28584 1 T2 4 T3 44 T6 16


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 1057 1 T6 1 T8 3 T10 3
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 813 1 T6 1 T8 3 T10 3
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 1047 1 T3 2 T8 3 T10 4
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 779 1 T8 3 T13 10 T23 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 1063 1 T3 2 T8 2 T10 5
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 831 1 T3 1 T8 2 T10 4
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1604 1 T3 3 T8 1 T10 3
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1310 1 T8 1 T10 3 T13 23
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 1016 1 T3 3 T6 1 T8 1
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 779 1 T6 1 T8 1 T10 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 972 1 T2 1 T3 3 T8 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 728 1 T2 1 T8 1 T13 11
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 1005 1 T8 2 T10 2 T13 14
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 755 1 T8 2 T10 1 T13 8
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 1004 1 T8 1 T13 22 T23 2
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 761 1 T8 1 T13 13 T23 2
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1071 1 T3 2 T6 2 T8 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 805 1 T3 1 T6 2 T8 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 982 1 T3 2 T8 1 T10 7
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 736 1 T3 1 T8 1 T10 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 1014 1 T3 4 T8 1 T10 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 778 1 T3 2 T8 1 T10 1
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 1029 1 T3 5 T8 1 T10 2
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 765 1 T3 1 T8 1 T10 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 1023 1 T3 4 T8 2 T10 3
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 762 1 T3 1 T8 2 T10 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1033 1 T3 2 T6 2 T10 2
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 755 1 T6 2 T10 2 T13 10
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 1032 1 T3 5 T6 1 T8 4
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 779 1 T6 1 T8 4 T10 2
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 1012 1 T3 5 T6 1 T8 3
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 795 1 T6 1 T8 3 T10 2
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 970 1 T3 1 T10 3 T13 17
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 730 1 T10 1 T13 11 T23 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 988 1 T3 1 T8 4 T10 5
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 749 1 T8 4 T10 3 T13 6
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 1007 1 T3 4 T10 1 T13 14
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 773 1 T10 1 T13 9 T23 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 1060 1 T3 1 T6 2 T8 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 794 1 T6 2 T8 1 T10 2
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 1065 1 T2 1 T3 4 T6 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 804 1 T3 1 T6 1 T10 2
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 1002 1 T3 3 T6 2 T10 3
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 758 1 T6 2 T10 1 T13 9
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 1041 1 T3 2 T8 1 T10 5
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 781 1 T8 1 T10 3 T13 11
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 1054 1 T3 3 T8 3 T10 4
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 802 1 T8 3 T10 2 T13 12
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1051 1 T2 1 T3 3 T8 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 813 1 T3 3 T8 1 T10 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1014 1 T3 2 T6 1 T8 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 743 1 T3 1 T6 1 T8 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1050 1 T3 3 T6 1 T8 2
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 799 1 T3 1 T6 1 T8 2
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 991 1 T2 1 T3 4 T8 1
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 746 1 T3 2 T8 1 T10 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 998 1 T3 2 T8 2 T10 3
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 738 1 T8 2 T10 3 T13 6
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 1001 1 T2 1 T3 2 T10 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 770 1 T3 1 T13 9 T23 3
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 1045 1 T3 1 T8 6 T10 3
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 768 1 T8 6 T10 1 T13 12
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 997 1 T3 2 T8 1 T10 2
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 749 1 T8 1 T10 2 T13 11

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