Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv


Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 64 0 64 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
core_cp 2 0 2 100.00 100 1 1 2
io_cp 2 0 2 100.00 100 1 1 2
main_pd_n_cp 2 0 2 100.00 100 1 1 2
sleep_cp 2 0 2 100.00 100 1 1 2
usb_active_cp 2 0 2 100.00 100 1 1 2
usb_lp_cp 2 0 2 100.00 100 1 1 2


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
control_cross 64 0 64 100.00 100 1 1 0


Summary for Variable core_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for core_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28199 1 T4 2 T5 2 T7 53
auto[1] 27117 1 T5 4 T7 42 T8 668


Summary for Variable io_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for io_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 27975 1 T4 2 T5 1 T7 51
auto[1] 27341 1 T5 5 T7 44 T8 730


Summary for Variable main_pd_n_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for main_pd_n_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 27060 1 T5 3 T7 40 T8 730
auto[1] 28256 1 T4 2 T5 3 T7 55


Summary for Variable sleep_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for sleep_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 31379 1 T4 1 T5 4 T7 60
auto[1] 23937 1 T4 1 T5 2 T7 35


Summary for Variable usb_active_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_active_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 27429 1 T5 1 T7 51 T8 714
auto[1] 27887 1 T4 2 T5 5 T7 44


Summary for Variable usb_lp_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for usb_lp_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 28375 1 T4 2 T7 40 T8 767
auto[1] 26941 1 T5 6 T7 55 T8 675


Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for control_cross

Bins
core_cpio_cpusb_lp_cpusb_active_cpmain_pd_n_cpsleep_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] auto[0] 973 1 T7 1 T8 21 T13 2
auto[0] auto[0] auto[0] auto[0] auto[0] auto[1] 750 1 T7 1 T8 17 T14 3
auto[0] auto[0] auto[0] auto[0] auto[1] auto[0] 970 1 T7 4 T8 19 T13 1
auto[0] auto[0] auto[0] auto[0] auto[1] auto[1] 755 1 T7 2 T8 11 T62 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[0] 992 1 T7 3 T8 26 T37 1
auto[0] auto[0] auto[0] auto[1] auto[0] auto[1] 734 1 T7 2 T8 22 T37 1
auto[0] auto[0] auto[0] auto[1] auto[1] auto[0] 1469 1 T4 1 T7 2 T8 38
auto[0] auto[0] auto[0] auto[1] auto[1] auto[1] 1243 1 T4 1 T7 1 T8 35
auto[0] auto[0] auto[1] auto[0] auto[0] auto[0] 974 1 T5 1 T7 2 T8 29
auto[0] auto[0] auto[1] auto[0] auto[0] auto[1] 732 1 T7 2 T8 25 T37 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[0] 942 1 T7 4 T8 15 T13 1
auto[0] auto[0] auto[1] auto[0] auto[1] auto[1] 729 1 T7 2 T8 11 T13 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[0] 920 1 T8 32 T13 1 T62 1
auto[0] auto[0] auto[1] auto[1] auto[0] auto[1] 708 1 T8 24 T62 1 T14 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[0] 982 1 T7 2 T8 24 T9 1
auto[0] auto[0] auto[1] auto[1] auto[1] auto[1] 737 1 T7 1 T8 19 T9 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[0] 1017 1 T7 2 T8 31 T13 1
auto[0] auto[1] auto[0] auto[0] auto[0] auto[1] 747 1 T8 21 T14 3 T73 1
auto[0] auto[1] auto[0] auto[0] auto[1] auto[0] 970 1 T7 3 T8 33 T13 4
auto[0] auto[1] auto[0] auto[0] auto[1] auto[1] 735 1 T7 2 T8 26 T13 2
auto[0] auto[1] auto[0] auto[1] auto[0] auto[0] 947 1 T7 1 T8 37 T13 1
auto[0] auto[1] auto[0] auto[1] auto[0] auto[1] 705 1 T7 1 T8 24 T14 2
auto[0] auto[1] auto[0] auto[1] auto[1] auto[0] 925 1 T7 1 T8 26 T13 4
auto[0] auto[1] auto[0] auto[1] auto[1] auto[1] 709 1 T8 17 T13 1 T14 3
auto[0] auto[1] auto[1] auto[0] auto[0] auto[0] 999 1 T7 2 T8 27 T9 1
auto[0] auto[1] auto[1] auto[0] auto[0] auto[1] 754 1 T7 1 T8 21 T62 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[0] 1001 1 T7 2 T8 29 T62 1
auto[0] auto[1] auto[1] auto[0] auto[1] auto[1] 751 1 T7 2 T8 24 T62 1
auto[0] auto[1] auto[1] auto[1] auto[0] auto[0] 944 1 T7 2 T8 27 T13 2
auto[0] auto[1] auto[1] auto[1] auto[0] auto[1] 712 1 T7 2 T8 22 T37 1
auto[0] auto[1] auto[1] auto[1] auto[1] auto[0] 966 1 T5 1 T7 2 T8 26
auto[0] auto[1] auto[1] auto[1] auto[1] auto[1] 707 1 T7 1 T8 15 T13 1
auto[1] auto[0] auto[0] auto[0] auto[0] auto[0] 941 1 T7 1 T8 29 T13 5
auto[1] auto[0] auto[0] auto[0] auto[0] auto[1] 710 1 T8 26 T13 1 T14 1
auto[1] auto[0] auto[0] auto[0] auto[1] auto[0] 991 1 T7 1 T8 19 T13 2
auto[1] auto[0] auto[0] auto[0] auto[1] auto[1] 740 1 T8 14 T37 1 T14 3
auto[1] auto[0] auto[0] auto[1] auto[0] auto[0] 918 1 T7 1 T8 29 T13 3
auto[1] auto[0] auto[0] auto[1] auto[0] auto[1] 692 1 T7 1 T8 20 T62 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[0] 903 1 T7 2 T8 25 T62 1
auto[1] auto[0] auto[0] auto[1] auto[1] auto[1] 688 1 T7 1 T8 18 T62 1
auto[1] auto[0] auto[1] auto[0] auto[0] auto[0] 921 1 T7 1 T8 25 T13 3
auto[1] auto[0] auto[1] auto[0] auto[0] auto[1] 705 1 T8 19 T62 1 T37 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[0] 957 1 T7 1 T8 28 T14 1
auto[1] auto[0] auto[1] auto[0] auto[1] auto[1] 749 1 T7 1 T8 20 T38 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[0] 962 1 T7 3 T8 20 T14 2
auto[1] auto[0] auto[1] auto[1] auto[0] auto[1] 732 1 T7 2 T8 13 T14 2
auto[1] auto[0] auto[1] auto[1] auto[1] auto[0] 994 1 T7 4 T8 22 T9 1
auto[1] auto[0] auto[1] auto[1] auto[1] auto[1] 762 1 T7 3 T8 17 T13 2
auto[1] auto[1] auto[0] auto[0] auto[0] auto[0] 1022 1 T7 1 T8 26 T13 1
auto[1] auto[1] auto[0] auto[0] auto[0] auto[1] 786 1 T7 1 T8 20 T13 1
auto[1] auto[1] auto[0] auto[0] auto[1] auto[0] 1050 1 T7 1 T8 30 T13 5
auto[1] auto[1] auto[0] auto[0] auto[1] auto[1] 815 1 T8 20 T13 3 T62 1
auto[1] auto[1] auto[0] auto[1] auto[0] auto[0] 1018 1 T8 24 T13 3 T62 2
auto[1] auto[1] auto[0] auto[1] auto[0] auto[1] 779 1 T8 18 T13 1 T62 2
auto[1] auto[1] auto[0] auto[1] auto[1] auto[0] 967 1 T7 2 T8 26 T13 3
auto[1] auto[1] auto[0] auto[1] auto[1] auto[1] 714 1 T7 2 T8 19 T13 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[0] 893 1 T7 4 T8 19 T13 1
auto[1] auto[1] auto[1] auto[0] auto[0] auto[1] 694 1 T7 3 T8 13 T56 1
auto[1] auto[1] auto[1] auto[0] auto[1] auto[0] 945 1 T7 3 T8 25 T13 4
auto[1] auto[1] auto[1] auto[0] auto[1] auto[1] 711 1 T7 1 T8 21 T13 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[0] 949 1 T5 1 T8 13 T9 1
auto[1] auto[1] auto[1] auto[1] auto[0] auto[1] 730 1 T5 1 T8 10 T9 1
auto[1] auto[1] auto[1] auto[1] auto[1] auto[0] 957 1 T5 1 T7 2 T8 24
auto[1] auto[1] auto[1] auto[1] auto[1] auto[1] 722 1 T5 1 T8 16 T56 1

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