Group : pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg
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Group : pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv



Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
debug_cp 2 0 2 100.00 100 1 1 0
dft_cp 2 0 2 100.00 100 1 1 0
done_cp 2 0 2 100.00 100 1 1 0
good_cp 2 0 2 100.00 100 1 1 0


Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::rom_active_blockers_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
blockers_cross 16 0 16 100.00 100 1 1 0


Summary for Variable debug_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for debug_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 43034 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
off 166038 1 T1 12 T2 1 T3 1
on 21641 1 T1 4 T6 1 T23 87



Summary for Variable dft_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for dft_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 49961 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
off 159842 1 T1 11 T2 1 T3 1
on 20910 1 T1 5 T6 1 T23 1274



Summary for Variable done_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for done_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 182874 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 29678 1 T1 3 T6 3 T7 88
true 18161 1 T1 11 T2 1 T3 1



Summary for Variable good_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for good_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 175397 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false 17650 1 T1 7 T6 5 T7 44
true 37666 1 T1 4 T2 1 T3 1



Summary for Cross blockers_cross

Samples crossed: done_cp good_cp dft_cp debug_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for blockers_cross

Bins
done_cpgood_cpdft_cpdebug_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
false false off off 14880 1 T1 1 T6 1 T7 44
false false off on 89 1 T1 1 T23 1 T131 5
false false on off 193 1 T23 36 T131 1 T145 1
false false on on 101 1 T131 3 T145 3 T143 1
false true off off 12227 1 T6 2 T7 44 T8 280
false true off on 2 1 T163 1 T164 1 - -
false true on off 4 1 T142 1 T165 1 T166 1
false true on on 1 1 T167 1 - - - -
true false off off 51 1 T1 1 T6 2 T138 1
true false off on 19 1 T1 1 T138 1 T141 1
true false on off 19 1 T1 1 T140 1 T141 1
true false on on 69 1 T1 1 T6 1 T138 2
true true off off 12572 1 T1 3 T2 1 T3 1
true true off on 278 1 T23 8 T131 7 T138 1
true true on off 367 1 T1 1 T23 41 T131 4
true true on on 226 1 T23 3 T131 9 T145 6

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