Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29214

1

T3

3

T4

2

T6

3

auto[1]

28164

1

T3

3

T6

3

T11

48

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29342

1

T3

2

T4

2

T6

3

auto[1]

28036

1

T3

4

T6

3

T11

64

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28098

1

T3

1

T6

4

T11

54

auto[1]

29280

1

T3

5

T4

2

T6

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32574

1

T3

6

T4

1

T6

4

auto[1]

24804

1

T4

1

T6

2

T11

50

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28275

1

T3

4

T6

2

T11

44

auto[1]

29103

1

T3

2

T4

2

T6

4

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29278

1

T3

2

T4

2

T6

4

auto[1]

28100

1

T3

4

T6

2

T11

46

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

985

1

T3

1

T13

7

T37

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

736

1

T13

4

T37

1

T38

3

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1022

1

T11

1

T13

9

T14

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

760

1

T11

1

T13

7

T14

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1002

1

T11

3

T13

9

T37

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

780

1

T11

3

T13

5

T37

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1618

1

T4

1

T11

3

T13

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1391

1

T4

1

T11

3

T13

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1044

1

T6

1

T13

5

T14

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

794

1

T13

4

T14

7

T38

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1028

1

T13

7

T14

2

T44

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

759

1

T13

6

T14

1

T38

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1007

1

T11

1

T13

12

T14

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

742

1

T11

1

T13

8

T14

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

970

1

T13

11

T37

1

T14

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

744

1

T13

8

T37

1

T14

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

986

1

T11

2

T13

12

T37

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

743

1

T11

2

T13

11

T37

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

960

1

T11

1

T13

8

T14

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

718

1

T11

1

T13

4

T14

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

987

1

T11

3

T13

8

T37

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

760

1

T11

3

T13

7

T37

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

985

1

T6

1

T11

3

T13

11

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

739

1

T6

1

T11

3

T13

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

979

1

T11

3

T13

9

T14

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

736

1

T11

3

T13

6

T14

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

996

1

T3

1

T13

11

T14

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

732

1

T13

7

T14

1

T86

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

978

1

T11

4

T12

1

T13

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

725

1

T11

4

T12

1

T13

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1032

1

T3

1

T11

2

T13

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

776

1

T11

2

T13

6

T14

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

987

1

T11

4

T13

9

T14

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

777

1

T11

4

T13

7

T14

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1003

1

T3

1

T11

1

T13

9

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

760

1

T11

1

T13

7

T37

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

992

1

T6

1

T11

1

T13

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

732

1

T6

1

T11

1

T13

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

998

1

T11

2

T13

12

T37

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

746

1

T11

2

T13

11

T37

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

985

1

T13

11

T14

3

T38

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

729

1

T13

8

T14

1

T38

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1008

1

T11

1

T13

11

T14

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

772

1

T11

1

T13

8

T14

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

987

1

T11

1

T13

9

T14

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

755

1

T11

1

T13

8

T14

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

987

1

T13

11

T14

5

T38

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

742

1

T13

8

T14

3

T38

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1055

1

T11

1

T13

12

T14

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

800

1

T11

1

T13

9

T14

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1034

1

T13

10

T14

3

T44

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

791

1

T13

6

T14

2

T38

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

981

1

T11

1

T13

12

T14

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

750

1

T11

1

T13

8

T14

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

962

1

T11

1

T13

13

T14

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

738

1

T11

1

T13

11

T14

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1030

1

T6

1

T11

2

T13

14

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

791

1

T11

2

T13

10

T37

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

998

1

T3

1

T11

6

T13

8

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

777

1

T11

6

T13

8

T14

5

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1002

1

T11

1

T13

7

T14

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

761

1

T11

1

T13

3

T14

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

986

1

T3

1

T11

2

T13

12

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

748

1

T11

2

T13

10

T14

1