Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_0_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
reset_cross	6	0	6	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15353

1

T2

5

T5

3

T18

4

auto[1]

23558

1

T2

4

T4

1

T5

5

---

Summary for Variable reset_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for reset_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33001

1

T2

3

T4

1

T5

6

auto[1]

8583

1

T2

6

T4

1

T5

2

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16892

1

T2

9

T4

1

T5

8

auto[1]

24692

1

T4

1

T11

50

T12

1

---

Summary for Cross reset_cross

Samples crossed: reset_cp enable_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for reset_cross

Bins

reset_cp

enable_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

3906

1

T2

1

T5

2

T18

1

auto[0]

auto[0]

auto[1]

8511

1

T11

21

T13

103

T37

7

auto[0]

auto[1]

auto[0]

4116

1

T2

2

T5

4

T18

1

auto[0]

auto[1]

auto[1]

13795

1

T11

29

T13

86

T37

5

auto[1]

auto[0]

auto[0]

2936

1

T2

4

T5

1

T18

3

auto[1]

auto[1]

auto[0]

5647

1

T2

2

T4

1

T5

1

User Defined Cross Bins for reset_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal	0	Illegal