Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30816

1

T2

1

T3

2

T4

11

auto[1]

28756

1

T2

5

T4

7

T7

2

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30639

1

T2

4

T3

2

T4

10

auto[1]

28933

1

T2

2

T4

8

T7

2

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29101

1

T2

5

T4

15

T10

1

auto[1]

30471

1

T2

1

T3

2

T4

3

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33940

1

T2

4

T3

1

T4

18

auto[1]

25632

1

T2

2

T3

1

T5

1

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28988

1

T2

1

T4

11

T10

3

auto[1]

30584

1

T2

5

T3

2

T4

7

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30300

1

T2

3

T3

2

T4

10

auto[1]

29272

1

T2

3

T4

8

T13

48

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1071

1

T4

3

T13

2

T56

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

809

1

T13

2

T56

1

T57

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1086

1

T13

1

T25

1

T26

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

810

1

T13

1

T25

1

T26

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1105

1

T10

1

T13

1

T25

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

844

1

T13

1

T25

4

T83

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1735

1

T3

1

T4

1

T5

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1445

1

T3

1

T5

1

T10

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1058

1

T4

1

T25

2

T43

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

821

1

T25

2

T43

3

T84

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1034

1

T13

3

T25

2

T26

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

776

1

T13

3

T25

2

T26

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1068

1

T4

1

T25

2

T26

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

787

1

T25

2

T26

1

T56

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1000

1

T13

4

T133

2

T44

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

732

1

T13

4

T133

2

T44

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1000

1

T4

1

T47

1

T84

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

726

1

T84

1

T133

1

T22

13

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1008

1

T4

1

T10

1

T25

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

747

1

T10

1

T25

2

T133

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

994

1

T2

1

T13

2

T25

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

749

1

T13

2

T25

1

T56

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1035

1

T13

2

T25

1

T43

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

769

1

T13

2

T25

1

T43

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1094

1

T4

2

T13

1

T25

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

833

1

T13

1

T25

2

T43

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1057

1

T13

2

T25

2

T56

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

812

1

T13

2

T25

2

T56

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1080

1

T4

1

T13

3

T25

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

813

1

T13

3

T25

1

T26

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1081

1

T56

1

T43

4

T84

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

837

1

T56

1

T43

4

T84

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

997

1

T4

1

T13

4

T25

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

755

1

T13

4

T25

3

T43

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

1060

1

T10

1

T13

2

T25

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

811

1

T13

2

T25

2

T26

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1035

1

T2

1

T4

1

T13

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

755

1

T2

1

T13

3

T25

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

987

1

T4

1

T13

1

T25

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

738

1

T13

1

T25

2

T43

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

1016

1

T4

1

T13

1

T25

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

775

1

T13

1

T25

2

T26

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1021

1

T25

4

T26

1

T43

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

772

1

T25

4

T26

1

T43

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

1122

1

T2

1

T13

2

T25

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

842

1

T2

1

T13

2

T25

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

1020

1

T13

4

T25

1

T16

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

752

1

T13

4

T25

1

T133

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1018

1

T13

2

T26

1

T15

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

749

1

T13

2

T26

1

T43

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

1039

1

T13

1

T25

2

T15

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

770

1

T13

1

T25

2

T56

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1017

1

T4

1

T13

2

T15

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

720

1

T13

2

T43

2

T84

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1085

1

T7

1

T13

2

T25

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

831

1

T7

1

T13

2

T25

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

935

1

T4

1

T25

2

T16

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

711

1

T25

2

T83

1

T44

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

1030

1

T2

1

T25

3

T56

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

787

1

T25

3

T56

1

T84

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

1022

1

T4

1

T13

2

T43

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

780

1

T13

2

T43

1

T57

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1030

1

T13

2

T25

2

T43

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

774

1

T13

2

T25

2

T43

4