Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 98.23 96.58 99.44 96.00 96.37 100.00 99.02


Total test records in report: 1105
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T1013 /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.2549724173 Apr 21 12:48:00 PM PDT 24 Apr 21 12:48:01 PM PDT 24 37447508 ps
T115 /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.2867684944 Apr 21 12:47:56 PM PDT 24 Apr 21 12:47:58 PM PDT 24 69028599 ps
T1014 /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.1016048857 Apr 21 12:48:10 PM PDT 24 Apr 21 12:48:11 PM PDT 24 19852627 ps
T1015 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.201963337 Apr 21 12:47:55 PM PDT 24 Apr 21 12:47:57 PM PDT 24 52637011 ps
T1016 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.336061151 Apr 21 12:47:48 PM PDT 24 Apr 21 12:47:51 PM PDT 24 156343201 ps
T1017 /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.1920155588 Apr 21 12:48:01 PM PDT 24 Apr 21 12:48:03 PM PDT 24 50963217 ps
T1018 /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.3389641068 Apr 21 12:48:12 PM PDT 24 Apr 21 12:48:13 PM PDT 24 23654539 ps
T1019 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3809915511 Apr 21 12:47:52 PM PDT 24 Apr 21 12:47:54 PM PDT 24 59377790 ps
T1020 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2462412541 Apr 21 12:47:51 PM PDT 24 Apr 21 12:47:52 PM PDT 24 52219651 ps
T1021 /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.4270471101 Apr 21 12:47:55 PM PDT 24 Apr 21 12:47:57 PM PDT 24 22127774 ps
T1022 /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3970895832 Apr 21 12:48:03 PM PDT 24 Apr 21 12:48:04 PM PDT 24 120949122 ps
T1023 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3840362505 Apr 21 12:47:44 PM PDT 24 Apr 21 12:47:47 PM PDT 24 580361314 ps
T1024 /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.1602149611 Apr 21 12:47:54 PM PDT 24 Apr 21 12:47:56 PM PDT 24 25088488 ps
T1025 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.3633930327 Apr 21 12:47:51 PM PDT 24 Apr 21 12:47:58 PM PDT 24 217332593 ps
T1026 /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.3208752027 Apr 21 12:48:02 PM PDT 24 Apr 21 12:48:03 PM PDT 24 29233359 ps
T1027 /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.1735467436 Apr 21 12:47:44 PM PDT 24 Apr 21 12:47:46 PM PDT 24 134497066 ps
T1028 /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.2750877260 Apr 21 12:47:55 PM PDT 24 Apr 21 12:47:57 PM PDT 24 141715376 ps
T1029 /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.1897058069 Apr 21 12:48:01 PM PDT 24 Apr 21 12:48:02 PM PDT 24 19590556 ps
T1030 /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3416353860 Apr 21 12:47:46 PM PDT 24 Apr 21 12:47:48 PM PDT 24 19660613 ps
T1031 /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2974546415 Apr 21 12:47:49 PM PDT 24 Apr 21 12:47:50 PM PDT 24 27532706 ps
T1032 /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.2732147159 Apr 21 12:47:55 PM PDT 24 Apr 21 12:47:57 PM PDT 24 18026651 ps
T1033 /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3349769041 Apr 21 12:47:42 PM PDT 24 Apr 21 12:47:44 PM PDT 24 76508581 ps
T1034 /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.1491577016 Apr 21 12:47:57 PM PDT 24 Apr 21 12:47:59 PM PDT 24 54513179 ps
T1035 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2252820284 Apr 21 12:47:51 PM PDT 24 Apr 21 12:47:52 PM PDT 24 36642770 ps
T148 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1470025512 Apr 21 12:47:58 PM PDT 24 Apr 21 12:48:01 PM PDT 24 210093401 ps
T1036 /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.1925963345 Apr 21 12:47:57 PM PDT 24 Apr 21 12:47:59 PM PDT 24 147775143 ps
T1037 /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.353759910 Apr 21 12:48:02 PM PDT 24 Apr 21 12:48:03 PM PDT 24 81963901 ps
T1038 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.1318707494 Apr 21 12:47:52 PM PDT 24 Apr 21 12:47:55 PM PDT 24 231866155 ps
T1039 /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.4185476928 Apr 21 12:48:11 PM PDT 24 Apr 21 12:48:13 PM PDT 24 21438212 ps
T116 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1609856202 Apr 21 12:48:00 PM PDT 24 Apr 21 12:48:01 PM PDT 24 55461506 ps
T1040 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1715352531 Apr 21 12:47:47 PM PDT 24 Apr 21 12:47:49 PM PDT 24 672322158 ps
T1041 /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.3097905832 Apr 21 12:48:04 PM PDT 24 Apr 21 12:48:06 PM PDT 24 124486379 ps
T80 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2228424666 Apr 21 12:47:44 PM PDT 24 Apr 21 12:47:47 PM PDT 24 223967675 ps
T1042 /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.3741239577 Apr 21 12:48:08 PM PDT 24 Apr 21 12:48:09 PM PDT 24 34417467 ps
T1043 /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3266887284 Apr 21 12:47:53 PM PDT 24 Apr 21 12:47:55 PM PDT 24 54622664 ps
T1044 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.1716093764 Apr 21 12:47:49 PM PDT 24 Apr 21 12:47:52 PM PDT 24 96219284 ps
T1045 /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2210263149 Apr 21 12:48:17 PM PDT 24 Apr 21 12:48:19 PM PDT 24 189536570 ps
T1046 /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.3111224094 Apr 21 12:48:08 PM PDT 24 Apr 21 12:48:09 PM PDT 24 40543507 ps
T1047 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.3922669873 Apr 21 12:47:51 PM PDT 24 Apr 21 12:47:53 PM PDT 24 292592334 ps
T1048 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.2377791063 Apr 21 12:48:12 PM PDT 24 Apr 21 12:48:13 PM PDT 24 67287678 ps
T1049 /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.3075876651 Apr 21 12:47:55 PM PDT 24 Apr 21 12:47:57 PM PDT 24 48876819 ps
T1050 /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.2047042485 Apr 21 12:47:58 PM PDT 24 Apr 21 12:47:59 PM PDT 24 23889031 ps
T1051 /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.510734708 Apr 21 12:47:44 PM PDT 24 Apr 21 12:47:46 PM PDT 24 149768336 ps
T1052 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.2461609969 Apr 21 12:48:02 PM PDT 24 Apr 21 12:48:03 PM PDT 24 47722792 ps
T1053 /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.348349551 Apr 21 12:47:40 PM PDT 24 Apr 21 12:47:42 PM PDT 24 18255798 ps
T1054 /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.3830159043 Apr 21 12:48:14 PM PDT 24 Apr 21 12:48:16 PM PDT 24 21911847 ps
T117 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2142999764 Apr 21 12:47:55 PM PDT 24 Apr 21 12:47:57 PM PDT 24 53671194 ps
T1055 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.2010995365 Apr 21 12:47:52 PM PDT 24 Apr 21 12:47:54 PM PDT 24 57127697 ps
T1056 /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.526228124 Apr 21 12:47:44 PM PDT 24 Apr 21 12:47:45 PM PDT 24 18842324 ps
T1057 /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.394702318 Apr 21 12:47:55 PM PDT 24 Apr 21 12:47:59 PM PDT 24 90861605 ps
T1058 /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1894895033 Apr 21 12:47:50 PM PDT 24 Apr 21 12:47:51 PM PDT 24 49753418 ps
T1059 /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.717339621 Apr 21 12:47:50 PM PDT 24 Apr 21 12:47:51 PM PDT 24 39186473 ps
T1060 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.2554584123 Apr 21 12:47:51 PM PDT 24 Apr 21 12:47:52 PM PDT 24 32501577 ps
T1061 /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.1821140665 Apr 21 12:47:44 PM PDT 24 Apr 21 12:47:48 PM PDT 24 46650336 ps
T1062 /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1732364299 Apr 21 12:47:44 PM PDT 24 Apr 21 12:47:45 PM PDT 24 18735452 ps
T1063 /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.2533976140 Apr 21 12:47:58 PM PDT 24 Apr 21 12:47:59 PM PDT 24 17698445 ps
T1064 /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.129025928 Apr 21 12:47:49 PM PDT 24 Apr 21 12:47:52 PM PDT 24 137945905 ps
T1065 /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.4153112361 Apr 21 12:48:13 PM PDT 24 Apr 21 12:48:15 PM PDT 24 17821786 ps
T1066 /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2591656457 Apr 21 12:47:50 PM PDT 24 Apr 21 12:47:52 PM PDT 24 132577607 ps
T1067 /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3269852110 Apr 21 12:48:10 PM PDT 24 Apr 21 12:48:11 PM PDT 24 19487884 ps
T147 /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.3320434617 Apr 21 12:47:43 PM PDT 24 Apr 21 12:47:45 PM PDT 24 178249137 ps
T1068 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1480141206 Apr 21 12:48:01 PM PDT 24 Apr 21 12:48:03 PM PDT 24 88542908 ps
T1069 /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.2776397983 Apr 21 12:48:02 PM PDT 24 Apr 21 12:48:04 PM PDT 24 73223495 ps
T1070 /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.1657878562 Apr 21 12:48:10 PM PDT 24 Apr 21 12:48:12 PM PDT 24 340597291 ps
T1071 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.3711821295 Apr 21 12:47:58 PM PDT 24 Apr 21 12:48:00 PM PDT 24 131401558 ps
T1072 /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.29269995 Apr 21 12:48:09 PM PDT 24 Apr 21 12:48:11 PM PDT 24 114077391 ps
T1073 /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.1389152840 Apr 21 12:47:54 PM PDT 24 Apr 21 12:47:56 PM PDT 24 198910595 ps
T1074 /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.231183192 Apr 21 12:47:40 PM PDT 24 Apr 21 12:47:42 PM PDT 24 21901042 ps
T1075 /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.111446520 Apr 21 12:47:53 PM PDT 24 Apr 21 12:47:54 PM PDT 24 26553042 ps
T81 /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.2138355643 Apr 21 12:47:56 PM PDT 24 Apr 21 12:47:59 PM PDT 24 892714932 ps
T1076 /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.3221441639 Apr 21 12:48:09 PM PDT 24 Apr 21 12:48:11 PM PDT 24 57098641 ps
T1077 /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3246324177 Apr 21 12:47:54 PM PDT 24 Apr 21 12:47:55 PM PDT 24 34109988 ps
T1078 /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.1745191925 Apr 21 12:47:47 PM PDT 24 Apr 21 12:47:49 PM PDT 24 92079643 ps
T1079 /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.1542832775 Apr 21 12:47:51 PM PDT 24 Apr 21 12:47:52 PM PDT 24 59807218 ps
T1080 /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3909953851 Apr 21 12:47:57 PM PDT 24 Apr 21 12:48:00 PM PDT 24 283968803 ps
T1081 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2805065244 Apr 21 12:47:57 PM PDT 24 Apr 21 12:47:59 PM PDT 24 60281928 ps
T1082 /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1231837342 Apr 21 12:48:13 PM PDT 24 Apr 21 12:48:15 PM PDT 24 112314718 ps
T1083 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.391663191 Apr 21 12:47:52 PM PDT 24 Apr 21 12:47:54 PM PDT 24 101101429 ps
T1084 /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.2110952297 Apr 21 12:47:44 PM PDT 24 Apr 21 12:47:46 PM PDT 24 24626678 ps
T118 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.975458620 Apr 21 12:47:42 PM PDT 24 Apr 21 12:47:43 PM PDT 24 82938058 ps
T76 /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.1612934994 Apr 21 12:47:50 PM PDT 24 Apr 21 12:47:52 PM PDT 24 103274050 ps
T119 /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.316626046 Apr 21 12:47:56 PM PDT 24 Apr 21 12:47:58 PM PDT 24 21988061 ps
T1085 /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.4045446201 Apr 21 12:47:45 PM PDT 24 Apr 21 12:47:47 PM PDT 24 52651068 ps
T1086 /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.997516885 Apr 21 12:47:54 PM PDT 24 Apr 21 12:47:56 PM PDT 24 48978424 ps
T1087 /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.989435842 Apr 21 12:48:00 PM PDT 24 Apr 21 12:48:02 PM PDT 24 19290902 ps
T1088 /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.2571058149 Apr 21 12:47:53 PM PDT 24 Apr 21 12:47:56 PM PDT 24 461416849 ps
T1089 /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.731453973 Apr 21 12:48:13 PM PDT 24 Apr 21 12:48:14 PM PDT 24 50076323 ps
T1090 /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.556332476 Apr 21 12:47:56 PM PDT 24 Apr 21 12:47:58 PM PDT 24 61704811 ps
T1091 /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1916079121 Apr 21 12:48:06 PM PDT 24 Apr 21 12:48:07 PM PDT 24 19850940 ps
T1092 /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.1478458636 Apr 21 12:47:48 PM PDT 24 Apr 21 12:47:49 PM PDT 24 66395467 ps
T1093 /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.2885993461 Apr 21 12:47:52 PM PDT 24 Apr 21 12:47:55 PM PDT 24 265320127 ps
T1094 /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.1206725084 Apr 21 12:48:12 PM PDT 24 Apr 21 12:48:14 PM PDT 24 39840634 ps
T120 /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.2763207122 Apr 21 12:47:54 PM PDT 24 Apr 21 12:47:56 PM PDT 24 18933339 ps
T1095 /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1875411083 Apr 21 12:48:07 PM PDT 24 Apr 21 12:48:08 PM PDT 24 59068888 ps
T1096 /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.3974941951 Apr 21 12:47:58 PM PDT 24 Apr 21 12:47:59 PM PDT 24 19364517 ps
T1097 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.551814750 Apr 21 12:47:46 PM PDT 24 Apr 21 12:47:48 PM PDT 24 65260290 ps
T1098 /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.572550563 Apr 21 12:47:53 PM PDT 24 Apr 21 12:47:54 PM PDT 24 182433264 ps
T1099 /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1361715823 Apr 21 12:47:50 PM PDT 24 Apr 21 12:47:51 PM PDT 24 20383625 ps
T1100 /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.1021635983 Apr 21 12:47:44 PM PDT 24 Apr 21 12:47:46 PM PDT 24 82472254 ps
T1101 /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1106447781 Apr 21 12:48:12 PM PDT 24 Apr 21 12:48:14 PM PDT 24 57851731 ps
T1102 /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2645125591 Apr 21 12:47:55 PM PDT 24 Apr 21 12:47:57 PM PDT 24 47062652 ps
T1103 /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1641114027 Apr 21 12:47:53 PM PDT 24 Apr 21 12:47:55 PM PDT 24 115743353 ps
T1104 /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.452032627 Apr 21 12:47:49 PM PDT 24 Apr 21 12:47:51 PM PDT 24 108398186 ps
T1105 /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1756025349 Apr 21 12:47:34 PM PDT 24 Apr 21 12:47:36 PM PDT 24 1336175925 ps
T77 /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.2118831249 Apr 21 12:47:53 PM PDT 24 Apr 21 12:47:56 PM PDT 24 200115015 ps


Test location /workspace/coverage/default/31.pwrmgr_aborted_low_power.645210950
Short name T4
Test name
Test status
Simulation time 38437024 ps
CPU time 1.02 seconds
Started Apr 21 04:07:14 PM PDT 24
Finished Apr 21 04:07:15 PM PDT 24
Peak memory 200600 kb
Host smart-b723a92e-a97c-435a-b6f2-4de84b5753f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645210950 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.645210950
Directory /workspace/31.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2405243194
Short name T25
Test name
Test status
Simulation time 816085343 ps
CPU time 3.12 seconds
Started Apr 21 04:08:20 PM PDT 24
Finished Apr 21 04:08:24 PM PDT 24
Peak memory 200844 kb
Host smart-22b587f9-b3f4-4655-afe3-91b383c7df3c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405243194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2405243194
Directory /workspace/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/1.pwrmgr_reset_invalid.590891805
Short name T1
Test name
Test status
Simulation time 100157997 ps
CPU time 1.07 seconds
Started Apr 21 04:05:24 PM PDT 24
Finished Apr 21 04:05:26 PM PDT 24
Peak memory 209120 kb
Host smart-0c3b6b33-be99-4fcb-883e-a746b55ede29
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590891805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.590891805
Directory /workspace/1.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/34.pwrmgr_stress_all_with_rand_reset.1299281219
Short name T22
Test name
Test status
Simulation time 10049450355 ps
CPU time 34.75 seconds
Started Apr 21 04:07:29 PM PDT 24
Finished Apr 21 04:08:04 PM PDT 24
Peak memory 200912 kb
Host smart-2398fc17-f877-483c-af11-efe31276351c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299281219 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all_with_rand_reset.1299281219
Directory /workspace/34.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/3.pwrmgr_sec_cm.126832050
Short name T21
Test name
Test status
Simulation time 471752759 ps
CPU time 1.16 seconds
Started Apr 21 04:05:31 PM PDT 24
Finished Apr 21 04:05:32 PM PDT 24
Peak memory 216528 kb
Host smart-3f4049bb-fe5e-4868-833a-03965dc19410
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126832050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.126832050
Directory /workspace/3.pwrmgr_sec_cm/latest


Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.2372885698
Short name T51
Test name
Test status
Simulation time 233474077 ps
CPU time 1.39 seconds
Started Apr 21 12:47:55 PM PDT 24
Finished Apr 21 12:47:58 PM PDT 24
Peak memory 195236 kb
Host smart-b6996ecf-55d0-4a62-b18a-3c880600a212
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372885698 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err
.2372885698
Directory /workspace/9.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/default/12.pwrmgr_lowpower_invalid.4145016445
Short name T183
Test name
Test status
Simulation time 45069640 ps
CPU time 0.76 seconds
Started Apr 21 04:06:06 PM PDT 24
Finished Apr 21 04:06:07 PM PDT 24
Peak memory 201032 kb
Host smart-d80779e9-7072-4c4a-b133-87a93649ac33
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145016445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_inval
id.4145016445
Directory /workspace/12.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/cover_reg_top/21.pwrmgr_intr_test.634671021
Short name T149
Test name
Test status
Simulation time 21318598 ps
CPU time 0.59 seconds
Started Apr 21 12:48:10 PM PDT 24
Finished Apr 21 12:48:11 PM PDT 24
Peak memory 194912 kb
Host smart-d708edd3-2a13-4750-a33b-b24cbe61d260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634671021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.634671021
Directory /workspace/21.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_rw.1742551793
Short name T113
Test name
Test status
Simulation time 38916041 ps
CPU time 0.72 seconds
Started Apr 21 12:47:59 PM PDT 24
Finished Apr 21 12:48:00 PM PDT 24
Peak memory 197100 kb
Host smart-c291998f-c5cf-495d-8d39-dae945ce1763
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742551793 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.1742551793
Directory /workspace/19.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_errors.2823866389
Short name T50
Test name
Test status
Simulation time 116634281 ps
CPU time 2.17 seconds
Started Apr 21 12:48:01 PM PDT 24
Finished Apr 21 12:48:04 PM PDT 24
Peak memory 196136 kb
Host smart-7182946b-463a-4c0a-a920-ee80f2b66e8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823866389 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.2823866389
Directory /workspace/16.pwrmgr_tl_errors/latest


Test location /workspace/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.2865072825
Short name T165
Test name
Test status
Simulation time 36467555 ps
CPU time 0.61 seconds
Started Apr 21 04:06:08 PM PDT 24
Finished Apr 21 04:06:09 PM PDT 24
Peak memory 197032 kb
Host smart-63846b6d-ab93-4282-9cd9-40bb31302da7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865072825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst
_malfunc.2865072825
Directory /workspace/13.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.4079967256
Short name T59
Test name
Test status
Simulation time 350266973 ps
CPU time 1.26 seconds
Started Apr 21 04:05:14 PM PDT 24
Finished Apr 21 04:05:16 PM PDT 24
Peak memory 200648 kb
Host smart-e1be4991-96f0-4c01-b0b1-f3936b7d85b6
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079967256 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_c
m_ctrl_config_regwen.4079967256
Directory /workspace/0.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/2.pwrmgr_disable_rom_integrity_check.2727661359
Short name T141
Test name
Test status
Simulation time 59877720 ps
CPU time 0.75 seconds
Started Apr 21 04:05:23 PM PDT 24
Finished Apr 21 04:05:24 PM PDT 24
Peak memory 198872 kb
Host smart-7b4dc545-8420-4633-bff0-1568c4c4e87a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727661359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disa
ble_rom_integrity_check.2727661359
Directory /workspace/2.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.449381158
Short name T78
Test name
Test status
Simulation time 103036116 ps
CPU time 1.19 seconds
Started Apr 21 12:47:51 PM PDT 24
Finished Apr 21 12:47:53 PM PDT 24
Peak memory 200008 kb
Host smart-5d2228bf-3890-49a1-944b-b2e9d66776ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449381158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err
.449381158
Directory /workspace/10.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/default/1.pwrmgr_stress_all_with_rand_reset.3643861022
Short name T93
Test name
Test status
Simulation time 4955578157 ps
CPU time 17.36 seconds
Started Apr 21 04:05:23 PM PDT 24
Finished Apr 21 04:05:41 PM PDT 24
Peak memory 201008 kb
Host smart-3d7ff943-8dba-4758-9f24-8f9219b9ca7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643861022 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all_with_rand_reset.3643861022
Directory /workspace/1.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/13.pwrmgr_intr_test.2319288930
Short name T994
Test name
Test status
Simulation time 21567744 ps
CPU time 0.62 seconds
Started Apr 21 12:47:57 PM PDT 24
Finished Apr 21 12:47:58 PM PDT 24
Peak memory 194824 kb
Host smart-e22db179-22e0-4840-ba01-2a25267d32b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319288930 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.2319288930
Directory /workspace/13.pwrmgr_intr_test/latest


Test location /workspace/coverage/default/15.pwrmgr_disable_rom_integrity_check.461779951
Short name T157
Test name
Test status
Simulation time 48787930 ps
CPU time 0.92 seconds
Started Apr 21 04:06:21 PM PDT 24
Finished Apr 21 04:06:22 PM PDT 24
Peak memory 198828 kb
Host smart-05c26ea6-03e4-4921-b1d2-7a3ec5260390
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461779951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_disa
ble_rom_integrity_check.461779951
Directory /workspace/15.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/22.pwrmgr_disable_rom_integrity_check.2007487005
Short name T152
Test name
Test status
Simulation time 86155490 ps
CPU time 0.73 seconds
Started Apr 21 04:06:42 PM PDT 24
Finished Apr 21 04:06:43 PM PDT 24
Peak memory 198344 kb
Host smart-717fbf97-ddd8-4b9f-a419-7ed7f98f16cb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007487005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_dis
able_rom_integrity_check.2007487005
Directory /workspace/22.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/32.pwrmgr_disable_rom_integrity_check.77259122
Short name T156
Test name
Test status
Simulation time 78507520 ps
CPU time 0.72 seconds
Started Apr 21 04:07:26 PM PDT 24
Finished Apr 21 04:07:27 PM PDT 24
Peak memory 198364 kb
Host smart-b47234cf-7839-4e99-80b6-aefce0cab2f8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77259122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_int
egrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_disab
le_rom_integrity_check.77259122
Directory /workspace/32.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_errors.1316585031
Short name T71
Test name
Test status
Simulation time 95554490 ps
CPU time 2.27 seconds
Started Apr 21 12:47:46 PM PDT 24
Finished Apr 21 12:47:49 PM PDT 24
Peak memory 195320 kb
Host smart-cfb12549-28eb-4c15-8c1e-9d4c0095d447
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316585031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.1316585031
Directory /workspace/0.pwrmgr_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.2138355643
Short name T81
Test name
Test status
Simulation time 892714932 ps
CPU time 1.12 seconds
Started Apr 21 12:47:56 PM PDT 24
Finished Apr 21 12:47:59 PM PDT 24
Peak memory 195172 kb
Host smart-154bb663-f609-486e-8085-1dec7e46ccc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138355643 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_er
r.2138355643
Directory /workspace/12.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.2118831249
Short name T77
Test name
Test status
Simulation time 200115015 ps
CPU time 1.7 seconds
Started Apr 21 12:47:53 PM PDT 24
Finished Apr 21 12:47:56 PM PDT 24
Peak memory 200200 kb
Host smart-d5c81634-6670-4d20-a8bb-580efb1382bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118831249 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_er
r.2118831249
Directory /workspace/18.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/default/12.pwrmgr_glitch.1252396679
Short name T200
Test name
Test status
Simulation time 48993161 ps
CPU time 0.62 seconds
Started Apr 21 04:06:04 PM PDT 24
Finished Apr 21 04:06:05 PM PDT 24
Peak memory 197676 kb
Host smart-5ad2bb16-5def-476d-82c1-3eba2609e604
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252396679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.1252396679
Directory /workspace/12.pwrmgr_glitch/latest


Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.1987732849
Short name T110
Test name
Test status
Simulation time 294158231 ps
CPU time 1.08 seconds
Started Apr 21 12:47:45 PM PDT 24
Finished Apr 21 12:47:47 PM PDT 24
Peak memory 194928 kb
Host smart-0863d47d-38b2-4f8c-8d44-600dca4ac9b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987732849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.1
987732849
Directory /workspace/0.pwrmgr_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.510734708
Short name T1051
Test name
Test status
Simulation time 149768336 ps
CPU time 1.68 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:46 PM PDT 24
Peak memory 195108 kb
Host smart-b4759a89-673a-4f25-8e58-d7416043f0af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510734708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.510734708
Directory /workspace/0.pwrmgr_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.1734246284
Short name T114
Test name
Test status
Simulation time 26373217 ps
CPU time 0.66 seconds
Started Apr 21 12:47:43 PM PDT 24
Finished Apr 21 12:47:45 PM PDT 24
Peak memory 194860 kb
Host smart-f105bb0a-ef37-4611-adeb-5c9822796e20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734246284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.1
734246284
Directory /workspace/0.pwrmgr_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2252820284
Short name T1035
Test name
Test status
Simulation time 36642770 ps
CPU time 0.84 seconds
Started Apr 21 12:47:51 PM PDT 24
Finished Apr 21 12:47:52 PM PDT 24
Peak memory 195000 kb
Host smart-3a8d180a-d256-4a07-becd-9c58c87fb046
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252820284 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_with_rand_reset.2252820284
Directory /workspace/0.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/0.pwrmgr_csr_rw.2695083755
Short name T992
Test name
Test status
Simulation time 19701562 ps
CPU time 0.66 seconds
Started Apr 21 12:47:49 PM PDT 24
Finished Apr 21 12:47:50 PM PDT 24
Peak memory 197148 kb
Host smart-6cfb5df0-0972-49b4-aac0-0bd36804308a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695083755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.2695083755
Directory /workspace/0.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/0.pwrmgr_intr_test.526228124
Short name T1056
Test name
Test status
Simulation time 18842324 ps
CPU time 0.69 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:45 PM PDT 24
Peak memory 194912 kb
Host smart-90f83599-e5da-425b-b316-60849d443c27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526228124 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.526228124
Directory /workspace/0.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.1504740763
Short name T996
Test name
Test status
Simulation time 49103261 ps
CPU time 0.74 seconds
Started Apr 21 12:47:38 PM PDT 24
Finished Apr 21 12:47:39 PM PDT 24
Peak memory 197108 kb
Host smart-3eb6143c-e07b-48ec-98bd-3f62bbfe0256
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504740763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sa
me_csr_outstanding.1504740763
Directory /workspace/0.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.3320434617
Short name T147
Test name
Test status
Simulation time 178249137 ps
CPU time 1.08 seconds
Started Apr 21 12:47:43 PM PDT 24
Finished Apr 21 12:47:45 PM PDT 24
Peak memory 194956 kb
Host smart-9e22d116-3c8d-4909-8f54-f8c01731416e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320434617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err
.3320434617
Directory /workspace/0.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1361715823
Short name T1099
Test name
Test status
Simulation time 20383625 ps
CPU time 0.78 seconds
Started Apr 21 12:47:50 PM PDT 24
Finished Apr 21 12:47:51 PM PDT 24
Peak memory 197228 kb
Host smart-e97edade-46bc-4719-8a96-4ef288d07288
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361715823 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.1
361715823
Directory /workspace/1.pwrmgr_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.1760050779
Short name T988
Test name
Test status
Simulation time 76640142 ps
CPU time 2.92 seconds
Started Apr 21 12:47:49 PM PDT 24
Finished Apr 21 12:47:53 PM PDT 24
Peak memory 195068 kb
Host smart-ede52065-7faf-409d-97a2-80056a295e3b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760050779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.1
760050779
Directory /workspace/1.pwrmgr_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.975458620
Short name T118
Test name
Test status
Simulation time 82938058 ps
CPU time 0.61 seconds
Started Apr 21 12:47:42 PM PDT 24
Finished Apr 21 12:47:43 PM PDT 24
Peak memory 194888 kb
Host smart-05c21b34-dc00-496a-a0ae-38078b553978
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975458620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.975458620
Directory /workspace/1.pwrmgr_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.3922669873
Short name T1047
Test name
Test status
Simulation time 292592334 ps
CPU time 0.91 seconds
Started Apr 21 12:47:51 PM PDT 24
Finished Apr 21 12:47:53 PM PDT 24
Peak memory 195044 kb
Host smart-bf6842ad-61ed-4e93-afab-3fcb158c0d96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922669873 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_with_rand_reset.3922669873
Directory /workspace/1.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/1.pwrmgr_csr_rw.2554584123
Short name T1060
Test name
Test status
Simulation time 32501577 ps
CPU time 0.65 seconds
Started Apr 21 12:47:51 PM PDT 24
Finished Apr 21 12:47:52 PM PDT 24
Peak memory 197152 kb
Host smart-097f6645-5ae9-4f2f-ba81-ce3a81742b84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554584123 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.2554584123
Directory /workspace/1.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/1.pwrmgr_intr_test.1542832775
Short name T1079
Test name
Test status
Simulation time 59807218 ps
CPU time 0.6 seconds
Started Apr 21 12:47:51 PM PDT 24
Finished Apr 21 12:47:52 PM PDT 24
Peak memory 194904 kb
Host smart-ee7c9184-0940-4352-b0fe-50bfdf0a6da0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542832775 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.1542832775
Directory /workspace/1.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.1735467436
Short name T1027
Test name
Test status
Simulation time 134497066 ps
CPU time 0.79 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:46 PM PDT 24
Peak memory 198140 kb
Host smart-bf15af7e-0bfb-4310-a5d7-265500613b3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735467436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sa
me_csr_outstanding.1735467436
Directory /workspace/1.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_errors.551814750
Short name T1097
Test name
Test status
Simulation time 65260290 ps
CPU time 1.48 seconds
Started Apr 21 12:47:46 PM PDT 24
Finished Apr 21 12:47:48 PM PDT 24
Peak memory 196240 kb
Host smart-b5b25822-8657-4845-b644-249015a76a8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551814750 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.551814750
Directory /workspace/1.pwrmgr_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1756025349
Short name T1105
Test name
Test status
Simulation time 1336175925 ps
CPU time 1.46 seconds
Started Apr 21 12:47:34 PM PDT 24
Finished Apr 21 12:47:36 PM PDT 24
Peak memory 195132 kb
Host smart-7a948a4b-0d18-48af-a502-3204adce4322
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756025349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err
.1756025349
Directory /workspace/1.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2805065244
Short name T1081
Test name
Test status
Simulation time 60281928 ps
CPU time 0.71 seconds
Started Apr 21 12:47:57 PM PDT 24
Finished Apr 21 12:47:59 PM PDT 24
Peak memory 195044 kb
Host smart-0bcfdff4-dac8-4787-9128-4e3ae95a22d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805065244 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_with_rand_reset.2805065244
Directory /workspace/10.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/10.pwrmgr_csr_rw.572550563
Short name T1098
Test name
Test status
Simulation time 182433264 ps
CPU time 0.65 seconds
Started Apr 21 12:47:53 PM PDT 24
Finished Apr 21 12:47:54 PM PDT 24
Peak memory 197192 kb
Host smart-39d69bed-0324-4e6d-815e-5cf47e4ac504
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572550563 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.572550563
Directory /workspace/10.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/10.pwrmgr_intr_test.1602149611
Short name T1024
Test name
Test status
Simulation time 25088488 ps
CPU time 0.59 seconds
Started Apr 21 12:47:54 PM PDT 24
Finished Apr 21 12:47:56 PM PDT 24
Peak memory 194944 kb
Host smart-acb17a73-7ed3-4c31-8678-cb560571eec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602149611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.1602149611
Directory /workspace/10.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.33444890
Short name T1001
Test name
Test status
Simulation time 115000536 ps
CPU time 0.87 seconds
Started Apr 21 12:48:18 PM PDT 24
Finished Apr 21 12:48:20 PM PDT 24
Peak memory 199392 kb
Host smart-d2c787d8-27b0-4de5-9e6c-8c7061385fec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33444890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sam
e_csr_outstanding.33444890
Directory /workspace/10.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/10.pwrmgr_tl_errors.129025928
Short name T1064
Test name
Test status
Simulation time 137945905 ps
CPU time 2.46 seconds
Started Apr 21 12:47:49 PM PDT 24
Finished Apr 21 12:47:52 PM PDT 24
Peak memory 197560 kb
Host smart-0e9af8ad-ee92-4644-80df-21c2112e31f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129025928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.129025928
Directory /workspace/10.pwrmgr_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1641114027
Short name T1103
Test name
Test status
Simulation time 115743353 ps
CPU time 0.93 seconds
Started Apr 21 12:47:53 PM PDT 24
Finished Apr 21 12:47:55 PM PDT 24
Peak memory 195968 kb
Host smart-479a3ee9-4612-4607-9d71-2ca65b8c1be3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641114027 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_with_rand_reset.1641114027
Directory /workspace/11.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/11.pwrmgr_csr_rw.2461609969
Short name T1052
Test name
Test status
Simulation time 47722792 ps
CPU time 0.63 seconds
Started Apr 21 12:48:02 PM PDT 24
Finished Apr 21 12:48:03 PM PDT 24
Peak memory 194968 kb
Host smart-2c8d5e95-a133-4e3a-9d0a-8fee2c499550
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461609969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.2461609969
Directory /workspace/11.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/11.pwrmgr_intr_test.1732364299
Short name T1062
Test name
Test status
Simulation time 18735452 ps
CPU time 0.63 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:45 PM PDT 24
Peak memory 194904 kb
Host smart-9bf70b3a-38bb-481d-b31b-c7b489ff3bc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732364299 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.1732364299
Directory /workspace/11.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.3269852110
Short name T1067
Test name
Test status
Simulation time 19487884 ps
CPU time 0.71 seconds
Started Apr 21 12:48:10 PM PDT 24
Finished Apr 21 12:48:11 PM PDT 24
Peak memory 197112 kb
Host smart-c3340e55-591e-4116-8144-fbb289b7836e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269852110 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_s
ame_csr_outstanding.3269852110
Directory /workspace/11.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_errors.3097905832
Short name T1041
Test name
Test status
Simulation time 124486379 ps
CPU time 2.28 seconds
Started Apr 21 12:48:04 PM PDT 24
Finished Apr 21 12:48:06 PM PDT 24
Peak memory 196176 kb
Host smart-cf7150ae-565d-4de9-b39a-2966b1a010e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097905832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.3097905832
Directory /workspace/11.pwrmgr_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1470025512
Short name T148
Test name
Test status
Simulation time 210093401 ps
CPU time 1.66 seconds
Started Apr 21 12:47:58 PM PDT 24
Finished Apr 21 12:48:01 PM PDT 24
Peak memory 200220 kb
Host smart-03fa371c-4e00-43da-a950-9b0c7b6845d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470025512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_er
r.1470025512
Directory /workspace/11.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1894895033
Short name T1058
Test name
Test status
Simulation time 49753418 ps
CPU time 0.78 seconds
Started Apr 21 12:47:50 PM PDT 24
Finished Apr 21 12:47:51 PM PDT 24
Peak memory 195100 kb
Host smart-10168454-91cb-4fd3-a903-dba5f54d6f23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894895033 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_with_rand_reset.1894895033
Directory /workspace/12.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/12.pwrmgr_csr_rw.2142999764
Short name T117
Test name
Test status
Simulation time 53671194 ps
CPU time 0.61 seconds
Started Apr 21 12:47:55 PM PDT 24
Finished Apr 21 12:47:57 PM PDT 24
Peak memory 194996 kb
Host smart-b14fba93-b574-44b4-98c9-6fdf6b6d2578
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142999764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.2142999764
Directory /workspace/12.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/12.pwrmgr_intr_test.3246324177
Short name T1077
Test name
Test status
Simulation time 34109988 ps
CPU time 0.59 seconds
Started Apr 21 12:47:54 PM PDT 24
Finished Apr 21 12:47:55 PM PDT 24
Peak memory 194928 kb
Host smart-ae5fa2ec-f3f2-4ab9-80e4-b8ec7680ac04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246324177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.3246324177
Directory /workspace/12.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.4049755548
Short name T124
Test name
Test status
Simulation time 191612116 ps
CPU time 0.7 seconds
Started Apr 21 12:47:53 PM PDT 24
Finished Apr 21 12:47:55 PM PDT 24
Peak memory 197136 kb
Host smart-e3d06912-3d48-499d-a553-6b0f3b8fe145
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049755548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_s
ame_csr_outstanding.4049755548
Directory /workspace/12.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/12.pwrmgr_tl_errors.336061151
Short name T1016
Test name
Test status
Simulation time 156343201 ps
CPU time 2.53 seconds
Started Apr 21 12:47:48 PM PDT 24
Finished Apr 21 12:47:51 PM PDT 24
Peak memory 196224 kb
Host smart-c9960db0-1b09-4dbb-93da-ea9be5146a15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336061151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.336061151
Directory /workspace/12.pwrmgr_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1106447781
Short name T1101
Test name
Test status
Simulation time 57851731 ps
CPU time 0.91 seconds
Started Apr 21 12:48:12 PM PDT 24
Finished Apr 21 12:48:14 PM PDT 24
Peak memory 194948 kb
Host smart-0d028d4e-217e-4363-b9b6-d15e51415080
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106447781 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_with_rand_reset.1106447781
Directory /workspace/13.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/13.pwrmgr_csr_rw.2010995365
Short name T1055
Test name
Test status
Simulation time 57127697 ps
CPU time 0.59 seconds
Started Apr 21 12:47:52 PM PDT 24
Finished Apr 21 12:47:54 PM PDT 24
Peak memory 194872 kb
Host smart-10795b75-73cd-4e34-adc9-0da0813f55be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010995365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.2010995365
Directory /workspace/13.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.109074865
Short name T123
Test name
Test status
Simulation time 49194867 ps
CPU time 0.91 seconds
Started Apr 21 12:47:52 PM PDT 24
Finished Apr 21 12:47:53 PM PDT 24
Peak memory 198368 kb
Host smart-0f534348-bada-4e6c-8a84-938288a38e4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109074865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sa
me_csr_outstanding.109074865
Directory /workspace/13.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_errors.3979582041
Short name T1003
Test name
Test status
Simulation time 227644382 ps
CPU time 1.47 seconds
Started Apr 21 12:47:53 PM PDT 24
Finished Apr 21 12:47:55 PM PDT 24
Peak memory 196184 kb
Host smart-cab42f9d-f966-4fbc-b70b-d906aa2d77ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979582041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.3979582041
Directory /workspace/13.pwrmgr_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3909953851
Short name T1080
Test name
Test status
Simulation time 283968803 ps
CPU time 1.71 seconds
Started Apr 21 12:47:57 PM PDT 24
Finished Apr 21 12:48:00 PM PDT 24
Peak memory 195172 kb
Host smart-e53b45c9-4714-414b-91ec-9172037953cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909953851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_er
r.3909953851
Directory /workspace/13.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.1480141206
Short name T1068
Test name
Test status
Simulation time 88542908 ps
CPU time 1.51 seconds
Started Apr 21 12:48:01 PM PDT 24
Finished Apr 21 12:48:03 PM PDT 24
Peak memory 200480 kb
Host smart-5bdd4acc-2fbd-46ac-b6b3-0ca03158dd8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480141206 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_with_rand_reset.1480141206
Directory /workspace/14.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/14.pwrmgr_csr_rw.2763207122
Short name T120
Test name
Test status
Simulation time 18933339 ps
CPU time 0.68 seconds
Started Apr 21 12:47:54 PM PDT 24
Finished Apr 21 12:47:56 PM PDT 24
Peak memory 197160 kb
Host smart-9b41674c-da01-45c0-9382-ae231deed549
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763207122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.2763207122
Directory /workspace/14.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/14.pwrmgr_intr_test.3075876651
Short name T1049
Test name
Test status
Simulation time 48876819 ps
CPU time 0.65 seconds
Started Apr 21 12:47:55 PM PDT 24
Finished Apr 21 12:47:57 PM PDT 24
Peak memory 194864 kb
Host smart-d034559a-a2d9-4f1a-a0a1-421f3447a141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075876651 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.3075876651
Directory /workspace/14.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.3830159043
Short name T1054
Test name
Test status
Simulation time 21911847 ps
CPU time 0.68 seconds
Started Apr 21 12:48:14 PM PDT 24
Finished Apr 21 12:48:16 PM PDT 24
Peak memory 194904 kb
Host smart-19cb2883-7648-4fb6-9fd7-01b319c05f5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830159043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_s
ame_csr_outstanding.3830159043
Directory /workspace/14.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_errors.1728654039
Short name T1012
Test name
Test status
Simulation time 143942175 ps
CPU time 1.11 seconds
Started Apr 21 12:47:55 PM PDT 24
Finished Apr 21 12:47:57 PM PDT 24
Peak memory 195288 kb
Host smart-4c434195-766b-4795-b9a5-3675e23f468e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728654039 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.1728654039
Directory /workspace/14.pwrmgr_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.828800494
Short name T146
Test name
Test status
Simulation time 193930848 ps
CPU time 1.73 seconds
Started Apr 21 12:48:09 PM PDT 24
Finished Apr 21 12:48:11 PM PDT 24
Peak memory 200472 kb
Host smart-b24c1d28-c9b6-4583-baad-c69232c49a33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828800494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_err
.828800494
Directory /workspace/14.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3585669772
Short name T1007
Test name
Test status
Simulation time 45803290 ps
CPU time 0.75 seconds
Started Apr 21 12:47:59 PM PDT 24
Finished Apr 21 12:48:00 PM PDT 24
Peak memory 195016 kb
Host smart-4dfca4af-8504-43f8-bfd5-2129a25068bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585669772 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_with_rand_reset.3585669772
Directory /workspace/15.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/15.pwrmgr_csr_rw.316626046
Short name T119
Test name
Test status
Simulation time 21988061 ps
CPU time 0.64 seconds
Started Apr 21 12:47:56 PM PDT 24
Finished Apr 21 12:47:58 PM PDT 24
Peak memory 197096 kb
Host smart-c82d6d60-0d54-4f6d-bbc6-362c9447c645
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316626046 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.316626046
Directory /workspace/15.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/15.pwrmgr_intr_test.3585049674
Short name T1000
Test name
Test status
Simulation time 19369832 ps
CPU time 0.59 seconds
Started Apr 21 12:47:49 PM PDT 24
Finished Apr 21 12:47:51 PM PDT 24
Peak memory 194940 kb
Host smart-0baecee7-6f0d-4190-8803-7d93e26fbe44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585049674 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.3585049674
Directory /workspace/15.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.3221441639
Short name T1076
Test name
Test status
Simulation time 57098641 ps
CPU time 0.74 seconds
Started Apr 21 12:48:09 PM PDT 24
Finished Apr 21 12:48:11 PM PDT 24
Peak memory 194840 kb
Host smart-656e903d-c5d7-4d66-8786-00ec4e77e08f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221441639 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_s
ame_csr_outstanding.3221441639
Directory /workspace/15.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_errors.1716093764
Short name T1044
Test name
Test status
Simulation time 96219284 ps
CPU time 1.66 seconds
Started Apr 21 12:47:49 PM PDT 24
Finished Apr 21 12:47:52 PM PDT 24
Peak memory 197212 kb
Host smart-e9989021-7be4-4a77-865b-c32ced06aa07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716093764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.1716093764
Directory /workspace/15.pwrmgr_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.1389152840
Short name T1073
Test name
Test status
Simulation time 198910595 ps
CPU time 1.73 seconds
Started Apr 21 12:47:54 PM PDT 24
Finished Apr 21 12:47:56 PM PDT 24
Peak memory 200408 kb
Host smart-8a6abd5d-f4ec-4851-a659-dc7184620748
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389152840 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_er
r.1389152840
Directory /workspace/15.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.2718330787
Short name T991
Test name
Test status
Simulation time 130039667 ps
CPU time 1.29 seconds
Started Apr 21 12:48:06 PM PDT 24
Finished Apr 21 12:48:07 PM PDT 24
Peak memory 197600 kb
Host smart-b1a1ed81-f6f9-4766-8b8a-8b9bd89c5306
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718330787 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_with_rand_reset.2718330787
Directory /workspace/16.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/16.pwrmgr_csr_rw.1875411083
Short name T1095
Test name
Test status
Simulation time 59068888 ps
CPU time 0.68 seconds
Started Apr 21 12:48:07 PM PDT 24
Finished Apr 21 12:48:08 PM PDT 24
Peak memory 197144 kb
Host smart-cdfb4ffe-138e-4a6a-975e-6ecd62a0718c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875411083 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.1875411083
Directory /workspace/16.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/16.pwrmgr_intr_test.731453973
Short name T1089
Test name
Test status
Simulation time 50076323 ps
CPU time 0.63 seconds
Started Apr 21 12:48:13 PM PDT 24
Finished Apr 21 12:48:14 PM PDT 24
Peak memory 194912 kb
Host smart-a55dc8ec-bb0a-490c-9ddf-0a374b15e76c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731453973 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.731453973
Directory /workspace/16.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1868769553
Short name T121
Test name
Test status
Simulation time 58015805 ps
CPU time 0.82 seconds
Started Apr 21 12:47:57 PM PDT 24
Finished Apr 21 12:47:59 PM PDT 24
Peak memory 198124 kb
Host smart-dc9b07ec-ad04-448b-9ff4-5661c7563ecd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868769553 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_s
ame_csr_outstanding.1868769553
Directory /workspace/16.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2210263149
Short name T1045
Test name
Test status
Simulation time 189536570 ps
CPU time 1.6 seconds
Started Apr 21 12:48:17 PM PDT 24
Finished Apr 21 12:48:19 PM PDT 24
Peak memory 200260 kb
Host smart-a8693527-579e-4760-bfd9-37a29f30f118
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210263149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_er
r.2210263149
Directory /workspace/16.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.3970895832
Short name T1022
Test name
Test status
Simulation time 120949122 ps
CPU time 0.86 seconds
Started Apr 21 12:48:03 PM PDT 24
Finished Apr 21 12:48:04 PM PDT 24
Peak memory 195040 kb
Host smart-75afc70a-e4bd-47fc-9009-86ceedd2a07d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970895832 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_with_rand_reset.3970895832
Directory /workspace/17.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/17.pwrmgr_csr_rw.2857144181
Short name T998
Test name
Test status
Simulation time 20662762 ps
CPU time 0.64 seconds
Started Apr 21 12:47:58 PM PDT 24
Finished Apr 21 12:47:59 PM PDT 24
Peak memory 194948 kb
Host smart-aa0506d1-fb12-45f5-8b91-11e7b46dda13
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857144181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.2857144181
Directory /workspace/17.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/17.pwrmgr_intr_test.1730262546
Short name T73
Test name
Test status
Simulation time 67486514 ps
CPU time 0.61 seconds
Started Apr 21 12:48:05 PM PDT 24
Finished Apr 21 12:48:06 PM PDT 24
Peak memory 194852 kb
Host smart-83f1322a-154a-414e-a73d-58ea4cc52699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730262546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.1730262546
Directory /workspace/17.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.1925963345
Short name T1036
Test name
Test status
Simulation time 147775143 ps
CPU time 0.9 seconds
Started Apr 21 12:47:57 PM PDT 24
Finished Apr 21 12:47:59 PM PDT 24
Peak memory 194840 kb
Host smart-ae96bfab-7822-4b6d-9e76-11f29bbd76b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925963345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_s
ame_csr_outstanding.1925963345
Directory /workspace/17.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_errors.1657878562
Short name T1070
Test name
Test status
Simulation time 340597291 ps
CPU time 1.76 seconds
Started Apr 21 12:48:10 PM PDT 24
Finished Apr 21 12:48:12 PM PDT 24
Peak memory 196308 kb
Host smart-e87db881-c089-4d25-bdea-8bf168c26438
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657878562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.1657878562
Directory /workspace/17.pwrmgr_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.383293037
Short name T1010
Test name
Test status
Simulation time 854328974 ps
CPU time 1.6 seconds
Started Apr 21 12:48:13 PM PDT 24
Finished Apr 21 12:48:16 PM PDT 24
Peak memory 200332 kb
Host smart-353ff31c-65b9-428b-a277-e9fa55f85263
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383293037 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_err
.383293037
Directory /workspace/17.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.29269995
Short name T1072
Test name
Test status
Simulation time 114077391 ps
CPU time 0.95 seconds
Started Apr 21 12:48:09 PM PDT 24
Finished Apr 21 12:48:11 PM PDT 24
Peak memory 194980 kb
Host smart-f0198579-9a90-469a-9a79-6268e2d3638c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29269995 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.pwrmgr_csr_mem_rw_with_rand_reset.29269995
Directory /workspace/18.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/18.pwrmgr_csr_rw.2377791063
Short name T1048
Test name
Test status
Simulation time 67287678 ps
CPU time 0.68 seconds
Started Apr 21 12:48:12 PM PDT 24
Finished Apr 21 12:48:13 PM PDT 24
Peak memory 198128 kb
Host smart-6daeb36a-6e79-4383-9f68-477ac6524d02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377791063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.2377791063
Directory /workspace/18.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/18.pwrmgr_intr_test.3389641068
Short name T1018
Test name
Test status
Simulation time 23654539 ps
CPU time 0.69 seconds
Started Apr 21 12:48:12 PM PDT 24
Finished Apr 21 12:48:13 PM PDT 24
Peak memory 194872 kb
Host smart-9357175e-4db3-40f5-85c3-deaaa48b2a39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389641068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.3389641068
Directory /workspace/18.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.4185476928
Short name T1039
Test name
Test status
Simulation time 21438212 ps
CPU time 0.88 seconds
Started Apr 21 12:48:11 PM PDT 24
Finished Apr 21 12:48:13 PM PDT 24
Peak memory 199592 kb
Host smart-85748ec0-d508-430d-ae5a-2d8723557acf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185476928 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_s
ame_csr_outstanding.4185476928
Directory /workspace/18.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/18.pwrmgr_tl_errors.1318707494
Short name T1038
Test name
Test status
Simulation time 231866155 ps
CPU time 2.14 seconds
Started Apr 21 12:47:52 PM PDT 24
Finished Apr 21 12:47:55 PM PDT 24
Peak memory 196368 kb
Host smart-f58362dc-a8d0-4c19-a45c-7e726f3b3823
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318707494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.1318707494
Directory /workspace/18.pwrmgr_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.1206725084
Short name T1094
Test name
Test status
Simulation time 39840634 ps
CPU time 0.77 seconds
Started Apr 21 12:48:12 PM PDT 24
Finished Apr 21 12:48:14 PM PDT 24
Peak memory 195084 kb
Host smart-949bb5b2-8955-4ee8-8d7c-2fd96754985f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206725084 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_with_rand_reset.1206725084
Directory /workspace/19.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/19.pwrmgr_intr_test.3111224094
Short name T1046
Test name
Test status
Simulation time 40543507 ps
CPU time 0.6 seconds
Started Apr 21 12:48:08 PM PDT 24
Finished Apr 21 12:48:09 PM PDT 24
Peak memory 194908 kb
Host smart-5c9265a9-7deb-4749-ae4e-a7af9e483e87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111224094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.3111224094
Directory /workspace/19.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1231837342
Short name T1082
Test name
Test status
Simulation time 112314718 ps
CPU time 0.82 seconds
Started Apr 21 12:48:13 PM PDT 24
Finished Apr 21 12:48:15 PM PDT 24
Peak memory 194896 kb
Host smart-0b5c52ea-1e28-4532-b26c-44cb62142587
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231837342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_s
ame_csr_outstanding.1231837342
Directory /workspace/19.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_errors.394702318
Short name T1057
Test name
Test status
Simulation time 90861605 ps
CPU time 2.06 seconds
Started Apr 21 12:47:55 PM PDT 24
Finished Apr 21 12:47:59 PM PDT 24
Peak memory 200592 kb
Host smart-e4a2d169-e2a3-41e4-be00-dcab397ef848
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394702318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.394702318
Directory /workspace/19.pwrmgr_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.1425047611
Short name T52
Test name
Test status
Simulation time 241821062 ps
CPU time 1.04 seconds
Started Apr 21 12:48:13 PM PDT 24
Finished Apr 21 12:48:19 PM PDT 24
Peak memory 195012 kb
Host smart-89f2b830-d2d3-4339-a2e4-b024ce335bf2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425047611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_er
r.1425047611
Directory /workspace/19.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.4270471101
Short name T1021
Test name
Test status
Simulation time 22127774 ps
CPU time 0.77 seconds
Started Apr 21 12:47:55 PM PDT 24
Finished Apr 21 12:47:57 PM PDT 24
Peak memory 194944 kb
Host smart-0a2e3771-eb7b-43a9-bdae-eb5ed9aed6ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270471101 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.4
270471101
Directory /workspace/2.pwrmgr_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.2773621481
Short name T1008
Test name
Test status
Simulation time 118422337 ps
CPU time 1.91 seconds
Started Apr 21 12:47:54 PM PDT 24
Finished Apr 21 12:47:57 PM PDT 24
Peak memory 195060 kb
Host smart-620ee349-f796-4c56-ab56-377425ac165d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773621481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.2
773621481
Directory /workspace/2.pwrmgr_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2462412541
Short name T1020
Test name
Test status
Simulation time 52219651 ps
CPU time 0.69 seconds
Started Apr 21 12:47:51 PM PDT 24
Finished Apr 21 12:47:52 PM PDT 24
Peak memory 196136 kb
Host smart-3827df67-4bca-455a-9387-e94cedb120f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462412541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.2
462412541
Directory /workspace/2.pwrmgr_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.201963337
Short name T1015
Test name
Test status
Simulation time 52637011 ps
CPU time 0.75 seconds
Started Apr 21 12:47:55 PM PDT 24
Finished Apr 21 12:47:57 PM PDT 24
Peak memory 195076 kb
Host smart-daac412f-b9d0-4b6d-bfea-bafa19e298b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201963337 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_with_rand_reset.201963337
Directory /workspace/2.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/2.pwrmgr_csr_rw.538140756
Short name T993
Test name
Test status
Simulation time 22010720 ps
CPU time 0.7 seconds
Started Apr 21 12:47:52 PM PDT 24
Finished Apr 21 12:47:54 PM PDT 24
Peak memory 194980 kb
Host smart-d663f3b9-c08b-4141-9452-c696a2ae9b74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538140756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.538140756
Directory /workspace/2.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/2.pwrmgr_intr_test.231183192
Short name T1074
Test name
Test status
Simulation time 21901042 ps
CPU time 0.66 seconds
Started Apr 21 12:47:40 PM PDT 24
Finished Apr 21 12:47:42 PM PDT 24
Peak memory 194896 kb
Host smart-c3d8416a-86d3-43aa-939d-089558c57ae4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231183192 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.231183192
Directory /workspace/2.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.1315044323
Short name T125
Test name
Test status
Simulation time 20357422 ps
CPU time 0.77 seconds
Started Apr 21 12:48:00 PM PDT 24
Finished Apr 21 12:48:01 PM PDT 24
Peak memory 194900 kb
Host smart-948e7f9d-a0cc-48fe-82fc-10e7993c4f83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315044323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sa
me_csr_outstanding.1315044323
Directory /workspace/2.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_errors.1021635983
Short name T1100
Test name
Test status
Simulation time 82472254 ps
CPU time 1.8 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:46 PM PDT 24
Peak memory 196116 kb
Host smart-56535f09-9f4c-4c10-9ff0-13dacf1c1471
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021635983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.1021635983
Directory /workspace/2.pwrmgr_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.3711821295
Short name T1071
Test name
Test status
Simulation time 131401558 ps
CPU time 1.23 seconds
Started Apr 21 12:47:58 PM PDT 24
Finished Apr 21 12:48:00 PM PDT 24
Peak memory 199908 kb
Host smart-aa16ccc5-6129-4328-92d8-4d18c48e6ac5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711821295 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err
.3711821295
Directory /workspace/2.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/20.pwrmgr_intr_test.3480074636
Short name T995
Test name
Test status
Simulation time 19641477 ps
CPU time 0.6 seconds
Started Apr 21 12:48:09 PM PDT 24
Finished Apr 21 12:48:11 PM PDT 24
Peak memory 194928 kb
Host smart-89c7169d-8cf6-4782-bf3c-668ad78bc74d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480074636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.3480074636
Directory /workspace/20.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/22.pwrmgr_intr_test.1491577016
Short name T1034
Test name
Test status
Simulation time 54513179 ps
CPU time 0.66 seconds
Started Apr 21 12:47:57 PM PDT 24
Finished Apr 21 12:47:59 PM PDT 24
Peak memory 194860 kb
Host smart-a94322a9-d480-4fc5-a3b0-b1d172e0445c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491577016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.1491577016
Directory /workspace/22.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/23.pwrmgr_intr_test.3474070285
Short name T987
Test name
Test status
Simulation time 18710077 ps
CPU time 0.61 seconds
Started Apr 21 12:47:59 PM PDT 24
Finished Apr 21 12:48:00 PM PDT 24
Peak memory 194912 kb
Host smart-2933a0df-3b36-44aa-b6eb-d57ff5ba4ef0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474070285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.3474070285
Directory /workspace/23.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/24.pwrmgr_intr_test.989435842
Short name T1087
Test name
Test status
Simulation time 19290902 ps
CPU time 0.62 seconds
Started Apr 21 12:48:00 PM PDT 24
Finished Apr 21 12:48:02 PM PDT 24
Peak memory 194944 kb
Host smart-99a525b1-8d9b-4371-b6bf-0b7148d84e1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989435842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.989435842
Directory /workspace/24.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/25.pwrmgr_intr_test.2932745660
Short name T1005
Test name
Test status
Simulation time 37153580 ps
CPU time 0.6 seconds
Started Apr 21 12:48:09 PM PDT 24
Finished Apr 21 12:48:11 PM PDT 24
Peak memory 194904 kb
Host smart-5ac72b2d-1bbf-4b39-b6bb-349adf3c7acd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932745660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.2932745660
Directory /workspace/25.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/26.pwrmgr_intr_test.2776397983
Short name T1069
Test name
Test status
Simulation time 73223495 ps
CPU time 0.63 seconds
Started Apr 21 12:48:02 PM PDT 24
Finished Apr 21 12:48:04 PM PDT 24
Peak memory 194892 kb
Host smart-68ed8a94-3f15-41ab-a342-59f1d0f24572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776397983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.2776397983
Directory /workspace/26.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/27.pwrmgr_intr_test.2732147159
Short name T1032
Test name
Test status
Simulation time 18026651 ps
CPU time 0.63 seconds
Started Apr 21 12:47:55 PM PDT 24
Finished Apr 21 12:47:57 PM PDT 24
Peak memory 194940 kb
Host smart-c5b9d607-fb88-49ee-b810-0d45131dd2cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732147159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.2732147159
Directory /workspace/27.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/28.pwrmgr_intr_test.556332476
Short name T1090
Test name
Test status
Simulation time 61704811 ps
CPU time 0.61 seconds
Started Apr 21 12:47:56 PM PDT 24
Finished Apr 21 12:47:58 PM PDT 24
Peak memory 194856 kb
Host smart-86c518ba-864e-40ec-8986-4b463e1b5ee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556332476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.556332476
Directory /workspace/28.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/29.pwrmgr_intr_test.1028433496
Short name T983
Test name
Test status
Simulation time 17771636 ps
CPU time 0.68 seconds
Started Apr 21 12:47:54 PM PDT 24
Finished Apr 21 12:47:56 PM PDT 24
Peak memory 194832 kb
Host smart-472b49eb-444a-4e32-9de5-17197aa1b167
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028433496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.1028433496
Directory /workspace/29.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.391663191
Short name T1083
Test name
Test status
Simulation time 101101429 ps
CPU time 1.04 seconds
Started Apr 21 12:47:52 PM PDT 24
Finished Apr 21 12:47:54 PM PDT 24
Peak memory 194720 kb
Host smart-9d7d0f84-f5d1-41ab-a21e-574f9663e527
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391663191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.391663191
Directory /workspace/3.pwrmgr_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.105686227
Short name T64
Test name
Test status
Simulation time 446841108 ps
CPU time 2.02 seconds
Started Apr 21 12:47:48 PM PDT 24
Finished Apr 21 12:47:51 PM PDT 24
Peak memory 195104 kb
Host smart-62a73eed-178c-4dd3-af06-29219f96193d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105686227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.105686227
Directory /workspace/3.pwrmgr_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.3566354448
Short name T111
Test name
Test status
Simulation time 31376574 ps
CPU time 0.64 seconds
Started Apr 21 12:47:50 PM PDT 24
Finished Apr 21 12:47:51 PM PDT 24
Peak memory 194804 kb
Host smart-84e3f6c4-75d6-4d10-a64e-9f640c296fe6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566354448 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.3
566354448
Directory /workspace/3.pwrmgr_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.452032627
Short name T1104
Test name
Test status
Simulation time 108398186 ps
CPU time 1.28 seconds
Started Apr 21 12:47:49 PM PDT 24
Finished Apr 21 12:47:51 PM PDT 24
Peak memory 195264 kb
Host smart-37773887-379a-43a4-a97e-702f2198e961
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452032627 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_with_rand_reset.452032627
Directory /workspace/3.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/3.pwrmgr_csr_rw.3633930327
Short name T1025
Test name
Test status
Simulation time 217332593 ps
CPU time 0.69 seconds
Started Apr 21 12:47:51 PM PDT 24
Finished Apr 21 12:47:58 PM PDT 24
Peak memory 194960 kb
Host smart-9a912e75-45e5-489a-b02c-48fbe71b0841
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633930327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.3633930327
Directory /workspace/3.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/3.pwrmgr_intr_test.348349551
Short name T1053
Test name
Test status
Simulation time 18255798 ps
CPU time 0.66 seconds
Started Apr 21 12:47:40 PM PDT 24
Finished Apr 21 12:47:42 PM PDT 24
Peak memory 194928 kb
Host smart-6aad5e7d-2294-4824-b3d0-c28a740dc972
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348349551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.348349551
Directory /workspace/3.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.4271565410
Short name T75
Test name
Test status
Simulation time 18297687 ps
CPU time 0.71 seconds
Started Apr 21 12:47:42 PM PDT 24
Finished Apr 21 12:47:43 PM PDT 24
Peak memory 197096 kb
Host smart-e2af4737-e972-44c3-9f41-8737f10f5341
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271565410 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sa
me_csr_outstanding.4271565410
Directory /workspace/3.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_errors.3232935236
Short name T69
Test name
Test status
Simulation time 192721638 ps
CPU time 2.06 seconds
Started Apr 21 12:47:52 PM PDT 24
Finished Apr 21 12:47:55 PM PDT 24
Peak memory 195984 kb
Host smart-ac183376-4849-43b4-a207-0bfdb15e7546
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232935236 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.3232935236
Directory /workspace/3.pwrmgr_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.2571058149
Short name T1088
Test name
Test status
Simulation time 461416849 ps
CPU time 1.56 seconds
Started Apr 21 12:47:53 PM PDT 24
Finished Apr 21 12:47:56 PM PDT 24
Peak memory 195272 kb
Host smart-63a95d0e-6564-4a51-a098-f373f6b29c41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571058149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err
.2571058149
Directory /workspace/3.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/30.pwrmgr_intr_test.125104995
Short name T74
Test name
Test status
Simulation time 19445633 ps
CPU time 0.65 seconds
Started Apr 21 12:48:09 PM PDT 24
Finished Apr 21 12:48:11 PM PDT 24
Peak memory 194936 kb
Host smart-5b943f20-ac22-4042-ac6b-e642f74cc26e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125104995 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.125104995
Directory /workspace/30.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/31.pwrmgr_intr_test.2448374704
Short name T985
Test name
Test status
Simulation time 20568861 ps
CPU time 0.66 seconds
Started Apr 21 12:47:57 PM PDT 24
Finished Apr 21 12:47:59 PM PDT 24
Peak memory 194876 kb
Host smart-5aa6695a-6cd1-4a54-93c3-9907ff41872d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448374704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.2448374704
Directory /workspace/31.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/32.pwrmgr_intr_test.1897058069
Short name T1029
Test name
Test status
Simulation time 19590556 ps
CPU time 0.68 seconds
Started Apr 21 12:48:01 PM PDT 24
Finished Apr 21 12:48:02 PM PDT 24
Peak memory 194848 kb
Host smart-08435ed2-e26e-4d81-b6b1-92cfeedf3e82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897058069 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.1897058069
Directory /workspace/32.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/33.pwrmgr_intr_test.3974941951
Short name T1096
Test name
Test status
Simulation time 19364517 ps
CPU time 0.62 seconds
Started Apr 21 12:47:58 PM PDT 24
Finished Apr 21 12:47:59 PM PDT 24
Peak memory 194856 kb
Host smart-549edc2e-780c-48ba-a331-362d5b64d25a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974941951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.3974941951
Directory /workspace/33.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/34.pwrmgr_intr_test.2645125591
Short name T1102
Test name
Test status
Simulation time 47062652 ps
CPU time 0.59 seconds
Started Apr 21 12:47:55 PM PDT 24
Finished Apr 21 12:47:57 PM PDT 24
Peak memory 194888 kb
Host smart-10ce8af8-601a-46d4-b540-e2d72d6d79f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645125591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.2645125591
Directory /workspace/34.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/35.pwrmgr_intr_test.3349738140
Short name T997
Test name
Test status
Simulation time 48489129 ps
CPU time 0.66 seconds
Started Apr 21 12:47:55 PM PDT 24
Finished Apr 21 12:47:57 PM PDT 24
Peak memory 194852 kb
Host smart-da9f7977-6e59-4e02-abed-9b297237683d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349738140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.3349738140
Directory /workspace/35.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/36.pwrmgr_intr_test.543965516
Short name T150
Test name
Test status
Simulation time 45512769 ps
CPU time 0.62 seconds
Started Apr 21 12:47:54 PM PDT 24
Finished Apr 21 12:47:55 PM PDT 24
Peak memory 194924 kb
Host smart-1fa99a8d-2e4f-42d0-9018-3ee0ca9351dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543965516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.543965516
Directory /workspace/36.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/37.pwrmgr_intr_test.2533976140
Short name T1063
Test name
Test status
Simulation time 17698445 ps
CPU time 0.62 seconds
Started Apr 21 12:47:58 PM PDT 24
Finished Apr 21 12:47:59 PM PDT 24
Peak memory 194936 kb
Host smart-1fe0b5ad-4e4a-4b1b-8bf8-be34837c74a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533976140 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.2533976140
Directory /workspace/37.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/38.pwrmgr_intr_test.3208752027
Short name T1026
Test name
Test status
Simulation time 29233359 ps
CPU time 0.62 seconds
Started Apr 21 12:48:02 PM PDT 24
Finished Apr 21 12:48:03 PM PDT 24
Peak memory 194936 kb
Host smart-13af35b5-06b8-43b1-9a88-8e2738536b7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208752027 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.3208752027
Directory /workspace/38.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/39.pwrmgr_intr_test.946477980
Short name T1006
Test name
Test status
Simulation time 27031562 ps
CPU time 0.6 seconds
Started Apr 21 12:48:07 PM PDT 24
Finished Apr 21 12:48:08 PM PDT 24
Peak memory 194896 kb
Host smart-e88d717b-1334-4d58-86fd-e85260082136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946477980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.946477980
Directory /workspace/39.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1715352531
Short name T1040
Test name
Test status
Simulation time 672322158 ps
CPU time 0.99 seconds
Started Apr 21 12:47:47 PM PDT 24
Finished Apr 21 12:47:49 PM PDT 24
Peak memory 194908 kb
Host smart-87f6be08-0319-48a1-b4c6-45d046f1748d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715352531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.1
715352531
Directory /workspace/4.pwrmgr_csr_aliasing/latest


Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.2885993461
Short name T1093
Test name
Test status
Simulation time 265320127 ps
CPU time 2.9 seconds
Started Apr 21 12:47:52 PM PDT 24
Finished Apr 21 12:47:55 PM PDT 24
Peak memory 195100 kb
Host smart-deec9109-e3e5-407f-acfd-5d1c8a0a4e6c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885993461 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.2
885993461
Directory /workspace/4.pwrmgr_csr_bit_bash/latest


Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.3157501857
Short name T999
Test name
Test status
Simulation time 75273692 ps
CPU time 0.71 seconds
Started Apr 21 12:47:58 PM PDT 24
Finished Apr 21 12:47:59 PM PDT 24
Peak memory 197532 kb
Host smart-8e437b31-4b45-49de-aa56-04995a73b413
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157501857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.3
157501857
Directory /workspace/4.pwrmgr_csr_hw_reset/latest


Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3809915511
Short name T1019
Test name
Test status
Simulation time 59377790 ps
CPU time 0.74 seconds
Started Apr 21 12:47:52 PM PDT 24
Finished Apr 21 12:47:54 PM PDT 24
Peak memory 195072 kb
Host smart-662e978b-80cb-4be6-a915-30568cdcdc23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809915511 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_with_rand_reset.3809915511
Directory /workspace/4.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/4.pwrmgr_csr_rw.907523619
Short name T112
Test name
Test status
Simulation time 62094404 ps
CPU time 0.66 seconds
Started Apr 21 12:47:47 PM PDT 24
Finished Apr 21 12:47:48 PM PDT 24
Peak memory 197076 kb
Host smart-666263f1-215b-4d4b-8353-bb0480e9b148
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907523619 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.907523619
Directory /workspace/4.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/4.pwrmgr_intr_test.4045446201
Short name T1085
Test name
Test status
Simulation time 52651068 ps
CPU time 0.66 seconds
Started Apr 21 12:47:45 PM PDT 24
Finished Apr 21 12:47:47 PM PDT 24
Peak memory 194916 kb
Host smart-9d309b18-53b3-4c9e-906c-3ad27f70f13b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045446201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.4045446201
Directory /workspace/4.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3416353860
Short name T1030
Test name
Test status
Simulation time 19660613 ps
CPU time 0.73 seconds
Started Apr 21 12:47:46 PM PDT 24
Finished Apr 21 12:47:48 PM PDT 24
Peak memory 197104 kb
Host smart-831bdc38-45b5-4cdd-9ec0-74f65630fe8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416353860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sa
me_csr_outstanding.3416353860
Directory /workspace/4.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_errors.2559896487
Short name T67
Test name
Test status
Simulation time 78251101 ps
CPU time 1.96 seconds
Started Apr 21 12:47:54 PM PDT 24
Finished Apr 21 12:47:58 PM PDT 24
Peak memory 196300 kb
Host smart-1d951bbc-cca9-4600-9588-3dbb448e82c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559896487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.2559896487
Directory /workspace/4.pwrmgr_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.2591656457
Short name T1066
Test name
Test status
Simulation time 132577607 ps
CPU time 1.07 seconds
Started Apr 21 12:47:50 PM PDT 24
Finished Apr 21 12:47:52 PM PDT 24
Peak memory 200152 kb
Host smart-86ffc550-aaae-464f-85fc-df790c047470
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591656457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err
.2591656457
Directory /workspace/4.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/40.pwrmgr_intr_test.2549724173
Short name T1013
Test name
Test status
Simulation time 37447508 ps
CPU time 0.59 seconds
Started Apr 21 12:48:00 PM PDT 24
Finished Apr 21 12:48:01 PM PDT 24
Peak memory 194944 kb
Host smart-71c0176c-9533-42da-8070-4880997872d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549724173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.2549724173
Directory /workspace/40.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/41.pwrmgr_intr_test.1016048857
Short name T1014
Test name
Test status
Simulation time 19852627 ps
CPU time 0.62 seconds
Started Apr 21 12:48:10 PM PDT 24
Finished Apr 21 12:48:11 PM PDT 24
Peak memory 194820 kb
Host smart-6ae206ab-6afe-4c5e-a6fc-91ade8aefdd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016048857 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.1016048857
Directory /workspace/41.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/42.pwrmgr_intr_test.3741239577
Short name T1042
Test name
Test status
Simulation time 34417467 ps
CPU time 0.62 seconds
Started Apr 21 12:48:08 PM PDT 24
Finished Apr 21 12:48:09 PM PDT 24
Peak memory 194880 kb
Host smart-438b4a80-3f3f-4bc1-b92a-203c26e8de7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741239577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.3741239577
Directory /workspace/42.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/43.pwrmgr_intr_test.111446520
Short name T1075
Test name
Test status
Simulation time 26553042 ps
CPU time 0.61 seconds
Started Apr 21 12:47:53 PM PDT 24
Finished Apr 21 12:47:54 PM PDT 24
Peak memory 194752 kb
Host smart-71ae104a-7a0c-4375-b2e5-5af491a6222b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111446520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.111446520
Directory /workspace/43.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/44.pwrmgr_intr_test.353759910
Short name T1037
Test name
Test status
Simulation time 81963901 ps
CPU time 0.6 seconds
Started Apr 21 12:48:02 PM PDT 24
Finished Apr 21 12:48:03 PM PDT 24
Peak memory 194844 kb
Host smart-daceac14-a8a9-41d7-8f76-63afadcb20e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353759910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.353759910
Directory /workspace/44.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/45.pwrmgr_intr_test.3375578719
Short name T72
Test name
Test status
Simulation time 23439707 ps
CPU time 0.65 seconds
Started Apr 21 12:48:12 PM PDT 24
Finished Apr 21 12:48:13 PM PDT 24
Peak memory 194940 kb
Host smart-c4616372-e9e5-4458-a0be-7722dc93d8dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375578719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.3375578719
Directory /workspace/45.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/46.pwrmgr_intr_test.1920155588
Short name T1017
Test name
Test status
Simulation time 50963217 ps
CPU time 0.68 seconds
Started Apr 21 12:48:01 PM PDT 24
Finished Apr 21 12:48:03 PM PDT 24
Peak memory 194856 kb
Host smart-6c0c6a9a-9d01-4a6c-8b81-9866237b7f46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920155588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.1920155588
Directory /workspace/46.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/47.pwrmgr_intr_test.1916079121
Short name T1091
Test name
Test status
Simulation time 19850940 ps
CPU time 0.63 seconds
Started Apr 21 12:48:06 PM PDT 24
Finished Apr 21 12:48:07 PM PDT 24
Peak memory 194856 kb
Host smart-d1f26407-f9ff-4de0-985d-41b40510a77b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916079121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.1916079121
Directory /workspace/47.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/48.pwrmgr_intr_test.4153112361
Short name T1065
Test name
Test status
Simulation time 17821786 ps
CPU time 0.61 seconds
Started Apr 21 12:48:13 PM PDT 24
Finished Apr 21 12:48:15 PM PDT 24
Peak memory 194936 kb
Host smart-c33f6235-b16b-4789-b663-e38daef083de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153112361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.4153112361
Directory /workspace/48.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/49.pwrmgr_intr_test.3211564252
Short name T1002
Test name
Test status
Simulation time 26633922 ps
CPU time 0.59 seconds
Started Apr 21 12:48:12 PM PDT 24
Finished Apr 21 12:48:14 PM PDT 24
Peak memory 194904 kb
Host smart-feacc504-9c62-445c-a9a5-ce3c8e02ca5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211564252 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.3211564252
Directory /workspace/49.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3349769041
Short name T1033
Test name
Test status
Simulation time 76508581 ps
CPU time 1 seconds
Started Apr 21 12:47:42 PM PDT 24
Finished Apr 21 12:47:44 PM PDT 24
Peak memory 195000 kb
Host smart-a67abcc8-c910-4956-8460-af4787070511
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349769041 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_with_rand_reset.3349769041
Directory /workspace/5.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/5.pwrmgr_csr_rw.46511617
Short name T986
Test name
Test status
Simulation time 47714614 ps
CPU time 0.7 seconds
Started Apr 21 12:47:48 PM PDT 24
Finished Apr 21 12:47:49 PM PDT 24
Peak memory 197132 kb
Host smart-89ffc6bc-2bf2-4e70-9742-d49be9d9dda6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46511617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.46511617
Directory /workspace/5.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/5.pwrmgr_intr_test.2110952297
Short name T1084
Test name
Test status
Simulation time 24626678 ps
CPU time 0.59 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:46 PM PDT 24
Peak memory 194932 kb
Host smart-6ad3274e-c87f-4879-9b7e-cfb467debaed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110952297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.2110952297
Directory /workspace/5.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2440250817
Short name T62
Test name
Test status
Simulation time 25144190 ps
CPU time 0.71 seconds
Started Apr 21 12:47:48 PM PDT 24
Finished Apr 21 12:47:50 PM PDT 24
Peak memory 194908 kb
Host smart-f99961e7-b252-4559-9007-58dc81a8a4e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440250817 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sa
me_csr_outstanding.2440250817
Directory /workspace/5.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_errors.1821140665
Short name T1061
Test name
Test status
Simulation time 46650336 ps
CPU time 2.08 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:48 PM PDT 24
Peak memory 196064 kb
Host smart-623ac576-22fe-442a-add7-273404b4a7d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821140665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.1821140665
Directory /workspace/5.pwrmgr_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3840362505
Short name T1023
Test name
Test status
Simulation time 580361314 ps
CPU time 1.54 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:47 PM PDT 24
Peak memory 200524 kb
Host smart-f75d9110-163e-4f04-8d51-8295d5d66154
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840362505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err
.3840362505
Directory /workspace/5.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.1478458636
Short name T1092
Test name
Test status
Simulation time 66395467 ps
CPU time 0.7 seconds
Started Apr 21 12:47:48 PM PDT 24
Finished Apr 21 12:47:49 PM PDT 24
Peak memory 195036 kb
Host smart-9ba10bbe-8a2e-4728-83e9-cf6e62eba287
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478458636 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_with_rand_reset.1478458636
Directory /workspace/6.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/6.pwrmgr_csr_rw.1609856202
Short name T116
Test name
Test status
Simulation time 55461506 ps
CPU time 0.72 seconds
Started Apr 21 12:48:00 PM PDT 24
Finished Apr 21 12:48:01 PM PDT 24
Peak memory 194940 kb
Host smart-b859602a-cfcf-41d3-a699-2b9cae27fbf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609856202 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.1609856202
Directory /workspace/6.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/6.pwrmgr_intr_test.997516885
Short name T1086
Test name
Test status
Simulation time 48978424 ps
CPU time 0.61 seconds
Started Apr 21 12:47:54 PM PDT 24
Finished Apr 21 12:47:56 PM PDT 24
Peak memory 194932 kb
Host smart-74057ad4-69fd-421f-8514-ade6b7798033
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997516885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.997516885
Directory /workspace/6.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2974546415
Short name T1031
Test name
Test status
Simulation time 27532706 ps
CPU time 0.76 seconds
Started Apr 21 12:47:49 PM PDT 24
Finished Apr 21 12:47:50 PM PDT 24
Peak memory 197092 kb
Host smart-3ebdeaeb-40eb-4ea3-b82a-237f868511a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974546415 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sa
me_csr_outstanding.2974546415
Directory /workspace/6.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_errors.1745191925
Short name T1078
Test name
Test status
Simulation time 92079643 ps
CPU time 1.21 seconds
Started Apr 21 12:47:47 PM PDT 24
Finished Apr 21 12:47:49 PM PDT 24
Peak memory 196112 kb
Host smart-aeca7818-6f2d-49cd-8e6d-de03eb4e369b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745191925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.1745191925
Directory /workspace/6.pwrmgr_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2228424666
Short name T80
Test name
Test status
Simulation time 223967675 ps
CPU time 1.07 seconds
Started Apr 21 12:47:44 PM PDT 24
Finished Apr 21 12:47:47 PM PDT 24
Peak memory 200200 kb
Host smart-e6e4bdf9-46c8-468a-943c-317853f74b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228424666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err
.2228424666
Directory /workspace/6.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.1338516911
Short name T63
Test name
Test status
Simulation time 54832683 ps
CPU time 0.83 seconds
Started Apr 21 12:47:55 PM PDT 24
Finished Apr 21 12:47:57 PM PDT 24
Peak memory 195028 kb
Host smart-2d1668b8-6446-4e7c-a6d4-17de5ef642f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338516911 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_with_rand_reset.1338516911
Directory /workspace/7.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/7.pwrmgr_csr_rw.3477209899
Short name T122
Test name
Test status
Simulation time 21156459 ps
CPU time 0.66 seconds
Started Apr 21 12:47:55 PM PDT 24
Finished Apr 21 12:47:57 PM PDT 24
Peak memory 197152 kb
Host smart-ec4516e3-5ff5-4323-b394-793a737009dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477209899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.3477209899
Directory /workspace/7.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/7.pwrmgr_intr_test.1100827907
Short name T1004
Test name
Test status
Simulation time 40055342 ps
CPU time 0.59 seconds
Started Apr 21 12:47:47 PM PDT 24
Finished Apr 21 12:47:48 PM PDT 24
Peak memory 194828 kb
Host smart-01a97f40-2625-4f92-952d-386edbcb89a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100827907 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.1100827907
Directory /workspace/7.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.2750877260
Short name T1028
Test name
Test status
Simulation time 141715376 ps
CPU time 0.87 seconds
Started Apr 21 12:47:55 PM PDT 24
Finished Apr 21 12:47:57 PM PDT 24
Peak memory 198320 kb
Host smart-a4c78693-48ca-4d4e-9140-9b3f0975e777
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750877260 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwr
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sa
me_csr_outstanding.2750877260
Directory /workspace/7.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_errors.3796005217
Short name T68
Test name
Test status
Simulation time 162025060 ps
CPU time 2.07 seconds
Started Apr 21 12:47:56 PM PDT 24
Finished Apr 21 12:47:59 PM PDT 24
Peak memory 196256 kb
Host smart-0876616f-e616-4f65-a053-41433ff10354
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796005217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.3796005217
Directory /workspace/7.pwrmgr_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.1612934994
Short name T76
Test name
Test status
Simulation time 103274050 ps
CPU time 1.17 seconds
Started Apr 21 12:47:50 PM PDT 24
Finished Apr 21 12:47:52 PM PDT 24
Peak memory 200168 kb
Host smart-fe172247-0933-4854-ac5f-8b4cd072a451
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612934994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err
.1612934994
Directory /workspace/7.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2243777245
Short name T1009
Test name
Test status
Simulation time 72898080 ps
CPU time 1.14 seconds
Started Apr 21 12:47:41 PM PDT 24
Finished Apr 21 12:47:43 PM PDT 24
Peak memory 197384 kb
Host smart-f41aa0c2-f2fd-4cf1-84a8-3300f4bc2dfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243777245 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_with_rand_reset.2243777245
Directory /workspace/8.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/8.pwrmgr_csr_rw.2867684944
Short name T115
Test name
Test status
Simulation time 69028599 ps
CPU time 0.64 seconds
Started Apr 21 12:47:56 PM PDT 24
Finished Apr 21 12:47:58 PM PDT 24
Peak memory 197044 kb
Host smart-577b8f3c-3562-4726-a721-370e08321432
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867684944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.2867684944
Directory /workspace/8.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/8.pwrmgr_intr_test.1580040056
Short name T984
Test name
Test status
Simulation time 47756995 ps
CPU time 0.62 seconds
Started Apr 21 12:47:47 PM PDT 24
Finished Apr 21 12:47:48 PM PDT 24
Peak memory 194872 kb
Host smart-6c586b87-3d97-48ce-aefe-1b8299dde17f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580040056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.1580040056
Directory /workspace/8.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.717339621
Short name T1059
Test name
Test status
Simulation time 39186473 ps
CPU time 0.92 seconds
Started Apr 21 12:47:50 PM PDT 24
Finished Apr 21 12:47:51 PM PDT 24
Peak memory 198240 kb
Host smart-f52a0db2-9253-433a-a424-2fd9945d5a86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717339621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sam
e_csr_outstanding.717339621
Directory /workspace/8.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_errors.3623401010
Short name T1011
Test name
Test status
Simulation time 86545602 ps
CPU time 1.9 seconds
Started Apr 21 12:47:53 PM PDT 24
Finished Apr 21 12:47:56 PM PDT 24
Peak memory 196224 kb
Host smart-187eef50-f6e8-419c-a3d6-69d46ce11bdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623401010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.3623401010
Directory /workspace/8.pwrmgr_tl_errors/latest


Test location /workspace/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.4125065648
Short name T55
Test name
Test status
Simulation time 213564598 ps
CPU time 1.64 seconds
Started Apr 21 12:47:43 PM PDT 24
Finished Apr 21 12:47:45 PM PDT 24
Peak memory 200404 kb
Host smart-cab0518e-4cd8-4d7e-96c6-adcd200f4d8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125065648 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err
.4125065648
Directory /workspace/8.pwrmgr_tl_intg_err/latest


Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.3266887284
Short name T1043
Test name
Test status
Simulation time 54622664 ps
CPU time 0.69 seconds
Started Apr 21 12:47:53 PM PDT 24
Finished Apr 21 12:47:55 PM PDT 24
Peak memory 195020 kb
Host smart-b667d830-3fec-409d-9b75-d71494671356
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266887284 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_with_rand_reset.3266887284
Directory /workspace/9.pwrmgr_csr_mem_rw_with_rand_reset/latest


Test location /workspace/coverage/cover_reg_top/9.pwrmgr_csr_rw.2820944882
Short name T65
Test name
Test status
Simulation time 42386002 ps
CPU time 0.66 seconds
Started Apr 21 12:47:50 PM PDT 24
Finished Apr 21 12:47:52 PM PDT 24
Peak memory 197604 kb
Host smart-0d23bf1b-172b-4355-9dad-7d0c198d9f88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820944882 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.2820944882
Directory /workspace/9.pwrmgr_csr_rw/latest


Test location /workspace/coverage/cover_reg_top/9.pwrmgr_intr_test.2047042485
Short name T1050
Test name
Test status
Simulation time 23889031 ps
CPU time 0.6 seconds
Started Apr 21 12:47:58 PM PDT 24
Finished Apr 21 12:47:59 PM PDT 24
Peak memory 194924 kb
Host smart-18553533-9b52-46a9-b512-d6acfc8dedd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047042485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.2047042485
Directory /workspace/9.pwrmgr_intr_test/latest


Test location /workspace/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.749441277
Short name T990
Test name
Test status
Simulation time 40885140 ps
CPU time 0.85 seconds
Started Apr 21 12:47:56 PM PDT 24
Finished Apr 21 12:47:58 PM PDT 24
Peak memory 198244 kb
Host smart-fc00b243-6e3e-4fd7-aa0b-faf08f272dfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749441277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sam
e_csr_outstanding.749441277
Directory /workspace/9.pwrmgr_same_csr_outstanding/latest


Test location /workspace/coverage/cover_reg_top/9.pwrmgr_tl_errors.1070176635
Short name T989
Test name
Test status
Simulation time 43641739 ps
CPU time 1.92 seconds
Started Apr 21 12:47:49 PM PDT 24
Finished Apr 21 12:47:51 PM PDT 24
Peak memory 197348 kb
Host smart-305582b7-ce2c-4fd5-9e46-7677a1b6e6c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070176635 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.1070176635
Directory /workspace/9.pwrmgr_tl_errors/latest


Test location /workspace/coverage/default/0.pwrmgr_aborted_low_power.2809925048
Short name T952
Test name
Test status
Simulation time 22292581 ps
CPU time 0.72 seconds
Started Apr 21 04:05:12 PM PDT 24
Finished Apr 21 04:05:13 PM PDT 24
Peak memory 198804 kb
Host smart-7db11ce8-3ad4-4f08-89da-fc20ddd5e437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809925048 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.2809925048
Directory /workspace/0.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/0.pwrmgr_disable_rom_integrity_check.258245516
Short name T847
Test name
Test status
Simulation time 61033254 ps
CPU time 0.87 seconds
Started Apr 21 04:05:21 PM PDT 24
Finished Apr 21 04:05:22 PM PDT 24
Peak memory 198808 kb
Host smart-3d231233-c60f-4814-a549-02600f15b3d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258245516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disab
le_rom_integrity_check.258245516
Directory /workspace/0.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.1721286291
Short name T767
Test name
Test status
Simulation time 40108803 ps
CPU time 0.62 seconds
Started Apr 21 04:05:14 PM PDT 24
Finished Apr 21 04:05:15 PM PDT 24
Peak memory 197640 kb
Host smart-5b9ebfbd-f758-4637-a389-756531162c3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721286291 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_
malfunc.1721286291
Directory /workspace/0.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/0.pwrmgr_escalation_timeout.1687204271
Short name T264
Test name
Test status
Simulation time 165113316 ps
CPU time 1.05 seconds
Started Apr 21 04:05:17 PM PDT 24
Finished Apr 21 04:05:19 PM PDT 24
Peak memory 197764 kb
Host smart-74537567-2c05-4a15-a172-8aaece39bc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687204271 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.1687204271
Directory /workspace/0.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/0.pwrmgr_glitch.3510420659
Short name T543
Test name
Test status
Simulation time 92135856 ps
CPU time 0.65 seconds
Started Apr 21 04:05:16 PM PDT 24
Finished Apr 21 04:05:17 PM PDT 24
Peak memory 197036 kb
Host smart-db68791a-3564-4f79-b60f-d71453dd8957
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510420659 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.3510420659
Directory /workspace/0.pwrmgr_glitch/latest


Test location /workspace/coverage/default/0.pwrmgr_global_esc.122965934
Short name T285
Test name
Test status
Simulation time 54953950 ps
CPU time 0.62 seconds
Started Apr 21 04:05:18 PM PDT 24
Finished Apr 21 04:05:19 PM PDT 24
Peak memory 197800 kb
Host smart-9d8dbcf4-2f84-48bc-b64a-f6c8be2ce19f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122965934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.122965934
Directory /workspace/0.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/0.pwrmgr_lowpower_invalid.524823164
Short name T617
Test name
Test status
Simulation time 39399691 ps
CPU time 0.78 seconds
Started Apr 21 04:05:21 PM PDT 24
Finished Apr 21 04:05:22 PM PDT 24
Peak memory 201060 kb
Host smart-2ac8d2b8-5373-4c97-a2a2-435f78eca296
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524823164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invalid
.524823164
Directory /workspace/0.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/0.pwrmgr_lowpower_wakeup_race.1747435348
Short name T334
Test name
Test status
Simulation time 185404521 ps
CPU time 1.09 seconds
Started Apr 21 04:05:12 PM PDT 24
Finished Apr 21 04:05:13 PM PDT 24
Peak memory 198108 kb
Host smart-a742b54a-40f9-4d00-8768-345621c4ee47
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747435348 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wa
keup_race.1747435348
Directory /workspace/0.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/0.pwrmgr_reset.3392808866
Short name T523
Test name
Test status
Simulation time 378911552 ps
CPU time 0.78 seconds
Started Apr 21 04:05:12 PM PDT 24
Finished Apr 21 04:05:13 PM PDT 24
Peak memory 198336 kb
Host smart-419a7697-f482-43fb-a15b-42936821ce32
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392808866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.3392808866
Directory /workspace/0.pwrmgr_reset/latest


Test location /workspace/coverage/default/0.pwrmgr_reset_invalid.979728919
Short name T471
Test name
Test status
Simulation time 445806566 ps
CPU time 0.79 seconds
Started Apr 21 04:05:21 PM PDT 24
Finished Apr 21 04:05:22 PM PDT 24
Peak memory 209092 kb
Host smart-372e9058-b98d-46d1-a8ca-053e08942d3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979728919 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.979728919
Directory /workspace/0.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/0.pwrmgr_sec_cm.1239882445
Short name T19
Test name
Test status
Simulation time 706181452 ps
CPU time 2.27 seconds
Started Apr 21 04:05:19 PM PDT 24
Finished Apr 21 04:05:21 PM PDT 24
Peak memory 217268 kb
Host smart-832fa4ef-8b87-45aa-b9f7-d1ae6b922700
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239882445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.1239882445
Directory /workspace/0.pwrmgr_sec_cm/latest


Test location /workspace/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3301072529
Short name T805
Test name
Test status
Simulation time 807985897 ps
CPU time 3.26 seconds
Started Apr 21 04:05:16 PM PDT 24
Finished Apr 21 04:05:19 PM PDT 24
Peak memory 200836 kb
Host smart-da0352b1-2151-4c05-af02-8f186b69401d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301072529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3301072529
Directory /workspace/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2189945999
Short name T791
Test name
Test status
Simulation time 876885865 ps
CPU time 3.34 seconds
Started Apr 21 04:05:15 PM PDT 24
Finished Apr 21 04:05:19 PM PDT 24
Peak memory 200656 kb
Host smart-041f4054-a0dd-4736-993c-8ab65bab5853
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189945999 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2189945999
Directory /workspace/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.1298811566
Short name T307
Test name
Test status
Simulation time 65361616 ps
CPU time 0.92 seconds
Started Apr 21 04:05:13 PM PDT 24
Finished Apr 21 04:05:14 PM PDT 24
Peak memory 198796 kb
Host smart-213e8ade-b859-4436-9c54-64148fe7cf73
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298811566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1298811566
Directory /workspace/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/0.pwrmgr_smoke.388847913
Short name T395
Test name
Test status
Simulation time 42582762 ps
CPU time 0.7 seconds
Started Apr 21 04:05:12 PM PDT 24
Finished Apr 21 04:05:13 PM PDT 24
Peak memory 198160 kb
Host smart-371c70f5-92e7-4eb5-b9a1-444026c4c650
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388847913 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.388847913
Directory /workspace/0.pwrmgr_smoke/latest


Test location /workspace/coverage/default/0.pwrmgr_stress_all.707608353
Short name T653
Test name
Test status
Simulation time 1108171827 ps
CPU time 2.48 seconds
Started Apr 21 04:05:19 PM PDT 24
Finished Apr 21 04:05:22 PM PDT 24
Peak memory 200844 kb
Host smart-4bc9bc2c-511a-4310-a820-4832020315dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707608353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.707608353
Directory /workspace/0.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/0.pwrmgr_wakeup.1159036217
Short name T311
Test name
Test status
Simulation time 173237070 ps
CPU time 0.86 seconds
Started Apr 21 04:05:12 PM PDT 24
Finished Apr 21 04:05:13 PM PDT 24
Peak memory 198128 kb
Host smart-cb85b097-1c44-4cc0-b6df-90f3b3faf3ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159036217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.1159036217
Directory /workspace/0.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/0.pwrmgr_wakeup_reset.1217967508
Short name T939
Test name
Test status
Simulation time 310046525 ps
CPU time 1.25 seconds
Started Apr 21 04:05:15 PM PDT 24
Finished Apr 21 04:05:17 PM PDT 24
Peak memory 200528 kb
Host smart-420dec89-83e9-4ab0-93f1-44f557506db5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217967508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.1217967508
Directory /workspace/0.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/1.pwrmgr_aborted_low_power.353437327
Short name T652
Test name
Test status
Simulation time 83269110 ps
CPU time 0.97 seconds
Started Apr 21 04:05:19 PM PDT 24
Finished Apr 21 04:05:20 PM PDT 24
Peak memory 200416 kb
Host smart-6c85dd24-c4e1-48b9-be92-73968dee55e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353437327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.353437327
Directory /workspace/1.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/1.pwrmgr_disable_rom_integrity_check.1364232405
Short name T868
Test name
Test status
Simulation time 67452080 ps
CPU time 0.72 seconds
Started Apr 21 04:05:19 PM PDT 24
Finished Apr 21 04:05:20 PM PDT 24
Peak memory 198804 kb
Host smart-66fa7bcd-4e06-4b67-afe4-f2fc253a9b40
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364232405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disa
ble_rom_integrity_check.1364232405
Directory /workspace/1.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.3540085695
Short name T648
Test name
Test status
Simulation time 36765727 ps
CPU time 0.63 seconds
Started Apr 21 04:05:27 PM PDT 24
Finished Apr 21 04:05:28 PM PDT 24
Peak memory 196928 kb
Host smart-c44ae556-f32d-4d8c-a671-1bc44736382f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540085695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_
malfunc.3540085695
Directory /workspace/1.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/1.pwrmgr_escalation_timeout.1148315629
Short name T488
Test name
Test status
Simulation time 164704825 ps
CPU time 0.98 seconds
Started Apr 21 04:05:24 PM PDT 24
Finished Apr 21 04:05:26 PM PDT 24
Peak memory 198104 kb
Host smart-28130897-54de-4c7d-87d4-34f9554d7701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148315629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.1148315629
Directory /workspace/1.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/1.pwrmgr_glitch.3988760697
Short name T583
Test name
Test status
Simulation time 63984272 ps
CPU time 0.61 seconds
Started Apr 21 04:05:21 PM PDT 24
Finished Apr 21 04:05:22 PM PDT 24
Peak memory 197800 kb
Host smart-280d3e5b-ccf3-4184-bdcd-92cea9cadf27
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988760697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.3988760697
Directory /workspace/1.pwrmgr_glitch/latest


Test location /workspace/coverage/default/1.pwrmgr_global_esc.2340311308
Short name T217
Test name
Test status
Simulation time 79032483 ps
CPU time 0.61 seconds
Started Apr 21 04:05:26 PM PDT 24
Finished Apr 21 04:05:26 PM PDT 24
Peak memory 197712 kb
Host smart-0b7fc9ad-33f0-4bda-8d8e-3b65f890869e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340311308 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.2340311308
Directory /workspace/1.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/1.pwrmgr_lowpower_invalid.2155890462
Short name T869
Test name
Test status
Simulation time 129798621 ps
CPU time 0.7 seconds
Started Apr 21 04:05:25 PM PDT 24
Finished Apr 21 04:05:26 PM PDT 24
Peak memory 200980 kb
Host smart-41d6844f-b7f0-4eeb-ab43-2fe45f786dbf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155890462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invali
d.2155890462
Directory /workspace/1.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/1.pwrmgr_lowpower_wakeup_race.2233679863
Short name T587
Test name
Test status
Simulation time 151450074 ps
CPU time 0.78 seconds
Started Apr 21 04:05:20 PM PDT 24
Finished Apr 21 04:05:21 PM PDT 24
Peak memory 197956 kb
Host smart-93aa7dc5-650d-4b8c-a4a9-e4cdb91a98af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233679863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wa
keup_race.2233679863
Directory /workspace/1.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/1.pwrmgr_reset.3971008312
Short name T42
Test name
Test status
Simulation time 36754040 ps
CPU time 0.75 seconds
Started Apr 21 04:05:19 PM PDT 24
Finished Apr 21 04:05:20 PM PDT 24
Peak memory 198172 kb
Host smart-f0506a6a-8ee8-4600-ab11-6f115ba5db8f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971008312 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.3971008312
Directory /workspace/1.pwrmgr_reset/latest


Test location /workspace/coverage/default/1.pwrmgr_sec_cm.913385490
Short name T20
Test name
Test status
Simulation time 402592547 ps
CPU time 1.3 seconds
Started Apr 21 04:05:32 PM PDT 24
Finished Apr 21 04:05:33 PM PDT 24
Peak memory 216512 kb
Host smart-63d9f7cd-38f0-4177-a1b8-515245ed5668
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913385490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.913385490
Directory /workspace/1.pwrmgr_sec_cm/latest


Test location /workspace/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.2969758380
Short name T60
Test name
Test status
Simulation time 256018351 ps
CPU time 1.41 seconds
Started Apr 21 04:05:23 PM PDT 24
Finished Apr 21 04:05:25 PM PDT 24
Peak memory 200648 kb
Host smart-9e3f1e02-a3ed-44ba-87dd-b26ba62a77f0
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969758380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_c
m_ctrl_config_regwen.2969758380
Directory /workspace/1.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.860508173
Short name T945
Test name
Test status
Simulation time 862080279 ps
CPU time 2.08 seconds
Started Apr 21 04:05:19 PM PDT 24
Finished Apr 21 04:05:22 PM PDT 24
Peak memory 200852 kb
Host smart-662d8b43-0f74-45ef-99fd-9ceaad411549
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860508173 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.860508173
Directory /workspace/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3312718591
Short name T500
Test name
Test status
Simulation time 1015771094 ps
CPU time 2.29 seconds
Started Apr 21 04:05:22 PM PDT 24
Finished Apr 21 04:05:25 PM PDT 24
Peak memory 200964 kb
Host smart-bf94bfcf-67bd-4662-b6c7-e8e28943ce66
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312718591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3312718591
Directory /workspace/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.1232362751
Short name T404
Test name
Test status
Simulation time 109818895 ps
CPU time 0.96 seconds
Started Apr 21 04:05:22 PM PDT 24
Finished Apr 21 04:05:23 PM PDT 24
Peak memory 198744 kb
Host smart-e1baf325-bf66-48a8-985e-fe2355c18147
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232362751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1232362751
Directory /workspace/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/1.pwrmgr_smoke.3289121791
Short name T384
Test name
Test status
Simulation time 77225856 ps
CPU time 0.69 seconds
Started Apr 21 04:05:17 PM PDT 24
Finished Apr 21 04:05:18 PM PDT 24
Peak memory 198080 kb
Host smart-de15cd2a-32e2-496c-9094-77bf28e59422
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289121791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.3289121791
Directory /workspace/1.pwrmgr_smoke/latest


Test location /workspace/coverage/default/1.pwrmgr_stress_all.747826566
Short name T824
Test name
Test status
Simulation time 3260733735 ps
CPU time 4.9 seconds
Started Apr 21 04:05:27 PM PDT 24
Finished Apr 21 04:05:32 PM PDT 24
Peak memory 201044 kb
Host smart-ec44ffe2-2216-4d8f-89c5-3c5738ef0b1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747826566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.747826566
Directory /workspace/1.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/1.pwrmgr_wakeup.1190548557
Short name T370
Test name
Test status
Simulation time 249443420 ps
CPU time 0.92 seconds
Started Apr 21 04:05:20 PM PDT 24
Finished Apr 21 04:05:21 PM PDT 24
Peak memory 198192 kb
Host smart-22b49c43-78a0-48ab-8c70-057c1aa74983
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190548557 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.1190548557
Directory /workspace/1.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/1.pwrmgr_wakeup_reset.3270567437
Short name T83
Test name
Test status
Simulation time 213445163 ps
CPU time 0.83 seconds
Started Apr 21 04:05:19 PM PDT 24
Finished Apr 21 04:05:20 PM PDT 24
Peak memory 198692 kb
Host smart-aecc3c49-d5e2-4f64-923c-6e792990b05b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270567437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.3270567437
Directory /workspace/1.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/10.pwrmgr_aborted_low_power.117223523
Short name T16
Test name
Test status
Simulation time 40976440 ps
CPU time 0.91 seconds
Started Apr 21 04:05:57 PM PDT 24
Finished Apr 21 04:05:58 PM PDT 24
Peak memory 199644 kb
Host smart-8a3e75a9-2e61-470a-abf6-1f35db2936e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117223523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.117223523
Directory /workspace/10.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/10.pwrmgr_disable_rom_integrity_check.1154064586
Short name T252
Test name
Test status
Simulation time 69815825 ps
CPU time 0.7 seconds
Started Apr 21 04:05:58 PM PDT 24
Finished Apr 21 04:05:59 PM PDT 24
Peak memory 198172 kb
Host smart-ee38df8d-7ff3-4f18-a62e-8c62a18c5dd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154064586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_dis
able_rom_integrity_check.1154064586
Directory /workspace/10.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.1649714134
Short name T456
Test name
Test status
Simulation time 32155270 ps
CPU time 0.63 seconds
Started Apr 21 04:05:58 PM PDT 24
Finished Apr 21 04:05:59 PM PDT 24
Peak memory 197040 kb
Host smart-a791fd5f-eff2-45f6-93ac-842dfbd078c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649714134 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst
_malfunc.1649714134
Directory /workspace/10.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/10.pwrmgr_escalation_timeout.1009823190
Short name T438
Test name
Test status
Simulation time 694642623 ps
CPU time 0.95 seconds
Started Apr 21 04:05:58 PM PDT 24
Finished Apr 21 04:05:59 PM PDT 24
Peak memory 197804 kb
Host smart-b97a1d11-9b29-4bf5-acc1-a476f3be197d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009823190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.1009823190
Directory /workspace/10.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/10.pwrmgr_glitch.1341733318
Short name T630
Test name
Test status
Simulation time 58068634 ps
CPU time 0.64 seconds
Started Apr 21 04:05:59 PM PDT 24
Finished Apr 21 04:06:00 PM PDT 24
Peak memory 197800 kb
Host smart-4db9685e-df01-45fa-8ee0-51900efd9126
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341733318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.1341733318
Directory /workspace/10.pwrmgr_glitch/latest


Test location /workspace/coverage/default/10.pwrmgr_global_esc.1131147890
Short name T511
Test name
Test status
Simulation time 103312047 ps
CPU time 0.63 seconds
Started Apr 21 04:05:59 PM PDT 24
Finished Apr 21 04:06:00 PM PDT 24
Peak memory 197776 kb
Host smart-772a4ae9-c781-4079-9e84-19c28f69794a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131147890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.1131147890
Directory /workspace/10.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/10.pwrmgr_lowpower_invalid.433205983
Short name T514
Test name
Test status
Simulation time 49994551 ps
CPU time 0.68 seconds
Started Apr 21 04:05:58 PM PDT 24
Finished Apr 21 04:05:59 PM PDT 24
Peak memory 201172 kb
Host smart-b5b6dc2e-89aa-4867-b8ae-805b797bd31f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433205983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_invali
d.433205983
Directory /workspace/10.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/10.pwrmgr_lowpower_wakeup_race.3650688242
Short name T718
Test name
Test status
Simulation time 287780106 ps
CPU time 0.91 seconds
Started Apr 21 04:05:56 PM PDT 24
Finished Apr 21 04:05:57 PM PDT 24
Peak memory 199324 kb
Host smart-37b91249-371c-458a-99fd-a4d2275756d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650688242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_w
akeup_race.3650688242
Directory /workspace/10.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/10.pwrmgr_reset.224613122
Short name T423
Test name
Test status
Simulation time 44705533 ps
CPU time 0.83 seconds
Started Apr 21 04:05:56 PM PDT 24
Finished Apr 21 04:05:58 PM PDT 24
Peak memory 198796 kb
Host smart-0468cd2f-0ce4-46c9-9b46-675b80a0e5d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224613122 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.224613122
Directory /workspace/10.pwrmgr_reset/latest


Test location /workspace/coverage/default/10.pwrmgr_reset_invalid.605441660
Short name T591
Test name
Test status
Simulation time 159721062 ps
CPU time 0.77 seconds
Started Apr 21 04:05:57 PM PDT 24
Finished Apr 21 04:05:58 PM PDT 24
Peak memory 209180 kb
Host smart-9632222f-6f76-45ac-a8fa-16501eac393e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605441660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.605441660
Directory /workspace/10.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.1342034345
Short name T503
Test name
Test status
Simulation time 201513023 ps
CPU time 1.17 seconds
Started Apr 21 04:05:57 PM PDT 24
Finished Apr 21 04:05:58 PM PDT 24
Peak memory 199816 kb
Host smart-a9daa4e4-1bb8-4a73-9f03-b0b38160a482
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342034345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_
cm_ctrl_config_regwen.1342034345
Directory /workspace/10.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2919859092
Short name T608
Test name
Test status
Simulation time 834984889 ps
CPU time 3.4 seconds
Started Apr 21 04:05:56 PM PDT 24
Finished Apr 21 04:06:00 PM PDT 24
Peak memory 200812 kb
Host smart-c8891f23-aa4c-4854-b1be-ce37c936fc09
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919859092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2919859092
Directory /workspace/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.191873302
Short name T286
Test name
Test status
Simulation time 932858408 ps
CPU time 3.08 seconds
Started Apr 21 04:05:58 PM PDT 24
Finished Apr 21 04:06:02 PM PDT 24
Peak memory 200820 kb
Host smart-871218d3-f285-41fc-b935-276a2e7a01d5
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191873302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.191873302
Directory /workspace/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.2106665618
Short name T305
Test name
Test status
Simulation time 74365264 ps
CPU time 0.96 seconds
Started Apr 21 04:05:57 PM PDT 24
Finished Apr 21 04:05:58 PM PDT 24
Peak memory 198940 kb
Host smart-91748c0e-3b67-4c11-9155-958fd6ace9d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106665618 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2106665618
Directory /workspace/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/10.pwrmgr_smoke.3474258452
Short name T188
Test name
Test status
Simulation time 29117341 ps
CPU time 0.71 seconds
Started Apr 21 04:05:56 PM PDT 24
Finished Apr 21 04:05:58 PM PDT 24
Peak memory 198988 kb
Host smart-5180789d-28a8-40d4-a4e1-056f1509ef4e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474258452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.3474258452
Directory /workspace/10.pwrmgr_smoke/latest


Test location /workspace/coverage/default/10.pwrmgr_stress_all.2843158770
Short name T506
Test name
Test status
Simulation time 1914558953 ps
CPU time 6.9 seconds
Started Apr 21 04:05:59 PM PDT 24
Finished Apr 21 04:06:06 PM PDT 24
Peak memory 200952 kb
Host smart-1ba5058c-37c7-43a1-b90a-f63fed804114
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843158770 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.2843158770
Directory /workspace/10.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/10.pwrmgr_stress_all_with_rand_reset.1847247292
Short name T58
Test name
Test status
Simulation time 4821919853 ps
CPU time 16.04 seconds
Started Apr 21 04:06:08 PM PDT 24
Finished Apr 21 04:06:25 PM PDT 24
Peak memory 201124 kb
Host smart-e07d66a8-33f8-407f-9199-029770178589
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847247292 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all_with_rand_reset.1847247292
Directory /workspace/10.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/10.pwrmgr_wakeup.1475338422
Short name T830
Test name
Test status
Simulation time 454207363 ps
CPU time 1.14 seconds
Started Apr 21 04:05:57 PM PDT 24
Finished Apr 21 04:05:58 PM PDT 24
Peak memory 199480 kb
Host smart-e65d942a-1a67-4006-b669-bb58fee6bd83
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475338422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.1475338422
Directory /workspace/10.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/10.pwrmgr_wakeup_reset.3705360638
Short name T170
Test name
Test status
Simulation time 238291092 ps
CPU time 1.38 seconds
Started Apr 21 04:05:58 PM PDT 24
Finished Apr 21 04:06:00 PM PDT 24
Peak memory 199864 kb
Host smart-e9e008cc-c2b7-4f2b-bb58-b7b4fe83ab34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705360638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.3705360638
Directory /workspace/10.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/11.pwrmgr_aborted_low_power.2661540669
Short name T308
Test name
Test status
Simulation time 44356039 ps
CPU time 0.95 seconds
Started Apr 21 04:06:06 PM PDT 24
Finished Apr 21 04:06:08 PM PDT 24
Peak memory 199980 kb
Host smart-8911419e-0f41-4ff9-971b-7a7b37b21534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661540669 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.2661540669
Directory /workspace/11.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/11.pwrmgr_disable_rom_integrity_check.3799205902
Short name T752
Test name
Test status
Simulation time 57205987 ps
CPU time 0.7 seconds
Started Apr 21 04:06:03 PM PDT 24
Finished Apr 21 04:06:05 PM PDT 24
Peak memory 198868 kb
Host smart-fb4c586d-e264-40b1-a48a-579d2019d206
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799205902 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_dis
able_rom_integrity_check.3799205902
Directory /workspace/11.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.4260339217
Short name T783
Test name
Test status
Simulation time 37463855 ps
CPU time 0.61 seconds
Started Apr 21 04:05:57 PM PDT 24
Finished Apr 21 04:05:58 PM PDT 24
Peak memory 197736 kb
Host smart-41eeeee4-03ec-4754-9fc6-b5ad36bb043b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260339217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst
_malfunc.4260339217
Directory /workspace/11.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/11.pwrmgr_escalation_timeout.3962351174
Short name T815
Test name
Test status
Simulation time 320671732 ps
CPU time 1.05 seconds
Started Apr 21 04:06:01 PM PDT 24
Finished Apr 21 04:06:03 PM PDT 24
Peak memory 198088 kb
Host smart-d2249759-25e3-4796-8779-d9d75e37359a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962351174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.3962351174
Directory /workspace/11.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/11.pwrmgr_glitch.935624177
Short name T355
Test name
Test status
Simulation time 65757634 ps
CPU time 0.67 seconds
Started Apr 21 04:06:02 PM PDT 24
Finished Apr 21 04:06:03 PM PDT 24
Peak memory 197020 kb
Host smart-a71c519f-04ef-40fa-b8a7-10f62957058f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935624177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.935624177
Directory /workspace/11.pwrmgr_glitch/latest


Test location /workspace/coverage/default/11.pwrmgr_global_esc.4272845829
Short name T387
Test name
Test status
Simulation time 28015751 ps
CPU time 0.62 seconds
Started Apr 21 04:06:00 PM PDT 24
Finished Apr 21 04:06:01 PM PDT 24
Peak memory 197652 kb
Host smart-d2685bc4-8bcd-4d1c-8ab4-42d4df47a584
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272845829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.4272845829
Directory /workspace/11.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/11.pwrmgr_lowpower_invalid.258992387
Short name T487
Test name
Test status
Simulation time 47580154 ps
CPU time 0.78 seconds
Started Apr 21 04:06:02 PM PDT 24
Finished Apr 21 04:06:03 PM PDT 24
Peak memory 200960 kb
Host smart-c3c6c731-03e6-4a7c-b0e8-e108065b2d05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258992387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_invali
d.258992387
Directory /workspace/11.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/11.pwrmgr_lowpower_wakeup_race.1466811210
Short name T843
Test name
Test status
Simulation time 135494967 ps
CPU time 0.92 seconds
Started Apr 21 04:06:07 PM PDT 24
Finished Apr 21 04:06:09 PM PDT 24
Peak memory 198160 kb
Host smart-c203caa6-6287-4fcf-9e1e-0af4ad33a0c1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466811210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_w
akeup_race.1466811210
Directory /workspace/11.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/11.pwrmgr_reset.1242145427
Short name T775
Test name
Test status
Simulation time 27814114 ps
CPU time 0.76 seconds
Started Apr 21 04:06:07 PM PDT 24
Finished Apr 21 04:06:09 PM PDT 24
Peak memory 198876 kb
Host smart-f7a13873-930e-404e-a2b0-e2fb3bef5da6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242145427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.1242145427
Directory /workspace/11.pwrmgr_reset/latest


Test location /workspace/coverage/default/11.pwrmgr_reset_invalid.3223273418
Short name T844
Test name
Test status
Simulation time 116325182 ps
CPU time 0.96 seconds
Started Apr 21 04:06:01 PM PDT 24
Finished Apr 21 04:06:02 PM PDT 24
Peak memory 209204 kb
Host smart-7e9ea2dd-4d07-4d1c-9076-e2206cb3a6bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223273418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.3223273418
Directory /workspace/11.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.65532276
Short name T782
Test name
Test status
Simulation time 222798493 ps
CPU time 1.22 seconds
Started Apr 21 04:06:05 PM PDT 24
Finished Apr 21 04:06:06 PM PDT 24
Peak memory 200520 kb
Host smart-e080d0a7-c0f6-4e68-91ed-2435a3d67ddc
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65532276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_co
nfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm
_ctrl_config_regwen.65532276
Directory /workspace/11.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1671635064
Short name T381
Test name
Test status
Simulation time 1114553398 ps
CPU time 2.25 seconds
Started Apr 21 04:06:01 PM PDT 24
Finished Apr 21 04:06:03 PM PDT 24
Peak memory 200656 kb
Host smart-e1c5e066-95fb-4ee7-a091-71c458c21e7d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671635064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1671635064
Directory /workspace/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3750145218
Short name T532
Test name
Test status
Simulation time 815414450 ps
CPU time 3.04 seconds
Started Apr 21 04:06:00 PM PDT 24
Finished Apr 21 04:06:03 PM PDT 24
Peak memory 200828 kb
Host smart-2550624f-07e7-4e54-832e-91fd7d0f030e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750145218 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3750145218
Directory /workspace/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.862604051
Short name T940
Test name
Test status
Simulation time 89451397 ps
CPU time 0.85 seconds
Started Apr 21 04:06:06 PM PDT 24
Finished Apr 21 04:06:08 PM PDT 24
Peak memory 198824 kb
Host smart-217e7bec-4018-4675-bec2-31d2b052fb46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862604051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig_
mubi.862604051
Directory /workspace/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/11.pwrmgr_smoke.3214662984
Short name T5
Test name
Test status
Simulation time 30098514 ps
CPU time 0.66 seconds
Started Apr 21 04:05:58 PM PDT 24
Finished Apr 21 04:05:59 PM PDT 24
Peak memory 198932 kb
Host smart-2023a19a-bc3a-430a-831f-7b519f22ee42
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214662984 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.3214662984
Directory /workspace/11.pwrmgr_smoke/latest


Test location /workspace/coverage/default/11.pwrmgr_stress_all.1573983746
Short name T581
Test name
Test status
Simulation time 2315788836 ps
CPU time 3.56 seconds
Started Apr 21 04:06:01 PM PDT 24
Finished Apr 21 04:06:05 PM PDT 24
Peak memory 200976 kb
Host smart-602b0dbc-d14d-48f1-b833-4c1669f28a2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573983746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.1573983746
Directory /workspace/11.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/11.pwrmgr_stress_all_with_rand_reset.3708072546
Short name T24
Test name
Test status
Simulation time 4587175798 ps
CPU time 16.05 seconds
Started Apr 21 04:06:01 PM PDT 24
Finished Apr 21 04:06:18 PM PDT 24
Peak memory 201012 kb
Host smart-dc24173d-0174-4c66-81fb-cfcbe4d06538
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708072546 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all_with_rand_reset.3708072546
Directory /workspace/11.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/11.pwrmgr_wakeup.1208215948
Short name T38
Test name
Test status
Simulation time 139871320 ps
CPU time 0.98 seconds
Started Apr 21 04:06:07 PM PDT 24
Finished Apr 21 04:06:08 PM PDT 24
Peak memory 198792 kb
Host smart-7df467de-e2cf-4d6f-9c59-0068dab0c54e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208215948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.1208215948
Directory /workspace/11.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/11.pwrmgr_wakeup_reset.76829455
Short name T242
Test name
Test status
Simulation time 37328595 ps
CPU time 0.65 seconds
Started Apr 21 04:06:07 PM PDT 24
Finished Apr 21 04:06:08 PM PDT 24
Peak memory 198956 kb
Host smart-1ebceb6f-a325-4429-a3bb-7bcfdd82314c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76829455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.76829455
Directory /workspace/11.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/12.pwrmgr_aborted_low_power.3805822858
Short name T963
Test name
Test status
Simulation time 22203234 ps
CPU time 0.74 seconds
Started Apr 21 04:06:05 PM PDT 24
Finished Apr 21 04:06:06 PM PDT 24
Peak memory 198776 kb
Host smart-7b2740f1-9a47-4d0e-895a-c3dc092e31ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805822858 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.3805822858
Directory /workspace/12.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/12.pwrmgr_disable_rom_integrity_check.3128679878
Short name T725
Test name
Test status
Simulation time 88031941 ps
CPU time 0.74 seconds
Started Apr 21 04:06:06 PM PDT 24
Finished Apr 21 04:06:07 PM PDT 24
Peak memory 198340 kb
Host smart-3ca27825-1f7e-4ffc-be5c-7c429ef8d3d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128679878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_dis
able_rom_integrity_check.3128679878
Directory /workspace/12.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.3940264290
Short name T638
Test name
Test status
Simulation time 41831004 ps
CPU time 0.59 seconds
Started Apr 21 04:06:04 PM PDT 24
Finished Apr 21 04:06:05 PM PDT 24
Peak memory 197712 kb
Host smart-502b8326-88ae-4171-b575-340511e747b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940264290 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst
_malfunc.3940264290
Directory /workspace/12.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/12.pwrmgr_escalation_timeout.870219275
Short name T728
Test name
Test status
Simulation time 1096772490 ps
CPU time 0.98 seconds
Started Apr 21 04:06:03 PM PDT 24
Finished Apr 21 04:06:05 PM PDT 24
Peak memory 198092 kb
Host smart-960e8974-c4ef-46ca-aa59-252274bc2c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870219275 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.870219275
Directory /workspace/12.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/12.pwrmgr_global_esc.2188762141
Short name T425
Test name
Test status
Simulation time 51254998 ps
CPU time 0.69 seconds
Started Apr 21 04:06:04 PM PDT 24
Finished Apr 21 04:06:05 PM PDT 24
Peak memory 197784 kb
Host smart-f9c58e10-2fc8-49ab-bd25-d7ad033886bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188762141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.2188762141
Directory /workspace/12.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/12.pwrmgr_lowpower_wakeup_race.3971973798
Short name T94
Test name
Test status
Simulation time 176367633 ps
CPU time 0.79 seconds
Started Apr 21 04:06:03 PM PDT 24
Finished Apr 21 04:06:05 PM PDT 24
Peak memory 198112 kb
Host smart-2810b40d-0f78-4bf4-a05f-23d593350bce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971973798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_w
akeup_race.3971973798
Directory /workspace/12.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/12.pwrmgr_reset.2013232717
Short name T684
Test name
Test status
Simulation time 96569116 ps
CPU time 0.78 seconds
Started Apr 21 04:06:04 PM PDT 24
Finished Apr 21 04:06:05 PM PDT 24
Peak memory 198796 kb
Host smart-1e2e31d3-e38a-4d42-8ee3-9c8c921d5161
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013232717 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.2013232717
Directory /workspace/12.pwrmgr_reset/latest


Test location /workspace/coverage/default/12.pwrmgr_reset_invalid.776529362
Short name T676
Test name
Test status
Simulation time 151641392 ps
CPU time 0.81 seconds
Started Apr 21 04:06:14 PM PDT 24
Finished Apr 21 04:06:15 PM PDT 24
Peak memory 209128 kb
Host smart-491b89f8-77e1-46d5-8efa-75238e9bcf5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776529362 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.776529362
Directory /workspace/12.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.3395681377
Short name T696
Test name
Test status
Simulation time 331486686 ps
CPU time 1.12 seconds
Started Apr 21 04:06:05 PM PDT 24
Finished Apr 21 04:06:07 PM PDT 24
Peak memory 200488 kb
Host smart-6207c55a-2f2a-4d3e-a560-acccaf56b773
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395681377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_
cm_ctrl_config_regwen.3395681377
Directory /workspace/12.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1561032117
Short name T327
Test name
Test status
Simulation time 926984112 ps
CPU time 2.14 seconds
Started Apr 21 04:06:06 PM PDT 24
Finished Apr 21 04:06:08 PM PDT 24
Peak memory 200728 kb
Host smart-f7eb2865-17f4-4817-bfd1-51b85ebd9366
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561032117 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1561032117
Directory /workspace/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1008190484
Short name T538
Test name
Test status
Simulation time 845281018 ps
CPU time 3.53 seconds
Started Apr 21 04:06:04 PM PDT 24
Finished Apr 21 04:06:08 PM PDT 24
Peak memory 200856 kb
Host smart-864a37f5-1133-4e0a-b7a5-21f204560b15
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008190484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1008190484
Directory /workspace/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.2075808427
Short name T666
Test name
Test status
Simulation time 54102996 ps
CPU time 0.9 seconds
Started Apr 21 04:06:04 PM PDT 24
Finished Apr 21 04:06:06 PM PDT 24
Peak memory 198936 kb
Host smart-f476babe-1944-4329-a6ab-ff4a7c4c1885
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075808427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2075808427
Directory /workspace/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/12.pwrmgr_smoke.1502512353
Short name T160
Test name
Test status
Simulation time 35239354 ps
CPU time 0.69 seconds
Started Apr 21 04:06:03 PM PDT 24
Finished Apr 21 04:06:04 PM PDT 24
Peak memory 198964 kb
Host smart-e0727fce-94ac-424a-a6c4-76517e2057a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502512353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.1502512353
Directory /workspace/12.pwrmgr_smoke/latest


Test location /workspace/coverage/default/12.pwrmgr_stress_all.15010231
Short name T706
Test name
Test status
Simulation time 611733559 ps
CPU time 1.5 seconds
Started Apr 21 04:06:09 PM PDT 24
Finished Apr 21 04:06:11 PM PDT 24
Peak memory 200892 kb
Host smart-52ff9a5b-200e-4e4e-861e-60ec3514d7f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15010231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.15010231
Directory /workspace/12.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/12.pwrmgr_stress_all_with_rand_reset.1223658114
Short name T980
Test name
Test status
Simulation time 14712314000 ps
CPU time 19.75 seconds
Started Apr 21 04:06:07 PM PDT 24
Finished Apr 21 04:06:27 PM PDT 24
Peak memory 200968 kb
Host smart-6a7cb5a4-f7db-460d-a922-359f78c3bc3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223658114 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all_with_rand_reset.1223658114
Directory /workspace/12.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/12.pwrmgr_wakeup.139126363
Short name T578
Test name
Test status
Simulation time 172075126 ps
CPU time 1.06 seconds
Started Apr 21 04:06:01 PM PDT 24
Finished Apr 21 04:06:03 PM PDT 24
Peak memory 199124 kb
Host smart-2ea5ccd8-48e5-45fd-8388-fb1f11041d47
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139126363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.139126363
Directory /workspace/12.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/12.pwrmgr_wakeup_reset.2427322751
Short name T818
Test name
Test status
Simulation time 43309643 ps
CPU time 0.66 seconds
Started Apr 21 04:06:03 PM PDT 24
Finished Apr 21 04:06:05 PM PDT 24
Peak memory 198356 kb
Host smart-da05d5fc-4540-40a3-8ae5-f9c97bebebcc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427322751 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.2427322751
Directory /workspace/12.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/13.pwrmgr_aborted_low_power.772044983
Short name T473
Test name
Test status
Simulation time 142630103 ps
CPU time 0.7 seconds
Started Apr 21 04:06:06 PM PDT 24
Finished Apr 21 04:06:07 PM PDT 24
Peak memory 198248 kb
Host smart-a6a17d61-97af-4709-a6b9-3b524647b7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772044983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.772044983
Directory /workspace/13.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/13.pwrmgr_disable_rom_integrity_check.2609443871
Short name T142
Test name
Test status
Simulation time 58983863 ps
CPU time 0.84 seconds
Started Apr 21 04:06:09 PM PDT 24
Finished Apr 21 04:06:10 PM PDT 24
Peak memory 198844 kb
Host smart-59e17ecf-7ed5-4051-abff-d785320cf878
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609443871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_dis
able_rom_integrity_check.2609443871
Directory /workspace/13.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/13.pwrmgr_escalation_timeout.4168365688
Short name T913
Test name
Test status
Simulation time 167244848 ps
CPU time 0.95 seconds
Started Apr 21 04:06:09 PM PDT 24
Finished Apr 21 04:06:10 PM PDT 24
Peak memory 197956 kb
Host smart-22e10877-0dae-4fee-8014-9770d5349d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168365688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.4168365688
Directory /workspace/13.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/13.pwrmgr_glitch.529048598
Short name T271
Test name
Test status
Simulation time 97688409 ps
CPU time 0.65 seconds
Started Apr 21 04:06:08 PM PDT 24
Finished Apr 21 04:06:09 PM PDT 24
Peak memory 197032 kb
Host smart-df90a2a3-612c-4f1b-ae72-a107afb97fae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529048598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.529048598
Directory /workspace/13.pwrmgr_glitch/latest


Test location /workspace/coverage/default/13.pwrmgr_global_esc.1750293906
Short name T971
Test name
Test status
Simulation time 55521085 ps
CPU time 0.63 seconds
Started Apr 21 04:06:11 PM PDT 24
Finished Apr 21 04:06:12 PM PDT 24
Peak memory 197784 kb
Host smart-0221b797-2fc2-466f-ac6d-aac56dde6ade
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750293906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.1750293906
Directory /workspace/13.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/13.pwrmgr_lowpower_invalid.3498050607
Short name T976
Test name
Test status
Simulation time 52471996 ps
CPU time 0.72 seconds
Started Apr 21 04:06:10 PM PDT 24
Finished Apr 21 04:06:11 PM PDT 24
Peak memory 201028 kb
Host smart-e7779be1-bf55-427c-8ac8-d018a06f6722
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498050607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_inval
id.3498050607
Directory /workspace/13.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/13.pwrmgr_lowpower_wakeup_race.3957201668
Short name T499
Test name
Test status
Simulation time 162592897 ps
CPU time 1 seconds
Started Apr 21 04:06:07 PM PDT 24
Finished Apr 21 04:06:09 PM PDT 24
Peak memory 198168 kb
Host smart-2da5ba3d-b7da-44c8-bdbc-153a2f03298e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957201668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_w
akeup_race.3957201668
Directory /workspace/13.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/13.pwrmgr_reset.2235052361
Short name T958
Test name
Test status
Simulation time 97219084 ps
CPU time 0.83 seconds
Started Apr 21 04:06:06 PM PDT 24
Finished Apr 21 04:06:07 PM PDT 24
Peak memory 198332 kb
Host smart-fdd3a815-0337-4080-851e-774bdbc3ec7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235052361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.2235052361
Directory /workspace/13.pwrmgr_reset/latest


Test location /workspace/coverage/default/13.pwrmgr_reset_invalid.1526633520
Short name T650
Test name
Test status
Simulation time 105262921 ps
CPU time 1 seconds
Started Apr 21 04:06:10 PM PDT 24
Finished Apr 21 04:06:11 PM PDT 24
Peak memory 209172 kb
Host smart-713d7b52-b66b-4b87-90dd-10ee118fbcff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526633520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.1526633520
Directory /workspace/13.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.1651858481
Short name T302
Test name
Test status
Simulation time 508412338 ps
CPU time 1.13 seconds
Started Apr 21 04:06:10 PM PDT 24
Finished Apr 21 04:06:11 PM PDT 24
Peak memory 200640 kb
Host smart-dca60383-8402-4960-a83a-4448dd87ccf7
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651858481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_
cm_ctrl_config_regwen.1651858481
Directory /workspace/13.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3616929486
Short name T674
Test name
Test status
Simulation time 988189847 ps
CPU time 2.76 seconds
Started Apr 21 04:06:08 PM PDT 24
Finished Apr 21 04:06:11 PM PDT 24
Peak memory 200816 kb
Host smart-a4779011-284e-4aa9-9b77-22105cb5c484
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616929486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3616929486
Directory /workspace/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2878990728
Short name T102
Test name
Test status
Simulation time 873794826 ps
CPU time 3.56 seconds
Started Apr 21 04:06:06 PM PDT 24
Finished Apr 21 04:06:10 PM PDT 24
Peak memory 200860 kb
Host smart-06b92aca-d815-422b-a13e-2a1ed7e8dce6
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878990728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2878990728
Directory /workspace/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.700656047
Short name T796
Test name
Test status
Simulation time 176285230 ps
CPU time 0.88 seconds
Started Apr 21 04:06:07 PM PDT 24
Finished Apr 21 04:06:09 PM PDT 24
Peak memory 198952 kb
Host smart-4296366a-3dfa-4b06-81d4-3b4674777f8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700656047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig_
mubi.700656047
Directory /workspace/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/13.pwrmgr_smoke.2639069702
Short name T492
Test name
Test status
Simulation time 33878485 ps
CPU time 0.72 seconds
Started Apr 21 04:06:12 PM PDT 24
Finished Apr 21 04:06:13 PM PDT 24
Peak memory 198988 kb
Host smart-12834447-0622-4aa7-bdaf-46a7a48e03cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639069702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.2639069702
Directory /workspace/13.pwrmgr_smoke/latest


Test location /workspace/coverage/default/13.pwrmgr_wakeup.1441180690
Short name T554
Test name
Test status
Simulation time 237443526 ps
CPU time 0.92 seconds
Started Apr 21 04:06:08 PM PDT 24
Finished Apr 21 04:06:09 PM PDT 24
Peak memory 199284 kb
Host smart-8d68fca1-be9b-4f80-b255-3a6b4c5b38a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441180690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.1441180690
Directory /workspace/13.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/13.pwrmgr_wakeup_reset.3619228184
Short name T836
Test name
Test status
Simulation time 227849634 ps
CPU time 1.19 seconds
Started Apr 21 04:06:06 PM PDT 24
Finished Apr 21 04:06:08 PM PDT 24
Peak memory 199808 kb
Host smart-8965c6d9-f070-47b0-8467-774b30d4b8e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619228184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.3619228184
Directory /workspace/13.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/14.pwrmgr_aborted_low_power.2794531054
Short name T497
Test name
Test status
Simulation time 80962549 ps
CPU time 0.74 seconds
Started Apr 21 04:06:13 PM PDT 24
Finished Apr 21 04:06:14 PM PDT 24
Peak memory 198388 kb
Host smart-b9547c10-b145-4c0f-ab0b-37b67955e93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794531054 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.2794531054
Directory /workspace/14.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/14.pwrmgr_disable_rom_integrity_check.1906517859
Short name T101
Test name
Test status
Simulation time 62242557 ps
CPU time 0.75 seconds
Started Apr 21 04:06:19 PM PDT 24
Finished Apr 21 04:06:20 PM PDT 24
Peak memory 198756 kb
Host smart-af30e692-e873-45ac-bb00-c22bad6ca542
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906517859 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_dis
able_rom_integrity_check.1906517859
Directory /workspace/14.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.1483250323
Short name T773
Test name
Test status
Simulation time 52365285 ps
CPU time 0.65 seconds
Started Apr 21 04:06:15 PM PDT 24
Finished Apr 21 04:06:16 PM PDT 24
Peak memory 197612 kb
Host smart-a84b6212-1988-4bd8-b2a4-fa948a5d0f3a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483250323 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst
_malfunc.1483250323
Directory /workspace/14.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/14.pwrmgr_escalation_timeout.3155400885
Short name T283
Test name
Test status
Simulation time 316991621 ps
CPU time 1.01 seconds
Started Apr 21 04:06:13 PM PDT 24
Finished Apr 21 04:06:14 PM PDT 24
Peak memory 198088 kb
Host smart-d7bd5309-4e7e-4646-87ba-16b00fc93c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155400885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.3155400885
Directory /workspace/14.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/14.pwrmgr_glitch.873228932
Short name T238
Test name
Test status
Simulation time 40459416 ps
CPU time 0.63 seconds
Started Apr 21 04:06:14 PM PDT 24
Finished Apr 21 04:06:15 PM PDT 24
Peak memory 197696 kb
Host smart-89771717-0782-401d-be42-2a45246ac823
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873228932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.873228932
Directory /workspace/14.pwrmgr_glitch/latest


Test location /workspace/coverage/default/14.pwrmgr_global_esc.1701274854
Short name T524
Test name
Test status
Simulation time 39356427 ps
CPU time 0.66 seconds
Started Apr 21 04:06:15 PM PDT 24
Finished Apr 21 04:06:16 PM PDT 24
Peak memory 197756 kb
Host smart-1c9ee992-eea0-48db-899a-de4ca5a8f0ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701274854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.1701274854
Directory /workspace/14.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/14.pwrmgr_lowpower_invalid.1764199430
Short name T546
Test name
Test status
Simulation time 274410508 ps
CPU time 0.67 seconds
Started Apr 21 04:06:17 PM PDT 24
Finished Apr 21 04:06:18 PM PDT 24
Peak memory 201000 kb
Host smart-73f17dd1-5375-45b7-a413-db8e6bd490bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764199430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_inval
id.1764199430
Directory /workspace/14.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/14.pwrmgr_lowpower_wakeup_race.4215333516
Short name T335
Test name
Test status
Simulation time 313171103 ps
CPU time 1.02 seconds
Started Apr 21 04:06:10 PM PDT 24
Finished Apr 21 04:06:11 PM PDT 24
Peak memory 199320 kb
Host smart-d0349032-1d1e-437e-91ef-e58ac7cdbe87
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215333516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_w
akeup_race.4215333516
Directory /workspace/14.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/14.pwrmgr_reset.520604391
Short name T206
Test name
Test status
Simulation time 42700332 ps
CPU time 0.75 seconds
Started Apr 21 04:06:11 PM PDT 24
Finished Apr 21 04:06:12 PM PDT 24
Peak memory 198872 kb
Host smart-5e5f19d3-c2ec-45f6-98fd-c36c8c1c54a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520604391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.520604391
Directory /workspace/14.pwrmgr_reset/latest


Test location /workspace/coverage/default/14.pwrmgr_reset_invalid.1749975724
Short name T699
Test name
Test status
Simulation time 101789655 ps
CPU time 1 seconds
Started Apr 21 04:06:17 PM PDT 24
Finished Apr 21 04:06:18 PM PDT 24
Peak memory 209204 kb
Host smart-b55a6650-b714-4e2e-821a-a62812bc732c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749975724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.1749975724
Directory /workspace/14.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.1106959581
Short name T624
Test name
Test status
Simulation time 335775529 ps
CPU time 1.13 seconds
Started Apr 21 04:06:13 PM PDT 24
Finished Apr 21 04:06:14 PM PDT 24
Peak memory 200456 kb
Host smart-39e8205f-436a-4b8e-8319-b6cd69135dea
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106959581 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_
cm_ctrl_config_regwen.1106959581
Directory /workspace/14.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1817503319
Short name T413
Test name
Test status
Simulation time 948746349 ps
CPU time 3.32 seconds
Started Apr 21 04:06:14 PM PDT 24
Finished Apr 21 04:06:18 PM PDT 24
Peak memory 200684 kb
Host smart-76627d49-ddae-4910-90a2-67aafcb3b956
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817503319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1817503319
Directory /workspace/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3967001584
Short name T675
Test name
Test status
Simulation time 966215815 ps
CPU time 2.14 seconds
Started Apr 21 04:06:15 PM PDT 24
Finished Apr 21 04:06:17 PM PDT 24
Peak memory 200848 kb
Host smart-0422dc50-e452-4a8f-a70f-9da3cb2a329f
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967001584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3967001584
Directory /workspace/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.229302991
Short name T876
Test name
Test status
Simulation time 173303911 ps
CPU time 0.94 seconds
Started Apr 21 04:06:15 PM PDT 24
Finished Apr 21 04:06:16 PM PDT 24
Peak memory 198864 kb
Host smart-87aff40e-c192-4d55-b6f0-0f8bd58b6270
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229302991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig_
mubi.229302991
Directory /workspace/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/14.pwrmgr_smoke.3858633977
Short name T651
Test name
Test status
Simulation time 29473583 ps
CPU time 0.73 seconds
Started Apr 21 04:06:12 PM PDT 24
Finished Apr 21 04:06:13 PM PDT 24
Peak memory 199012 kb
Host smart-bfd50ddb-95d4-480a-9b6e-4417552c8fa5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858633977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.3858633977
Directory /workspace/14.pwrmgr_smoke/latest


Test location /workspace/coverage/default/14.pwrmgr_stress_all_with_rand_reset.1548179081
Short name T99
Test name
Test status
Simulation time 7317807364 ps
CPU time 22.61 seconds
Started Apr 21 04:06:17 PM PDT 24
Finished Apr 21 04:06:39 PM PDT 24
Peak memory 201028 kb
Host smart-d56f70aa-94c7-45df-b277-658ee03a20e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548179081 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all_with_rand_reset.1548179081
Directory /workspace/14.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/14.pwrmgr_wakeup.3434767547
Short name T182
Test name
Test status
Simulation time 147132658 ps
CPU time 0.8 seconds
Started Apr 21 04:06:11 PM PDT 24
Finished Apr 21 04:06:12 PM PDT 24
Peak memory 198244 kb
Host smart-f0c34777-2893-4676-98f7-bced8dd9a02b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434767547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.3434767547
Directory /workspace/14.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/14.pwrmgr_wakeup_reset.2979059474
Short name T32
Test name
Test status
Simulation time 288930855 ps
CPU time 1.6 seconds
Started Apr 21 04:06:12 PM PDT 24
Finished Apr 21 04:06:14 PM PDT 24
Peak memory 200852 kb
Host smart-0c672c45-1407-4cd2-9b3d-0c2f6850f2de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979059474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.2979059474
Directory /workspace/14.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/15.pwrmgr_aborted_low_power.3539156986
Short name T605
Test name
Test status
Simulation time 58100087 ps
CPU time 0.83 seconds
Started Apr 21 04:06:17 PM PDT 24
Finished Apr 21 04:06:18 PM PDT 24
Peak memory 198556 kb
Host smart-64c39fef-7832-4bcc-afb7-63820129806f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539156986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.3539156986
Directory /workspace/15.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.1706785003
Short name T686
Test name
Test status
Simulation time 28548718 ps
CPU time 0.66 seconds
Started Apr 21 04:06:18 PM PDT 24
Finished Apr 21 04:06:19 PM PDT 24
Peak memory 197604 kb
Host smart-2d9f962b-8ca6-4266-a405-72ec8eb46b94
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706785003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst
_malfunc.1706785003
Directory /workspace/15.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/15.pwrmgr_escalation_timeout.4240454167
Short name T314
Test name
Test status
Simulation time 337398729 ps
CPU time 1.02 seconds
Started Apr 21 04:06:21 PM PDT 24
Finished Apr 21 04:06:22 PM PDT 24
Peak memory 197792 kb
Host smart-80db3129-f537-4eae-b2c0-dce4e4df05bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240454167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.4240454167
Directory /workspace/15.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/15.pwrmgr_glitch.135118012
Short name T390
Test name
Test status
Simulation time 134203607 ps
CPU time 0.61 seconds
Started Apr 21 04:06:18 PM PDT 24
Finished Apr 21 04:06:19 PM PDT 24
Peak memory 197824 kb
Host smart-7b816a4b-042a-4461-9ea2-f6a184540b72
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135118012 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.135118012
Directory /workspace/15.pwrmgr_glitch/latest


Test location /workspace/coverage/default/15.pwrmgr_global_esc.767966429
Short name T336
Test name
Test status
Simulation time 47319564 ps
CPU time 0.7 seconds
Started Apr 21 04:06:19 PM PDT 24
Finished Apr 21 04:06:20 PM PDT 24
Peak memory 197776 kb
Host smart-7f32248e-c253-441c-8820-f3414cc10727
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767966429 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.767966429
Directory /workspace/15.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/15.pwrmgr_lowpower_invalid.4010465038
Short name T670
Test name
Test status
Simulation time 70597648 ps
CPU time 0.68 seconds
Started Apr 21 04:06:17 PM PDT 24
Finished Apr 21 04:06:18 PM PDT 24
Peak memory 200808 kb
Host smart-a1eb2085-67d6-405a-8743-865715c6d1d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010465038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_inval
id.4010465038
Directory /workspace/15.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/15.pwrmgr_lowpower_wakeup_race.1993284074
Short name T701
Test name
Test status
Simulation time 372334087 ps
CPU time 1.23 seconds
Started Apr 21 04:06:17 PM PDT 24
Finished Apr 21 04:06:18 PM PDT 24
Peak memory 199240 kb
Host smart-7772c63e-a97b-4052-8bbd-c3fe4d400cb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993284074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_w
akeup_race.1993284074
Directory /workspace/15.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/15.pwrmgr_reset.1817705942
Short name T655
Test name
Test status
Simulation time 352130105 ps
CPU time 0.87 seconds
Started Apr 21 04:06:17 PM PDT 24
Finished Apr 21 04:06:18 PM PDT 24
Peak memory 198848 kb
Host smart-c55e696a-181c-426d-9982-486fe12ef1c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817705942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.1817705942
Directory /workspace/15.pwrmgr_reset/latest


Test location /workspace/coverage/default/15.pwrmgr_reset_invalid.11660954
Short name T340
Test name
Test status
Simulation time 214720854 ps
CPU time 0.77 seconds
Started Apr 21 04:06:26 PM PDT 24
Finished Apr 21 04:06:27 PM PDT 24
Peak memory 209200 kb
Host smart-c72afcc8-daf0-422b-8bd7-24fba3adfd8a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11660954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.11660954
Directory /workspace/15.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.269248781
Short name T231
Test name
Test status
Simulation time 288750849 ps
CPU time 0.99 seconds
Started Apr 21 04:06:26 PM PDT 24
Finished Apr 21 04:06:28 PM PDT 24
Peak memory 199860 kb
Host smart-b414d881-ba45-42b6-8d9e-6239ad0fd253
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269248781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_c
m_ctrl_config_regwen.269248781
Directory /workspace/15.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3752044238
Short name T385
Test name
Test status
Simulation time 1742251503 ps
CPU time 2.26 seconds
Started Apr 21 04:06:20 PM PDT 24
Finished Apr 21 04:06:22 PM PDT 24
Peak memory 200800 kb
Host smart-7d3ce2b6-5787-478b-bcda-9b42adc9a496
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752044238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3752044238
Directory /workspace/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1474922980
Short name T794
Test name
Test status
Simulation time 830083163 ps
CPU time 3.44 seconds
Started Apr 21 04:06:19 PM PDT 24
Finished Apr 21 04:06:23 PM PDT 24
Peak memory 200904 kb
Host smart-46c16d98-c885-4e16-82bf-b782946a1e3b
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474922980 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1474922980
Directory /workspace/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.4116348760
Short name T392
Test name
Test status
Simulation time 59535215 ps
CPU time 0.85 seconds
Started Apr 21 04:06:25 PM PDT 24
Finished Apr 21 04:06:26 PM PDT 24
Peak memory 198800 kb
Host smart-c7c8b373-407b-4b63-9d42-5c59eaa4bea0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116348760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4116348760
Directory /workspace/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/15.pwrmgr_smoke.3004552893
Short name T763
Test name
Test status
Simulation time 43645227 ps
CPU time 0.72 seconds
Started Apr 21 04:06:16 PM PDT 24
Finished Apr 21 04:06:17 PM PDT 24
Peak memory 198168 kb
Host smart-59dd84f8-586f-4cd6-a1aa-e44b37c1af92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004552893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.3004552893
Directory /workspace/15.pwrmgr_smoke/latest


Test location /workspace/coverage/default/15.pwrmgr_stress_all.557730983
Short name T961
Test name
Test status
Simulation time 2502650066 ps
CPU time 5.86 seconds
Started Apr 21 04:06:21 PM PDT 24
Finished Apr 21 04:06:27 PM PDT 24
Peak memory 201000 kb
Host smart-414434d0-71a5-4281-a560-dacf527bbef6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557730983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.557730983
Directory /workspace/15.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/15.pwrmgr_stress_all_with_rand_reset.3593558679
Short name T419
Test name
Test status
Simulation time 5018708452 ps
CPU time 10.78 seconds
Started Apr 21 04:06:28 PM PDT 24
Finished Apr 21 04:06:39 PM PDT 24
Peak memory 201104 kb
Host smart-b9333e3f-f196-4831-94c8-88d4bb02931e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593558679 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all_with_rand_reset.3593558679
Directory /workspace/15.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/15.pwrmgr_wakeup.1429998755
Short name T309
Test name
Test status
Simulation time 50648530 ps
CPU time 0.81 seconds
Started Apr 21 04:06:18 PM PDT 24
Finished Apr 21 04:06:19 PM PDT 24
Peak memory 198736 kb
Host smart-ea43b59e-b3e5-4d08-9fcd-8a5859b15499
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429998755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.1429998755
Directory /workspace/15.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/15.pwrmgr_wakeup_reset.3987350104
Short name T516
Test name
Test status
Simulation time 105625756 ps
CPU time 0.93 seconds
Started Apr 21 04:06:18 PM PDT 24
Finished Apr 21 04:06:20 PM PDT 24
Peak memory 199024 kb
Host smart-b128da7c-56ff-4bd3-ba8e-8a365c53a8ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987350104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.3987350104
Directory /workspace/15.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/16.pwrmgr_aborted_low_power.2867146298
Short name T15
Test name
Test status
Simulation time 26241879 ps
CPU time 0.85 seconds
Started Apr 21 04:06:24 PM PDT 24
Finished Apr 21 04:06:25 PM PDT 24
Peak memory 199420 kb
Host smart-3f0df9ac-8610-4ffd-81ec-238c35ce5560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867146298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.2867146298
Directory /workspace/16.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/16.pwrmgr_disable_rom_integrity_check.2051843241
Short name T446
Test name
Test status
Simulation time 145163089 ps
CPU time 0.74 seconds
Started Apr 21 04:06:24 PM PDT 24
Finished Apr 21 04:06:25 PM PDT 24
Peak memory 198428 kb
Host smart-3adcb25f-b8a2-46a4-aa0d-772fc5be9cf6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051843241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_dis
able_rom_integrity_check.2051843241
Directory /workspace/16.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.3419183269
Short name T278
Test name
Test status
Simulation time 30897909 ps
CPU time 0.65 seconds
Started Apr 21 04:06:30 PM PDT 24
Finished Apr 21 04:06:31 PM PDT 24
Peak memory 196952 kb
Host smart-8428a268-cca8-440b-ac68-acd23f757391
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419183269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst
_malfunc.3419183269
Directory /workspace/16.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/16.pwrmgr_escalation_timeout.3683009245
Short name T8
Test name
Test status
Simulation time 165237563 ps
CPU time 0.96 seconds
Started Apr 21 04:06:22 PM PDT 24
Finished Apr 21 04:06:24 PM PDT 24
Peak memory 197804 kb
Host smart-93d01a0d-0a47-4aef-b178-3dafb0f233aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683009245 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.3683009245
Directory /workspace/16.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/16.pwrmgr_glitch.1717390130
Short name T595
Test name
Test status
Simulation time 69785501 ps
CPU time 0.65 seconds
Started Apr 21 04:06:23 PM PDT 24
Finished Apr 21 04:06:24 PM PDT 24
Peak memory 197656 kb
Host smart-a2d7ccf2-aa45-4192-a4f4-1bc61a3e98a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717390130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.1717390130
Directory /workspace/16.pwrmgr_glitch/latest


Test location /workspace/coverage/default/16.pwrmgr_global_esc.764391316
Short name T764
Test name
Test status
Simulation time 35254393 ps
CPU time 0.61 seconds
Started Apr 21 04:06:30 PM PDT 24
Finished Apr 21 04:06:31 PM PDT 24
Peak memory 197760 kb
Host smart-24bba575-1cfb-42f8-ae02-96bf4c43ea09
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764391316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.764391316
Directory /workspace/16.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/16.pwrmgr_lowpower_invalid.1017650649
Short name T612
Test name
Test status
Simulation time 113008566 ps
CPU time 0.73 seconds
Started Apr 21 04:06:24 PM PDT 24
Finished Apr 21 04:06:25 PM PDT 24
Peak memory 201036 kb
Host smart-6bb93be6-e3ff-406d-97aa-f13fdfee40f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017650649 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_inval
id.1017650649
Directory /workspace/16.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/16.pwrmgr_lowpower_wakeup_race.1462396969
Short name T241
Test name
Test status
Simulation time 107700140 ps
CPU time 0.74 seconds
Started Apr 21 04:06:23 PM PDT 24
Finished Apr 21 04:06:24 PM PDT 24
Peak memory 198192 kb
Host smart-bc12b3d6-355c-4bc2-bf46-06ffc09c7129
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462396969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_w
akeup_race.1462396969
Directory /workspace/16.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/16.pwrmgr_reset.1856010647
Short name T273
Test name
Test status
Simulation time 51537548 ps
CPU time 0.81 seconds
Started Apr 21 04:06:26 PM PDT 24
Finished Apr 21 04:06:27 PM PDT 24
Peak memory 198800 kb
Host smart-bcd72284-39d5-4e4d-b1ea-c8646a3b59e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856010647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.1856010647
Directory /workspace/16.pwrmgr_reset/latest


Test location /workspace/coverage/default/16.pwrmgr_reset_invalid.362980287
Short name T104
Test name
Test status
Simulation time 114940168 ps
CPU time 1 seconds
Started Apr 21 04:06:28 PM PDT 24
Finished Apr 21 04:06:29 PM PDT 24
Peak memory 209052 kb
Host smart-7535310f-714e-4c99-9365-5198b8347489
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362980287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.362980287
Directory /workspace/16.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.3262806638
Short name T619
Test name
Test status
Simulation time 49522780 ps
CPU time 0.66 seconds
Started Apr 21 04:06:22 PM PDT 24
Finished Apr 21 04:06:23 PM PDT 24
Peak memory 198772 kb
Host smart-d60f671d-d4c6-4733-aaea-315d98a211da
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262806638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_
cm_ctrl_config_regwen.3262806638
Directory /workspace/16.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3860237901
Short name T268
Test name
Test status
Simulation time 906222817 ps
CPU time 2.33 seconds
Started Apr 21 04:06:21 PM PDT 24
Finished Apr 21 04:06:23 PM PDT 24
Peak memory 200968 kb
Host smart-bb721478-edb9-459b-8126-0020de3661de
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860237901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3860237901
Directory /workspace/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1983930783
Short name T36
Test name
Test status
Simulation time 1340951231 ps
CPU time 2.14 seconds
Started Apr 21 04:06:26 PM PDT 24
Finished Apr 21 04:06:29 PM PDT 24
Peak memory 200868 kb
Host smart-0b9f2a63-6918-4010-92c9-bc10b48eec93
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983930783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1983930783
Directory /workspace/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.1978030679
Short name T727
Test name
Test status
Simulation time 66634902 ps
CPU time 0.95 seconds
Started Apr 21 04:06:22 PM PDT 24
Finished Apr 21 04:06:24 PM PDT 24
Peak memory 198804 kb
Host smart-66bec634-97b7-4ce6-8f1f-236f5c601172
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978030679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1978030679
Directory /workspace/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/16.pwrmgr_smoke.1495610280
Short name T82
Test name
Test status
Simulation time 31215548 ps
CPU time 0.74 seconds
Started Apr 21 04:06:21 PM PDT 24
Finished Apr 21 04:06:22 PM PDT 24
Peak memory 199028 kb
Host smart-d68a657f-daa7-4ecc-b7dd-5ea0b07d1a7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495610280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.1495610280
Directory /workspace/16.pwrmgr_smoke/latest


Test location /workspace/coverage/default/16.pwrmgr_stress_all.3317981660
Short name T440
Test name
Test status
Simulation time 2249581549 ps
CPU time 2.13 seconds
Started Apr 21 04:06:24 PM PDT 24
Finished Apr 21 04:06:27 PM PDT 24
Peak memory 201024 kb
Host smart-16397f80-2f8e-4bb8-a08f-9b8c72300d21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317981660 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.3317981660
Directory /workspace/16.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/16.pwrmgr_stress_all_with_rand_reset.1151643156
Short name T129
Test name
Test status
Simulation time 1950570780 ps
CPU time 5.76 seconds
Started Apr 21 04:06:23 PM PDT 24
Finished Apr 21 04:06:29 PM PDT 24
Peak memory 201080 kb
Host smart-44897dd1-7597-4802-b8f1-f330e0f58868
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151643156 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all_with_rand_reset.1151643156
Directory /workspace/16.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/16.pwrmgr_wakeup.375333051
Short name T643
Test name
Test status
Simulation time 181023648 ps
CPU time 1.09 seconds
Started Apr 21 04:06:21 PM PDT 24
Finished Apr 21 04:06:23 PM PDT 24
Peak memory 199356 kb
Host smart-efd41ac8-9b5c-490f-a6bc-9a699cbef51c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375333051 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup.375333051
Directory /workspace/16.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/16.pwrmgr_wakeup_reset.2543016983
Short name T526
Test name
Test status
Simulation time 104674375 ps
CPU time 0.87 seconds
Started Apr 21 04:06:22 PM PDT 24
Finished Apr 21 04:06:23 PM PDT 24
Peak memory 198960 kb
Host smart-9acefb50-44a5-4ec8-bc1b-ae547a681e03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543016983 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.2543016983
Directory /workspace/16.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/17.pwrmgr_aborted_low_power.2515736489
Short name T762
Test name
Test status
Simulation time 41679579 ps
CPU time 0.93 seconds
Started Apr 21 04:06:28 PM PDT 24
Finished Apr 21 04:06:29 PM PDT 24
Peak memory 199820 kb
Host smart-68a0db39-f0b7-4b73-98b0-4ae516a8d155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515736489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.2515736489
Directory /workspace/17.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/17.pwrmgr_disable_rom_integrity_check.317546393
Short name T508
Test name
Test status
Simulation time 55405405 ps
CPU time 0.84 seconds
Started Apr 21 04:06:28 PM PDT 24
Finished Apr 21 04:06:29 PM PDT 24
Peak memory 198828 kb
Host smart-579f81b1-475a-410c-b0ab-681114184358
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317546393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_disa
ble_rom_integrity_check.317546393
Directory /workspace/17.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.1411544934
Short name T517
Test name
Test status
Simulation time 32884014 ps
CPU time 0.59 seconds
Started Apr 21 04:06:31 PM PDT 24
Finished Apr 21 04:06:32 PM PDT 24
Peak memory 197668 kb
Host smart-bac1f556-e309-4d62-b72f-e3db7a1f7fc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411544934 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst
_malfunc.1411544934
Directory /workspace/17.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/17.pwrmgr_escalation_timeout.1003925805
Short name T618
Test name
Test status
Simulation time 641411733 ps
CPU time 0.93 seconds
Started Apr 21 04:06:32 PM PDT 24
Finished Apr 21 04:06:33 PM PDT 24
Peak memory 197788 kb
Host smart-ba46c1a2-0d65-4a37-8904-4d7c7d53cf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003925805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.1003925805
Directory /workspace/17.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/17.pwrmgr_glitch.1609042407
Short name T855
Test name
Test status
Simulation time 103977200 ps
CPU time 0.61 seconds
Started Apr 21 04:06:25 PM PDT 24
Finished Apr 21 04:06:26 PM PDT 24
Peak memory 197064 kb
Host smart-09e64f9e-a2dc-447f-a532-5011c11fddf9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609042407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.1609042407
Directory /workspace/17.pwrmgr_glitch/latest


Test location /workspace/coverage/default/17.pwrmgr_global_esc.3229329128
Short name T218
Test name
Test status
Simulation time 31569655 ps
CPU time 0.6 seconds
Started Apr 21 04:06:30 PM PDT 24
Finished Apr 21 04:06:31 PM PDT 24
Peak memory 197744 kb
Host smart-a953d712-5873-42d6-86b1-7609f4cde23b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229329128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.3229329128
Directory /workspace/17.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/17.pwrmgr_lowpower_invalid.2105376805
Short name T755
Test name
Test status
Simulation time 82138131 ps
CPU time 0.71 seconds
Started Apr 21 04:06:27 PM PDT 24
Finished Apr 21 04:06:28 PM PDT 24
Peak memory 200964 kb
Host smart-7b98ec01-9129-40f0-a456-038428cef49e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105376805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_inval
id.2105376805
Directory /workspace/17.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/17.pwrmgr_lowpower_wakeup_race.1146134367
Short name T713
Test name
Test status
Simulation time 267745828 ps
CPU time 0.9 seconds
Started Apr 21 04:06:25 PM PDT 24
Finished Apr 21 04:06:26 PM PDT 24
Peak memory 197992 kb
Host smart-f1ab53f8-370c-456d-b65d-e20c94295885
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146134367 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_w
akeup_race.1146134367
Directory /workspace/17.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/17.pwrmgr_reset_invalid.2696363492
Short name T965
Test name
Test status
Simulation time 143556948 ps
CPU time 0.89 seconds
Started Apr 21 04:06:27 PM PDT 24
Finished Apr 21 04:06:28 PM PDT 24
Peak memory 209092 kb
Host smart-709a8e64-5eeb-417f-a869-c8d7a13d8df3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696363492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.2696363492
Directory /workspace/17.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.3686047985
Short name T785
Test name
Test status
Simulation time 45028747 ps
CPU time 0.76 seconds
Started Apr 21 04:06:26 PM PDT 24
Finished Apr 21 04:06:27 PM PDT 24
Peak memory 198748 kb
Host smart-f00e267f-34ea-40fe-85ef-aa9302a14e50
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686047985 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_
cm_ctrl_config_regwen.3686047985
Directory /workspace/17.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3762624723
Short name T13
Test name
Test status
Simulation time 875374838 ps
CPU time 2.25 seconds
Started Apr 21 04:06:32 PM PDT 24
Finished Apr 21 04:06:35 PM PDT 24
Peak memory 200824 kb
Host smart-2405be32-7a71-47d5-8a02-a5e48ba3047c
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762624723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3762624723
Directory /workspace/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2942687301
Short name T665
Test name
Test status
Simulation time 1119203423 ps
CPU time 2 seconds
Started Apr 21 04:06:32 PM PDT 24
Finished Apr 21 04:06:34 PM PDT 24
Peak memory 200948 kb
Host smart-137aeef3-cdc5-453d-b1bf-5bd211f165cc
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942687301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2942687301
Directory /workspace/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1820276508
Short name T633
Test name
Test status
Simulation time 108615566 ps
CPU time 0.83 seconds
Started Apr 21 04:06:27 PM PDT 24
Finished Apr 21 04:06:28 PM PDT 24
Peak memory 198972 kb
Host smart-c76c3ddc-2db6-4277-a61c-667c9ebd4902
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820276508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1820276508
Directory /workspace/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/17.pwrmgr_smoke.3939687219
Short name T232
Test name
Test status
Simulation time 29974020 ps
CPU time 0.77 seconds
Started Apr 21 04:06:24 PM PDT 24
Finished Apr 21 04:06:25 PM PDT 24
Peak memory 199148 kb
Host smart-06b7c6fd-e559-40e6-9123-eef70c3c9255
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939687219 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.3939687219
Directory /workspace/17.pwrmgr_smoke/latest


Test location /workspace/coverage/default/17.pwrmgr_stress_all.1717253647
Short name T257
Test name
Test status
Simulation time 2516666202 ps
CPU time 8.54 seconds
Started Apr 21 04:06:30 PM PDT 24
Finished Apr 21 04:06:39 PM PDT 24
Peak memory 200968 kb
Host smart-72d85963-e46b-4abb-8e1c-22ed71d94f1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717253647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.1717253647
Directory /workspace/17.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/17.pwrmgr_stress_all_with_rand_reset.1492879788
Short name T91
Test name
Test status
Simulation time 2528688432 ps
CPU time 10.98 seconds
Started Apr 21 04:06:31 PM PDT 24
Finished Apr 21 04:06:42 PM PDT 24
Peak memory 201052 kb
Host smart-6899f27d-db13-42dd-ba32-0eba6682a9f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492879788 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all_with_rand_reset.1492879788
Directory /workspace/17.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/17.pwrmgr_wakeup.2571281746
Short name T56
Test name
Test status
Simulation time 183261579 ps
CPU time 0.91 seconds
Started Apr 21 04:06:24 PM PDT 24
Finished Apr 21 04:06:25 PM PDT 24
Peak memory 198240 kb
Host smart-e1141a20-3f39-4c4f-ad86-634f61114507
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571281746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.2571281746
Directory /workspace/17.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/17.pwrmgr_wakeup_reset.3560315781
Short name T169
Test name
Test status
Simulation time 292561459 ps
CPU time 1.25 seconds
Started Apr 21 04:06:23 PM PDT 24
Finished Apr 21 04:06:25 PM PDT 24
Peak memory 199668 kb
Host smart-60526686-1cad-4683-80ba-90ed60994ae3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560315781 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.3560315781
Directory /workspace/17.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/18.pwrmgr_aborted_low_power.483281547
Short name T654
Test name
Test status
Simulation time 26415825 ps
CPU time 0.7 seconds
Started Apr 21 04:06:29 PM PDT 24
Finished Apr 21 04:06:30 PM PDT 24
Peak memory 198320 kb
Host smart-253dc1f5-d4d2-438d-b484-01f7e4449742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483281547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.483281547
Directory /workspace/18.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/18.pwrmgr_disable_rom_integrity_check.3325639487
Short name T799
Test name
Test status
Simulation time 72258316 ps
CPU time 0.8 seconds
Started Apr 21 04:06:30 PM PDT 24
Finished Apr 21 04:06:31 PM PDT 24
Peak memory 198800 kb
Host smart-bfd6af9c-6a2f-4971-8835-fc0b9f113108
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325639487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_dis
able_rom_integrity_check.3325639487
Directory /workspace/18.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.1664019197
Short name T376
Test name
Test status
Simulation time 31295854 ps
CPU time 0.66 seconds
Started Apr 21 04:06:29 PM PDT 24
Finished Apr 21 04:06:30 PM PDT 24
Peak memory 197696 kb
Host smart-aa6a3ba4-9675-4094-94ce-0fb0e43eb047
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664019197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst
_malfunc.1664019197
Directory /workspace/18.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/18.pwrmgr_escalation_timeout.38671667
Short name T905
Test name
Test status
Simulation time 167403901 ps
CPU time 0.97 seconds
Started Apr 21 04:06:30 PM PDT 24
Finished Apr 21 04:06:32 PM PDT 24
Peak memory 197808 kb
Host smart-818a1eec-7e3a-48d2-8ea0-2b4e5d979696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38671667 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.38671667
Directory /workspace/18.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/18.pwrmgr_glitch.2020674248
Short name T389
Test name
Test status
Simulation time 40836843 ps
CPU time 0.63 seconds
Started Apr 21 04:06:29 PM PDT 24
Finished Apr 21 04:06:30 PM PDT 24
Peak memory 197760 kb
Host smart-6032079c-7527-4445-bf20-587ea4663873
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020674248 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.2020674248
Directory /workspace/18.pwrmgr_glitch/latest


Test location /workspace/coverage/default/18.pwrmgr_global_esc.1969326623
Short name T771
Test name
Test status
Simulation time 41591121 ps
CPU time 0.66 seconds
Started Apr 21 04:06:30 PM PDT 24
Finished Apr 21 04:06:31 PM PDT 24
Peak memory 197732 kb
Host smart-aaea26a5-96d0-40ad-975a-1282f1d772bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969326623 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.1969326623
Directory /workspace/18.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/18.pwrmgr_lowpower_invalid.1219314865
Short name T576
Test name
Test status
Simulation time 69531926 ps
CPU time 0.75 seconds
Started Apr 21 04:06:30 PM PDT 24
Finished Apr 21 04:06:31 PM PDT 24
Peak memory 200972 kb
Host smart-235020a4-67b5-411c-9c53-a9da111d3ce8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219314865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_inval
id.1219314865
Directory /workspace/18.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/18.pwrmgr_lowpower_wakeup_race.1896450776
Short name T888
Test name
Test status
Simulation time 285666130 ps
CPU time 0.84 seconds
Started Apr 21 04:06:32 PM PDT 24
Finished Apr 21 04:06:33 PM PDT 24
Peak memory 199180 kb
Host smart-51473572-be7f-4d97-a5d0-3fdc548e2030
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896450776 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_w
akeup_race.1896450776
Directory /workspace/18.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/18.pwrmgr_reset.3129373956
Short name T253
Test name
Test status
Simulation time 84149850 ps
CPU time 1.01 seconds
Started Apr 21 04:06:27 PM PDT 24
Finished Apr 21 04:06:28 PM PDT 24
Peak memory 199544 kb
Host smart-5b900ba0-2f98-4283-a653-04c5d7ba175d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129373956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.3129373956
Directory /workspace/18.pwrmgr_reset/latest


Test location /workspace/coverage/default/18.pwrmgr_reset_invalid.2552438841
Short name T931
Test name
Test status
Simulation time 112385357 ps
CPU time 1.03 seconds
Started Apr 21 04:06:29 PM PDT 24
Finished Apr 21 04:06:31 PM PDT 24
Peak memory 209148 kb
Host smart-cc23ca6b-7563-41f7-a387-f4db5d6ca236
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552438841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.2552438841
Directory /workspace/18.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.2125172609
Short name T689
Test name
Test status
Simulation time 123310909 ps
CPU time 1.1 seconds
Started Apr 21 04:06:28 PM PDT 24
Finished Apr 21 04:06:30 PM PDT 24
Peak memory 200484 kb
Host smart-185a6b32-76e0-4938-b9dc-f5757c621d44
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125172609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_
cm_ctrl_config_regwen.2125172609
Directory /workspace/18.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.516397648
Short name T673
Test name
Test status
Simulation time 844973487 ps
CPU time 2.52 seconds
Started Apr 21 04:06:30 PM PDT 24
Finished Apr 21 04:06:32 PM PDT 24
Peak memory 200900 kb
Host smart-11d75634-777a-4a0c-8859-1cb8d7042337
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516397648 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.516397648
Directory /workspace/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4171434089
Short name T682
Test name
Test status
Simulation time 1163458358 ps
CPU time 2.32 seconds
Started Apr 21 04:06:32 PM PDT 24
Finished Apr 21 04:06:35 PM PDT 24
Peak memory 200820 kb
Host smart-653290ae-3183-4271-bfa7-56f6cfe40ea2
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171434089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4171434089
Directory /workspace/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.2102419365
Short name T750
Test name
Test status
Simulation time 179489841 ps
CPU time 0.94 seconds
Started Apr 21 04:06:28 PM PDT 24
Finished Apr 21 04:06:30 PM PDT 24
Peak memory 199288 kb
Host smart-16792164-b0c3-4ccd-bf25-3535e6094ea2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102419365 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2102419365
Directory /workspace/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/18.pwrmgr_smoke.836404177
Short name T664
Test name
Test status
Simulation time 177469322 ps
CPU time 0.65 seconds
Started Apr 21 04:06:32 PM PDT 24
Finished Apr 21 04:06:33 PM PDT 24
Peak memory 198120 kb
Host smart-1655bbfd-984f-4237-accc-610330edc1b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836404177 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.836404177
Directory /workspace/18.pwrmgr_smoke/latest


Test location /workspace/coverage/default/18.pwrmgr_stress_all.3350857482
Short name T330
Test name
Test status
Simulation time 1966501579 ps
CPU time 4.54 seconds
Started Apr 21 04:06:33 PM PDT 24
Finished Apr 21 04:06:38 PM PDT 24
Peak memory 200900 kb
Host smart-d1d074b2-f795-4651-ab89-0badd465fe67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350857482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all.3350857482
Directory /workspace/18.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/18.pwrmgr_wakeup.1319490005
Short name T213
Test name
Test status
Simulation time 36058067 ps
CPU time 0.67 seconds
Started Apr 21 04:06:27 PM PDT 24
Finished Apr 21 04:06:28 PM PDT 24
Peak memory 197932 kb
Host smart-b24e55e1-f2a7-473c-82b2-e7c5a03c75a9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319490005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.1319490005
Directory /workspace/18.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/18.pwrmgr_wakeup_reset.2797360665
Short name T918
Test name
Test status
Simulation time 192414180 ps
CPU time 1.22 seconds
Started Apr 21 04:06:29 PM PDT 24
Finished Apr 21 04:06:31 PM PDT 24
Peak memory 199836 kb
Host smart-fa66ede6-0549-47b5-8464-9908ae6921cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797360665 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.2797360665
Directory /workspace/18.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/19.pwrmgr_aborted_low_power.1850030353
Short name T749
Test name
Test status
Simulation time 51843436 ps
CPU time 0.78 seconds
Started Apr 21 04:06:36 PM PDT 24
Finished Apr 21 04:06:37 PM PDT 24
Peak memory 198572 kb
Host smart-6048544b-33a6-4fd7-aa0e-2244f46e6213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850030353 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.1850030353
Directory /workspace/19.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/19.pwrmgr_disable_rom_integrity_check.4281810915
Short name T323
Test name
Test status
Simulation time 52095224 ps
CPU time 0.81 seconds
Started Apr 21 04:06:34 PM PDT 24
Finished Apr 21 04:06:36 PM PDT 24
Peak memory 198840 kb
Host smart-e69bcd44-d597-46d2-b602-9ee0516c1aef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281810915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_dis
able_rom_integrity_check.4281810915
Directory /workspace/19.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.3180217505
Short name T178
Test name
Test status
Simulation time 38612785 ps
CPU time 0.61 seconds
Started Apr 21 04:06:33 PM PDT 24
Finished Apr 21 04:06:33 PM PDT 24
Peak memory 197724 kb
Host smart-7e51bc9b-29ad-451a-92f5-b67be3c73996
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180217505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst
_malfunc.3180217505
Directory /workspace/19.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/19.pwrmgr_escalation_timeout.1771366382
Short name T444
Test name
Test status
Simulation time 317613890 ps
CPU time 0.94 seconds
Started Apr 21 04:06:35 PM PDT 24
Finished Apr 21 04:06:36 PM PDT 24
Peak memory 197748 kb
Host smart-e7f85b75-313e-45c8-9a8d-64ff4ac2ae98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771366382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.1771366382
Directory /workspace/19.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/19.pwrmgr_glitch.215065898
Short name T343
Test name
Test status
Simulation time 72802173 ps
CPU time 0.64 seconds
Started Apr 21 04:06:39 PM PDT 24
Finished Apr 21 04:06:41 PM PDT 24
Peak memory 197552 kb
Host smart-9b885c3d-97fa-4092-8b41-5db6113eceb8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215065898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.215065898
Directory /workspace/19.pwrmgr_glitch/latest


Test location /workspace/coverage/default/19.pwrmgr_global_esc.3908644346
Short name T933
Test name
Test status
Simulation time 34158181 ps
CPU time 0.64 seconds
Started Apr 21 04:06:35 PM PDT 24
Finished Apr 21 04:06:36 PM PDT 24
Peak memory 197732 kb
Host smart-872cd21d-cd25-4fff-83ab-cea1f84ac6a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908644346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.3908644346
Directory /workspace/19.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/19.pwrmgr_lowpower_invalid.1934628006
Short name T48
Test name
Test status
Simulation time 56377475 ps
CPU time 0.77 seconds
Started Apr 21 04:06:34 PM PDT 24
Finished Apr 21 04:06:36 PM PDT 24
Peak memory 201020 kb
Host smart-db157509-a884-461f-888a-11e9f30b9598
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934628006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_inval
id.1934628006
Directory /workspace/19.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/19.pwrmgr_lowpower_wakeup_race.1287006043
Short name T472
Test name
Test status
Simulation time 120946488 ps
CPU time 0.7 seconds
Started Apr 21 04:06:36 PM PDT 24
Finished Apr 21 04:06:37 PM PDT 24
Peak memory 198116 kb
Host smart-22bba63b-117f-4c3b-ab0b-9a872882cc6f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287006043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_w
akeup_race.1287006043
Directory /workspace/19.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/19.pwrmgr_reset.1566694715
Short name T571
Test name
Test status
Simulation time 47014592 ps
CPU time 0.68 seconds
Started Apr 21 04:06:35 PM PDT 24
Finished Apr 21 04:06:36 PM PDT 24
Peak memory 198036 kb
Host smart-2cc9e680-7b83-4b5b-90c7-ceede777b7ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566694715 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.1566694715
Directory /workspace/19.pwrmgr_reset/latest


Test location /workspace/coverage/default/19.pwrmgr_reset_invalid.795229498
Short name T100
Test name
Test status
Simulation time 226539933 ps
CPU time 0.79 seconds
Started Apr 21 04:06:36 PM PDT 24
Finished Apr 21 04:06:37 PM PDT 24
Peak memory 209140 kb
Host smart-c2dd17f0-a8ac-4f6a-936e-e9032131dfa1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795229498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.795229498
Directory /workspace/19.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.2536929307
Short name T262
Test name
Test status
Simulation time 346551672 ps
CPU time 1.4 seconds
Started Apr 21 04:06:34 PM PDT 24
Finished Apr 21 04:06:35 PM PDT 24
Peak memory 200660 kb
Host smart-1ad7f2e3-32fe-472d-9f94-e70042061581
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536929307 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_
cm_ctrl_config_regwen.2536929307
Directory /workspace/19.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.197145561
Short name T951
Test name
Test status
Simulation time 844673924 ps
CPU time 2.38 seconds
Started Apr 21 04:06:34 PM PDT 24
Finished Apr 21 04:06:37 PM PDT 24
Peak memory 200916 kb
Host smart-181924a5-d2e6-4961-972d-4e513f789938
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197145561 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.197145561
Directory /workspace/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2648277778
Short name T677
Test name
Test status
Simulation time 798153240 ps
CPU time 3.24 seconds
Started Apr 21 04:06:35 PM PDT 24
Finished Apr 21 04:06:39 PM PDT 24
Peak memory 200912 kb
Host smart-935ff424-6f93-41ad-bbcc-d9044ebb2f8c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648277778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2648277778
Directory /workspace/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.2118705657
Short name T377
Test name
Test status
Simulation time 51207689 ps
CPU time 0.9 seconds
Started Apr 21 04:06:30 PM PDT 24
Finished Apr 21 04:06:31 PM PDT 24
Peak memory 198816 kb
Host smart-518fbeb7-c2bd-40f3-883b-d79cdb59a581
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118705657 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2118705657
Directory /workspace/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/19.pwrmgr_smoke.1468773880
Short name T641
Test name
Test status
Simulation time 58480034 ps
CPU time 0.7 seconds
Started Apr 21 04:06:32 PM PDT 24
Finished Apr 21 04:06:33 PM PDT 24
Peak memory 198136 kb
Host smart-b4be71a4-f972-4449-8663-bbb9ed7e0354
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468773880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.1468773880
Directory /workspace/19.pwrmgr_smoke/latest


Test location /workspace/coverage/default/19.pwrmgr_stress_all.3473720529
Short name T87
Test name
Test status
Simulation time 369714437 ps
CPU time 2.51 seconds
Started Apr 21 04:06:39 PM PDT 24
Finished Apr 21 04:06:42 PM PDT 24
Peak memory 200848 kb
Host smart-5d6bf7b3-586f-403a-ae6b-5e29fbb58ee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473720529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all.3473720529
Directory /workspace/19.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/19.pwrmgr_stress_all_with_rand_reset.3076758870
Short name T138
Test name
Test status
Simulation time 13058029858 ps
CPU time 28.5 seconds
Started Apr 21 04:06:33 PM PDT 24
Finished Apr 21 04:07:02 PM PDT 24
Peak memory 201024 kb
Host smart-8fead714-ebed-492b-8309-370fbdd46b22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076758870 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all_with_rand_reset.3076758870
Directory /workspace/19.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/19.pwrmgr_wakeup.2412747707
Short name T704
Test name
Test status
Simulation time 27976096 ps
CPU time 0.73 seconds
Started Apr 21 04:06:31 PM PDT 24
Finished Apr 21 04:06:32 PM PDT 24
Peak memory 198164 kb
Host smart-246e0b6c-53b9-4d9c-ae6c-67f3d46a0ea3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412747707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.2412747707
Directory /workspace/19.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/19.pwrmgr_wakeup_reset.916997831
Short name T345
Test name
Test status
Simulation time 338940244 ps
CPU time 1.05 seconds
Started Apr 21 04:06:33 PM PDT 24
Finished Apr 21 04:06:35 PM PDT 24
Peak memory 199828 kb
Host smart-fa316bf6-a787-49ff-bef9-a94922524d7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916997831 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.916997831
Directory /workspace/19.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/2.pwrmgr_aborted_low_power.3157587254
Short name T698
Test name
Test status
Simulation time 33055843 ps
CPU time 0.78 seconds
Started Apr 21 04:05:23 PM PDT 24
Finished Apr 21 04:05:24 PM PDT 24
Peak memory 199028 kb
Host smart-f7d720f6-e723-468d-8da1-ce82238959c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157587254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.3157587254
Directory /workspace/2.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.373015650
Short name T863
Test name
Test status
Simulation time 29725949 ps
CPU time 0.65 seconds
Started Apr 21 04:05:24 PM PDT 24
Finished Apr 21 04:05:25 PM PDT 24
Peak memory 196916 kb
Host smart-67f0b9fd-6122-4d27-a3c4-684506625956
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373015650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_m
alfunc.373015650
Directory /workspace/2.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/2.pwrmgr_escalation_timeout.2625481483
Short name T220
Test name
Test status
Simulation time 169541072 ps
CPU time 1.09 seconds
Started Apr 21 04:05:24 PM PDT 24
Finished Apr 21 04:05:26 PM PDT 24
Peak memory 198104 kb
Host smart-ce58cce0-5a2c-45ea-8bed-bd3ae7f2acbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625481483 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.2625481483
Directory /workspace/2.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/2.pwrmgr_glitch.2749178141
Short name T328
Test name
Test status
Simulation time 37685159 ps
CPU time 0.67 seconds
Started Apr 21 04:05:24 PM PDT 24
Finished Apr 21 04:05:25 PM PDT 24
Peak memory 197752 kb
Host smart-e70d6e52-71f6-438b-9072-88fe6f753852
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749178141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.2749178141
Directory /workspace/2.pwrmgr_glitch/latest


Test location /workspace/coverage/default/2.pwrmgr_global_esc.1597060654
Short name T797
Test name
Test status
Simulation time 107174225 ps
CPU time 0.64 seconds
Started Apr 21 04:05:28 PM PDT 24
Finished Apr 21 04:05:29 PM PDT 24
Peak memory 197768 kb
Host smart-d5125796-8f7d-4c1f-8100-7f5eaf0eccaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597060654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.1597060654
Directory /workspace/2.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/2.pwrmgr_lowpower_invalid.1473504774
Short name T265
Test name
Test status
Simulation time 74861558 ps
CPU time 0.69 seconds
Started Apr 21 04:05:25 PM PDT 24
Finished Apr 21 04:05:26 PM PDT 24
Peak memory 201028 kb
Host smart-d1046a25-db4e-4b19-bf1b-6178cde59207
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473504774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invali
d.1473504774
Directory /workspace/2.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/2.pwrmgr_lowpower_wakeup_race.1547011375
Short name T85
Test name
Test status
Simulation time 359667665 ps
CPU time 1.2 seconds
Started Apr 21 04:05:23 PM PDT 24
Finished Apr 21 04:05:24 PM PDT 24
Peak memory 199200 kb
Host smart-7ad902e0-d4cd-4900-894f-5aa03c91f183
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547011375 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wa
keup_race.1547011375
Directory /workspace/2.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/2.pwrmgr_reset.188919342
Short name T312
Test name
Test status
Simulation time 53100183 ps
CPU time 0.83 seconds
Started Apr 21 04:05:25 PM PDT 24
Finished Apr 21 04:05:27 PM PDT 24
Peak memory 198316 kb
Host smart-5c23a349-f2d9-44b1-bdbc-64492badc23f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188919342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.188919342
Directory /workspace/2.pwrmgr_reset/latest


Test location /workspace/coverage/default/2.pwrmgr_reset_invalid.1321344425
Short name T777
Test name
Test status
Simulation time 140223756 ps
CPU time 0.79 seconds
Started Apr 21 04:05:29 PM PDT 24
Finished Apr 21 04:05:30 PM PDT 24
Peak memory 209076 kb
Host smart-17efdb0a-898c-446e-88b1-50506e995df0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321344425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.1321344425
Directory /workspace/2.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/2.pwrmgr_sec_cm.1151066836
Short name T29
Test name
Test status
Simulation time 626231948 ps
CPU time 2.08 seconds
Started Apr 21 04:05:27 PM PDT 24
Finished Apr 21 04:05:29 PM PDT 24
Peak memory 216548 kb
Host smart-8742772d-6a60-4a37-a890-844028b4f507
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151066836 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.1151066836
Directory /workspace/2.pwrmgr_sec_cm/latest


Test location /workspace/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.3708698723
Short name T687
Test name
Test status
Simulation time 98508587 ps
CPU time 0.71 seconds
Started Apr 21 04:05:27 PM PDT 24
Finished Apr 21 04:05:28 PM PDT 24
Peak memory 198752 kb
Host smart-985c7f56-cc04-4ea6-9fff-5e299f10f776
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708698723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_c
m_ctrl_config_regwen.3708698723
Directory /workspace/2.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4268201480
Short name T880
Test name
Test status
Simulation time 1088608682 ps
CPU time 2.26 seconds
Started Apr 21 04:05:25 PM PDT 24
Finished Apr 21 04:05:27 PM PDT 24
Peak memory 200956 kb
Host smart-09288610-21a3-46e2-873f-d4d5d915ec68
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268201480 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4268201480
Directory /workspace/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2516977506
Short name T282
Test name
Test status
Simulation time 908411697 ps
CPU time 3.52 seconds
Started Apr 21 04:05:24 PM PDT 24
Finished Apr 21 04:05:28 PM PDT 24
Peak memory 200904 kb
Host smart-f61c98ee-6091-4d16-a2e2-f7bc9d2559ad
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516977506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2516977506
Directory /workspace/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.2831570547
Short name T854
Test name
Test status
Simulation time 182259739 ps
CPU time 0.9 seconds
Started Apr 21 04:05:24 PM PDT 24
Finished Apr 21 04:05:26 PM PDT 24
Peak memory 198828 kb
Host smart-1b336169-003a-42ae-9506-6acfeb6dfdfb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831570547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2831570547
Directory /workspace/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/2.pwrmgr_smoke.3677919150
Short name T486
Test name
Test status
Simulation time 29570204 ps
CPU time 0.71 seconds
Started Apr 21 04:05:22 PM PDT 24
Finished Apr 21 04:05:23 PM PDT 24
Peak memory 199144 kb
Host smart-f4ba4b2f-8a0d-4857-a8ec-828f4e7cee71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677919150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.3677919150
Directory /workspace/2.pwrmgr_smoke/latest


Test location /workspace/coverage/default/2.pwrmgr_stress_all.4163349690
Short name T649
Test name
Test status
Simulation time 818771554 ps
CPU time 1.63 seconds
Started Apr 21 04:05:26 PM PDT 24
Finished Apr 21 04:05:28 PM PDT 24
Peak memory 200716 kb
Host smart-d59f93bf-b44e-4c0d-980c-fecf477d23c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163349690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.4163349690
Directory /workspace/2.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/2.pwrmgr_stress_all_with_rand_reset.2379911006
Short name T751
Test name
Test status
Simulation time 9371225110 ps
CPU time 10.01 seconds
Started Apr 21 04:05:26 PM PDT 24
Finished Apr 21 04:05:36 PM PDT 24
Peak memory 201072 kb
Host smart-0c2de75c-af5e-4fb3-8dac-68b1899cdf00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379911006 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all_with_rand_reset.2379911006
Directory /workspace/2.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/2.pwrmgr_wakeup.3310571407
Short name T298
Test name
Test status
Simulation time 49857212 ps
CPU time 0.69 seconds
Started Apr 21 04:05:31 PM PDT 24
Finished Apr 21 04:05:32 PM PDT 24
Peak memory 197904 kb
Host smart-cb0674af-4042-4d33-a96f-1c0bb70ae7e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310571407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.3310571407
Directory /workspace/2.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/2.pwrmgr_wakeup_reset.1085469511
Short name T577
Test name
Test status
Simulation time 188365784 ps
CPU time 1.05 seconds
Started Apr 21 04:05:28 PM PDT 24
Finished Apr 21 04:05:30 PM PDT 24
Peak memory 199612 kb
Host smart-6cfaa2c7-528c-42f2-af8b-bb366d1f291e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085469511 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.1085469511
Directory /workspace/2.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/20.pwrmgr_aborted_low_power.2497208591
Short name T921
Test name
Test status
Simulation time 71745938 ps
CPU time 0.81 seconds
Started Apr 21 04:06:36 PM PDT 24
Finished Apr 21 04:06:37 PM PDT 24
Peak memory 198360 kb
Host smart-68a3318b-170c-4815-8627-eeb38294e351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497208591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.2497208591
Directory /workspace/20.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/20.pwrmgr_disable_rom_integrity_check.3188500400
Short name T570
Test name
Test status
Simulation time 89564015 ps
CPU time 0.78 seconds
Started Apr 21 04:06:36 PM PDT 24
Finished Apr 21 04:06:38 PM PDT 24
Peak memory 198996 kb
Host smart-a6d465f9-2714-4308-92d8-833709cd9852
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188500400 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_dis
able_rom_integrity_check.3188500400
Directory /workspace/20.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.1666793713
Short name T284
Test name
Test status
Simulation time 30410332 ps
CPU time 0.65 seconds
Started Apr 21 04:06:39 PM PDT 24
Finished Apr 21 04:06:40 PM PDT 24
Peak memory 197772 kb
Host smart-761dae24-9abe-46cd-9686-b12efab27d57
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666793713 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst
_malfunc.1666793713
Directory /workspace/20.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/20.pwrmgr_escalation_timeout.3570673540
Short name T533
Test name
Test status
Simulation time 1889319546 ps
CPU time 0.99 seconds
Started Apr 21 04:06:38 PM PDT 24
Finished Apr 21 04:06:40 PM PDT 24
Peak memory 197784 kb
Host smart-8879109f-15dc-47f7-8d0e-cfa333dc8168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570673540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.3570673540
Directory /workspace/20.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/20.pwrmgr_glitch.4283444020
Short name T224
Test name
Test status
Simulation time 45376237 ps
CPU time 0.69 seconds
Started Apr 21 04:06:39 PM PDT 24
Finished Apr 21 04:06:40 PM PDT 24
Peak memory 197768 kb
Host smart-840daeaa-10bf-4fbf-92d4-da8158950c89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283444020 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.4283444020
Directory /workspace/20.pwrmgr_glitch/latest


Test location /workspace/coverage/default/20.pwrmgr_global_esc.1616226952
Short name T105
Test name
Test status
Simulation time 89668928 ps
CPU time 0.67 seconds
Started Apr 21 04:06:37 PM PDT 24
Finished Apr 21 04:06:38 PM PDT 24
Peak memory 198100 kb
Host smart-8ca0d117-3ae3-47fa-a040-055d55cdf5c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616226952 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.1616226952
Directory /workspace/20.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/20.pwrmgr_lowpower_invalid.3111413695
Short name T561
Test name
Test status
Simulation time 44298183 ps
CPU time 0.75 seconds
Started Apr 21 04:06:35 PM PDT 24
Finished Apr 21 04:06:36 PM PDT 24
Peak memory 200984 kb
Host smart-b76ccb56-adeb-4cc3-8480-eed52ec92df8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111413695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_inval
id.3111413695
Directory /workspace/20.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/20.pwrmgr_lowpower_wakeup_race.4123920615
Short name T274
Test name
Test status
Simulation time 248098739 ps
CPU time 1.31 seconds
Started Apr 21 04:06:40 PM PDT 24
Finished Apr 21 04:06:41 PM PDT 24
Peak memory 199280 kb
Host smart-45e02a93-8b62-4312-997f-9c57db3b02b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123920615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_w
akeup_race.4123920615
Directory /workspace/20.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/20.pwrmgr_reset.1710676782
Short name T96
Test name
Test status
Simulation time 33590552 ps
CPU time 0.76 seconds
Started Apr 21 04:06:34 PM PDT 24
Finished Apr 21 04:06:35 PM PDT 24
Peak memory 198880 kb
Host smart-932eab3c-2be7-4cf3-8eeb-29733058a98d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710676782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.1710676782
Directory /workspace/20.pwrmgr_reset/latest


Test location /workspace/coverage/default/20.pwrmgr_reset_invalid.2758980183
Short name T41
Test name
Test status
Simulation time 114536723 ps
CPU time 0.97 seconds
Started Apr 21 04:06:41 PM PDT 24
Finished Apr 21 04:06:42 PM PDT 24
Peak memory 209164 kb
Host smart-bb308d1e-5940-4247-807f-cea12a92a797
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758980183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.2758980183
Directory /workspace/20.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.3403873684
Short name T640
Test name
Test status
Simulation time 39782467 ps
CPU time 0.82 seconds
Started Apr 21 04:06:36 PM PDT 24
Finished Apr 21 04:06:38 PM PDT 24
Peak memory 198708 kb
Host smart-8305f840-fca0-4573-8618-5eb525d45e71
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403873684 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_
cm_ctrl_config_regwen.3403873684
Directory /workspace/20.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.448209266
Short name T739
Test name
Test status
Simulation time 868107624 ps
CPU time 3.33 seconds
Started Apr 21 04:06:39 PM PDT 24
Finished Apr 21 04:06:42 PM PDT 24
Peak memory 200800 kb
Host smart-e539285a-816f-4caa-bda4-f1445385a8bf
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448209266 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.448209266
Directory /workspace/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3997488856
Short name T43
Test name
Test status
Simulation time 804188596 ps
CPU time 3.53 seconds
Started Apr 21 04:06:36 PM PDT 24
Finished Apr 21 04:06:40 PM PDT 24
Peak memory 200828 kb
Host smart-39e3dfc2-e52d-496c-b31d-7d5492cc1061
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997488856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3997488856
Directory /workspace/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.1391269923
Short name T716
Test name
Test status
Simulation time 99508344 ps
CPU time 0.88 seconds
Started Apr 21 04:06:38 PM PDT 24
Finished Apr 21 04:06:39 PM PDT 24
Peak memory 198932 kb
Host smart-600b2d15-3a34-4e00-b95a-83a919256719
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391269923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1391269923
Directory /workspace/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/20.pwrmgr_smoke.755156241
Short name T361
Test name
Test status
Simulation time 66323667 ps
CPU time 0.68 seconds
Started Apr 21 04:06:36 PM PDT 24
Finished Apr 21 04:06:37 PM PDT 24
Peak memory 198200 kb
Host smart-24499fd9-2eb4-4239-9518-ce004099c656
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755156241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.755156241
Directory /workspace/20.pwrmgr_smoke/latest


Test location /workspace/coverage/default/20.pwrmgr_stress_all.3463003107
Short name T735
Test name
Test status
Simulation time 2604199322 ps
CPU time 2.53 seconds
Started Apr 21 04:06:41 PM PDT 24
Finished Apr 21 04:06:44 PM PDT 24
Peak memory 201040 kb
Host smart-0a605797-92a2-4d5b-89f2-bf8fa3b098db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463003107 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.3463003107
Directory /workspace/20.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/20.pwrmgr_wakeup.2741097733
Short name T586
Test name
Test status
Simulation time 336756905 ps
CPU time 0.99 seconds
Started Apr 21 04:06:35 PM PDT 24
Finished Apr 21 04:06:37 PM PDT 24
Peak memory 199356 kb
Host smart-f19def20-1124-490b-ad13-ae51e4d2af53
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741097733 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.2741097733
Directory /workspace/20.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/20.pwrmgr_wakeup_reset.1761563508
Short name T197
Test name
Test status
Simulation time 365012619 ps
CPU time 1.66 seconds
Started Apr 21 04:06:37 PM PDT 24
Finished Apr 21 04:06:39 PM PDT 24
Peak memory 200708 kb
Host smart-e5b1f24a-391d-4548-b727-f5aa8b67133c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761563508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.1761563508
Directory /workspace/20.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/21.pwrmgr_aborted_low_power.3925780541
Short name T914
Test name
Test status
Simulation time 36355726 ps
CPU time 0.69 seconds
Started Apr 21 04:06:47 PM PDT 24
Finished Apr 21 04:06:48 PM PDT 24
Peak memory 198260 kb
Host smart-96848a34-6cc6-49f5-baa0-414418c3b80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925780541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.3925780541
Directory /workspace/21.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/21.pwrmgr_disable_rom_integrity_check.3543113568
Short name T700
Test name
Test status
Simulation time 83062292 ps
CPU time 0.74 seconds
Started Apr 21 04:06:41 PM PDT 24
Finished Apr 21 04:06:42 PM PDT 24
Peak memory 198908 kb
Host smart-d56b11d2-604e-4691-86aa-c697abbf6c28
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543113568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_dis
able_rom_integrity_check.3543113568
Directory /workspace/21.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.309727270
Short name T397
Test name
Test status
Simulation time 31798187 ps
CPU time 0.61 seconds
Started Apr 21 04:06:40 PM PDT 24
Finished Apr 21 04:06:41 PM PDT 24
Peak memory 197700 kb
Host smart-2fe20953-0db6-4ed5-8573-9c9474617600
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309727270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst_
malfunc.309727270
Directory /workspace/21.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/21.pwrmgr_escalation_timeout.1818907797
Short name T916
Test name
Test status
Simulation time 884090810 ps
CPU time 1.02 seconds
Started Apr 21 04:06:43 PM PDT 24
Finished Apr 21 04:06:45 PM PDT 24
Peak memory 197768 kb
Host smart-6f172ce3-797e-4980-9b46-bf59cff55008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818907797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.1818907797
Directory /workspace/21.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/21.pwrmgr_glitch.3352389652
Short name T431
Test name
Test status
Simulation time 38583757 ps
CPU time 0.72 seconds
Started Apr 21 04:06:39 PM PDT 24
Finished Apr 21 04:06:41 PM PDT 24
Peak memory 197024 kb
Host smart-c0476601-5eb7-45e4-8ae6-707b1c44ca65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352389652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.3352389652
Directory /workspace/21.pwrmgr_glitch/latest


Test location /workspace/coverage/default/21.pwrmgr_global_esc.2699307819
Short name T463
Test name
Test status
Simulation time 46574966 ps
CPU time 0.61 seconds
Started Apr 21 04:06:43 PM PDT 24
Finished Apr 21 04:06:44 PM PDT 24
Peak memory 197748 kb
Host smart-b2593dde-8d07-40e4-b14d-7a5eac9c4dda
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699307819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.2699307819
Directory /workspace/21.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/21.pwrmgr_lowpower_invalid.1189867627
Short name T774
Test name
Test status
Simulation time 79733358 ps
CPU time 0.7 seconds
Started Apr 21 04:06:39 PM PDT 24
Finished Apr 21 04:06:40 PM PDT 24
Peak memory 201036 kb
Host smart-42f0e727-28a2-4058-9cbf-9735eba6a914
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189867627 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_inval
id.1189867627
Directory /workspace/21.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/21.pwrmgr_lowpower_wakeup_race.3422094740
Short name T304
Test name
Test status
Simulation time 141820058 ps
CPU time 0.73 seconds
Started Apr 21 04:06:43 PM PDT 24
Finished Apr 21 04:06:44 PM PDT 24
Peak memory 197980 kb
Host smart-6b176223-4990-4cd3-bc0d-ed4f291a3254
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422094740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_w
akeup_race.3422094740
Directory /workspace/21.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/21.pwrmgr_reset.1003676305
Short name T770
Test name
Test status
Simulation time 62348724 ps
CPU time 0.85 seconds
Started Apr 21 04:06:41 PM PDT 24
Finished Apr 21 04:06:43 PM PDT 24
Peak memory 198352 kb
Host smart-995443d9-8260-4c78-83f1-f0672ae25637
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003676305 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.1003676305
Directory /workspace/21.pwrmgr_reset/latest


Test location /workspace/coverage/default/21.pwrmgr_reset_invalid.1358129247
Short name T862
Test name
Test status
Simulation time 172741453 ps
CPU time 0.78 seconds
Started Apr 21 04:06:41 PM PDT 24
Finished Apr 21 04:06:42 PM PDT 24
Peak memory 209144 kb
Host smart-4c90de26-a905-45c5-a2de-8efd936e04de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358129247 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.1358129247
Directory /workspace/21.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.3737576191
Short name T887
Test name
Test status
Simulation time 228500537 ps
CPU time 0.97 seconds
Started Apr 21 04:06:38 PM PDT 24
Finished Apr 21 04:06:39 PM PDT 24
Peak memory 199700 kb
Host smart-8c274de5-0d1e-4734-bb4b-afcc384dc622
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737576191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_
cm_ctrl_config_regwen.3737576191
Directory /workspace/21.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.141390518
Short name T562
Test name
Test status
Simulation time 887330357 ps
CPU time 2.67 seconds
Started Apr 21 04:06:39 PM PDT 24
Finished Apr 21 04:06:42 PM PDT 24
Peak memory 200828 kb
Host smart-ff2e5d56-56f6-467f-a5dd-9f97f5870bca
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141390518 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.141390518
Directory /workspace/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3597446566
Short name T788
Test name
Test status
Simulation time 718407283 ps
CPU time 3.28 seconds
Started Apr 21 04:06:39 PM PDT 24
Finished Apr 21 04:06:43 PM PDT 24
Peak memory 200788 kb
Host smart-3c43be91-1089-4e0e-bc66-34fa8a441cd4
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597446566 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3597446566
Directory /workspace/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.1459529809
Short name T934
Test name
Test status
Simulation time 87374896 ps
CPU time 0.88 seconds
Started Apr 21 04:06:39 PM PDT 24
Finished Apr 21 04:06:40 PM PDT 24
Peak memory 198752 kb
Host smart-b0ed31fc-9a7e-409d-8ecd-6b77807d8abe
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459529809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1459529809
Directory /workspace/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/21.pwrmgr_smoke.1354228329
Short name T207
Test name
Test status
Simulation time 38703327 ps
CPU time 0.69 seconds
Started Apr 21 04:06:43 PM PDT 24
Finished Apr 21 04:06:44 PM PDT 24
Peak memory 198980 kb
Host smart-b696c73f-f628-4288-ba51-39fd069cd3a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354228329 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.1354228329
Directory /workspace/21.pwrmgr_smoke/latest


Test location /workspace/coverage/default/21.pwrmgr_stress_all.697067434
Short name T393
Test name
Test status
Simulation time 1257267573 ps
CPU time 3.19 seconds
Started Apr 21 04:06:41 PM PDT 24
Finished Apr 21 04:06:45 PM PDT 24
Peak memory 200936 kb
Host smart-9c92bfb0-d860-46d4-8b2e-154ed90d88f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697067434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.697067434
Directory /workspace/21.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/21.pwrmgr_stress_all_with_rand_reset.3558775786
Short name T53
Test name
Test status
Simulation time 8586596607 ps
CPU time 33.49 seconds
Started Apr 21 04:06:43 PM PDT 24
Finished Apr 21 04:07:16 PM PDT 24
Peak memory 201036 kb
Host smart-6883ca0b-7955-4dbc-8f36-55a429615ea4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558775786 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all_with_rand_reset.3558775786
Directory /workspace/21.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/21.pwrmgr_wakeup.1313384853
Short name T324
Test name
Test status
Simulation time 97195543 ps
CPU time 0.89 seconds
Started Apr 21 04:06:41 PM PDT 24
Finished Apr 21 04:06:42 PM PDT 24
Peak memory 198748 kb
Host smart-4b916797-eec1-4e00-a225-69a5b50a628d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313384853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.1313384853
Directory /workspace/21.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/21.pwrmgr_wakeup_reset.3866111116
Short name T936
Test name
Test status
Simulation time 159007976 ps
CPU time 0.78 seconds
Started Apr 21 04:06:40 PM PDT 24
Finished Apr 21 04:06:41 PM PDT 24
Peak memory 199080 kb
Host smart-1778facf-2011-40a1-9949-0aafcbbfaf03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866111116 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.3866111116
Directory /workspace/21.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/22.pwrmgr_aborted_low_power.3546001604
Short name T536
Test name
Test status
Simulation time 52553280 ps
CPU time 0.96 seconds
Started Apr 21 04:06:42 PM PDT 24
Finished Apr 21 04:06:43 PM PDT 24
Peak memory 199804 kb
Host smart-9a0bacc9-6438-42f0-9884-b0e3fee911d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546001604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.3546001604
Directory /workspace/22.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.2027973611
Short name T598
Test name
Test status
Simulation time 37458758 ps
CPU time 0.61 seconds
Started Apr 21 04:06:41 PM PDT 24
Finished Apr 21 04:06:43 PM PDT 24
Peak memory 197756 kb
Host smart-8d66c302-1382-4e10-b19a-eca0edae0d8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027973611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst
_malfunc.2027973611
Directory /workspace/22.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/22.pwrmgr_escalation_timeout.1572915481
Short name T726
Test name
Test status
Simulation time 631278223 ps
CPU time 0.98 seconds
Started Apr 21 04:06:42 PM PDT 24
Finished Apr 21 04:06:43 PM PDT 24
Peak memory 197768 kb
Host smart-aedbfe3e-57ca-4458-8800-ea6283e0dd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572915481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.1572915481
Directory /workspace/22.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/22.pwrmgr_glitch.3390344588
Short name T212
Test name
Test status
Simulation time 52573043 ps
CPU time 0.59 seconds
Started Apr 21 04:06:43 PM PDT 24
Finished Apr 21 04:06:44 PM PDT 24
Peak memory 197696 kb
Host smart-074e63fa-e925-4146-a59f-da1c4486a681
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390344588 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.3390344588
Directory /workspace/22.pwrmgr_glitch/latest


Test location /workspace/coverage/default/22.pwrmgr_global_esc.3269408903
Short name T429
Test name
Test status
Simulation time 39914974 ps
CPU time 0.64 seconds
Started Apr 21 04:06:41 PM PDT 24
Finished Apr 21 04:06:42 PM PDT 24
Peak memory 198088 kb
Host smart-a2713d04-00f7-45ec-80dd-e66d4e095777
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269408903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.3269408903
Directory /workspace/22.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/22.pwrmgr_lowpower_invalid.1681454688
Short name T418
Test name
Test status
Simulation time 50790357 ps
CPU time 0.72 seconds
Started Apr 21 04:06:45 PM PDT 24
Finished Apr 21 04:06:46 PM PDT 24
Peak memory 201044 kb
Host smart-7a08f0f8-0701-437c-92f4-bc4af2892c29
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681454688 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_inval
id.1681454688
Directory /workspace/22.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/22.pwrmgr_lowpower_wakeup_race.388857476
Short name T189
Test name
Test status
Simulation time 209633613 ps
CPU time 1.28 seconds
Started Apr 21 04:06:44 PM PDT 24
Finished Apr 21 04:06:46 PM PDT 24
Peak memory 199440 kb
Host smart-069cade8-c6b4-4471-8874-d63a9078f4b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388857476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_wa
keup_race.388857476
Directory /workspace/22.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/22.pwrmgr_reset.3794487310
Short name T962
Test name
Test status
Simulation time 40607457 ps
CPU time 0.86 seconds
Started Apr 21 04:06:42 PM PDT 24
Finished Apr 21 04:06:43 PM PDT 24
Peak memory 198864 kb
Host smart-06897e2f-42aa-4c1b-b455-05bb5a0cbe78
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794487310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.3794487310
Directory /workspace/22.pwrmgr_reset/latest


Test location /workspace/coverage/default/22.pwrmgr_reset_invalid.1597899151
Short name T539
Test name
Test status
Simulation time 117173904 ps
CPU time 0.92 seconds
Started Apr 21 04:06:44 PM PDT 24
Finished Apr 21 04:06:45 PM PDT 24
Peak memory 209184 kb
Host smart-37b9aee0-95ec-49c8-90a1-095361c56ef8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597899151 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.1597899151
Directory /workspace/22.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.118369141
Short name T870
Test name
Test status
Simulation time 105837153 ps
CPU time 0.78 seconds
Started Apr 21 04:06:41 PM PDT 24
Finished Apr 21 04:06:43 PM PDT 24
Peak memory 198296 kb
Host smart-4cceafa0-4584-4765-a7b9-b51cddd202d7
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118369141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_c
m_ctrl_config_regwen.118369141
Directory /workspace/22.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3054401854
Short name T191
Test name
Test status
Simulation time 852134097 ps
CPU time 3.11 seconds
Started Apr 21 04:06:42 PM PDT 24
Finished Apr 21 04:06:45 PM PDT 24
Peak memory 200792 kb
Host smart-6d77b2a8-287f-441a-a4d2-4ae427bdcd7d
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054401854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3054401854
Directory /workspace/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.920916895
Short name T386
Test name
Test status
Simulation time 893374540 ps
CPU time 3.26 seconds
Started Apr 21 04:06:42 PM PDT 24
Finished Apr 21 04:06:46 PM PDT 24
Peak memory 200888 kb
Host smart-49ae6c45-39bb-459a-a3f1-897a10d64e87
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920916895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.920916895
Directory /workspace/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.1716722499
Short name T671
Test name
Test status
Simulation time 74218279 ps
CPU time 0.95 seconds
Started Apr 21 04:06:42 PM PDT 24
Finished Apr 21 04:06:43 PM PDT 24
Peak memory 198856 kb
Host smart-cddc8800-6545-4dba-885f-aede0c2f7ed3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716722499 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1716722499
Directory /workspace/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/22.pwrmgr_smoke.2197601394
Short name T482
Test name
Test status
Simulation time 50493403 ps
CPU time 0.65 seconds
Started Apr 21 04:06:43 PM PDT 24
Finished Apr 21 04:06:44 PM PDT 24
Peak memory 198096 kb
Host smart-b5ba1753-2522-4201-b7bd-5cffca2f5290
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197601394 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.2197601394
Directory /workspace/22.pwrmgr_smoke/latest


Test location /workspace/coverage/default/22.pwrmgr_stress_all.2341168779
Short name T849
Test name
Test status
Simulation time 1869412465 ps
CPU time 6.39 seconds
Started Apr 21 04:06:45 PM PDT 24
Finished Apr 21 04:06:52 PM PDT 24
Peak memory 200828 kb
Host smart-1883f066-4ca5-441f-b471-ef39183974e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341168779 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.2341168779
Directory /workspace/22.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/22.pwrmgr_stress_all_with_rand_reset.1065458339
Short name T135
Test name
Test status
Simulation time 4093932165 ps
CPU time 12.1 seconds
Started Apr 21 04:06:45 PM PDT 24
Finished Apr 21 04:06:58 PM PDT 24
Peak memory 201040 kb
Host smart-bac19880-b4a6-4db6-b2c3-546c0f867792
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065458339 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all_with_rand_reset.1065458339
Directory /workspace/22.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/22.pwrmgr_wakeup.71640216
Short name T823
Test name
Test status
Simulation time 165532649 ps
CPU time 0.85 seconds
Started Apr 21 04:06:42 PM PDT 24
Finished Apr 21 04:06:43 PM PDT 24
Peak memory 198056 kb
Host smart-43559798-f69e-4eb6-a77f-2d2513c6cf44
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71640216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup.71640216
Directory /workspace/22.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/22.pwrmgr_wakeup_reset.3827381457
Short name T337
Test name
Test status
Simulation time 326669903 ps
CPU time 1.17 seconds
Started Apr 21 04:06:41 PM PDT 24
Finished Apr 21 04:06:43 PM PDT 24
Peak memory 200000 kb
Host smart-4c9978ea-a30a-4351-803a-8997135f8021
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827381457 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup_reset.3827381457
Directory /workspace/22.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/23.pwrmgr_aborted_low_power.1488426620
Short name T826
Test name
Test status
Simulation time 104713690 ps
CPU time 0.82 seconds
Started Apr 21 04:06:46 PM PDT 24
Finished Apr 21 04:06:48 PM PDT 24
Peak memory 198588 kb
Host smart-2f2cabb4-29f9-4b49-a913-aeb66f954048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488426620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.1488426620
Directory /workspace/23.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/23.pwrmgr_disable_rom_integrity_check.3768166261
Short name T910
Test name
Test status
Simulation time 71864134 ps
CPU time 0.79 seconds
Started Apr 21 04:06:52 PM PDT 24
Finished Apr 21 04:06:53 PM PDT 24
Peak memory 198816 kb
Host smart-6d38fbb6-5bce-418c-a4dc-5ce4bddc14df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768166261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_dis
able_rom_integrity_check.3768166261
Directory /workspace/23.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.2010287892
Short name T435
Test name
Test status
Simulation time 38073868 ps
CPU time 0.6 seconds
Started Apr 21 04:06:46 PM PDT 24
Finished Apr 21 04:06:47 PM PDT 24
Peak memory 197736 kb
Host smart-72cc1cda-49c2-4b1e-a402-847a5db2f456
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010287892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst
_malfunc.2010287892
Directory /workspace/23.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/23.pwrmgr_escalation_timeout.3089484842
Short name T977
Test name
Test status
Simulation time 589772704 ps
CPU time 1.08 seconds
Started Apr 21 04:06:52 PM PDT 24
Finished Apr 21 04:06:54 PM PDT 24
Peak memory 197796 kb
Host smart-f087cc27-f023-4f57-8500-5d8ab427ff90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089484842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.3089484842
Directory /workspace/23.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/23.pwrmgr_glitch.1366640364
Short name T759
Test name
Test status
Simulation time 75500373 ps
CPU time 0.64 seconds
Started Apr 21 04:06:52 PM PDT 24
Finished Apr 21 04:06:53 PM PDT 24
Peak memory 197760 kb
Host smart-5ed85340-e952-43aa-a8e4-4895741c3972
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366640364 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.1366640364
Directory /workspace/23.pwrmgr_glitch/latest


Test location /workspace/coverage/default/23.pwrmgr_global_esc.965496908
Short name T711
Test name
Test status
Simulation time 34889930 ps
CPU time 0.66 seconds
Started Apr 21 04:06:46 PM PDT 24
Finished Apr 21 04:06:47 PM PDT 24
Peak memory 198100 kb
Host smart-0e8e389b-b270-4908-aa1b-f61d21ecf751
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965496908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.965496908
Directory /workspace/23.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/23.pwrmgr_lowpower_invalid.1418368738
Short name T270
Test name
Test status
Simulation time 57031506 ps
CPU time 0.74 seconds
Started Apr 21 04:06:51 PM PDT 24
Finished Apr 21 04:06:52 PM PDT 24
Peak memory 201016 kb
Host smart-aaf63ca9-00cf-4e4e-aff4-529d08737c09
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418368738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_inval
id.1418368738
Directory /workspace/23.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/23.pwrmgr_lowpower_wakeup_race.1772875379
Short name T426
Test name
Test status
Simulation time 48748840 ps
CPU time 0.71 seconds
Started Apr 21 04:06:45 PM PDT 24
Finished Apr 21 04:06:47 PM PDT 24
Peak memory 198768 kb
Host smart-9c1582ab-c7fd-40f3-88c5-6f070f250a11
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772875379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_w
akeup_race.1772875379
Directory /workspace/23.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/23.pwrmgr_reset.981944176
Short name T850
Test name
Test status
Simulation time 156250430 ps
CPU time 0.87 seconds
Started Apr 21 04:06:46 PM PDT 24
Finished Apr 21 04:06:47 PM PDT 24
Peak memory 199500 kb
Host smart-7cc36e5e-1e4a-4195-bcd1-e79230a62494
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981944176 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.981944176
Directory /workspace/23.pwrmgr_reset/latest


Test location /workspace/coverage/default/23.pwrmgr_reset_invalid.237558273
Short name T621
Test name
Test status
Simulation time 170709191 ps
CPU time 0.83 seconds
Started Apr 21 04:06:51 PM PDT 24
Finished Apr 21 04:06:53 PM PDT 24
Peak memory 209140 kb
Host smart-c7a7cfec-beb8-4994-bd86-a579d87bd890
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237558273 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.237558273
Directory /workspace/23.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.785150083
Short name T956
Test name
Test status
Simulation time 118046412 ps
CPU time 0.76 seconds
Started Apr 21 04:06:49 PM PDT 24
Finished Apr 21 04:06:50 PM PDT 24
Peak memory 198272 kb
Host smart-692f6d4e-ccd3-4af7-a229-5b1bccc0493e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785150083 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_c
m_ctrl_config_regwen.785150083
Directory /workspace/23.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.523504011
Short name T541
Test name
Test status
Simulation time 794535171 ps
CPU time 3.28 seconds
Started Apr 21 04:06:46 PM PDT 24
Finished Apr 21 04:06:50 PM PDT 24
Peak memory 200964 kb
Host smart-42e6f386-23e0-46d9-8eb9-ef28df394d3a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523504011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.523504011
Directory /workspace/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2886607216
Short name T668
Test name
Test status
Simulation time 1229496709 ps
CPU time 2.26 seconds
Started Apr 21 04:06:45 PM PDT 24
Finished Apr 21 04:06:48 PM PDT 24
Peak memory 200856 kb
Host smart-db84d916-2360-43eb-a7bb-78f18b411c65
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886607216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2886607216
Directory /workspace/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.1858385484
Short name T911
Test name
Test status
Simulation time 70536041 ps
CPU time 0.89 seconds
Started Apr 21 04:06:47 PM PDT 24
Finished Apr 21 04:06:48 PM PDT 24
Peak memory 198828 kb
Host smart-0ad9ed5c-15e1-4ad1-85f6-af0a8d531463
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858385484 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1858385484
Directory /workspace/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/23.pwrmgr_smoke.3812136988
Short name T558
Test name
Test status
Simulation time 29431179 ps
CPU time 0.69 seconds
Started Apr 21 04:06:44 PM PDT 24
Finished Apr 21 04:06:45 PM PDT 24
Peak memory 199032 kb
Host smart-27e3e372-3593-40ea-95e6-065d08fbb43e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812136988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.3812136988
Directory /workspace/23.pwrmgr_smoke/latest


Test location /workspace/coverage/default/23.pwrmgr_stress_all.2055015442
Short name T781
Test name
Test status
Simulation time 1168806997 ps
CPU time 4.78 seconds
Started Apr 21 04:06:49 PM PDT 24
Finished Apr 21 04:06:54 PM PDT 24
Peak memory 200996 kb
Host smart-bfe6c91b-da7e-4110-bd6f-48691eb074e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055015442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.2055015442
Directory /workspace/23.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/23.pwrmgr_stress_all_with_rand_reset.1462855234
Short name T137
Test name
Test status
Simulation time 28338200017 ps
CPU time 22.28 seconds
Started Apr 21 04:06:50 PM PDT 24
Finished Apr 21 04:07:12 PM PDT 24
Peak memory 201096 kb
Host smart-e794625c-a46e-411b-b183-4b1df0fb1b14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462855234 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all_with_rand_reset.1462855234
Directory /workspace/23.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/23.pwrmgr_wakeup.3823075929
Short name T549
Test name
Test status
Simulation time 97279834 ps
CPU time 0.92 seconds
Started Apr 21 04:06:45 PM PDT 24
Finished Apr 21 04:06:46 PM PDT 24
Peak memory 197992 kb
Host smart-8c6a618c-4b69-4763-939e-d536999fbdaa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823075929 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.3823075929
Directory /workspace/23.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/23.pwrmgr_wakeup_reset.3922489735
Short name T436
Test name
Test status
Simulation time 134845922 ps
CPU time 0.96 seconds
Started Apr 21 04:06:44 PM PDT 24
Finished Apr 21 04:06:45 PM PDT 24
Peak memory 198924 kb
Host smart-c8901771-7c6c-4cc4-8bfc-e917c190fe0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922489735 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.3922489735
Directory /workspace/23.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/24.pwrmgr_aborted_low_power.2221065292
Short name T525
Test name
Test status
Simulation time 107268332 ps
CPU time 0.85 seconds
Started Apr 21 04:06:49 PM PDT 24
Finished Apr 21 04:06:50 PM PDT 24
Peak memory 199700 kb
Host smart-af640f06-6e8d-4a14-bb38-5e54828f2396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221065292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.2221065292
Directory /workspace/24.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/24.pwrmgr_disable_rom_integrity_check.2515434280
Short name T433
Test name
Test status
Simulation time 144808855 ps
CPU time 0.76 seconds
Started Apr 21 04:06:55 PM PDT 24
Finished Apr 21 04:06:56 PM PDT 24
Peak memory 198852 kb
Host smart-1127e363-fa14-4ba9-9335-ddf461de52da
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515434280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_dis
able_rom_integrity_check.2515434280
Directory /workspace/24.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3750896508
Short name T814
Test name
Test status
Simulation time 31107234 ps
CPU time 0.64 seconds
Started Apr 21 04:06:53 PM PDT 24
Finished Apr 21 04:06:54 PM PDT 24
Peak memory 197636 kb
Host smart-07aa1e1d-8135-4bfe-9fe4-c29cd60044c7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750896508 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst
_malfunc.3750896508
Directory /workspace/24.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/24.pwrmgr_escalation_timeout.294458883
Short name T504
Test name
Test status
Simulation time 604793491 ps
CPU time 1 seconds
Started Apr 21 04:06:53 PM PDT 24
Finished Apr 21 04:06:54 PM PDT 24
Peak memory 197764 kb
Host smart-0fbad3f3-98f3-4dd7-b61f-5607f82364e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294458883 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.294458883
Directory /workspace/24.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/24.pwrmgr_glitch.3637031534
Short name T634
Test name
Test status
Simulation time 39620585 ps
CPU time 0.66 seconds
Started Apr 21 04:06:51 PM PDT 24
Finished Apr 21 04:06:52 PM PDT 24
Peak memory 197696 kb
Host smart-ce868ac6-695b-4fd0-8762-ec7800a6a934
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637031534 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.3637031534
Directory /workspace/24.pwrmgr_glitch/latest


Test location /workspace/coverage/default/24.pwrmgr_global_esc.3316957361
Short name T553
Test name
Test status
Simulation time 28554887 ps
CPU time 0.64 seconds
Started Apr 21 04:06:51 PM PDT 24
Finished Apr 21 04:06:52 PM PDT 24
Peak memory 197744 kb
Host smart-0975a70f-988e-4a6d-b059-c4fc67f5cf24
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316957361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.3316957361
Directory /workspace/24.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/24.pwrmgr_lowpower_invalid.647921038
Short name T927
Test name
Test status
Simulation time 69686511 ps
CPU time 0.71 seconds
Started Apr 21 04:06:53 PM PDT 24
Finished Apr 21 04:06:54 PM PDT 24
Peak memory 200956 kb
Host smart-a3d1e659-d7b2-418c-b668-db4c2992c4f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647921038 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_invali
d.647921038
Directory /workspace/24.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/24.pwrmgr_lowpower_wakeup_race.4153098441
Short name T885
Test name
Test status
Simulation time 136317660 ps
CPU time 0.73 seconds
Started Apr 21 04:06:49 PM PDT 24
Finished Apr 21 04:06:50 PM PDT 24
Peak memory 198140 kb
Host smart-df1d157b-4fdd-4129-9886-09ee78364427
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153098441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_w
akeup_race.4153098441
Directory /workspace/24.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/24.pwrmgr_reset.140738129
Short name T14
Test name
Test status
Simulation time 91668384 ps
CPU time 0.82 seconds
Started Apr 21 04:06:51 PM PDT 24
Finished Apr 21 04:06:52 PM PDT 24
Peak memory 198312 kb
Host smart-0d97ccb4-c264-42be-9b63-7fee600d7934
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140738129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.140738129
Directory /workspace/24.pwrmgr_reset/latest


Test location /workspace/coverage/default/24.pwrmgr_reset_invalid.539610706
Short name T400
Test name
Test status
Simulation time 108432346 ps
CPU time 1.13 seconds
Started Apr 21 04:06:53 PM PDT 24
Finished Apr 21 04:06:54 PM PDT 24
Peak memory 209088 kb
Host smart-ee29b60e-3b46-478b-b45a-76389901efea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539610706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.539610706
Directory /workspace/24.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.2411345374
Short name T351
Test name
Test status
Simulation time 36607840 ps
CPU time 0.73 seconds
Started Apr 21 04:06:52 PM PDT 24
Finished Apr 21 04:06:53 PM PDT 24
Peak memory 198224 kb
Host smart-5fe1b622-34ae-4e23-a2bd-389eccc15662
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411345374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_
cm_ctrl_config_regwen.2411345374
Directory /workspace/24.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1534812787
Short name T211
Test name
Test status
Simulation time 1012281897 ps
CPU time 2.28 seconds
Started Apr 21 04:06:49 PM PDT 24
Finished Apr 21 04:06:52 PM PDT 24
Peak memory 200860 kb
Host smart-7fe0b149-91e9-4a82-a98e-a89dc6791eca
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534812787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1534812787
Directory /workspace/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3378868399
Short name T776
Test name
Test status
Simulation time 804330643 ps
CPU time 2.97 seconds
Started Apr 21 04:06:49 PM PDT 24
Finished Apr 21 04:06:52 PM PDT 24
Peak memory 200848 kb
Host smart-8d938d86-c24c-428a-9848-09831d333611
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378868399 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3378868399
Directory /workspace/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.3914197168
Short name T614
Test name
Test status
Simulation time 76340352 ps
CPU time 0.81 seconds
Started Apr 21 04:06:47 PM PDT 24
Finished Apr 21 04:06:48 PM PDT 24
Peak memory 198760 kb
Host smart-f75914f1-92cc-431e-b9aa-5660d94746ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914197168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3914197168
Directory /workspace/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/24.pwrmgr_smoke.1334687369
Short name T510
Test name
Test status
Simulation time 55572485 ps
CPU time 0.66 seconds
Started Apr 21 04:06:51 PM PDT 24
Finished Apr 21 04:06:52 PM PDT 24
Peak memory 199016 kb
Host smart-dc16039d-439b-4265-8bb1-980bfbab814b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334687369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.1334687369
Directory /workspace/24.pwrmgr_smoke/latest


Test location /workspace/coverage/default/24.pwrmgr_stress_all.2267660863
Short name T968
Test name
Test status
Simulation time 1719675506 ps
CPU time 4.43 seconds
Started Apr 21 04:06:55 PM PDT 24
Finished Apr 21 04:07:00 PM PDT 24
Peak memory 200924 kb
Host smart-a963cf22-f899-4459-a4af-a4853866e11a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267660863 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.2267660863
Directory /workspace/24.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/24.pwrmgr_stress_all_with_rand_reset.2790281433
Short name T90
Test name
Test status
Simulation time 10004344236 ps
CPU time 11.6 seconds
Started Apr 21 04:06:55 PM PDT 24
Finished Apr 21 04:07:07 PM PDT 24
Peak memory 201076 kb
Host smart-94b69948-1daf-462a-9895-be3b8d289457
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790281433 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all_with_rand_reset.2790281433
Directory /workspace/24.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/24.pwrmgr_wakeup.3762886589
Short name T57
Test name
Test status
Simulation time 123147777 ps
CPU time 0.84 seconds
Started Apr 21 04:06:49 PM PDT 24
Finished Apr 21 04:06:50 PM PDT 24
Peak memory 197996 kb
Host smart-f62f4dd7-2f57-4270-8bd3-c342b1b939e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762886589 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.3762886589
Directory /workspace/24.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/24.pwrmgr_wakeup_reset.1937376439
Short name T970
Test name
Test status
Simulation time 317987494 ps
CPU time 0.95 seconds
Started Apr 21 04:06:49 PM PDT 24
Finished Apr 21 04:06:50 PM PDT 24
Peak memory 199780 kb
Host smart-1e590906-4d15-4b17-9cf0-1925061eb49a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937376439 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.1937376439
Directory /workspace/24.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/25.pwrmgr_aborted_low_power.586007159
Short name T828
Test name
Test status
Simulation time 102800343 ps
CPU time 0.79 seconds
Started Apr 21 04:06:56 PM PDT 24
Finished Apr 21 04:06:57 PM PDT 24
Peak memory 198500 kb
Host smart-1922f8ae-c1be-4254-8af1-2e8cce3f4ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586007159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.586007159
Directory /workspace/25.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/25.pwrmgr_disable_rom_integrity_check.3599570893
Short name T469
Test name
Test status
Simulation time 74151044 ps
CPU time 0.78 seconds
Started Apr 21 04:07:02 PM PDT 24
Finished Apr 21 04:07:03 PM PDT 24
Peak memory 198272 kb
Host smart-30bb101b-e3b7-4742-ba97-c51affd1c02f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599570893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_dis
able_rom_integrity_check.3599570893
Directory /workspace/25.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.3022560427
Short name T12
Test name
Test status
Simulation time 39583301 ps
CPU time 0.6 seconds
Started Apr 21 04:06:56 PM PDT 24
Finished Apr 21 04:06:57 PM PDT 24
Peak memory 197736 kb
Host smart-30a73158-aab9-4e00-8000-04589a6d6c5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022560427 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst
_malfunc.3022560427
Directory /workspace/25.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/25.pwrmgr_escalation_timeout.2053697832
Short name T296
Test name
Test status
Simulation time 616864645 ps
CPU time 0.98 seconds
Started Apr 21 04:07:00 PM PDT 24
Finished Apr 21 04:07:01 PM PDT 24
Peak memory 197784 kb
Host smart-a207ad2e-eae6-44ed-a1b5-677263ce11db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053697832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.2053697832
Directory /workspace/25.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/25.pwrmgr_glitch.4229229703
Short name T354
Test name
Test status
Simulation time 57041513 ps
CPU time 0.64 seconds
Started Apr 21 04:06:59 PM PDT 24
Finished Apr 21 04:07:00 PM PDT 24
Peak memory 197684 kb
Host smart-548ac959-fa87-471c-8fc3-38c8d33200b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229229703 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.4229229703
Directory /workspace/25.pwrmgr_glitch/latest


Test location /workspace/coverage/default/25.pwrmgr_global_esc.3966411919
Short name T721
Test name
Test status
Simulation time 87610351 ps
CPU time 0.64 seconds
Started Apr 21 04:06:57 PM PDT 24
Finished Apr 21 04:06:58 PM PDT 24
Peak memory 197756 kb
Host smart-6b7de705-ea36-41b4-94c1-64832f63ef76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966411919 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.3966411919
Directory /workspace/25.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/25.pwrmgr_lowpower_invalid.3375755897
Short name T966
Test name
Test status
Simulation time 90085671 ps
CPU time 0.69 seconds
Started Apr 21 04:06:57 PM PDT 24
Finished Apr 21 04:06:58 PM PDT 24
Peak memory 201060 kb
Host smart-4463b3d7-f512-467d-8c20-fb16e1b6b29e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375755897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_inval
id.3375755897
Directory /workspace/25.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/25.pwrmgr_lowpower_wakeup_race.3554397806
Short name T223
Test name
Test status
Simulation time 64029317 ps
CPU time 0.67 seconds
Started Apr 21 04:06:57 PM PDT 24
Finished Apr 21 04:06:58 PM PDT 24
Peak memory 197904 kb
Host smart-3e9ab94a-4d8a-4eba-b298-74c18996cd02
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554397806 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_w
akeup_race.3554397806
Directory /workspace/25.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/25.pwrmgr_reset.834699184
Short name T601
Test name
Test status
Simulation time 147777782 ps
CPU time 0.88 seconds
Started Apr 21 04:06:54 PM PDT 24
Finished Apr 21 04:06:55 PM PDT 24
Peak memory 199680 kb
Host smart-3592ae3c-b969-48f6-ae7b-28b410d0d160
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834699184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.834699184
Directory /workspace/25.pwrmgr_reset/latest


Test location /workspace/coverage/default/25.pwrmgr_reset_invalid.2775566898
Short name T293
Test name
Test status
Simulation time 108647623 ps
CPU time 0.92 seconds
Started Apr 21 04:07:00 PM PDT 24
Finished Apr 21 04:07:01 PM PDT 24
Peak memory 209132 kb
Host smart-3b2387a4-03bc-4e90-aa7a-2dc7ca41098f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775566898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.2775566898
Directory /workspace/25.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.1038627102
Short name T714
Test name
Test status
Simulation time 27041794 ps
CPU time 0.71 seconds
Started Apr 21 04:06:57 PM PDT 24
Finished Apr 21 04:06:58 PM PDT 24
Peak memory 199056 kb
Host smart-7cf147dc-aaa2-4df8-8adb-44a96cc2480c
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038627102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_
cm_ctrl_config_regwen.1038627102
Directory /workspace/25.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3071455506
Short name T746
Test name
Test status
Simulation time 993266216 ps
CPU time 2.68 seconds
Started Apr 21 04:06:54 PM PDT 24
Finished Apr 21 04:06:57 PM PDT 24
Peak memory 200884 kb
Host smart-3abc75eb-7be3-4bce-9e42-c7afc1cd78f2
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071455506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3071455506
Directory /workspace/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3051370693
Short name T509
Test name
Test status
Simulation time 897870992 ps
CPU time 3.62 seconds
Started Apr 21 04:06:54 PM PDT 24
Finished Apr 21 04:06:58 PM PDT 24
Peak memory 200888 kb
Host smart-4a05ea3c-b30a-43fc-8ce1-f02318b81977
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051370693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3051370693
Directory /workspace/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.2615710986
Short name T162
Test name
Test status
Simulation time 62007185 ps
CPU time 0.91 seconds
Started Apr 21 04:06:54 PM PDT 24
Finished Apr 21 04:06:55 PM PDT 24
Peak memory 198900 kb
Host smart-aa882e4d-2bfb-44f9-8938-0c023f3b3f32
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615710986 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2615710986
Directory /workspace/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/25.pwrmgr_smoke.2064658949
Short name T357
Test name
Test status
Simulation time 51795300 ps
CPU time 0.66 seconds
Started Apr 21 04:06:56 PM PDT 24
Finished Apr 21 04:06:57 PM PDT 24
Peak memory 199004 kb
Host smart-0f862641-b760-44f0-a41a-58c9b0902f4d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064658949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.2064658949
Directory /workspace/25.pwrmgr_smoke/latest


Test location /workspace/coverage/default/25.pwrmgr_stress_all.2875700384
Short name T772
Test name
Test status
Simulation time 628154064 ps
CPU time 2.6 seconds
Started Apr 21 04:07:02 PM PDT 24
Finished Apr 21 04:07:05 PM PDT 24
Peak memory 200860 kb
Host smart-a7998c43-318d-44c8-bdc7-525a3311d092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875700384 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.2875700384
Directory /workspace/25.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/25.pwrmgr_stress_all_with_rand_reset.1952713980
Short name T442
Test name
Test status
Simulation time 6983477323 ps
CPU time 28.07 seconds
Started Apr 21 04:06:58 PM PDT 24
Finished Apr 21 04:07:26 PM PDT 24
Peak memory 201028 kb
Host smart-0d84a5ff-ac38-4b75-a946-0733a72fe3c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952713980 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all_with_rand_reset.1952713980
Directory /workspace/25.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/25.pwrmgr_wakeup.745214970
Short name T233
Test name
Test status
Simulation time 308139833 ps
CPU time 1.25 seconds
Started Apr 21 04:06:55 PM PDT 24
Finished Apr 21 04:06:57 PM PDT 24
Peak memory 199236 kb
Host smart-fefb06f5-b27f-4ead-962d-48a1ae47067c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745214970 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.745214970
Directory /workspace/25.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/25.pwrmgr_wakeup_reset.3200624949
Short name T741
Test name
Test status
Simulation time 211337313 ps
CPU time 1.18 seconds
Started Apr 21 04:06:55 PM PDT 24
Finished Apr 21 04:06:56 PM PDT 24
Peak memory 199740 kb
Host smart-ff918514-b2d5-4b80-aaac-74181c43ca82
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200624949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.3200624949
Directory /workspace/25.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/26.pwrmgr_aborted_low_power.3905908442
Short name T662
Test name
Test status
Simulation time 49391752 ps
CPU time 0.65 seconds
Started Apr 21 04:07:01 PM PDT 24
Finished Apr 21 04:07:02 PM PDT 24
Peak memory 198268 kb
Host smart-9e515c1a-23d4-4190-abbb-bc3c5fbd90e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905908442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.3905908442
Directory /workspace/26.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/26.pwrmgr_disable_rom_integrity_check.2536342642
Short name T391
Test name
Test status
Simulation time 72834229 ps
CPU time 0.8 seconds
Started Apr 21 04:07:02 PM PDT 24
Finished Apr 21 04:07:03 PM PDT 24
Peak memory 198812 kb
Host smart-258c1cb5-122c-468f-af84-b07137a844b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536342642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_dis
able_rom_integrity_check.2536342642
Directory /workspace/26.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.1405673516
Short name T167
Test name
Test status
Simulation time 37266380 ps
CPU time 0.61 seconds
Started Apr 21 04:07:00 PM PDT 24
Finished Apr 21 04:07:00 PM PDT 24
Peak memory 196988 kb
Host smart-d9150605-2a92-471c-ab0d-3f881809b628
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405673516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst
_malfunc.1405673516
Directory /workspace/26.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/26.pwrmgr_escalation_timeout.1478700458
Short name T732
Test name
Test status
Simulation time 760666132 ps
CPU time 0.97 seconds
Started Apr 21 04:07:02 PM PDT 24
Finished Apr 21 04:07:03 PM PDT 24
Peak memory 197796 kb
Host smart-0d5a73de-5993-4e6e-821d-8aed7fa46222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478700458 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.1478700458
Directory /workspace/26.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/26.pwrmgr_glitch.2445289031
Short name T434
Test name
Test status
Simulation time 57446340 ps
CPU time 0.68 seconds
Started Apr 21 04:07:00 PM PDT 24
Finished Apr 21 04:07:01 PM PDT 24
Peak memory 197768 kb
Host smart-16fcc488-4fb1-400a-bb66-ed21d9a7e26e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445289031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.2445289031
Directory /workspace/26.pwrmgr_glitch/latest


Test location /workspace/coverage/default/26.pwrmgr_global_esc.3418938391
Short name T466
Test name
Test status
Simulation time 29880630 ps
CPU time 0.64 seconds
Started Apr 21 04:07:03 PM PDT 24
Finished Apr 21 04:07:03 PM PDT 24
Peak memory 198064 kb
Host smart-9c4e2b3c-e83f-450d-b8f0-d92d5256ba91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418938391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.3418938391
Directory /workspace/26.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/26.pwrmgr_lowpower_invalid.2744590386
Short name T2
Test name
Test status
Simulation time 44620877 ps
CPU time 0.68 seconds
Started Apr 21 04:06:58 PM PDT 24
Finished Apr 21 04:06:59 PM PDT 24
Peak memory 201036 kb
Host smart-ec873704-270e-4a40-8695-e6095419f2b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744590386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_inval
id.2744590386
Directory /workspace/26.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/26.pwrmgr_lowpower_wakeup_race.2317142995
Short name T834
Test name
Test status
Simulation time 53591837 ps
CPU time 0.75 seconds
Started Apr 21 04:06:58 PM PDT 24
Finished Apr 21 04:07:00 PM PDT 24
Peak memory 197904 kb
Host smart-8d504b5e-07ae-450b-8648-e9e84a0862d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317142995 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_w
akeup_race.2317142995
Directory /workspace/26.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/26.pwrmgr_reset.3816114909
Short name T859
Test name
Test status
Simulation time 237737743 ps
CPU time 0.95 seconds
Started Apr 21 04:06:57 PM PDT 24
Finished Apr 21 04:06:58 PM PDT 24
Peak memory 199740 kb
Host smart-e74bdf09-2bfd-4da3-a424-aba06b7d51d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816114909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.3816114909
Directory /workspace/26.pwrmgr_reset/latest


Test location /workspace/coverage/default/26.pwrmgr_reset_invalid.2177812092
Short name T230
Test name
Test status
Simulation time 149300523 ps
CPU time 0.87 seconds
Started Apr 21 04:07:03 PM PDT 24
Finished Apr 21 04:07:04 PM PDT 24
Peak memory 209092 kb
Host smart-e6b8f80d-2822-42ea-87d3-1f12ac2eacfd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177812092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.2177812092
Directory /workspace/26.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.1015278813
Short name T61
Test name
Test status
Simulation time 237639928 ps
CPU time 1.37 seconds
Started Apr 21 04:07:01 PM PDT 24
Finished Apr 21 04:07:03 PM PDT 24
Peak memory 200436 kb
Host smart-07bc1509-6b2b-4ddb-8895-1f623d0e7bbd
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015278813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_
cm_ctrl_config_regwen.1015278813
Directory /workspace/26.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1771831933
Short name T145
Test name
Test status
Simulation time 885327192 ps
CPU time 3.16 seconds
Started Apr 21 04:06:59 PM PDT 24
Finished Apr 21 04:07:02 PM PDT 24
Peak memory 200848 kb
Host smart-35b60930-6492-4129-b379-d091284d0311
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771831933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1771831933
Directory /workspace/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3968541603
Short name T299
Test name
Test status
Simulation time 841855222 ps
CPU time 3.53 seconds
Started Apr 21 04:07:01 PM PDT 24
Finished Apr 21 04:07:05 PM PDT 24
Peak memory 200836 kb
Host smart-9e052205-1bef-48c1-a07f-430d28926247
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968541603 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3968541603
Directory /workspace/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.738801686
Short name T748
Test name
Test status
Simulation time 92609868 ps
CPU time 0.92 seconds
Started Apr 21 04:07:01 PM PDT 24
Finished Apr 21 04:07:02 PM PDT 24
Peak memory 198820 kb
Host smart-7fab4466-e2a5-4ab8-8c49-f46ed2f6155d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738801686 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig_
mubi.738801686
Directory /workspace/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/26.pwrmgr_smoke.1666432760
Short name T959
Test name
Test status
Simulation time 41254984 ps
CPU time 0.71 seconds
Started Apr 21 04:06:56 PM PDT 24
Finished Apr 21 04:06:57 PM PDT 24
Peak memory 199004 kb
Host smart-05af79d9-f358-46b7-a2a3-b24ffacec5f1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666432760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.1666432760
Directory /workspace/26.pwrmgr_smoke/latest


Test location /workspace/coverage/default/26.pwrmgr_stress_all.2265469041
Short name T944
Test name
Test status
Simulation time 1910416002 ps
CPU time 5.06 seconds
Started Apr 21 04:07:03 PM PDT 24
Finished Apr 21 04:07:09 PM PDT 24
Peak memory 200976 kb
Host smart-ae21276d-6a33-4ad1-9b32-1037733a4da6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265469041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all.2265469041
Directory /workspace/26.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/26.pwrmgr_wakeup.2977546220
Short name T978
Test name
Test status
Simulation time 173533980 ps
CPU time 0.94 seconds
Started Apr 21 04:06:58 PM PDT 24
Finished Apr 21 04:06:59 PM PDT 24
Peak memory 198792 kb
Host smart-74f5cda1-fa88-43df-8a6a-70fb3ac94792
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977546220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.2977546220
Directory /workspace/26.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/26.pwrmgr_wakeup_reset.2436237222
Short name T627
Test name
Test status
Simulation time 330024101 ps
CPU time 1 seconds
Started Apr 21 04:06:56 PM PDT 24
Finished Apr 21 04:06:58 PM PDT 24
Peak memory 199876 kb
Host smart-2b7a566b-0a04-4d7b-b5d0-4ae45463c383
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436237222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup_reset.2436237222
Directory /workspace/26.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/27.pwrmgr_aborted_low_power.1776784423
Short name T346
Test name
Test status
Simulation time 43637506 ps
CPU time 0.92 seconds
Started Apr 21 04:07:05 PM PDT 24
Finished Apr 21 04:07:06 PM PDT 24
Peak memory 200120 kb
Host smart-6274ba71-7cdd-4c40-801e-04329d470e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776784423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.1776784423
Directory /workspace/27.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/27.pwrmgr_disable_rom_integrity_check.535784811
Short name T332
Test name
Test status
Simulation time 81438557 ps
CPU time 0.69 seconds
Started Apr 21 04:07:12 PM PDT 24
Finished Apr 21 04:07:13 PM PDT 24
Peak memory 198768 kb
Host smart-d7319808-157e-4285-8c00-00ce4904befa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535784811 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_disa
ble_rom_integrity_check.535784811
Directory /workspace/27.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.3419475411
Short name T163
Test name
Test status
Simulation time 38323740 ps
CPU time 0.62 seconds
Started Apr 21 04:07:05 PM PDT 24
Finished Apr 21 04:07:06 PM PDT 24
Peak memory 196932 kb
Host smart-a5de94f6-5b20-4c61-8637-5952ff7d0def
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419475411 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst
_malfunc.3419475411
Directory /workspace/27.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/27.pwrmgr_escalation_timeout.2296221864
Short name T756
Test name
Test status
Simulation time 607014660 ps
CPU time 1.02 seconds
Started Apr 21 04:07:05 PM PDT 24
Finished Apr 21 04:07:06 PM PDT 24
Peak memory 197756 kb
Host smart-f9c41775-d1e1-4c11-b5c5-fc793a8c448c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296221864 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.2296221864
Directory /workspace/27.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/27.pwrmgr_glitch.2590244239
Short name T319
Test name
Test status
Simulation time 46527314 ps
CPU time 0.7 seconds
Started Apr 21 04:07:06 PM PDT 24
Finished Apr 21 04:07:07 PM PDT 24
Peak memory 197624 kb
Host smart-131d00be-509f-440c-ae2b-8390756cff20
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590244239 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.2590244239
Directory /workspace/27.pwrmgr_glitch/latest


Test location /workspace/coverage/default/27.pwrmgr_global_esc.1937471789
Short name T807
Test name
Test status
Simulation time 71251087 ps
CPU time 0.65 seconds
Started Apr 21 04:07:03 PM PDT 24
Finished Apr 21 04:07:04 PM PDT 24
Peak memory 197784 kb
Host smart-62fdd596-51c4-4c2a-a2a1-bd7b4793ce79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937471789 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.1937471789
Directory /workspace/27.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/27.pwrmgr_lowpower_invalid.1845484055
Short name T210
Test name
Test status
Simulation time 72639460 ps
CPU time 0.74 seconds
Started Apr 21 04:07:04 PM PDT 24
Finished Apr 21 04:07:05 PM PDT 24
Peak memory 200996 kb
Host smart-ec775a9c-5488-411d-a5d5-3ea20c1118e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845484055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_inval
id.1845484055
Directory /workspace/27.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/27.pwrmgr_lowpower_wakeup_race.753285008
Short name T900
Test name
Test status
Simulation time 123100740 ps
CPU time 0.97 seconds
Started Apr 21 04:07:00 PM PDT 24
Finished Apr 21 04:07:02 PM PDT 24
Peak memory 198796 kb
Host smart-969682ff-bae7-4870-9391-ee113f98276e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753285008 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_wa
keup_race.753285008
Directory /workspace/27.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/27.pwrmgr_reset.3434898927
Short name T350
Test name
Test status
Simulation time 114174091 ps
CPU time 0.97 seconds
Started Apr 21 04:07:00 PM PDT 24
Finished Apr 21 04:07:01 PM PDT 24
Peak memory 199564 kb
Host smart-d135dee7-1b76-4c9e-8e1a-c2546bd7514f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434898927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.3434898927
Directory /workspace/27.pwrmgr_reset/latest


Test location /workspace/coverage/default/27.pwrmgr_reset_invalid.2278422437
Short name T202
Test name
Test status
Simulation time 161109574 ps
CPU time 0.83 seconds
Started Apr 21 04:07:04 PM PDT 24
Finished Apr 21 04:07:05 PM PDT 24
Peak memory 209184 kb
Host smart-45d91ff6-d530-4f06-a398-2a733b0ff1e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278422437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.2278422437
Directory /workspace/27.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.339250747
Short name T678
Test name
Test status
Simulation time 355250686 ps
CPU time 0.89 seconds
Started Apr 21 04:07:02 PM PDT 24
Finished Apr 21 04:07:03 PM PDT 24
Peak memory 199592 kb
Host smart-76138720-0e8c-40f1-88e5-cfed86222669
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339250747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_c
m_ctrl_config_regwen.339250747
Directory /workspace/27.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3378705900
Short name T289
Test name
Test status
Simulation time 1164682992 ps
CPU time 2.26 seconds
Started Apr 21 04:07:12 PM PDT 24
Finished Apr 21 04:07:14 PM PDT 24
Peak memory 200860 kb
Host smart-bc22b9f0-a6c4-42cf-b48a-7a3dfaedfcfe
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378705900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3378705900
Directory /workspace/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3478565339
Short name T636
Test name
Test status
Simulation time 2727134424 ps
CPU time 2.14 seconds
Started Apr 21 04:07:03 PM PDT 24
Finished Apr 21 04:07:05 PM PDT 24
Peak memory 201132 kb
Host smart-88fc2cae-25fd-455e-82d5-768b7ae30b69
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478565339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3478565339
Directory /workspace/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.4237565352
Short name T920
Test name
Test status
Simulation time 70406518 ps
CPU time 0.93 seconds
Started Apr 21 04:07:11 PM PDT 24
Finished Apr 21 04:07:13 PM PDT 24
Peak memory 198924 kb
Host smart-2eec0eb7-7cc3-44fd-a195-ae2bcb8f893d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237565352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4237565352
Directory /workspace/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/27.pwrmgr_smoke.3969718013
Short name T66
Test name
Test status
Simulation time 29147738 ps
CPU time 0.73 seconds
Started Apr 21 04:07:00 PM PDT 24
Finished Apr 21 04:07:01 PM PDT 24
Peak memory 199028 kb
Host smart-f6b05118-bce3-434f-a058-a1e13595e9ac
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969718013 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.3969718013
Directory /workspace/27.pwrmgr_smoke/latest


Test location /workspace/coverage/default/27.pwrmgr_stress_all.183866714
Short name T599
Test name
Test status
Simulation time 2134998276 ps
CPU time 7.74 seconds
Started Apr 21 04:07:05 PM PDT 24
Finished Apr 21 04:07:13 PM PDT 24
Peak memory 200928 kb
Host smart-dcf1af94-1348-4ff3-9b14-34c4721e4c47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183866714 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.183866714
Directory /workspace/27.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/27.pwrmgr_stress_all_with_rand_reset.3861546598
Short name T130
Test name
Test status
Simulation time 5364428339 ps
CPU time 18.98 seconds
Started Apr 21 04:07:03 PM PDT 24
Finished Apr 21 04:07:23 PM PDT 24
Peak memory 201068 kb
Host smart-6430273e-2cc8-44b8-b5c4-4cfdeeb5df45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861546598 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all_with_rand_reset.3861546598
Directory /workspace/27.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/27.pwrmgr_wakeup.2028642010
Short name T858
Test name
Test status
Simulation time 92035658 ps
CPU time 0.75 seconds
Started Apr 21 04:07:02 PM PDT 24
Finished Apr 21 04:07:03 PM PDT 24
Peak memory 198164 kb
Host smart-c9c1d2ab-ada6-42fe-88c3-ed0f944fe620
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028642010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.2028642010
Directory /workspace/27.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/27.pwrmgr_wakeup_reset.2443638403
Short name T352
Test name
Test status
Simulation time 410549604 ps
CPU time 1.14 seconds
Started Apr 21 04:07:05 PM PDT 24
Finished Apr 21 04:07:07 PM PDT 24
Peak memory 199892 kb
Host smart-72db1920-b075-4d1d-8e59-54b19429a0e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443638403 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.2443638403
Directory /workspace/27.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/28.pwrmgr_aborted_low_power.2577814509
Short name T616
Test name
Test status
Simulation time 18125689 ps
CPU time 0.68 seconds
Started Apr 21 04:07:06 PM PDT 24
Finished Apr 21 04:07:07 PM PDT 24
Peak memory 198828 kb
Host smart-583fe1ee-6743-4f21-a869-e60e2f3786e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577814509 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.2577814509
Directory /workspace/28.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/28.pwrmgr_disable_rom_integrity_check.2898921194
Short name T144
Test name
Test status
Simulation time 86383639 ps
CPU time 0.72 seconds
Started Apr 21 04:07:08 PM PDT 24
Finished Apr 21 04:07:09 PM PDT 24
Peak memory 198888 kb
Host smart-0d31c8d3-7523-45d3-a6b6-d06a0105fbb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898921194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_dis
able_rom_integrity_check.2898921194
Directory /workspace/28.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.3923231765
Short name T658
Test name
Test status
Simulation time 31829477 ps
CPU time 0.61 seconds
Started Apr 21 04:07:06 PM PDT 24
Finished Apr 21 04:07:07 PM PDT 24
Peak memory 196976 kb
Host smart-3be7d824-0f14-462f-babd-506f46508d65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923231765 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst
_malfunc.3923231765
Directory /workspace/28.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/28.pwrmgr_escalation_timeout.1376318325
Short name T907
Test name
Test status
Simulation time 322173957 ps
CPU time 0.97 seconds
Started Apr 21 04:07:08 PM PDT 24
Finished Apr 21 04:07:10 PM PDT 24
Peak memory 197792 kb
Host smart-b70b2343-1875-48cf-a79e-ebc002ff856a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376318325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.1376318325
Directory /workspace/28.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/28.pwrmgr_glitch.810948584
Short name T906
Test name
Test status
Simulation time 46145767 ps
CPU time 0.72 seconds
Started Apr 21 04:07:07 PM PDT 24
Finished Apr 21 04:07:08 PM PDT 24
Peak memory 197040 kb
Host smart-9c71595f-2039-49a6-b978-daf2512d71f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810948584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.810948584
Directory /workspace/28.pwrmgr_glitch/latest


Test location /workspace/coverage/default/28.pwrmgr_global_esc.624870702
Short name T530
Test name
Test status
Simulation time 42039955 ps
CPU time 0.66 seconds
Started Apr 21 04:07:07 PM PDT 24
Finished Apr 21 04:07:08 PM PDT 24
Peak memory 198084 kb
Host smart-71072ef6-62b8-45ec-ad5f-f7e339da4861
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624870702 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.624870702
Directory /workspace/28.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/28.pwrmgr_lowpower_invalid.369706304
Short name T245
Test name
Test status
Simulation time 55932068 ps
CPU time 0.72 seconds
Started Apr 21 04:07:07 PM PDT 24
Finished Apr 21 04:07:08 PM PDT 24
Peak memory 201036 kb
Host smart-6384604b-bc19-4654-b7b3-9faa268f8925
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369706304 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_invali
d.369706304
Directory /workspace/28.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/28.pwrmgr_lowpower_wakeup_race.3364103196
Short name T225
Test name
Test status
Simulation time 522774447 ps
CPU time 0.93 seconds
Started Apr 21 04:07:04 PM PDT 24
Finished Apr 21 04:07:06 PM PDT 24
Peak memory 199192 kb
Host smart-76624d83-fab2-4279-b5dc-975e5dcacda0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364103196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_w
akeup_race.3364103196
Directory /workspace/28.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/28.pwrmgr_reset.96456240
Short name T190
Test name
Test status
Simulation time 70587590 ps
CPU time 0.7 seconds
Started Apr 21 04:07:04 PM PDT 24
Finished Apr 21 04:07:05 PM PDT 24
Peak memory 198184 kb
Host smart-028805b6-22cd-4f0f-ae94-8fd4ea52a535
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96456240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.96456240
Directory /workspace/28.pwrmgr_reset/latest


Test location /workspace/coverage/default/28.pwrmgr_reset_invalid.3114970901
Short name T362
Test name
Test status
Simulation time 116801408 ps
CPU time 1.01 seconds
Started Apr 21 04:07:09 PM PDT 24
Finished Apr 21 04:07:11 PM PDT 24
Peak memory 209144 kb
Host smart-c8310877-9442-45e1-9dee-2b5e9e040e39
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114970901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.3114970901
Directory /workspace/28.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.1121918361
Short name T948
Test name
Test status
Simulation time 206528187 ps
CPU time 0.77 seconds
Started Apr 21 04:07:08 PM PDT 24
Finished Apr 21 04:07:09 PM PDT 24
Peak memory 198372 kb
Host smart-d53fba1e-f33b-471d-bbc1-b122bd6a963e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121918361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_
cm_ctrl_config_regwen.1121918361
Directory /workspace/28.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4069978505
Short name T596
Test name
Test status
Simulation time 2967139091 ps
CPU time 1.92 seconds
Started Apr 21 04:07:05 PM PDT 24
Finished Apr 21 04:07:07 PM PDT 24
Peak memory 201012 kb
Host smart-691dd382-4e70-478b-bbf3-b490399d8aca
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069978505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4069978505
Directory /workspace/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3791512726
Short name T476
Test name
Test status
Simulation time 1614988399 ps
CPU time 2.16 seconds
Started Apr 21 04:07:05 PM PDT 24
Finished Apr 21 04:07:08 PM PDT 24
Peak memory 200900 kb
Host smart-7ad24ce5-ead9-4e27-94c4-8746d459fad9
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791512726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3791512726
Directory /workspace/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.353963690
Short name T449
Test name
Test status
Simulation time 100188876 ps
CPU time 0.87 seconds
Started Apr 21 04:07:11 PM PDT 24
Finished Apr 21 04:07:12 PM PDT 24
Peak memory 198752 kb
Host smart-9162a05b-55d1-4730-9ee9-104461f3279b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353963690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig_
mubi.353963690
Directory /workspace/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/28.pwrmgr_smoke.4015426320
Short name T853
Test name
Test status
Simulation time 57125319 ps
CPU time 0.67 seconds
Started Apr 21 04:07:05 PM PDT 24
Finished Apr 21 04:07:06 PM PDT 24
Peak memory 198236 kb
Host smart-a3482b0b-52fd-49dc-b754-df8b3b7ac188
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015426320 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.4015426320
Directory /workspace/28.pwrmgr_smoke/latest


Test location /workspace/coverage/default/28.pwrmgr_stress_all_with_rand_reset.92142454
Short name T106
Test name
Test status
Simulation time 15327871606 ps
CPU time 21.67 seconds
Started Apr 21 04:07:09 PM PDT 24
Finished Apr 21 04:07:32 PM PDT 24
Peak memory 200964 kb
Host smart-c48cba5c-8c4f-464e-8cc0-bcda2229d741
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92142454 -assert nopostp
roc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all_with_rand_reset.92142454
Directory /workspace/28.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/28.pwrmgr_wakeup.586375318
Short name T866
Test name
Test status
Simulation time 172106753 ps
CPU time 0.83 seconds
Started Apr 21 04:07:11 PM PDT 24
Finished Apr 21 04:07:12 PM PDT 24
Peak memory 198196 kb
Host smart-8168ee4d-1c09-4128-8b1f-7e49b7c8a4a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586375318 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.586375318
Directory /workspace/28.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/28.pwrmgr_wakeup_reset.1582866419
Short name T632
Test name
Test status
Simulation time 42214540 ps
CPU time 0.74 seconds
Started Apr 21 04:07:07 PM PDT 24
Finished Apr 21 04:07:08 PM PDT 24
Peak memory 198912 kb
Host smart-d0a3c794-160f-4156-89f9-7a3c1370c677
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582866419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.1582866419
Directory /workspace/28.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/29.pwrmgr_aborted_low_power.690326168
Short name T430
Test name
Test status
Simulation time 244153278 ps
CPU time 0.8 seconds
Started Apr 21 04:07:08 PM PDT 24
Finished Apr 21 04:07:09 PM PDT 24
Peak memory 198508 kb
Host smart-b8a47789-c110-4d2d-b250-c5376f4143e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690326168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.690326168
Directory /workspace/29.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/29.pwrmgr_disable_rom_integrity_check.1571973633
Short name T151
Test name
Test status
Simulation time 50154197 ps
CPU time 0.82 seconds
Started Apr 21 04:07:19 PM PDT 24
Finished Apr 21 04:07:20 PM PDT 24
Peak memory 198864 kb
Host smart-7f3a9b33-c96d-4697-a892-ffeb17616c58
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571973633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_dis
able_rom_integrity_check.1571973633
Directory /workspace/29.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.2684234111
Short name T593
Test name
Test status
Simulation time 31857642 ps
CPU time 0.63 seconds
Started Apr 21 04:07:11 PM PDT 24
Finished Apr 21 04:07:12 PM PDT 24
Peak memory 196964 kb
Host smart-91d5ae92-9c4e-4f70-89a1-91b198097b6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684234111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst
_malfunc.2684234111
Directory /workspace/29.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/29.pwrmgr_escalation_timeout.2598894373
Short name T496
Test name
Test status
Simulation time 638580826 ps
CPU time 0.93 seconds
Started Apr 21 04:07:18 PM PDT 24
Finished Apr 21 04:07:19 PM PDT 24
Peak memory 198076 kb
Host smart-052cfa7a-7176-45f5-9735-7b9e3ed777d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598894373 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.2598894373
Directory /workspace/29.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/29.pwrmgr_glitch.1003814670
Short name T424
Test name
Test status
Simulation time 64155481 ps
CPU time 0.61 seconds
Started Apr 21 04:07:10 PM PDT 24
Finished Apr 21 04:07:11 PM PDT 24
Peak memory 197696 kb
Host smart-aa2c7660-78e8-466d-8fce-b19655dc31d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003814670 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.1003814670
Directory /workspace/29.pwrmgr_glitch/latest


Test location /workspace/coverage/default/29.pwrmgr_global_esc.2001566898
Short name T6
Test name
Test status
Simulation time 31181503 ps
CPU time 0.67 seconds
Started Apr 21 04:07:12 PM PDT 24
Finished Apr 21 04:07:13 PM PDT 24
Peak memory 197760 kb
Host smart-fdda1f73-a868-41fe-b386-49355e4ca560
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001566898 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.2001566898
Directory /workspace/29.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/29.pwrmgr_lowpower_invalid.3220306803
Short name T757
Test name
Test status
Simulation time 41949519 ps
CPU time 0.7 seconds
Started Apr 21 04:07:12 PM PDT 24
Finished Apr 21 04:07:13 PM PDT 24
Peak memory 200976 kb
Host smart-b9f9000a-80fc-4a7b-8045-bbbab3f784c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220306803 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_inval
id.3220306803
Directory /workspace/29.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/29.pwrmgr_lowpower_wakeup_race.2361231824
Short name T837
Test name
Test status
Simulation time 285424911 ps
CPU time 1.07 seconds
Started Apr 21 04:07:07 PM PDT 24
Finished Apr 21 04:07:09 PM PDT 24
Peak memory 199128 kb
Host smart-4e04d0d5-cc62-4ea8-b68c-a03868676242
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361231824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_w
akeup_race.2361231824
Directory /workspace/29.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/29.pwrmgr_reset.3692169832
Short name T784
Test name
Test status
Simulation time 50013650 ps
CPU time 0.84 seconds
Started Apr 21 04:07:08 PM PDT 24
Finished Apr 21 04:07:09 PM PDT 24
Peak memory 198844 kb
Host smart-3a60b539-40c2-4087-8199-12e2a90864e1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692169832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.3692169832
Directory /workspace/29.pwrmgr_reset/latest


Test location /workspace/coverage/default/29.pwrmgr_reset_invalid.2653540585
Short name T280
Test name
Test status
Simulation time 97090259 ps
CPU time 1.17 seconds
Started Apr 21 04:07:12 PM PDT 24
Finished Apr 21 04:07:13 PM PDT 24
Peak memory 209168 kb
Host smart-eadfd29f-00a0-4a56-9847-3c97f904fab2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653540585 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.2653540585
Directory /workspace/29.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.3144260846
Short name T871
Test name
Test status
Simulation time 33973073 ps
CPU time 0.63 seconds
Started Apr 21 04:07:08 PM PDT 24
Finished Apr 21 04:07:09 PM PDT 24
Peak memory 198224 kb
Host smart-d9f95fad-25b6-4ec9-8a9a-083ad7d758d4
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144260846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_
cm_ctrl_config_regwen.3144260846
Directory /workspace/29.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.384138637
Short name T730
Test name
Test status
Simulation time 1105108841 ps
CPU time 2.35 seconds
Started Apr 21 04:07:10 PM PDT 24
Finished Apr 21 04:07:13 PM PDT 24
Peak memory 200960 kb
Host smart-b9bfe9ec-53a4-4acd-941c-372503656795
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384138637 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.384138637
Directory /workspace/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3167390169
Short name T810
Test name
Test status
Simulation time 886464333 ps
CPU time 2.93 seconds
Started Apr 21 04:07:17 PM PDT 24
Finished Apr 21 04:07:20 PM PDT 24
Peak memory 200884 kb
Host smart-ea04a557-137a-4e62-9145-b9abf6de06ca
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167390169 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3167390169
Directory /workspace/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.2990958404
Short name T804
Test name
Test status
Simulation time 192816749 ps
CPU time 0.9 seconds
Started Apr 21 04:07:18 PM PDT 24
Finished Apr 21 04:07:20 PM PDT 24
Peak memory 198944 kb
Host smart-c7cf542c-2ae8-44a9-9d53-607f5a7deb6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990958404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2990958404
Directory /workspace/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/29.pwrmgr_smoke.2259709369
Short name T694
Test name
Test status
Simulation time 32525109 ps
CPU time 0.72 seconds
Started Apr 21 04:07:09 PM PDT 24
Finished Apr 21 04:07:10 PM PDT 24
Peak memory 199024 kb
Host smart-9cfd1f40-28d6-4770-99d9-e5c6a7055561
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259709369 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.2259709369
Directory /workspace/29.pwrmgr_smoke/latest


Test location /workspace/coverage/default/29.pwrmgr_stress_all.2042948371
Short name T768
Test name
Test status
Simulation time 8658657590 ps
CPU time 3.48 seconds
Started Apr 21 04:07:18 PM PDT 24
Finished Apr 21 04:07:22 PM PDT 24
Peak memory 200956 kb
Host smart-6e57433f-b10a-4f4e-9540-b33be4cd6682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042948371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.2042948371
Directory /workspace/29.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/29.pwrmgr_stress_all_with_rand_reset.2472703261
Short name T79
Test name
Test status
Simulation time 9534936719 ps
CPU time 15.31 seconds
Started Apr 21 04:07:10 PM PDT 24
Finished Apr 21 04:07:26 PM PDT 24
Peak memory 201076 kb
Host smart-bdc75089-b738-4a39-b07d-89e2ee0ae69b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472703261 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all_with_rand_reset.2472703261
Directory /workspace/29.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/29.pwrmgr_wakeup.1046972474
Short name T368
Test name
Test status
Simulation time 81239103 ps
CPU time 0.63 seconds
Started Apr 21 04:07:11 PM PDT 24
Finished Apr 21 04:07:12 PM PDT 24
Peak memory 197912 kb
Host smart-fa18c3aa-314f-48d2-a8f8-f2101c03f274
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046972474 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.1046972474
Directory /workspace/29.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/29.pwrmgr_wakeup_reset.62535029
Short name T848
Test name
Test status
Simulation time 258636995 ps
CPU time 1.16 seconds
Started Apr 21 04:07:10 PM PDT 24
Finished Apr 21 04:07:12 PM PDT 24
Peak memory 200672 kb
Host smart-d167efc4-5c6e-499d-a8a5-efe2aa2eaf1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62535029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.62535029
Directory /workspace/29.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/3.pwrmgr_aborted_low_power.3281004086
Short name T194
Test name
Test status
Simulation time 43556828 ps
CPU time 1.01 seconds
Started Apr 21 04:05:24 PM PDT 24
Finished Apr 21 04:05:26 PM PDT 24
Peak memory 200492 kb
Host smart-e88e2c0e-5fe5-433c-a706-dc881b1ff1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281004086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.3281004086
Directory /workspace/3.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/3.pwrmgr_disable_rom_integrity_check.3753807402
Short name T143
Test name
Test status
Simulation time 54464175 ps
CPU time 0.93 seconds
Started Apr 21 04:05:33 PM PDT 24
Finished Apr 21 04:05:34 PM PDT 24
Peak memory 198812 kb
Host smart-641520cd-8a40-46d9-bb3e-a100a27789d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753807402 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disa
ble_rom_integrity_check.3753807402
Directory /workspace/3.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2211590523
Short name T342
Test name
Test status
Simulation time 31900592 ps
CPU time 0.63 seconds
Started Apr 21 04:05:35 PM PDT 24
Finished Apr 21 04:05:36 PM PDT 24
Peak memory 197664 kb
Host smart-e2499a9c-38f0-4e95-9224-f14e924a51e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211590523 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_
malfunc.2211590523
Directory /workspace/3.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/3.pwrmgr_escalation_timeout.32694056
Short name T164
Test name
Test status
Simulation time 162766640 ps
CPU time 1.02 seconds
Started Apr 21 04:05:28 PM PDT 24
Finished Apr 21 04:05:29 PM PDT 24
Peak memory 197780 kb
Host smart-46f27a5d-e25c-4583-aa1c-ee00b884cf8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32694056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.32694056
Directory /workspace/3.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/3.pwrmgr_glitch.1184734704
Short name T461
Test name
Test status
Simulation time 39333255 ps
CPU time 0.6 seconds
Started Apr 21 04:05:32 PM PDT 24
Finished Apr 21 04:05:33 PM PDT 24
Peak memory 197632 kb
Host smart-3cf15b6e-e255-4dcc-afe6-483326dd2582
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184734704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.1184734704
Directory /workspace/3.pwrmgr_glitch/latest


Test location /workspace/coverage/default/3.pwrmgr_global_esc.1284512327
Short name T822
Test name
Test status
Simulation time 26823031 ps
CPU time 0.63 seconds
Started Apr 21 04:05:30 PM PDT 24
Finished Apr 21 04:05:31 PM PDT 24
Peak memory 198100 kb
Host smart-c7e033d9-2844-40e0-8cd8-be99305acf51
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284512327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.1284512327
Directory /workspace/3.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/3.pwrmgr_lowpower_invalid.1915684945
Short name T557
Test name
Test status
Simulation time 86348702 ps
CPU time 0.7 seconds
Started Apr 21 04:05:30 PM PDT 24
Finished Apr 21 04:05:31 PM PDT 24
Peak memory 201060 kb
Host smart-73303a67-d9d5-43e8-a9c8-efdaa9e365de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915684945 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invali
d.1915684945
Directory /workspace/3.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/3.pwrmgr_lowpower_wakeup_race.3385392615
Short name T261
Test name
Test status
Simulation time 237788264 ps
CPU time 1.05 seconds
Started Apr 21 04:05:27 PM PDT 24
Finished Apr 21 04:05:28 PM PDT 24
Peak memory 199340 kb
Host smart-cb2b5c75-30e8-4d1f-8ce5-3d6052e0df86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385392615 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wa
keup_race.3385392615
Directory /workspace/3.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/3.pwrmgr_reset.2708642736
Short name T325
Test name
Test status
Simulation time 105584904 ps
CPU time 0.89 seconds
Started Apr 21 04:05:25 PM PDT 24
Finished Apr 21 04:05:27 PM PDT 24
Peak memory 199632 kb
Host smart-9b14cb14-267e-49a0-8a04-87c7e00a46d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708642736 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.2708642736
Directory /workspace/3.pwrmgr_reset/latest


Test location /workspace/coverage/default/3.pwrmgr_reset_invalid.2725304432
Short name T565
Test name
Test status
Simulation time 198065546 ps
CPU time 0.81 seconds
Started Apr 21 04:05:30 PM PDT 24
Finished Apr 21 04:05:31 PM PDT 24
Peak memory 209132 kb
Host smart-857c12a2-4d73-43d0-b495-cba26cf741a4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725304432 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.2725304432
Directory /workspace/3.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.299232809
Short name T348
Test name
Test status
Simulation time 173615203 ps
CPU time 1.13 seconds
Started Apr 21 04:05:29 PM PDT 24
Finished Apr 21 04:05:30 PM PDT 24
Peak memory 200652 kb
Host smart-5036c570-a8c0-4dca-80f3-a0dd3b77d242
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299232809 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm
_ctrl_config_regwen.299232809
Directory /workspace/3.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1269532824
Short name T566
Test name
Test status
Simulation time 817061579 ps
CPU time 2.37 seconds
Started Apr 21 04:05:28 PM PDT 24
Finished Apr 21 04:05:31 PM PDT 24
Peak memory 200780 kb
Host smart-253ed448-899b-4452-b5c7-42ebe5b47428
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269532824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1269532824
Directory /workspace/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1401996053
Short name T139
Test name
Test status
Simulation time 1170359736 ps
CPU time 2.2 seconds
Started Apr 21 04:05:28 PM PDT 24
Finished Apr 21 04:05:31 PM PDT 24
Peak memory 200920 kb
Host smart-04e461ce-db2d-4eae-9cfa-2bfe6b9359ff
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401996053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1401996053
Directory /workspace/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.753147936
Short name T373
Test name
Test status
Simulation time 73206389 ps
CPU time 0.95 seconds
Started Apr 21 04:05:28 PM PDT 24
Finished Apr 21 04:05:30 PM PDT 24
Peak memory 198812 kb
Host smart-d50d4259-4e41-4a4a-9be7-36deb8b64e1e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753147936 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.753147936
Directory /workspace/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/3.pwrmgr_smoke.828556092
Short name T808
Test name
Test status
Simulation time 54442008 ps
CPU time 0.68 seconds
Started Apr 21 04:05:26 PM PDT 24
Finished Apr 21 04:05:27 PM PDT 24
Peak memory 198132 kb
Host smart-1de658ba-a91c-47d0-ae4a-f13d277109ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828556092 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.828556092
Directory /workspace/3.pwrmgr_smoke/latest


Test location /workspace/coverage/default/3.pwrmgr_stress_all.1882746097
Short name T484
Test name
Test status
Simulation time 6227940420 ps
CPU time 4.11 seconds
Started Apr 21 04:05:34 PM PDT 24
Finished Apr 21 04:05:38 PM PDT 24
Peak memory 201016 kb
Host smart-eb065901-48da-47d3-a149-2c5cf0f32a05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882746097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all.1882746097
Directory /workspace/3.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/3.pwrmgr_stress_all_with_rand_reset.2676257647
Short name T70
Test name
Test status
Simulation time 15901027720 ps
CPU time 28.22 seconds
Started Apr 21 04:05:32 PM PDT 24
Finished Apr 21 04:06:01 PM PDT 24
Peak memory 201024 kb
Host smart-99d2debd-359a-425d-802e-031af1325aac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676257647 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all_with_rand_reset.2676257647
Directory /workspace/3.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/3.pwrmgr_wakeup.1569743285
Short name T710
Test name
Test status
Simulation time 240760928 ps
CPU time 1.28 seconds
Started Apr 21 04:05:26 PM PDT 24
Finished Apr 21 04:05:28 PM PDT 24
Peak memory 199456 kb
Host smart-5e48a150-ec62-48a8-bcfd-09a95723cb2a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569743285 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.1569743285
Directory /workspace/3.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/3.pwrmgr_wakeup_reset.544925025
Short name T527
Test name
Test status
Simulation time 193840605 ps
CPU time 1.15 seconds
Started Apr 21 04:05:27 PM PDT 24
Finished Apr 21 04:05:29 PM PDT 24
Peak memory 199872 kb
Host smart-b408359c-b048-4e7c-905f-949682e4084c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544925025 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.544925025
Directory /workspace/3.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/30.pwrmgr_aborted_low_power.1992329595
Short name T744
Test name
Test status
Simulation time 31674527 ps
CPU time 0.72 seconds
Started Apr 21 04:07:18 PM PDT 24
Finished Apr 21 04:07:19 PM PDT 24
Peak memory 198560 kb
Host smart-93c40c97-e0bb-4074-8ddf-829fa3b94a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992329595 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.1992329595
Directory /workspace/30.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/30.pwrmgr_disable_rom_integrity_check.1112182535
Short name T209
Test name
Test status
Simulation time 73675334 ps
CPU time 0.78 seconds
Started Apr 21 04:07:12 PM PDT 24
Finished Apr 21 04:07:13 PM PDT 24
Peak memory 198816 kb
Host smart-1e18a143-bdb6-4f48-9969-e9673c3dfd60
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112182535 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_dis
able_rom_integrity_check.1112182535
Directory /workspace/30.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.1145997169
Short name T185
Test name
Test status
Simulation time 83046871 ps
CPU time 0.59 seconds
Started Apr 21 04:07:15 PM PDT 24
Finished Apr 21 04:07:16 PM PDT 24
Peak memory 197628 kb
Host smart-aada0095-f5a6-4a82-a613-b53112b1505d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145997169 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst
_malfunc.1145997169
Directory /workspace/30.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/30.pwrmgr_escalation_timeout.1501980961
Short name T175
Test name
Test status
Simulation time 728562063 ps
CPU time 0.98 seconds
Started Apr 21 04:07:21 PM PDT 24
Finished Apr 21 04:07:22 PM PDT 24
Peak memory 198052 kb
Host smart-69641b3d-4b45-46b4-b008-8308991684ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501980961 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.1501980961
Directory /workspace/30.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/30.pwrmgr_glitch.2725954835
Short name T657
Test name
Test status
Simulation time 43722051 ps
CPU time 0.65 seconds
Started Apr 21 04:07:15 PM PDT 24
Finished Apr 21 04:07:16 PM PDT 24
Peak memory 197740 kb
Host smart-a7f1ff54-f66f-4d9e-b282-4334d913b441
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725954835 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.2725954835
Directory /workspace/30.pwrmgr_glitch/latest


Test location /workspace/coverage/default/30.pwrmgr_global_esc.1094752160
Short name T228
Test name
Test status
Simulation time 46726142 ps
CPU time 0.66 seconds
Started Apr 21 04:07:13 PM PDT 24
Finished Apr 21 04:07:14 PM PDT 24
Peak memory 197780 kb
Host smart-8e68637a-706c-4335-9044-ce0d5edd3af4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094752160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.1094752160
Directory /workspace/30.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/30.pwrmgr_lowpower_invalid.2122476355
Short name T707
Test name
Test status
Simulation time 45865994 ps
CPU time 0.76 seconds
Started Apr 21 04:07:19 PM PDT 24
Finished Apr 21 04:07:20 PM PDT 24
Peak memory 201020 kb
Host smart-2d10c25a-2b84-4561-8e26-c2411accdfb5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122476355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_inval
id.2122476355
Directory /workspace/30.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/30.pwrmgr_lowpower_wakeup_race.1751413087
Short name T743
Test name
Test status
Simulation time 134569015 ps
CPU time 0.82 seconds
Started Apr 21 04:07:09 PM PDT 24
Finished Apr 21 04:07:11 PM PDT 24
Peak memory 198000 kb
Host smart-4f81b84a-e8af-49d0-8a1c-c31887cab8e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751413087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_w
akeup_race.1751413087
Directory /workspace/30.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/30.pwrmgr_reset.538765953
Short name T922
Test name
Test status
Simulation time 197798719 ps
CPU time 0.95 seconds
Started Apr 21 04:07:10 PM PDT 24
Finished Apr 21 04:07:11 PM PDT 24
Peak memory 199560 kb
Host smart-e36fc6ce-b3c5-410d-a90c-6c42164dcc85
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538765953 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.538765953
Directory /workspace/30.pwrmgr_reset/latest


Test location /workspace/coverage/default/30.pwrmgr_reset_invalid.1531560763
Short name T443
Test name
Test status
Simulation time 159832034 ps
CPU time 0.79 seconds
Started Apr 21 04:07:15 PM PDT 24
Finished Apr 21 04:07:16 PM PDT 24
Peak memory 209100 kb
Host smart-f53f39e2-3980-4a2c-b16f-205df33043e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531560763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.1531560763
Directory /workspace/30.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.388465053
Short name T902
Test name
Test status
Simulation time 188929075 ps
CPU time 1.2 seconds
Started Apr 21 04:07:18 PM PDT 24
Finished Apr 21 04:07:19 PM PDT 24
Peak memory 199920 kb
Host smart-5239e429-1440-40d3-ad89-3525dc00a004
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388465053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_c
m_ctrl_config_regwen.388465053
Directory /workspace/30.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2278502024
Short name T383
Test name
Test status
Simulation time 1208566498 ps
CPU time 2.4 seconds
Started Apr 21 04:07:12 PM PDT 24
Finished Apr 21 04:07:15 PM PDT 24
Peak memory 200880 kb
Host smart-96ff3951-1554-4d62-ac2e-6bdb508d5eaa
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278502024 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2278502024
Directory /workspace/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1167313621
Short name T705
Test name
Test status
Simulation time 904990998 ps
CPU time 3.05 seconds
Started Apr 21 04:07:18 PM PDT 24
Finished Apr 21 04:07:21 PM PDT 24
Peak memory 200812 kb
Host smart-e9bce625-ff3c-4f14-ae8e-a65db1da6ae6
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167313621 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1167313621
Directory /workspace/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.1187246681
Short name T555
Test name
Test status
Simulation time 158813986 ps
CPU time 0.93 seconds
Started Apr 21 04:07:13 PM PDT 24
Finished Apr 21 04:07:14 PM PDT 24
Peak memory 198896 kb
Host smart-e7f3d587-cc60-477f-86a3-8d027a19d864
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187246681 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1187246681
Directory /workspace/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/30.pwrmgr_smoke.3137589661
Short name T441
Test name
Test status
Simulation time 59251895 ps
CPU time 0.65 seconds
Started Apr 21 04:07:17 PM PDT 24
Finished Apr 21 04:07:18 PM PDT 24
Peak memory 199008 kb
Host smart-9b1b0420-5a9b-4cb7-a49d-2741def1f0d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137589661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.3137589661
Directory /workspace/30.pwrmgr_smoke/latest


Test location /workspace/coverage/default/30.pwrmgr_stress_all.3920912695
Short name T574
Test name
Test status
Simulation time 175209769 ps
CPU time 1.14 seconds
Started Apr 21 04:07:15 PM PDT 24
Finished Apr 21 04:07:17 PM PDT 24
Peak memory 199596 kb
Host smart-a76ab8ca-bdb3-441d-9c5c-63c2269f31fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920912695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all.3920912695
Directory /workspace/30.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/30.pwrmgr_wakeup.525959425
Short name T374
Test name
Test status
Simulation time 234475385 ps
CPU time 0.86 seconds
Started Apr 21 04:07:15 PM PDT 24
Finished Apr 21 04:07:17 PM PDT 24
Peak memory 199212 kb
Host smart-c11dcb4a-b223-456f-8841-d7d38d6882a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525959425 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup.525959425
Directory /workspace/30.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/30.pwrmgr_wakeup_reset.1800497268
Short name T313
Test name
Test status
Simulation time 337258389 ps
CPU time 1.68 seconds
Started Apr 21 04:07:13 PM PDT 24
Finished Apr 21 04:07:15 PM PDT 24
Peak memory 200696 kb
Host smart-9c6d9f33-4ca8-4513-8d05-56ba7cc32e8b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800497268 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.1800497268
Directory /workspace/30.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/31.pwrmgr_disable_rom_integrity_check.1463293340
Short name T49
Test name
Test status
Simulation time 67947463 ps
CPU time 0.85 seconds
Started Apr 21 04:07:21 PM PDT 24
Finished Apr 21 04:07:22 PM PDT 24
Peak memory 198784 kb
Host smart-ff34e0f4-60c2-4770-bd3d-4e4a7dc6d62f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463293340 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_dis
able_rom_integrity_check.1463293340
Directory /workspace/31.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.1886397925
Short name T812
Test name
Test status
Simulation time 55704865 ps
CPU time 0.62 seconds
Started Apr 21 04:07:15 PM PDT 24
Finished Apr 21 04:07:16 PM PDT 24
Peak memory 197668 kb
Host smart-13b155ad-1af5-4674-beb3-bc9c5684c038
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886397925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst
_malfunc.1886397925
Directory /workspace/31.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/31.pwrmgr_escalation_timeout.1647818504
Short name T973
Test name
Test status
Simulation time 693037419 ps
CPU time 0.96 seconds
Started Apr 21 04:07:21 PM PDT 24
Finished Apr 21 04:07:22 PM PDT 24
Peak memory 197672 kb
Host smart-e5a96b64-def6-4aaa-bd3a-800bb8223287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647818504 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.1647818504
Directory /workspace/31.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/31.pwrmgr_glitch.309974699
Short name T176
Test name
Test status
Simulation time 63861418 ps
CPU time 0.68 seconds
Started Apr 21 04:07:15 PM PDT 24
Finished Apr 21 04:07:16 PM PDT 24
Peak memory 197740 kb
Host smart-7673924c-2e59-4783-8a2c-07c4b6afbc86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309974699 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.309974699
Directory /workspace/31.pwrmgr_glitch/latest


Test location /workspace/coverage/default/31.pwrmgr_global_esc.2063731453
Short name T950
Test name
Test status
Simulation time 50244840 ps
CPU time 0.58 seconds
Started Apr 21 04:07:15 PM PDT 24
Finished Apr 21 04:07:16 PM PDT 24
Peak memory 197768 kb
Host smart-7913b1de-20b4-4b31-8f15-41e443f4cec2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063731453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.2063731453
Directory /workspace/31.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/31.pwrmgr_lowpower_invalid.1115073382
Short name T287
Test name
Test status
Simulation time 52966927 ps
CPU time 0.73 seconds
Started Apr 21 04:07:22 PM PDT 24
Finished Apr 21 04:07:24 PM PDT 24
Peak memory 200944 kb
Host smart-68601d4c-9121-4e9a-a3ae-a33842f83f9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115073382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_inval
id.1115073382
Directory /workspace/31.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/31.pwrmgr_lowpower_wakeup_race.3579559255
Short name T31
Test name
Test status
Simulation time 237104074 ps
CPU time 0.84 seconds
Started Apr 21 04:07:21 PM PDT 24
Finished Apr 21 04:07:22 PM PDT 24
Peak memory 198144 kb
Host smart-9889a085-1af9-49af-b744-22a9ab517917
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579559255 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_w
akeup_race.3579559255
Directory /workspace/31.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/31.pwrmgr_reset.1457273049
Short name T227
Test name
Test status
Simulation time 105959817 ps
CPU time 0.84 seconds
Started Apr 21 04:07:15 PM PDT 24
Finished Apr 21 04:07:16 PM PDT 24
Peak memory 199600 kb
Host smart-3703f622-2386-468b-9377-604145d6a4c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457273049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.1457273049
Directory /workspace/31.pwrmgr_reset/latest


Test location /workspace/coverage/default/31.pwrmgr_reset_invalid.572271936
Short name T181
Test name
Test status
Simulation time 162980823 ps
CPU time 0.88 seconds
Started Apr 21 04:07:26 PM PDT 24
Finished Apr 21 04:07:27 PM PDT 24
Peak memory 209024 kb
Host smart-a429b053-9d50-4253-b5a3-82ad347bed2d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572271936 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.572271936
Directory /workspace/31.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.1279461837
Short name T291
Test name
Test status
Simulation time 355645942 ps
CPU time 1.19 seconds
Started Apr 21 04:07:18 PM PDT 24
Finished Apr 21 04:07:20 PM PDT 24
Peak memory 200468 kb
Host smart-20be64cc-3150-4adf-8333-c237fd4f24fa
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279461837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_
cm_ctrl_config_regwen.1279461837
Directory /workspace/31.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2177581264
Short name T192
Test name
Test status
Simulation time 932249202 ps
CPU time 3.43 seconds
Started Apr 21 04:07:17 PM PDT 24
Finished Apr 21 04:07:21 PM PDT 24
Peak memory 200840 kb
Host smart-cefe830a-0054-45f2-a3eb-95e3f366ad7a
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177581264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2177581264
Directory /workspace/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3753768531
Short name T594
Test name
Test status
Simulation time 1272367634 ps
CPU time 2.32 seconds
Started Apr 21 04:07:23 PM PDT 24
Finished Apr 21 04:07:26 PM PDT 24
Peak memory 200752 kb
Host smart-51237e6d-08a4-45d9-98a9-22e4f7e483a3
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753768531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3753768531
Directory /workspace/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.3048223925
Short name T937
Test name
Test status
Simulation time 474684402 ps
CPU time 0.87 seconds
Started Apr 21 04:07:17 PM PDT 24
Finished Apr 21 04:07:18 PM PDT 24
Peak memory 198788 kb
Host smart-2e4101ed-303a-4ba5-9f43-48088c893ec6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048223925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3048223925
Directory /workspace/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/31.pwrmgr_smoke.1251406854
Short name T917
Test name
Test status
Simulation time 32797123 ps
CPU time 0.7 seconds
Started Apr 21 04:07:15 PM PDT 24
Finished Apr 21 04:07:17 PM PDT 24
Peak memory 199148 kb
Host smart-4dc008f6-0791-4d14-821c-4251a16aa396
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251406854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.1251406854
Directory /workspace/31.pwrmgr_smoke/latest


Test location /workspace/coverage/default/31.pwrmgr_stress_all.364192726
Short name T109
Test name
Test status
Simulation time 1474916642 ps
CPU time 5.51 seconds
Started Apr 21 04:07:18 PM PDT 24
Finished Apr 21 04:07:24 PM PDT 24
Peak memory 200980 kb
Host smart-f9865556-d47a-400a-9b30-09ebacf88352
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364192726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.364192726
Directory /workspace/31.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/31.pwrmgr_stress_all_with_rand_reset.659190700
Short name T528
Test name
Test status
Simulation time 17514821440 ps
CPU time 10.21 seconds
Started Apr 21 04:07:20 PM PDT 24
Finished Apr 21 04:07:30 PM PDT 24
Peak memory 201076 kb
Host smart-e7bba2fc-60c4-4c64-9c15-f6350875c7c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659190700 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all_with_rand_reset.659190700
Directory /workspace/31.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/31.pwrmgr_wakeup.2006391746
Short name T568
Test name
Test status
Simulation time 265360653 ps
CPU time 0.76 seconds
Started Apr 21 04:07:15 PM PDT 24
Finished Apr 21 04:07:16 PM PDT 24
Peak memory 198112 kb
Host smart-d710a98e-1be4-4775-998e-f3e998026125
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006391746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.2006391746
Directory /workspace/31.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/31.pwrmgr_wakeup_reset.3482603594
Short name T604
Test name
Test status
Simulation time 284057780 ps
CPU time 1.1 seconds
Started Apr 21 04:07:21 PM PDT 24
Finished Apr 21 04:07:22 PM PDT 24
Peak memory 199964 kb
Host smart-ad77062c-19c9-4c15-b30b-e55bea891160
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482603594 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.3482603594
Directory /workspace/31.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/32.pwrmgr_aborted_low_power.3305859008
Short name T47
Test name
Test status
Simulation time 128592095 ps
CPU time 0.81 seconds
Started Apr 21 04:07:25 PM PDT 24
Finished Apr 21 04:07:26 PM PDT 24
Peak memory 199520 kb
Host smart-f59a4061-d5e0-4064-ae1a-212a372c10f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305859008 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.3305859008
Directory /workspace/32.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.2232387278
Short name T579
Test name
Test status
Simulation time 33989776 ps
CPU time 0.64 seconds
Started Apr 21 04:07:22 PM PDT 24
Finished Apr 21 04:07:23 PM PDT 24
Peak memory 196964 kb
Host smart-a08ee783-75b8-4b34-9c5d-29d23349ffa4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232387278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst
_malfunc.2232387278
Directory /workspace/32.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/32.pwrmgr_escalation_timeout.2045382222
Short name T661
Test name
Test status
Simulation time 1247744099 ps
CPU time 0.95 seconds
Started Apr 21 04:07:21 PM PDT 24
Finished Apr 21 04:07:22 PM PDT 24
Peak memory 197780 kb
Host smart-54274389-2056-44ef-9830-69a977a7cf8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045382222 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.2045382222
Directory /workspace/32.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/32.pwrmgr_glitch.3749690346
Short name T592
Test name
Test status
Simulation time 48855739 ps
CPU time 0.64 seconds
Started Apr 21 04:07:18 PM PDT 24
Finished Apr 21 04:07:20 PM PDT 24
Peak memory 197804 kb
Host smart-df4635a3-8ddf-46db-a31d-7aa5efa316c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749690346 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.3749690346
Directory /workspace/32.pwrmgr_glitch/latest


Test location /workspace/coverage/default/32.pwrmgr_global_esc.1577655380
Short name T573
Test name
Test status
Simulation time 127797168 ps
CPU time 0.61 seconds
Started Apr 21 04:07:22 PM PDT 24
Finished Apr 21 04:07:23 PM PDT 24
Peak memory 198032 kb
Host smart-d97db087-88dc-4ba9-92d5-aa2039ad98b5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577655380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.1577655380
Directory /workspace/32.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/32.pwrmgr_lowpower_invalid.4144867251
Short name T806
Test name
Test status
Simulation time 45199510 ps
CPU time 0.71 seconds
Started Apr 21 04:07:20 PM PDT 24
Finished Apr 21 04:07:21 PM PDT 24
Peak memory 200848 kb
Host smart-8c16b99b-dd19-4128-8c24-afb559180eb3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144867251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_inval
id.4144867251
Directory /workspace/32.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/32.pwrmgr_lowpower_wakeup_race.2871899826
Short name T559
Test name
Test status
Simulation time 190690794 ps
CPU time 1.15 seconds
Started Apr 21 04:07:17 PM PDT 24
Finished Apr 21 04:07:19 PM PDT 24
Peak memory 199320 kb
Host smart-4d4662ce-7ed3-48cf-95a2-6b920c1f4125
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871899826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_w
akeup_race.2871899826
Directory /workspace/32.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/32.pwrmgr_reset.2702640855
Short name T301
Test name
Test status
Simulation time 154756757 ps
CPU time 0.88 seconds
Started Apr 21 04:07:19 PM PDT 24
Finished Apr 21 04:07:20 PM PDT 24
Peak memory 199432 kb
Host smart-01e7dce4-0274-4134-a808-1c37a0d9548c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702640855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.2702640855
Directory /workspace/32.pwrmgr_reset/latest


Test location /workspace/coverage/default/32.pwrmgr_reset_invalid.1786319339
Short name T40
Test name
Test status
Simulation time 212060047 ps
CPU time 0.84 seconds
Started Apr 21 04:07:22 PM PDT 24
Finished Apr 21 04:07:24 PM PDT 24
Peak memory 209004 kb
Host smart-7777bf80-5507-4b4c-bae9-6217c1a480ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786319339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.1786319339
Directory /workspace/32.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.2129698954
Short name T789
Test name
Test status
Simulation time 200655929 ps
CPU time 1.02 seconds
Started Apr 21 04:07:21 PM PDT 24
Finished Apr 21 04:07:22 PM PDT 24
Peak memory 199612 kb
Host smart-12046f69-c745-435b-a97c-348f3636095f
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129698954 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_
cm_ctrl_config_regwen.2129698954
Directory /workspace/32.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.83885989
Short name T375
Test name
Test status
Simulation time 2406539329 ps
CPU time 1.91 seconds
Started Apr 21 04:07:23 PM PDT 24
Finished Apr 21 04:07:26 PM PDT 24
Peak memory 200984 kb
Host smart-c8433619-7aa1-4c7a-8141-fbf2c0df7e72
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83885989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +
UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.83885989
Directory /workspace/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1431197077
Short name T846
Test name
Test status
Simulation time 896050151 ps
CPU time 3.21 seconds
Started Apr 21 04:07:19 PM PDT 24
Finished Apr 21 04:07:23 PM PDT 24
Peak memory 200676 kb
Host smart-e4a21bba-8242-4c3e-a3e0-6fbb487e4b49
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431197077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1431197077
Directory /workspace/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.433033470
Short name T585
Test name
Test status
Simulation time 67404280 ps
CPU time 1.04 seconds
Started Apr 21 04:07:22 PM PDT 24
Finished Apr 21 04:07:24 PM PDT 24
Peak memory 199228 kb
Host smart-70ff4eb1-471a-4353-bbe1-18591c74503d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433033470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig_
mubi.433033470
Directory /workspace/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/32.pwrmgr_smoke.325604522
Short name T875
Test name
Test status
Simulation time 30855818 ps
CPU time 0.76 seconds
Started Apr 21 04:07:20 PM PDT 24
Finished Apr 21 04:07:21 PM PDT 24
Peak memory 198996 kb
Host smart-d901afa9-8702-4a12-b162-69ce15b5c099
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325604522 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.325604522
Directory /workspace/32.pwrmgr_smoke/latest


Test location /workspace/coverage/default/32.pwrmgr_stress_all.3291868653
Short name T505
Test name
Test status
Simulation time 2326383964 ps
CPU time 4.23 seconds
Started Apr 21 04:07:23 PM PDT 24
Finished Apr 21 04:07:28 PM PDT 24
Peak memory 200996 kb
Host smart-a6d8ca21-c4e2-4261-93b5-9c1c3c3860c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291868653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.3291868653
Directory /workspace/32.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/32.pwrmgr_stress_all_with_rand_reset.1370598350
Short name T136
Test name
Test status
Simulation time 17984411460 ps
CPU time 11.29 seconds
Started Apr 21 04:07:22 PM PDT 24
Finished Apr 21 04:07:33 PM PDT 24
Peak memory 201112 kb
Host smart-637f9b7f-ca05-42f4-8bb5-705c28070c0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370598350 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all_with_rand_reset.1370598350
Directory /workspace/32.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/32.pwrmgr_wakeup.3230536469
Short name T179
Test name
Test status
Simulation time 212568625 ps
CPU time 1 seconds
Started Apr 21 04:07:19 PM PDT 24
Finished Apr 21 04:07:20 PM PDT 24
Peak memory 199424 kb
Host smart-2afcb946-3df5-47e6-80bb-39a98585a54a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230536469 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.3230536469
Directory /workspace/32.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/32.pwrmgr_wakeup_reset.3684901376
Short name T184
Test name
Test status
Simulation time 361951989 ps
CPU time 1.23 seconds
Started Apr 21 04:07:19 PM PDT 24
Finished Apr 21 04:07:21 PM PDT 24
Peak memory 200784 kb
Host smart-00bb21e5-b8f8-45a2-ae45-81a9db192acb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684901376 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.3684901376
Directory /workspace/32.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/33.pwrmgr_aborted_low_power.806759487
Short name T462
Test name
Test status
Simulation time 36264914 ps
CPU time 1.29 seconds
Started Apr 21 04:07:23 PM PDT 24
Finished Apr 21 04:07:24 PM PDT 24
Peak memory 200664 kb
Host smart-2b6fe9bf-949f-4523-a928-df77a3fe79e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806759487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.806759487
Directory /workspace/33.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/33.pwrmgr_disable_rom_integrity_check.3611617500
Short name T154
Test name
Test status
Simulation time 59013287 ps
CPU time 0.89 seconds
Started Apr 21 04:07:28 PM PDT 24
Finished Apr 21 04:07:29 PM PDT 24
Peak memory 198852 kb
Host smart-df52f9ef-4582-4efc-8070-bac1abc74285
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611617500 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_dis
able_rom_integrity_check.3611617500
Directory /workspace/33.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.2188770168
Short name T410
Test name
Test status
Simulation time 29324998 ps
CPU time 0.65 seconds
Started Apr 21 04:07:24 PM PDT 24
Finished Apr 21 04:07:25 PM PDT 24
Peak memory 197652 kb
Host smart-6b507d63-602f-459c-a0c3-6859b54e6497
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188770168 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst
_malfunc.2188770168
Directory /workspace/33.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/33.pwrmgr_escalation_timeout.2910313486
Short name T427
Test name
Test status
Simulation time 634265793 ps
CPU time 0.95 seconds
Started Apr 21 04:07:26 PM PDT 24
Finished Apr 21 04:07:27 PM PDT 24
Peak memory 198036 kb
Host smart-9b86aa8c-f13f-45c4-8f9d-18a3b4007440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910313486 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.2910313486
Directory /workspace/33.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/33.pwrmgr_glitch.3926799685
Short name T88
Test name
Test status
Simulation time 29980480 ps
CPU time 0.73 seconds
Started Apr 21 04:07:28 PM PDT 24
Finished Apr 21 04:07:29 PM PDT 24
Peak memory 197712 kb
Host smart-20b2b553-f94b-4fa3-9004-99adce88f5a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926799685 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.3926799685
Directory /workspace/33.pwrmgr_glitch/latest


Test location /workspace/coverage/default/33.pwrmgr_global_esc.2973147987
Short name T925
Test name
Test status
Simulation time 50491238 ps
CPU time 0.68 seconds
Started Apr 21 04:07:23 PM PDT 24
Finished Apr 21 04:07:24 PM PDT 24
Peak memory 197780 kb
Host smart-93d03eb9-2bc8-4648-af5c-683ad89a43ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973147987 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.2973147987
Directory /workspace/33.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/33.pwrmgr_lowpower_invalid.1619908573
Short name T753
Test name
Test status
Simulation time 54026897 ps
CPU time 0.73 seconds
Started Apr 21 04:07:25 PM PDT 24
Finished Apr 21 04:07:27 PM PDT 24
Peak memory 200980 kb
Host smart-1ae1beee-c258-4d31-b160-56d41119130f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619908573 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_inval
id.1619908573
Directory /workspace/33.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/33.pwrmgr_lowpower_wakeup_race.2341855104
Short name T35
Test name
Test status
Simulation time 102872616 ps
CPU time 0.68 seconds
Started Apr 21 04:07:21 PM PDT 24
Finished Apr 21 04:07:22 PM PDT 24
Peak memory 197848 kb
Host smart-1606497e-f216-44ce-a49e-8d663e0a184e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341855104 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_w
akeup_race.2341855104
Directory /workspace/33.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/33.pwrmgr_reset.3320922871
Short name T544
Test name
Test status
Simulation time 97296302 ps
CPU time 0.82 seconds
Started Apr 21 04:07:20 PM PDT 24
Finished Apr 21 04:07:21 PM PDT 24
Peak memory 199352 kb
Host smart-9ed5793c-96ec-47db-8294-d340adfcf3bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320922871 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.3320922871
Directory /workspace/33.pwrmgr_reset/latest


Test location /workspace/coverage/default/33.pwrmgr_reset_invalid.1271069379
Short name T708
Test name
Test status
Simulation time 97178670 ps
CPU time 1.04 seconds
Started Apr 21 04:07:26 PM PDT 24
Finished Apr 21 04:07:27 PM PDT 24
Peak memory 209172 kb
Host smart-f45dadca-8ca2-4170-b3e7-39a67aff152e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271069379 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.1271069379
Directory /workspace/33.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.1930061841
Short name T520
Test name
Test status
Simulation time 277206262 ps
CPU time 1.66 seconds
Started Apr 21 04:07:28 PM PDT 24
Finished Apr 21 04:07:30 PM PDT 24
Peak memory 200608 kb
Host smart-a98d3a7c-7649-474a-ad9b-a4705514501a
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930061841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_
cm_ctrl_config_regwen.1930061841
Directory /workspace/33.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1358660663
Short name T364
Test name
Test status
Simulation time 780147354 ps
CPU time 2.98 seconds
Started Apr 21 04:07:22 PM PDT 24
Finished Apr 21 04:07:25 PM PDT 24
Peak memory 200732 kb
Host smart-94db513d-9f46-42a3-9ca7-e9f5bbfd9430
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358660663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1358660663
Directory /workspace/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2452983137
Short name T493
Test name
Test status
Simulation time 975851885 ps
CPU time 2.91 seconds
Started Apr 21 04:07:22 PM PDT 24
Finished Apr 21 04:07:25 PM PDT 24
Peak memory 200892 kb
Host smart-020e96a4-9492-4111-a4e5-c2c7528493c8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452983137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2452983137
Directory /workspace/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.4121302072
Short name T609
Test name
Test status
Simulation time 62272198 ps
CPU time 0.85 seconds
Started Apr 21 04:07:22 PM PDT 24
Finished Apr 21 04:07:23 PM PDT 24
Peak memory 198772 kb
Host smart-36432dba-664e-499b-a3f3-f4cc34af9ab1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121302072 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4121302072
Directory /workspace/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/33.pwrmgr_smoke.3725144591
Short name T895
Test name
Test status
Simulation time 32035765 ps
CPU time 0.69 seconds
Started Apr 21 04:07:20 PM PDT 24
Finished Apr 21 04:07:21 PM PDT 24
Peak memory 198188 kb
Host smart-fbe71e2d-3055-427c-b364-d106e8af9322
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725144591 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.3725144591
Directory /workspace/33.pwrmgr_smoke/latest


Test location /workspace/coverage/default/33.pwrmgr_stress_all.3509836109
Short name T44
Test name
Test status
Simulation time 2290916861 ps
CPU time 3.43 seconds
Started Apr 21 04:07:24 PM PDT 24
Finished Apr 21 04:07:28 PM PDT 24
Peak memory 200976 kb
Host smart-7c1de69c-3bd6-4ce4-b90d-f7c2f94fac70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509836109 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all.3509836109
Directory /workspace/33.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/33.pwrmgr_stress_all_with_rand_reset.1319403083
Short name T747
Test name
Test status
Simulation time 15994384321 ps
CPU time 12.14 seconds
Started Apr 21 04:07:26 PM PDT 24
Finished Apr 21 04:07:39 PM PDT 24
Peak memory 201064 kb
Host smart-44e466c6-0a0e-4e40-b78a-e977808975d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319403083 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all_with_rand_reset.1319403083
Directory /workspace/33.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/33.pwrmgr_wakeup.2329298203
Short name T464
Test name
Test status
Simulation time 181473452 ps
CPU time 0.78 seconds
Started Apr 21 04:07:23 PM PDT 24
Finished Apr 21 04:07:24 PM PDT 24
Peak memory 198084 kb
Host smart-ca706e49-aa62-4e2a-97c8-96e4cb0103f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329298203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.2329298203
Directory /workspace/33.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/33.pwrmgr_wakeup_reset.4224864490
Short name T416
Test name
Test status
Simulation time 319576768 ps
CPU time 0.83 seconds
Started Apr 21 04:07:23 PM PDT 24
Finished Apr 21 04:07:24 PM PDT 24
Peak memory 199628 kb
Host smart-0c48eb42-e8d9-4e76-a071-7c2dbf395d92
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224864490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.4224864490
Directory /workspace/33.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/34.pwrmgr_aborted_low_power.758997860
Short name T479
Test name
Test status
Simulation time 33457012 ps
CPU time 1.07 seconds
Started Apr 21 04:07:26 PM PDT 24
Finished Apr 21 04:07:27 PM PDT 24
Peak memory 200680 kb
Host smart-0db9c7cc-1018-4dfd-83b5-0563d70f7478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758997860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.758997860
Directory /workspace/34.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/34.pwrmgr_disable_rom_integrity_check.2058301401
Short name T454
Test name
Test status
Simulation time 76625473 ps
CPU time 0.8 seconds
Started Apr 21 04:07:31 PM PDT 24
Finished Apr 21 04:07:33 PM PDT 24
Peak memory 198256 kb
Host smart-2098a7a3-c213-4563-a4e2-c387737d2d0c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058301401 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_dis
able_rom_integrity_check.2058301401
Directory /workspace/34.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.2126581481
Short name T198
Test name
Test status
Simulation time 31094300 ps
CPU time 0.64 seconds
Started Apr 21 04:07:30 PM PDT 24
Finished Apr 21 04:07:31 PM PDT 24
Peak memory 196968 kb
Host smart-c5bd5ecb-0142-4980-87b3-3718523ed95d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126581481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst
_malfunc.2126581481
Directory /workspace/34.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/34.pwrmgr_escalation_timeout.123452141
Short name T326
Test name
Test status
Simulation time 180159156 ps
CPU time 0.98 seconds
Started Apr 21 04:07:30 PM PDT 24
Finished Apr 21 04:07:31 PM PDT 24
Peak memory 197824 kb
Host smart-0fbe225d-9120-4603-bcf6-e57beaa7e635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123452141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.123452141
Directory /workspace/34.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/34.pwrmgr_glitch.388500042
Short name T534
Test name
Test status
Simulation time 59427022 ps
CPU time 0.64 seconds
Started Apr 21 04:07:29 PM PDT 24
Finished Apr 21 04:07:30 PM PDT 24
Peak memory 197240 kb
Host smart-015130be-3188-4431-a150-a3c5d3cf53ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388500042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.388500042
Directory /workspace/34.pwrmgr_glitch/latest


Test location /workspace/coverage/default/34.pwrmgr_global_esc.4009704156
Short name T972
Test name
Test status
Simulation time 26344776 ps
CPU time 0.63 seconds
Started Apr 21 04:07:28 PM PDT 24
Finished Apr 21 04:07:29 PM PDT 24
Peak memory 197768 kb
Host smart-ae9080f8-10a8-4963-b663-75b796f43c2b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009704156 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.4009704156
Directory /workspace/34.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/34.pwrmgr_lowpower_invalid.2084672489
Short name T560
Test name
Test status
Simulation time 51697744 ps
CPU time 0.71 seconds
Started Apr 21 04:07:31 PM PDT 24
Finished Apr 21 04:07:32 PM PDT 24
Peak memory 200768 kb
Host smart-817ac8ac-6139-4dbb-8137-5b95d33da3af
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084672489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_inval
id.2084672489
Directory /workspace/34.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/34.pwrmgr_lowpower_wakeup_race.368270647
Short name T399
Test name
Test status
Simulation time 328441755 ps
CPU time 0.99 seconds
Started Apr 21 04:07:25 PM PDT 24
Finished Apr 21 04:07:27 PM PDT 24
Peak memory 199192 kb
Host smart-523c9828-acd3-4c41-9a4a-7e4776352a2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368270647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_wa
keup_race.368270647
Directory /workspace/34.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/34.pwrmgr_reset.1403326482
Short name T567
Test name
Test status
Simulation time 94100712 ps
CPU time 0.78 seconds
Started Apr 21 04:07:26 PM PDT 24
Finished Apr 21 04:07:27 PM PDT 24
Peak memory 198308 kb
Host smart-aab45e1e-1c7b-42bf-a18b-2c09b0807dd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403326482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.1403326482
Directory /workspace/34.pwrmgr_reset/latest


Test location /workspace/coverage/default/34.pwrmgr_reset_invalid.3687156844
Short name T891
Test name
Test status
Simulation time 113146158 ps
CPU time 0.92 seconds
Started Apr 21 04:07:31 PM PDT 24
Finished Apr 21 04:07:33 PM PDT 24
Peak memory 200780 kb
Host smart-740b5fb0-fd74-43c0-b3e1-095fa6cb5fb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687156844 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.3687156844
Directory /workspace/34.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.1259168227
Short name T547
Test name
Test status
Simulation time 366927522 ps
CPU time 1.06 seconds
Started Apr 21 04:07:28 PM PDT 24
Finished Apr 21 04:07:29 PM PDT 24
Peak memory 200516 kb
Host smart-4de5c4d3-025e-4fc8-bb10-3486fb2a4883
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259168227 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_
cm_ctrl_config_regwen.1259168227
Directory /workspace/34.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2906260096
Short name T628
Test name
Test status
Simulation time 896656708 ps
CPU time 3 seconds
Started Apr 21 04:07:32 PM PDT 24
Finished Apr 21 04:07:35 PM PDT 24
Peak memory 200932 kb
Host smart-c4448990-a58f-48ce-ac55-cfbd53ed1069
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906260096 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2906260096
Directory /workspace/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4190578349
Short name T540
Test name
Test status
Simulation time 1019736789 ps
CPU time 2.27 seconds
Started Apr 21 04:07:31 PM PDT 24
Finished Apr 21 04:07:33 PM PDT 24
Peak memory 200788 kb
Host smart-9790fdb4-2e26-442b-b1e6-fc47d3c14a7c
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190578349 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4190578349
Directory /workspace/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.67011974
Short name T556
Test name
Test status
Simulation time 71784802 ps
CPU time 0.91 seconds
Started Apr 21 04:07:24 PM PDT 24
Finished Apr 21 04:07:26 PM PDT 24
Peak memory 199088 kb
Host smart-27d7e481-0e62-4f7d-b65f-2dd5bbeaedc8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67011974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.67011974
Directory /workspace/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/34.pwrmgr_smoke.2905805487
Short name T402
Test name
Test status
Simulation time 54661614 ps
CPU time 0.67 seconds
Started Apr 21 04:07:24 PM PDT 24
Finished Apr 21 04:07:25 PM PDT 24
Peak memory 199004 kb
Host smart-ab8cf3f3-2389-4dac-a1d5-01eabda9fd65
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905805487 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.2905805487
Directory /workspace/34.pwrmgr_smoke/latest


Test location /workspace/coverage/default/34.pwrmgr_stress_all.4046371130
Short name T338
Test name
Test status
Simulation time 570905277 ps
CPU time 2.06 seconds
Started Apr 21 04:07:33 PM PDT 24
Finished Apr 21 04:07:36 PM PDT 24
Peak memory 200924 kb
Host smart-9bd870ee-370a-48a9-81b1-a5dde0588e9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046371130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all.4046371130
Directory /workspace/34.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/34.pwrmgr_wakeup.1486478737
Short name T515
Test name
Test status
Simulation time 56196286 ps
CPU time 0.64 seconds
Started Apr 21 04:07:31 PM PDT 24
Finished Apr 21 04:07:32 PM PDT 24
Peak memory 198120 kb
Host smart-d50d9c58-c7c9-4d14-a5ec-05c643460746
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486478737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.1486478737
Directory /workspace/34.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/34.pwrmgr_wakeup_reset.2185903264
Short name T932
Test name
Test status
Simulation time 71150149 ps
CPU time 0.78 seconds
Started Apr 21 04:07:28 PM PDT 24
Finished Apr 21 04:07:29 PM PDT 24
Peak memory 198792 kb
Host smart-97b14a75-2580-429b-a208-e4c314077207
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185903264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.2185903264
Directory /workspace/34.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/35.pwrmgr_aborted_low_power.739999652
Short name T33
Test name
Test status
Simulation time 65971423 ps
CPU time 0.83 seconds
Started Apr 21 04:07:31 PM PDT 24
Finished Apr 21 04:07:32 PM PDT 24
Peak memory 199744 kb
Host smart-2209ec13-243f-4d09-a376-715b9d606cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739999652 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.739999652
Directory /workspace/35.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/35.pwrmgr_disable_rom_integrity_check.1536940139
Short name T153
Test name
Test status
Simulation time 86862689 ps
CPU time 0.73 seconds
Started Apr 21 04:07:33 PM PDT 24
Finished Apr 21 04:07:34 PM PDT 24
Peak memory 198896 kb
Host smart-ac2f9d37-479e-4bd9-8581-a38ded0e7c75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536940139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_dis
able_rom_integrity_check.1536940139
Directory /workspace/35.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.655310923
Short name T356
Test name
Test status
Simulation time 39186505 ps
CPU time 0.63 seconds
Started Apr 21 04:07:32 PM PDT 24
Finished Apr 21 04:07:33 PM PDT 24
Peak memory 197604 kb
Host smart-a20ec0b7-b4cf-4c68-8561-ab307415ce66
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655310923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_
malfunc.655310923
Directory /workspace/35.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/35.pwrmgr_escalation_timeout.2853390506
Short name T518
Test name
Test status
Simulation time 583358929 ps
CPU time 0.99 seconds
Started Apr 21 04:07:33 PM PDT 24
Finished Apr 21 04:07:34 PM PDT 24
Peak memory 198088 kb
Host smart-29346428-5d70-403d-a3d2-83bd7a065d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853390506 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.2853390506
Directory /workspace/35.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/35.pwrmgr_glitch.2701818802
Short name T369
Test name
Test status
Simulation time 42273281 ps
CPU time 0.68 seconds
Started Apr 21 04:07:35 PM PDT 24
Finished Apr 21 04:07:36 PM PDT 24
Peak memory 197084 kb
Host smart-f66cf915-0d06-4b29-bacd-1b542ab69cd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701818802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.2701818802
Directory /workspace/35.pwrmgr_glitch/latest


Test location /workspace/coverage/default/35.pwrmgr_global_esc.1295457246
Short name T258
Test name
Test status
Simulation time 23969227 ps
CPU time 0.63 seconds
Started Apr 21 04:07:32 PM PDT 24
Finished Apr 21 04:07:33 PM PDT 24
Peak memory 197772 kb
Host smart-fedcfe1c-4f96-4e0e-a4b5-9fc0396f9d57
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295457246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.1295457246
Directory /workspace/35.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/35.pwrmgr_lowpower_invalid.2074128810
Short name T611
Test name
Test status
Simulation time 49788455 ps
CPU time 0.71 seconds
Started Apr 21 04:07:36 PM PDT 24
Finished Apr 21 04:07:37 PM PDT 24
Peak memory 200980 kb
Host smart-2042c09c-f63d-42ab-a7e6-2fe99923d86c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074128810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_inval
id.2074128810
Directory /workspace/35.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/35.pwrmgr_reset.342929001
Short name T450
Test name
Test status
Simulation time 29197827 ps
CPU time 0.75 seconds
Started Apr 21 04:07:31 PM PDT 24
Finished Apr 21 04:07:32 PM PDT 24
Peak memory 198840 kb
Host smart-f64a9adc-3888-4f05-8850-9eccbf4dc6bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342929001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.342929001
Directory /workspace/35.pwrmgr_reset/latest


Test location /workspace/coverage/default/35.pwrmgr_reset_invalid.821650138
Short name T246
Test name
Test status
Simulation time 94748359 ps
CPU time 1.11 seconds
Started Apr 21 04:07:34 PM PDT 24
Finished Apr 21 04:07:35 PM PDT 24
Peak memory 209200 kb
Host smart-2ac1c945-d670-4e36-b524-74c737981cda
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821650138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.821650138
Directory /workspace/35.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.1128576876
Short name T811
Test name
Test status
Simulation time 90004314 ps
CPU time 0.91 seconds
Started Apr 21 04:07:30 PM PDT 24
Finished Apr 21 04:07:31 PM PDT 24
Peak memory 199068 kb
Host smart-07f4371d-d9e3-4ffd-a537-8bf63db87fbe
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128576876 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_
cm_ctrl_config_regwen.1128576876
Directory /workspace/35.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2645494358
Short name T841
Test name
Test status
Simulation time 775883877 ps
CPU time 3.22 seconds
Started Apr 21 04:07:36 PM PDT 24
Finished Apr 21 04:07:39 PM PDT 24
Peak memory 200860 kb
Host smart-54041c92-3230-41a5-be79-e76eda733406
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645494358 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2645494358
Directory /workspace/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.168682696
Short name T610
Test name
Test status
Simulation time 854539660 ps
CPU time 3.25 seconds
Started Apr 21 04:07:31 PM PDT 24
Finished Apr 21 04:07:35 PM PDT 24
Peak memory 200916 kb
Host smart-6f568a1d-059b-4d6b-bc06-38b14f05cc04
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168682696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.168682696
Directory /workspace/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.3687105231
Short name T787
Test name
Test status
Simulation time 574496937 ps
CPU time 0.85 seconds
Started Apr 21 04:07:34 PM PDT 24
Finished Apr 21 04:07:35 PM PDT 24
Peak memory 198824 kb
Host smart-225573fc-7d49-47ec-b293-d2bba669400c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687105231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig
_mubi.3687105231
Directory /workspace/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/35.pwrmgr_smoke.2400197131
Short name T422
Test name
Test status
Simulation time 33591441 ps
CPU time 0.71 seconds
Started Apr 21 04:07:28 PM PDT 24
Finished Apr 21 04:07:29 PM PDT 24
Peak memory 198164 kb
Host smart-e34e5332-4f3a-4b9d-8dee-1c3286660913
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400197131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.2400197131
Directory /workspace/35.pwrmgr_smoke/latest


Test location /workspace/coverage/default/35.pwrmgr_stress_all.3844910485
Short name T398
Test name
Test status
Simulation time 589298710 ps
CPU time 1.18 seconds
Started Apr 21 04:07:33 PM PDT 24
Finished Apr 21 04:07:34 PM PDT 24
Peak memory 200848 kb
Host smart-540521b1-41cd-4c66-93d3-914bfae5c2df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844910485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.3844910485
Directory /workspace/35.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/35.pwrmgr_stress_all_with_rand_reset.3832090903
Short name T54
Test name
Test status
Simulation time 12471384023 ps
CPU time 27.16 seconds
Started Apr 21 04:07:36 PM PDT 24
Finished Apr 21 04:08:04 PM PDT 24
Peak memory 201052 kb
Host smart-22c2499d-ee9c-4a14-ab20-d5a9a028420f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832090903 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all_with_rand_reset.3832090903
Directory /workspace/35.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/35.pwrmgr_wakeup.755186908
Short name T660
Test name
Test status
Simulation time 234810526 ps
CPU time 0.91 seconds
Started Apr 21 04:07:32 PM PDT 24
Finished Apr 21 04:07:33 PM PDT 24
Peak memory 199284 kb
Host smart-a0359610-5f92-48c8-a7cb-7f906056f4e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755186908 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.755186908
Directory /workspace/35.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/35.pwrmgr_wakeup_reset.1415553004
Short name T196
Test name
Test status
Simulation time 218453809 ps
CPU time 1.23 seconds
Started Apr 21 04:07:30 PM PDT 24
Finished Apr 21 04:07:31 PM PDT 24
Peak memory 199924 kb
Host smart-58771c19-1765-4fcb-9136-763dff75c0f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415553004 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.1415553004
Directory /workspace/35.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/36.pwrmgr_aborted_low_power.370324350
Short name T39
Test name
Test status
Simulation time 42121440 ps
CPU time 0.91 seconds
Started Apr 21 04:07:33 PM PDT 24
Finished Apr 21 04:07:35 PM PDT 24
Peak memory 199704 kb
Host smart-3ab888dc-9f10-4f1d-845a-9be2396d2751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370324350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.370324350
Directory /workspace/36.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/36.pwrmgr_disable_rom_integrity_check.2873083629
Short name T365
Test name
Test status
Simulation time 56632964 ps
CPU time 0.78 seconds
Started Apr 21 04:07:43 PM PDT 24
Finished Apr 21 04:07:45 PM PDT 24
Peak memory 198780 kb
Host smart-23d4d104-b8d0-421b-98c6-6ca648648861
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873083629 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_dis
able_rom_integrity_check.2873083629
Directory /workspace/36.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.2919449667
Short name T879
Test name
Test status
Simulation time 29017125 ps
CPU time 0.65 seconds
Started Apr 21 04:07:44 PM PDT 24
Finished Apr 21 04:07:45 PM PDT 24
Peak memory 197660 kb
Host smart-945024f1-3fd1-4d87-b02b-1205886135de
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919449667 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst
_malfunc.2919449667
Directory /workspace/36.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/36.pwrmgr_escalation_timeout.264162897
Short name T174
Test name
Test status
Simulation time 636646526 ps
CPU time 0.99 seconds
Started Apr 21 04:07:37 PM PDT 24
Finished Apr 21 04:07:38 PM PDT 24
Peak memory 197788 kb
Host smart-7ad87102-61b1-46ae-9474-6378313ad0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264162897 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.264162897
Directory /workspace/36.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/36.pwrmgr_glitch.546372452
Short name T606
Test name
Test status
Simulation time 45373227 ps
CPU time 0.73 seconds
Started Apr 21 04:07:34 PM PDT 24
Finished Apr 21 04:07:35 PM PDT 24
Peak memory 197692 kb
Host smart-b01157d8-50da-44dc-abeb-a7cc360a3010
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546372452 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.546372452
Directory /workspace/36.pwrmgr_glitch/latest


Test location /workspace/coverage/default/36.pwrmgr_global_esc.3299880010
Short name T535
Test name
Test status
Simulation time 45745472 ps
CPU time 0.63 seconds
Started Apr 21 04:07:49 PM PDT 24
Finished Apr 21 04:07:50 PM PDT 24
Peak memory 197720 kb
Host smart-980cd15c-43b4-4471-a086-5949d746ed84
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299880010 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.3299880010
Directory /workspace/36.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/36.pwrmgr_lowpower_invalid.4069674662
Short name T10
Test name
Test status
Simulation time 212660055 ps
CPU time 0.74 seconds
Started Apr 21 04:07:35 PM PDT 24
Finished Apr 21 04:07:36 PM PDT 24
Peak memory 201004 kb
Host smart-6f51823b-7452-470d-b583-73eb61f339ff
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069674662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_inval
id.4069674662
Directory /workspace/36.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/36.pwrmgr_lowpower_wakeup_race.1148173220
Short name T358
Test name
Test status
Simulation time 374429127 ps
CPU time 1.05 seconds
Started Apr 21 04:07:33 PM PDT 24
Finished Apr 21 04:07:35 PM PDT 24
Peak memory 199452 kb
Host smart-f2efa9eb-838b-4975-be84-d3487b9a868c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148173220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_w
akeup_race.1148173220
Directory /workspace/36.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/36.pwrmgr_reset.3872709064
Short name T955
Test name
Test status
Simulation time 42951297 ps
CPU time 0.64 seconds
Started Apr 21 04:07:34 PM PDT 24
Finished Apr 21 04:07:34 PM PDT 24
Peak memory 198000 kb
Host smart-0e5f0e5a-49e6-4843-a6ce-548dbe46a40f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872709064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.3872709064
Directory /workspace/36.pwrmgr_reset/latest


Test location /workspace/coverage/default/36.pwrmgr_reset_invalid.3746916892
Short name T240
Test name
Test status
Simulation time 162993642 ps
CPU time 0.82 seconds
Started Apr 21 04:07:36 PM PDT 24
Finished Apr 21 04:07:38 PM PDT 24
Peak memory 209068 kb
Host smart-2183b732-3837-4ac4-94f8-014f2e3ecd7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746916892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.3746916892
Directory /workspace/36.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.3919982890
Short name T512
Test name
Test status
Simulation time 172134806 ps
CPU time 1.03 seconds
Started Apr 21 04:07:38 PM PDT 24
Finished Apr 21 04:07:40 PM PDT 24
Peak memory 199828 kb
Host smart-e3e045b9-26cb-4d39-941d-e8c39295d552
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919982890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_
cm_ctrl_config_regwen.3919982890
Directory /workspace/36.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3034166330
Short name T831
Test name
Test status
Simulation time 1003921134 ps
CPU time 2.31 seconds
Started Apr 21 04:07:34 PM PDT 24
Finished Apr 21 04:07:36 PM PDT 24
Peak memory 200808 kb
Host smart-2d4662bd-d0b5-46da-ab0b-24b3b5a1d270
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034166330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3034166330
Directory /workspace/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3290010531
Short name T625
Test name
Test status
Simulation time 2278520526 ps
CPU time 2.23 seconds
Started Apr 21 04:07:35 PM PDT 24
Finished Apr 21 04:07:38 PM PDT 24
Peak memory 201020 kb
Host smart-8475da10-ef5a-425d-aa41-826c54dc3101
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290010531 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3290010531
Directory /workspace/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.1638573787
Short name T186
Test name
Test status
Simulation time 75545127 ps
CPU time 1.02 seconds
Started Apr 21 04:07:36 PM PDT 24
Finished Apr 21 04:07:37 PM PDT 24
Peak memory 199032 kb
Host smart-bf936c11-6541-4f87-b71c-a13c5dfc79e4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638573787 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1638573787
Directory /workspace/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/36.pwrmgr_smoke.2485343689
Short name T491
Test name
Test status
Simulation time 44823714 ps
CPU time 0.74 seconds
Started Apr 21 04:07:35 PM PDT 24
Finished Apr 21 04:07:37 PM PDT 24
Peak memory 199032 kb
Host smart-16f2c85c-79bd-4c8c-b827-ac4ccedfaf83
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485343689 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.2485343689
Directory /workspace/36.pwrmgr_smoke/latest


Test location /workspace/coverage/default/36.pwrmgr_stress_all.3553460611
Short name T867
Test name
Test status
Simulation time 121418537 ps
CPU time 0.89 seconds
Started Apr 21 04:07:47 PM PDT 24
Finished Apr 21 04:07:48 PM PDT 24
Peak memory 199696 kb
Host smart-a2767826-5d2f-4f88-9507-44e30871168e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553460611 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.3553460611
Directory /workspace/36.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/36.pwrmgr_stress_all_with_rand_reset.2552436946
Short name T107
Test name
Test status
Simulation time 6824815930 ps
CPU time 24 seconds
Started Apr 21 04:07:46 PM PDT 24
Finished Apr 21 04:08:10 PM PDT 24
Peak memory 201080 kb
Host smart-48f5d1c0-41d1-437c-95d8-03d72e9a2e5c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552436946 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all_with_rand_reset.2552436946
Directory /workspace/36.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/36.pwrmgr_wakeup.4135936810
Short name T244
Test name
Test status
Simulation time 58758102 ps
CPU time 0.7 seconds
Started Apr 21 04:07:37 PM PDT 24
Finished Apr 21 04:07:38 PM PDT 24
Peak memory 197912 kb
Host smart-3f96f028-35d4-4c70-9929-f879da0b1c4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135936810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.4135936810
Directory /workspace/36.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/36.pwrmgr_wakeup_reset.560499017
Short name T623
Test name
Test status
Simulation time 360416563 ps
CPU time 1.23 seconds
Started Apr 21 04:07:38 PM PDT 24
Finished Apr 21 04:07:39 PM PDT 24
Peak memory 200708 kb
Host smart-21e7db02-804c-493b-b91e-c5d218e8e1ba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560499017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.560499017
Directory /workspace/36.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/37.pwrmgr_aborted_low_power.2860386650
Short name T947
Test name
Test status
Simulation time 114738089 ps
CPU time 0.87 seconds
Started Apr 21 04:07:43 PM PDT 24
Finished Apr 21 04:07:45 PM PDT 24
Peak memory 199676 kb
Host smart-aa840a97-ddc1-449c-8a14-eff995756512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860386650 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.2860386650
Directory /workspace/37.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/37.pwrmgr_disable_rom_integrity_check.842110610
Short name T458
Test name
Test status
Simulation time 64113658 ps
CPU time 0.89 seconds
Started Apr 21 04:07:41 PM PDT 24
Finished Apr 21 04:07:42 PM PDT 24
Peak memory 198352 kb
Host smart-3c929c66-dfec-4da1-bcc3-bf8692fbefe2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842110610 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_disa
ble_rom_integrity_check.842110610
Directory /workspace/37.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.2683032846
Short name T915
Test name
Test status
Simulation time 30064983 ps
CPU time 0.64 seconds
Started Apr 21 04:07:44 PM PDT 24
Finished Apr 21 04:07:45 PM PDT 24
Peak memory 197628 kb
Host smart-6e757b21-3e13-4490-bdb0-041080626646
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683032846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst
_malfunc.2683032846
Directory /workspace/37.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/37.pwrmgr_escalation_timeout.2433352724
Short name T260
Test name
Test status
Simulation time 161065533 ps
CPU time 1.02 seconds
Started Apr 21 04:07:37 PM PDT 24
Finished Apr 21 04:07:39 PM PDT 24
Peak memory 197808 kb
Host smart-e49a939b-3366-4e53-a599-fb4b24db5eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433352724 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.2433352724
Directory /workspace/37.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/37.pwrmgr_glitch.4134939003
Short name T277
Test name
Test status
Simulation time 35764989 ps
CPU time 0.62 seconds
Started Apr 21 04:07:43 PM PDT 24
Finished Apr 21 04:07:44 PM PDT 24
Peak memory 197732 kb
Host smart-bcf4dd3b-42ff-482a-8ea4-2f673ac13289
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134939003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.4134939003
Directory /workspace/37.pwrmgr_glitch/latest


Test location /workspace/coverage/default/37.pwrmgr_global_esc.2380142935
Short name T647
Test name
Test status
Simulation time 33768952 ps
CPU time 0.61 seconds
Started Apr 21 04:07:38 PM PDT 24
Finished Apr 21 04:07:39 PM PDT 24
Peak memory 197788 kb
Host smart-12098521-15c9-448c-8cca-170df7e43bc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380142935 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.2380142935
Directory /workspace/37.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/37.pwrmgr_lowpower_invalid.2928561331
Short name T432
Test name
Test status
Simulation time 41687875 ps
CPU time 0.73 seconds
Started Apr 21 04:07:40 PM PDT 24
Finished Apr 21 04:07:41 PM PDT 24
Peak memory 201044 kb
Host smart-a5409128-dc1b-4396-8c87-57757febe250
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928561331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_inval
id.2928561331
Directory /workspace/37.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/37.pwrmgr_lowpower_wakeup_race.4033563516
Short name T485
Test name
Test status
Simulation time 211694541 ps
CPU time 1.25 seconds
Started Apr 21 04:07:38 PM PDT 24
Finished Apr 21 04:07:40 PM PDT 24
Peak memory 199220 kb
Host smart-e2d37338-a1df-462b-a842-44942b2490d9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033563516 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_w
akeup_race.4033563516
Directory /workspace/37.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/37.pwrmgr_reset.3872854001
Short name T690
Test name
Test status
Simulation time 34135103 ps
CPU time 0.78 seconds
Started Apr 21 04:07:37 PM PDT 24
Finished Apr 21 04:07:38 PM PDT 24
Peak memory 198856 kb
Host smart-6cfea8f0-9118-4df3-8a14-adc74362860a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872854001 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.3872854001
Directory /workspace/37.pwrmgr_reset/latest


Test location /workspace/coverage/default/37.pwrmgr_reset_invalid.1984173363
Short name T833
Test name
Test status
Simulation time 105620066 ps
CPU time 0.9 seconds
Started Apr 21 04:07:41 PM PDT 24
Finished Apr 21 04:07:42 PM PDT 24
Peak memory 209112 kb
Host smart-ff96576a-edda-4861-91ea-43e4c2d100fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984173363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.1984173363
Directory /workspace/37.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.1015170095
Short name T693
Test name
Test status
Simulation time 42595241 ps
CPU time 0.76 seconds
Started Apr 21 04:07:40 PM PDT 24
Finished Apr 21 04:07:41 PM PDT 24
Peak memory 199044 kb
Host smart-c0796885-141b-41f0-9242-3ad23ff83e6b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015170095 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_
cm_ctrl_config_regwen.1015170095
Directory /workspace/37.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4100590009
Short name T494
Test name
Test status
Simulation time 1211672325 ps
CPU time 2.27 seconds
Started Apr 21 04:07:43 PM PDT 24
Finished Apr 21 04:07:45 PM PDT 24
Peak memory 200888 kb
Host smart-aa2c2edf-9264-446f-b85d-fcb0bb804e07
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100590009 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4100590009
Directory /workspace/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.536630816
Short name T729
Test name
Test status
Simulation time 879079778 ps
CPU time 3.07 seconds
Started Apr 21 04:07:47 PM PDT 24
Finished Apr 21 04:07:51 PM PDT 24
Peak memory 200860 kb
Host smart-61e2f8ec-6b4d-45d4-9409-cdf6db250dff
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536630816 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.536630816
Directory /workspace/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.2553546505
Short name T171
Test name
Test status
Simulation time 52020754 ps
CPU time 0.92 seconds
Started Apr 21 04:07:37 PM PDT 24
Finished Apr 21 04:07:39 PM PDT 24
Peak memory 198972 kb
Host smart-8ed4c4c9-e41a-4ad0-81dc-bd36ad8870d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553546505 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2553546505
Directory /workspace/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/37.pwrmgr_smoke.3372878525
Short name T864
Test name
Test status
Simulation time 53919132 ps
CPU time 0.64 seconds
Started Apr 21 04:07:35 PM PDT 24
Finished Apr 21 04:07:36 PM PDT 24
Peak memory 198152 kb
Host smart-f138496d-b0a7-476d-9719-769a3f6c2c03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372878525 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.3372878525
Directory /workspace/37.pwrmgr_smoke/latest


Test location /workspace/coverage/default/37.pwrmgr_stress_all.3598791029
Short name T894
Test name
Test status
Simulation time 1737597290 ps
CPU time 5.12 seconds
Started Apr 21 04:07:42 PM PDT 24
Finished Apr 21 04:07:48 PM PDT 24
Peak memory 200916 kb
Host smart-d1fdd4c0-2792-40ec-a710-4ae82eec7898
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598791029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all.3598791029
Directory /workspace/37.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/37.pwrmgr_stress_all_with_rand_reset.2221052124
Short name T379
Test name
Test status
Simulation time 16771728287 ps
CPU time 25.09 seconds
Started Apr 21 04:07:43 PM PDT 24
Finished Apr 21 04:08:09 PM PDT 24
Peak memory 201036 kb
Host smart-b150c3fb-8128-498c-a908-e98981682793
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221052124 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all_with_rand_reset.2221052124
Directory /workspace/37.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/37.pwrmgr_wakeup.2955397442
Short name T695
Test name
Test status
Simulation time 448055724 ps
CPU time 0.81 seconds
Started Apr 21 04:07:42 PM PDT 24
Finished Apr 21 04:07:43 PM PDT 24
Peak memory 198152 kb
Host smart-5bd55958-0497-4eaa-ac2a-12d0a5dd26a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955397442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.2955397442
Directory /workspace/37.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/37.pwrmgr_wakeup_reset.1018546990
Short name T26
Test name
Test status
Simulation time 216248348 ps
CPU time 0.85 seconds
Started Apr 21 04:07:39 PM PDT 24
Finished Apr 21 04:07:40 PM PDT 24
Peak memory 198992 kb
Host smart-c191c984-7663-434a-90e6-006d7797b3e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018546990 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.1018546990
Directory /workspace/37.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/38.pwrmgr_aborted_low_power.4166606201
Short name T108
Test name
Test status
Simulation time 38644409 ps
CPU time 0.88 seconds
Started Apr 21 04:07:46 PM PDT 24
Finished Apr 21 04:07:47 PM PDT 24
Peak memory 199844 kb
Host smart-cb2ef888-37ba-448d-910a-7448d91bae49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166606201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.4166606201
Directory /workspace/38.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/38.pwrmgr_disable_rom_integrity_check.2190209184
Short name T27
Test name
Test status
Simulation time 52480880 ps
CPU time 0.81 seconds
Started Apr 21 04:07:44 PM PDT 24
Finished Apr 21 04:07:46 PM PDT 24
Peak memory 198872 kb
Host smart-2d1a3a83-be4f-4f02-853a-2ec8a008a8eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190209184 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_dis
able_rom_integrity_check.2190209184
Directory /workspace/38.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.1496918376
Short name T877
Test name
Test status
Simulation time 39146940 ps
CPU time 0.6 seconds
Started Apr 21 04:07:51 PM PDT 24
Finished Apr 21 04:07:52 PM PDT 24
Peak memory 197712 kb
Host smart-86d766e7-fad4-499f-81b5-fed4e45e2ff9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496918376 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst
_malfunc.1496918376
Directory /workspace/38.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/38.pwrmgr_escalation_timeout.3212009059
Short name T411
Test name
Test status
Simulation time 642061892 ps
CPU time 1.08 seconds
Started Apr 21 04:07:47 PM PDT 24
Finished Apr 21 04:07:48 PM PDT 24
Peak memory 198080 kb
Host smart-a08391dc-e76f-4270-865e-19f27dec4c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212009059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.3212009059
Directory /workspace/38.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/38.pwrmgr_glitch.72279807
Short name T943
Test name
Test status
Simulation time 57748548 ps
CPU time 0.66 seconds
Started Apr 21 04:07:44 PM PDT 24
Finished Apr 21 04:07:45 PM PDT 24
Peak memory 197712 kb
Host smart-5c8687fa-fdd2-4377-9c63-59ad64663cbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72279807 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.72279807
Directory /workspace/38.pwrmgr_glitch/latest


Test location /workspace/coverage/default/38.pwrmgr_global_esc.4039572466
Short name T281
Test name
Test status
Simulation time 27976905 ps
CPU time 0.6 seconds
Started Apr 21 04:07:47 PM PDT 24
Finished Apr 21 04:07:48 PM PDT 24
Peak memory 197748 kb
Host smart-d21777b0-9d87-4a59-8559-e468e16e92bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039572466 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.4039572466
Directory /workspace/38.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/38.pwrmgr_lowpower_invalid.2772404893
Short name T603
Test name
Test status
Simulation time 53639109 ps
CPU time 0.7 seconds
Started Apr 21 04:07:52 PM PDT 24
Finished Apr 21 04:07:53 PM PDT 24
Peak memory 201040 kb
Host smart-41dcb4e0-dba7-4a9d-b487-a000f5847ad5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772404893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_inval
id.2772404893
Directory /workspace/38.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/38.pwrmgr_lowpower_wakeup_race.1050745413
Short name T316
Test name
Test status
Simulation time 304034058 ps
CPU time 1.38 seconds
Started Apr 21 04:07:43 PM PDT 24
Finished Apr 21 04:07:45 PM PDT 24
Peak memory 199412 kb
Host smart-88d8fea1-eb9f-496d-916c-c55576cb4c3e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050745413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_w
akeup_race.1050745413
Directory /workspace/38.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/38.pwrmgr_reset.1793606074
Short name T816
Test name
Test status
Simulation time 45085010 ps
CPU time 0.83 seconds
Started Apr 21 04:07:41 PM PDT 24
Finished Apr 21 04:07:43 PM PDT 24
Peak memory 198864 kb
Host smart-8b8712fb-0dd9-41f1-af5a-10be367918bb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793606074 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.1793606074
Directory /workspace/38.pwrmgr_reset/latest


Test location /workspace/coverage/default/38.pwrmgr_reset_invalid.1273754873
Short name T215
Test name
Test status
Simulation time 385107882 ps
CPU time 0.8 seconds
Started Apr 21 04:07:44 PM PDT 24
Finished Apr 21 04:07:45 PM PDT 24
Peak memory 209100 kb
Host smart-7835d23d-ab57-4d02-8a1e-4531153bb186
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273754873 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.1273754873
Directory /workspace/38.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.2056610774
Short name T800
Test name
Test status
Simulation time 331265298 ps
CPU time 0.93 seconds
Started Apr 21 04:07:44 PM PDT 24
Finished Apr 21 04:07:46 PM PDT 24
Peak memory 199756 kb
Host smart-8f14b61e-3341-4e85-823c-fb9a684394d2
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056610774 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_
cm_ctrl_config_regwen.2056610774
Directory /workspace/38.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1784979746
Short name T477
Test name
Test status
Simulation time 795130944 ps
CPU time 2.47 seconds
Started Apr 21 04:07:41 PM PDT 24
Finished Apr 21 04:07:44 PM PDT 24
Peak memory 200920 kb
Host smart-7e1a6513-5dd1-4da1-91e4-791f522f3118
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784979746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1784979746
Directory /workspace/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2577623778
Short name T321
Test name
Test status
Simulation time 1446200911 ps
CPU time 2.32 seconds
Started Apr 21 04:07:43 PM PDT 24
Finished Apr 21 04:07:46 PM PDT 24
Peak memory 200836 kb
Host smart-d720de65-e490-4f12-88d7-49d0d71dd821
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577623778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2577623778
Directory /workspace/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.555716708
Short name T731
Test name
Test status
Simulation time 326686073 ps
CPU time 0.84 seconds
Started Apr 21 04:07:41 PM PDT 24
Finished Apr 21 04:07:42 PM PDT 24
Peak memory 198888 kb
Host smart-78572a5e-a364-4149-93a9-a63167c6eae1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555716708 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig_
mubi.555716708
Directory /workspace/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/38.pwrmgr_smoke.2255870269
Short name T723
Test name
Test status
Simulation time 214706196 ps
CPU time 0.66 seconds
Started Apr 21 04:07:40 PM PDT 24
Finished Apr 21 04:07:41 PM PDT 24
Peak memory 198192 kb
Host smart-66cdc8db-10c8-4bb1-8008-a6e61d4b869d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255870269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.2255870269
Directory /workspace/38.pwrmgr_smoke/latest


Test location /workspace/coverage/default/38.pwrmgr_stress_all.644484865
Short name T563
Test name
Test status
Simulation time 37005881 ps
CPU time 0.75 seconds
Started Apr 21 04:07:53 PM PDT 24
Finished Apr 21 04:07:54 PM PDT 24
Peak memory 198936 kb
Host smart-252a384e-8a6d-4afd-91ca-3df90adc4a86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644484865 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all.644484865
Directory /workspace/38.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/38.pwrmgr_stress_all_with_rand_reset.1760389555
Short name T23
Test name
Test status
Simulation time 8183492819 ps
CPU time 26.16 seconds
Started Apr 21 04:07:52 PM PDT 24
Finished Apr 21 04:08:18 PM PDT 24
Peak memory 201032 kb
Host smart-e7c93ced-820c-4ffb-bd18-d3b310ad6202
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760389555 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all_with_rand_reset.1760389555
Directory /workspace/38.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/38.pwrmgr_wakeup.6430206
Short name T417
Test name
Test status
Simulation time 157526724 ps
CPU time 0.85 seconds
Started Apr 21 04:07:45 PM PDT 24
Finished Apr 21 04:07:46 PM PDT 24
Peak memory 197996 kb
Host smart-9fbbf880-5fea-43e3-ac2f-ed0b96638c11
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6430206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.6430206
Directory /workspace/38.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/38.pwrmgr_wakeup_reset.1917834061
Short name T792
Test name
Test status
Simulation time 219359143 ps
CPU time 1.03 seconds
Started Apr 21 04:07:47 PM PDT 24
Finished Apr 21 04:07:49 PM PDT 24
Peak memory 199960 kb
Host smart-4ed5105b-11a1-4e50-b131-0ec0d06f03a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917834061 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.1917834061
Directory /workspace/38.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/39.pwrmgr_aborted_low_power.3742323968
Short name T34
Test name
Test status
Simulation time 130336848 ps
CPU time 0.83 seconds
Started Apr 21 04:07:58 PM PDT 24
Finished Apr 21 04:07:59 PM PDT 24
Peak memory 199624 kb
Host smart-5c3e02a7-f3c9-426d-adf7-9d86cef69e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742323968 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.3742323968
Directory /workspace/39.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/39.pwrmgr_disable_rom_integrity_check.4185893019
Short name T256
Test name
Test status
Simulation time 91868365 ps
CPU time 0.82 seconds
Started Apr 21 04:07:49 PM PDT 24
Finished Apr 21 04:07:50 PM PDT 24
Peak memory 198224 kb
Host smart-7ac300cc-6a6c-49be-a54c-e6ac71882dba
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185893019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_dis
able_rom_integrity_check.4185893019
Directory /workspace/39.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.4161740276
Short name T173
Test name
Test status
Simulation time 30182257 ps
CPU time 0.65 seconds
Started Apr 21 04:07:45 PM PDT 24
Finished Apr 21 04:07:46 PM PDT 24
Peak memory 197684 kb
Host smart-34eb81e9-20d3-4dad-8166-8e91511d020b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161740276 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst
_malfunc.4161740276
Directory /workspace/39.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/39.pwrmgr_escalation_timeout.1823197126
Short name T11
Test name
Test status
Simulation time 686110274 ps
CPU time 0.97 seconds
Started Apr 21 04:07:45 PM PDT 24
Finished Apr 21 04:07:46 PM PDT 24
Peak memory 197784 kb
Host smart-b15585f1-36ee-42be-adc8-2b7bc410376a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823197126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.1823197126
Directory /workspace/39.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/39.pwrmgr_glitch.3381059018
Short name T873
Test name
Test status
Simulation time 149812647 ps
CPU time 0.6 seconds
Started Apr 21 04:07:45 PM PDT 24
Finished Apr 21 04:07:46 PM PDT 24
Peak memory 197008 kb
Host smart-2638599c-2776-422d-b55a-149a5b3c8aea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381059018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.3381059018
Directory /workspace/39.pwrmgr_glitch/latest


Test location /workspace/coverage/default/39.pwrmgr_global_esc.3365130279
Short name T294
Test name
Test status
Simulation time 28012592 ps
CPU time 0.64 seconds
Started Apr 21 04:07:46 PM PDT 24
Finished Apr 21 04:07:47 PM PDT 24
Peak memory 197732 kb
Host smart-58d3981c-70f4-4eb0-a924-e54057aca3b3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365130279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.3365130279
Directory /workspace/39.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/39.pwrmgr_lowpower_invalid.4194744909
Short name T453
Test name
Test status
Simulation time 84446248 ps
CPU time 0.7 seconds
Started Apr 21 04:07:45 PM PDT 24
Finished Apr 21 04:07:46 PM PDT 24
Peak memory 201044 kb
Host smart-6237bc78-ce55-4339-bc9e-7f981970d6c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194744909 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_inval
id.4194744909
Directory /workspace/39.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/39.pwrmgr_lowpower_wakeup_race.3014994210
Short name T344
Test name
Test status
Simulation time 246933839 ps
CPU time 1.22 seconds
Started Apr 21 04:07:44 PM PDT 24
Finished Apr 21 04:07:46 PM PDT 24
Peak memory 199136 kb
Host smart-ea249253-cca5-45ea-a7e0-855369f05ba9
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014994210 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_w
akeup_race.3014994210
Directory /workspace/39.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/39.pwrmgr_reset.3592848040
Short name T969
Test name
Test status
Simulation time 84698461 ps
CPU time 0.74 seconds
Started Apr 21 04:07:49 PM PDT 24
Finished Apr 21 04:07:50 PM PDT 24
Peak memory 198816 kb
Host smart-84612ada-fc7e-46ca-8af8-eb453306714d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592848040 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.3592848040
Directory /workspace/39.pwrmgr_reset/latest


Test location /workspace/coverage/default/39.pwrmgr_reset_invalid.851069512
Short name T95
Test name
Test status
Simulation time 116481812 ps
CPU time 0.92 seconds
Started Apr 21 04:07:46 PM PDT 24
Finished Apr 21 04:07:47 PM PDT 24
Peak memory 209124 kb
Host smart-5b449b14-1fd6-457c-9d53-1e37fe242d03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851069512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.851069512
Directory /workspace/39.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.163751936
Short name T243
Test name
Test status
Simulation time 52658668 ps
CPU time 0.73 seconds
Started Apr 21 04:07:45 PM PDT 24
Finished Apr 21 04:07:47 PM PDT 24
Peak memory 198328 kb
Host smart-9d80a1a2-c57c-418e-9894-4b8c7c35b0b0
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163751936 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_c
m_ctrl_config_regwen.163751936
Directory /workspace/39.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.50371995
Short name T498
Test name
Test status
Simulation time 1212824333 ps
CPU time 2.19 seconds
Started Apr 21 04:07:44 PM PDT 24
Finished Apr 21 04:07:47 PM PDT 24
Peak memory 201052 kb
Host smart-baa4171e-08d9-4870-a068-0fcc0f33acf5
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50371995 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +
UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.50371995
Directory /workspace/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.288695070
Short name T290
Test name
Test status
Simulation time 1081526867 ps
CPU time 2.31 seconds
Started Apr 21 04:07:53 PM PDT 24
Finished Apr 21 04:07:56 PM PDT 24
Peak memory 200924 kb
Host smart-5cf82f23-7335-4133-ac6c-d504d0d95f7f
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288695070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.288695070
Directory /workspace/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2379384824
Short name T359
Test name
Test status
Simulation time 214986098 ps
CPU time 0.91 seconds
Started Apr 21 04:07:57 PM PDT 24
Finished Apr 21 04:07:59 PM PDT 24
Peak memory 198832 kb
Host smart-4ac48fd6-3d07-4896-a1e3-a7e97e92b0fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379384824 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig
_mubi.2379384824
Directory /workspace/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/39.pwrmgr_smoke.3722019382
Short name T600
Test name
Test status
Simulation time 32547855 ps
CPU time 0.67 seconds
Started Apr 21 04:07:44 PM PDT 24
Finished Apr 21 04:07:46 PM PDT 24
Peak memory 198160 kb
Host smart-f688e72a-25b7-4af8-90a7-be327e31234c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722019382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.3722019382
Directory /workspace/39.pwrmgr_smoke/latest


Test location /workspace/coverage/default/39.pwrmgr_stress_all.1184328181
Short name T663
Test name
Test status
Simulation time 1460634689 ps
CPU time 5.24 seconds
Started Apr 21 04:07:51 PM PDT 24
Finished Apr 21 04:07:57 PM PDT 24
Peak memory 200980 kb
Host smart-05550789-ab9c-4bb3-9397-922c1ad2d48d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184328181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all.1184328181
Directory /workspace/39.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/39.pwrmgr_stress_all_with_rand_reset.2551439145
Short name T414
Test name
Test status
Simulation time 9600109611 ps
CPU time 35.96 seconds
Started Apr 21 04:07:50 PM PDT 24
Finished Apr 21 04:08:26 PM PDT 24
Peak memory 201040 kb
Host smart-f31f5204-c41e-4fbf-8898-6a1aaa6a93b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551439145 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all_with_rand_reset.2551439145
Directory /workspace/39.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/39.pwrmgr_wakeup.3148813383
Short name T597
Test name
Test status
Simulation time 242069059 ps
CPU time 1.24 seconds
Started Apr 21 04:07:49 PM PDT 24
Finished Apr 21 04:07:51 PM PDT 24
Peak memory 199404 kb
Host smart-ebc14f97-b517-4692-a5bb-dab82a8ce22a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148813383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.3148813383
Directory /workspace/39.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/39.pwrmgr_wakeup_reset.108574546
Short name T941
Test name
Test status
Simulation time 130885946 ps
CPU time 0.75 seconds
Started Apr 21 04:07:46 PM PDT 24
Finished Apr 21 04:07:47 PM PDT 24
Peak memory 198988 kb
Host smart-7e91fe1b-0146-4030-beaf-7f12baafa714
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108574546 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.108574546
Directory /workspace/39.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/4.pwrmgr_aborted_low_power.3021018023
Short name T898
Test name
Test status
Simulation time 96465737 ps
CPU time 0.75 seconds
Started Apr 21 04:05:32 PM PDT 24
Finished Apr 21 04:05:33 PM PDT 24
Peak memory 198408 kb
Host smart-028528d7-52af-4495-acbc-be42fb080202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021018023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.3021018023
Directory /workspace/4.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/4.pwrmgr_disable_rom_integrity_check.803700918
Short name T219
Test name
Test status
Simulation time 65573040 ps
CPU time 0.86 seconds
Started Apr 21 04:05:34 PM PDT 24
Finished Apr 21 04:05:35 PM PDT 24
Peak memory 198756 kb
Host smart-a1b046f4-0a4f-4699-8c20-ae8ab7e4455a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803700918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disab
le_rom_integrity_check.803700918
Directory /workspace/4.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.590728063
Short name T656
Test name
Test status
Simulation time 30357982 ps
CPU time 0.64 seconds
Started Apr 21 04:05:36 PM PDT 24
Finished Apr 21 04:05:37 PM PDT 24
Peak memory 197660 kb
Host smart-4a9835e3-af3f-4577-a4d9-cb261832ef70
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590728063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_m
alfunc.590728063
Directory /workspace/4.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/4.pwrmgr_escalation_timeout.383557656
Short name T467
Test name
Test status
Simulation time 312558388 ps
CPU time 0.98 seconds
Started Apr 21 04:05:36 PM PDT 24
Finished Apr 21 04:05:37 PM PDT 24
Peak memory 197792 kb
Host smart-dbf4f67c-61b2-4767-8148-b62e126a30ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383557656 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.383557656
Directory /workspace/4.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/4.pwrmgr_glitch.3887154742
Short name T967
Test name
Test status
Simulation time 64227930 ps
CPU time 0.64 seconds
Started Apr 21 04:05:35 PM PDT 24
Finished Apr 21 04:05:36 PM PDT 24
Peak memory 197680 kb
Host smart-99503a63-8ddc-4f2c-a119-23fb267a4def
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887154742 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.3887154742
Directory /workspace/4.pwrmgr_glitch/latest


Test location /workspace/coverage/default/4.pwrmgr_global_esc.1422287636
Short name T322
Test name
Test status
Simulation time 76664754 ps
CPU time 0.64 seconds
Started Apr 21 04:05:34 PM PDT 24
Finished Apr 21 04:05:35 PM PDT 24
Peak memory 197792 kb
Host smart-465200ee-08d7-47c4-a0b6-d60278c2742e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422287636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.1422287636
Directory /workspace/4.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/4.pwrmgr_lowpower_invalid.1416268501
Short name T821
Test name
Test status
Simulation time 48671927 ps
CPU time 0.67 seconds
Started Apr 21 04:05:35 PM PDT 24
Finished Apr 21 04:05:36 PM PDT 24
Peak memory 201020 kb
Host smart-5011cc8f-9341-46cd-a33e-ca6f9f1e5bf5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416268501 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invali
d.1416268501
Directory /workspace/4.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/4.pwrmgr_lowpower_wakeup_race.2291268081
Short name T216
Test name
Test status
Simulation time 56928600 ps
CPU time 0.68 seconds
Started Apr 21 04:05:35 PM PDT 24
Finished Apr 21 04:05:36 PM PDT 24
Peak memory 198720 kb
Host smart-78c2f363-cb04-422f-9944-f6f2b598095a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291268081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wa
keup_race.2291268081
Directory /workspace/4.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/4.pwrmgr_reset.3639303683
Short name T680
Test name
Test status
Simulation time 50986231 ps
CPU time 0.8 seconds
Started Apr 21 04:05:31 PM PDT 24
Finished Apr 21 04:05:32 PM PDT 24
Peak memory 198800 kb
Host smart-a71152a3-5f6f-4baf-8c6e-ad9468d03f1d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639303683 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.3639303683
Directory /workspace/4.pwrmgr_reset/latest


Test location /workspace/coverage/default/4.pwrmgr_reset_invalid.1707290117
Short name T659
Test name
Test status
Simulation time 108231623 ps
CPU time 1.17 seconds
Started Apr 21 04:05:35 PM PDT 24
Finished Apr 21 04:05:36 PM PDT 24
Peak memory 208980 kb
Host smart-02b73c4c-b00b-4410-bf5c-87948f910c94
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707290117 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.1707290117
Directory /workspace/4.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/4.pwrmgr_sec_cm.2364731217
Short name T30
Test name
Test status
Simulation time 706664585 ps
CPU time 1.59 seconds
Started Apr 21 04:05:40 PM PDT 24
Finished Apr 21 04:05:42 PM PDT 24
Peak memory 217564 kb
Host smart-ecd0e69f-0709-4c96-8da6-7b0e359d85e1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364731217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.2364731217
Directory /workspace/4.pwrmgr_sec_cm/latest


Test location /workspace/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.3707636567
Short name T702
Test name
Test status
Simulation time 47296734 ps
CPU time 0.7 seconds
Started Apr 21 04:05:39 PM PDT 24
Finished Apr 21 04:05:40 PM PDT 24
Peak memory 198212 kb
Host smart-5f5ee688-fc25-46a3-b4bc-894eea55bfea
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707636567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_c
m_ctrl_config_regwen.3707636567
Directory /workspace/4.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3099158181
Short name T452
Test name
Test status
Simulation time 1122538482 ps
CPU time 2.26 seconds
Started Apr 21 04:05:31 PM PDT 24
Finished Apr 21 04:05:34 PM PDT 24
Peak memory 200796 kb
Host smart-1a371801-94af-487c-99c4-3668a236f1e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099158181 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3099158181
Directory /workspace/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.662493513
Short name T409
Test name
Test status
Simulation time 891269312 ps
CPU time 2.98 seconds
Started Apr 21 04:05:35 PM PDT 24
Finished Apr 21 04:05:38 PM PDT 24
Peak memory 200892 kb
Host smart-5e5150e4-55a4-4c04-b622-c52646e404f6
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662493513 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.662493513
Directory /workspace/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.1884729377
Short name T569
Test name
Test status
Simulation time 73349799 ps
CPU time 0.91 seconds
Started Apr 21 04:05:35 PM PDT 24
Finished Apr 21 04:05:36 PM PDT 24
Peak memory 198888 kb
Host smart-b633ed0b-e502-4f29-a967-2e463eccb292
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884729377 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1884729377
Directory /workspace/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/4.pwrmgr_smoke.1166130866
Short name T938
Test name
Test status
Simulation time 33322918 ps
CPU time 0.68 seconds
Started Apr 21 04:05:30 PM PDT 24
Finished Apr 21 04:05:31 PM PDT 24
Peak memory 198964 kb
Host smart-bbc0f125-e17f-4ca2-bd7e-9c1b4d2501e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166130866 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.1166130866
Directory /workspace/4.pwrmgr_smoke/latest


Test location /workspace/coverage/default/4.pwrmgr_stress_all_with_rand_reset.4049488847
Short name T92
Test name
Test status
Simulation time 5415160709 ps
CPU time 19.89 seconds
Started Apr 21 04:05:37 PM PDT 24
Finished Apr 21 04:05:57 PM PDT 24
Peak memory 201084 kb
Host smart-4a5513fd-7364-48bd-819e-b9710ad2c8a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049488847 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all_with_rand_reset.4049488847
Directory /workspace/4.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/4.pwrmgr_wakeup.1358155494
Short name T982
Test name
Test status
Simulation time 66534840 ps
CPU time 0.79 seconds
Started Apr 21 04:05:32 PM PDT 24
Finished Apr 21 04:05:33 PM PDT 24
Peak memory 197924 kb
Host smart-182e76a3-d67d-4ac0-aea0-613a2e572598
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358155494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.1358155494
Directory /workspace/4.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/4.pwrmgr_wakeup_reset.2059596005
Short name T421
Test name
Test status
Simulation time 254701637 ps
CPU time 1.13 seconds
Started Apr 21 04:05:32 PM PDT 24
Finished Apr 21 04:05:34 PM PDT 24
Peak memory 199724 kb
Host smart-fb287460-53a0-462f-96d2-75a7b2ff558d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059596005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.2059596005
Directory /workspace/4.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/40.pwrmgr_aborted_low_power.2437194189
Short name T126
Test name
Test status
Simulation time 25015590 ps
CPU time 0.72 seconds
Started Apr 21 04:07:50 PM PDT 24
Finished Apr 21 04:07:52 PM PDT 24
Peak memory 198260 kb
Host smart-aa5ec0fd-858b-456e-91d7-b4de58eb7cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437194189 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.2437194189
Directory /workspace/40.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/40.pwrmgr_disable_rom_integrity_check.3749462042
Short name T360
Test name
Test status
Simulation time 60802524 ps
CPU time 0.95 seconds
Started Apr 21 04:07:54 PM PDT 24
Finished Apr 21 04:07:55 PM PDT 24
Peak memory 198788 kb
Host smart-64abdac9-22da-4eb9-98f9-05731bb16a4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749462042 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_dis
able_rom_integrity_check.3749462042
Directory /workspace/40.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.1996680343
Short name T177
Test name
Test status
Simulation time 40138987 ps
CPU time 0.58 seconds
Started Apr 21 04:07:51 PM PDT 24
Finished Apr 21 04:07:51 PM PDT 24
Peak memory 197712 kb
Host smart-7ceda519-e03c-4cd6-937a-ec714e904238
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996680343 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst
_malfunc.1996680343
Directory /workspace/40.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/40.pwrmgr_escalation_timeout.2172787770
Short name T639
Test name
Test status
Simulation time 164503071 ps
CPU time 1.05 seconds
Started Apr 21 04:07:55 PM PDT 24
Finished Apr 21 04:07:56 PM PDT 24
Peak memory 198064 kb
Host smart-f0a7ec30-ac9b-459a-808e-0fa27f520a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172787770 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.2172787770
Directory /workspace/40.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/40.pwrmgr_glitch.4160719701
Short name T685
Test name
Test status
Simulation time 57783925 ps
CPU time 0.68 seconds
Started Apr 21 04:07:55 PM PDT 24
Finished Apr 21 04:07:56 PM PDT 24
Peak memory 197680 kb
Host smart-6e7dcec8-357e-4472-8bc8-861f92d110a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160719701 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.4160719701
Directory /workspace/40.pwrmgr_glitch/latest


Test location /workspace/coverage/default/40.pwrmgr_global_esc.2807499294
Short name T161
Test name
Test status
Simulation time 46036669 ps
CPU time 0.63 seconds
Started Apr 21 04:08:12 PM PDT 24
Finished Apr 21 04:08:13 PM PDT 24
Peak memory 198060 kb
Host smart-2fe4c471-79a1-48b6-b74a-ca90614cb1fa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807499294 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.2807499294
Directory /workspace/40.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/40.pwrmgr_lowpower_invalid.2892514228
Short name T881
Test name
Test status
Simulation time 78665317 ps
CPU time 0.74 seconds
Started Apr 21 04:07:51 PM PDT 24
Finished Apr 21 04:07:52 PM PDT 24
Peak memory 201040 kb
Host smart-604a2014-70c8-4b56-bedf-4fc2f5909b87
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892514228 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_inval
id.2892514228
Directory /workspace/40.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/40.pwrmgr_lowpower_wakeup_race.71743861
Short name T548
Test name
Test status
Simulation time 148203148 ps
CPU time 0.77 seconds
Started Apr 21 04:07:49 PM PDT 24
Finished Apr 21 04:07:50 PM PDT 24
Peak memory 197972 kb
Host smart-b21b54d0-d7be-4150-8b1f-f00af042a84f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71743861 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup
_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_wak
eup_race.71743861
Directory /workspace/40.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/40.pwrmgr_reset.651367562
Short name T923
Test name
Test status
Simulation time 119803600 ps
CPU time 0.86 seconds
Started Apr 21 04:07:49 PM PDT 24
Finished Apr 21 04:07:50 PM PDT 24
Peak memory 198880 kb
Host smart-aa85ae2a-59ce-46b8-a075-95df5c525cd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651367562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.651367562
Directory /workspace/40.pwrmgr_reset/latest


Test location /workspace/coverage/default/40.pwrmgr_reset_invalid.673499075
Short name T439
Test name
Test status
Simulation time 159277253 ps
CPU time 0.9 seconds
Started Apr 21 04:07:53 PM PDT 24
Finished Apr 21 04:07:54 PM PDT 24
Peak memory 209024 kb
Host smart-3e319abb-fb71-437c-ad9a-c6bb10050225
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673499075 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.673499075
Directory /workspace/40.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.218643111
Short name T331
Test name
Test status
Simulation time 219254112 ps
CPU time 1.26 seconds
Started Apr 21 04:07:50 PM PDT 24
Finished Apr 21 04:07:52 PM PDT 24
Peak memory 200464 kb
Host smart-26a6c1d6-23c4-401b-8f1a-d5be0ebbe5ea
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218643111 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_c
m_ctrl_config_regwen.218643111
Directory /workspace/40.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3625264397
Short name T475
Test name
Test status
Simulation time 928409681 ps
CPU time 2.44 seconds
Started Apr 21 04:07:49 PM PDT 24
Finished Apr 21 04:07:52 PM PDT 24
Peak memory 200796 kb
Host smart-507dd105-2ce5-4f80-b1c3-45d56317642e
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625264397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3625264397
Directory /workspace/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4015024179
Short name T180
Test name
Test status
Simulation time 958432881 ps
CPU time 3.57 seconds
Started Apr 21 04:07:50 PM PDT 24
Finished Apr 21 04:07:54 PM PDT 24
Peak memory 200876 kb
Host smart-a56eff25-36ed-46ec-9bc4-2bc68a3a065e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015024179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4015024179
Directory /workspace/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.1045695697
Short name T199
Test name
Test status
Simulation time 71592366 ps
CPU time 0.99 seconds
Started Apr 21 04:07:50 PM PDT 24
Finished Apr 21 04:07:51 PM PDT 24
Peak memory 199260 kb
Host smart-22af68aa-5a91-4d24-bf5a-b200142de5df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045695697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1045695697
Directory /workspace/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/40.pwrmgr_smoke.836534179
Short name T255
Test name
Test status
Simulation time 37532728 ps
CPU time 0.66 seconds
Started Apr 21 04:07:50 PM PDT 24
Finished Apr 21 04:07:51 PM PDT 24
Peak memory 199032 kb
Host smart-04c75242-c5a8-4b07-a1ab-43fb04a84d73
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836534179 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.836534179
Directory /workspace/40.pwrmgr_smoke/latest


Test location /workspace/coverage/default/40.pwrmgr_stress_all.1380738900
Short name T259
Test name
Test status
Simulation time 3058444246 ps
CPU time 4.54 seconds
Started Apr 21 04:07:57 PM PDT 24
Finished Apr 21 04:08:02 PM PDT 24
Peak memory 201004 kb
Host smart-f070fc8b-3bc4-481b-b756-78b6e1017bfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380738900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.1380738900
Directory /workspace/40.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/40.pwrmgr_stress_all_with_rand_reset.2699264604
Short name T975
Test name
Test status
Simulation time 4130906741 ps
CPU time 13.76 seconds
Started Apr 21 04:07:50 PM PDT 24
Finished Apr 21 04:08:04 PM PDT 24
Peak memory 200964 kb
Host smart-c9614c18-62e6-4965-be6a-729df7842f1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699264604 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all_with_rand_reset.2699264604
Directory /workspace/40.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/40.pwrmgr_wakeup.658784904
Short name T460
Test name
Test status
Simulation time 77201373 ps
CPU time 0.8 seconds
Started Apr 21 04:07:49 PM PDT 24
Finished Apr 21 04:07:51 PM PDT 24
Peak memory 198760 kb
Host smart-00662223-78c8-482b-90bb-f355e931e8f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658784904 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.658784904
Directory /workspace/40.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/40.pwrmgr_wakeup_reset.3837337229
Short name T437
Test name
Test status
Simulation time 72022269 ps
CPU time 0.71 seconds
Started Apr 21 04:07:50 PM PDT 24
Finished Apr 21 04:07:51 PM PDT 24
Peak memory 199004 kb
Host smart-0e6997be-64be-4713-a3c7-b3ef09537c64
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837337229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.3837337229
Directory /workspace/40.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/41.pwrmgr_aborted_low_power.2118274045
Short name T803
Test name
Test status
Simulation time 50579871 ps
CPU time 0.86 seconds
Started Apr 21 04:08:03 PM PDT 24
Finished Apr 21 04:08:05 PM PDT 24
Peak memory 199724 kb
Host smart-c9fdf2d1-01d4-4bda-9be9-024a26d0003d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118274045 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.2118274045
Directory /workspace/41.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/41.pwrmgr_disable_rom_integrity_check.1692441893
Short name T140
Test name
Test status
Simulation time 83607931 ps
CPU time 0.73 seconds
Started Apr 21 04:07:57 PM PDT 24
Finished Apr 21 04:07:58 PM PDT 24
Peak memory 198888 kb
Host smart-a7036803-1904-46c5-89b4-efb575c8d04d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692441893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_dis
able_rom_integrity_check.1692441893
Directory /workspace/41.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.3906665664
Short name T926
Test name
Test status
Simulation time 37477833 ps
CPU time 0.66 seconds
Started Apr 21 04:07:56 PM PDT 24
Finished Apr 21 04:07:57 PM PDT 24
Peak memory 197684 kb
Host smart-67c425c2-13cc-43a6-b722-a6248ef6fb9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906665664 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst
_malfunc.3906665664
Directory /workspace/41.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/41.pwrmgr_escalation_timeout.2277970387
Short name T960
Test name
Test status
Simulation time 169005784 ps
CPU time 1.02 seconds
Started Apr 21 04:07:59 PM PDT 24
Finished Apr 21 04:08:00 PM PDT 24
Peak memory 197776 kb
Host smart-c0cff005-f190-4ba2-8d08-1708049bc375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277970387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.2277970387
Directory /workspace/41.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/41.pwrmgr_glitch.2713603570
Short name T288
Test name
Test status
Simulation time 44343987 ps
CPU time 0.65 seconds
Started Apr 21 04:07:59 PM PDT 24
Finished Apr 21 04:08:00 PM PDT 24
Peak memory 197052 kb
Host smart-994bb22f-acf2-42fb-8e87-2d649b833bd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713603570 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.2713603570
Directory /workspace/41.pwrmgr_glitch/latest


Test location /workspace/coverage/default/41.pwrmgr_global_esc.931165949
Short name T254
Test name
Test status
Simulation time 66890243 ps
CPU time 0.64 seconds
Started Apr 21 04:07:57 PM PDT 24
Finished Apr 21 04:07:58 PM PDT 24
Peak memory 197828 kb
Host smart-6be5fc2c-c7a8-4712-ac88-d2f09979c8f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931165949 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.931165949
Directory /workspace/41.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/41.pwrmgr_lowpower_invalid.1866483731
Short name T904
Test name
Test status
Simulation time 58054024 ps
CPU time 0.71 seconds
Started Apr 21 04:07:57 PM PDT 24
Finished Apr 21 04:07:58 PM PDT 24
Peak memory 201016 kb
Host smart-2a995511-0243-452c-9d90-6d7c672a93c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866483731 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_inval
id.1866483731
Directory /workspace/41.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/41.pwrmgr_lowpower_wakeup_race.129848757
Short name T229
Test name
Test status
Simulation time 218299143 ps
CPU time 1.22 seconds
Started Apr 21 04:07:54 PM PDT 24
Finished Apr 21 04:07:56 PM PDT 24
Peak memory 199164 kb
Host smart-c393f84d-50d2-4cf5-b043-5b88c3255386
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129848757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_wa
keup_race.129848757
Directory /workspace/41.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/41.pwrmgr_reset.112658832
Short name T669
Test name
Test status
Simulation time 113622186 ps
CPU time 0.74 seconds
Started Apr 21 04:07:55 PM PDT 24
Finished Apr 21 04:07:56 PM PDT 24
Peak memory 198788 kb
Host smart-c57ae60d-d143-4000-9522-add1ec752087
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112658832 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.112658832
Directory /workspace/41.pwrmgr_reset/latest


Test location /workspace/coverage/default/41.pwrmgr_reset_invalid.4025510015
Short name T872
Test name
Test status
Simulation time 101915446 ps
CPU time 1.08 seconds
Started Apr 21 04:07:58 PM PDT 24
Finished Apr 21 04:08:00 PM PDT 24
Peak memory 209120 kb
Host smart-a2d84129-e47f-4ca7-a4fd-d4a20d3f7156
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025510015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.4025510015
Directory /workspace/41.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.1177467612
Short name T366
Test name
Test status
Simulation time 87749120 ps
CPU time 0.89 seconds
Started Apr 21 04:07:56 PM PDT 24
Finished Apr 21 04:07:58 PM PDT 24
Peak memory 199576 kb
Host smart-0280696a-df7f-4a34-81db-c9fa76c9fbfd
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177467612 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_
cm_ctrl_config_regwen.1177467612
Directory /workspace/41.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.840649455
Short name T266
Test name
Test status
Simulation time 961098034 ps
CPU time 2.53 seconds
Started Apr 21 04:07:53 PM PDT 24
Finished Apr 21 04:07:56 PM PDT 24
Peak memory 200560 kb
Host smart-12e3b452-c2a2-4276-a14f-fb1636758cdd
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840649455 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.840649455
Directory /workspace/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2127529250
Short name T874
Test name
Test status
Simulation time 819278355 ps
CPU time 3.19 seconds
Started Apr 21 04:07:57 PM PDT 24
Finished Apr 21 04:08:01 PM PDT 24
Peak memory 200912 kb
Host smart-6e3395d7-c900-4621-9c52-e17f6e54cfde
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127529250 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2127529250
Directory /workspace/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.58831404
Short name T363
Test name
Test status
Simulation time 69137559 ps
CPU time 1.06 seconds
Started Apr 21 04:07:53 PM PDT 24
Finished Apr 21 04:07:54 PM PDT 24
Peak memory 198876 kb
Host smart-e8b0c7ab-8540-46aa-875f-17369508a2ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58831404 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig_m
ubi.58831404
Directory /workspace/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/41.pwrmgr_smoke.4064248944
Short name T580
Test name
Test status
Simulation time 33426778 ps
CPU time 0.71 seconds
Started Apr 21 04:07:57 PM PDT 24
Finished Apr 21 04:07:58 PM PDT 24
Peak memory 198952 kb
Host smart-ac4a2c21-b911-4d86-9f90-371adf00f86a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064248944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.4064248944
Directory /workspace/41.pwrmgr_smoke/latest


Test location /workspace/coverage/default/41.pwrmgr_stress_all.4258263541
Short name T737
Test name
Test status
Simulation time 931208305 ps
CPU time 4.08 seconds
Started Apr 21 04:07:58 PM PDT 24
Finished Apr 21 04:08:03 PM PDT 24
Peak memory 200896 kb
Host smart-8e78a20a-86ae-4161-a22a-aec0111b6733
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258263541 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.4258263541
Directory /workspace/41.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/41.pwrmgr_stress_all_with_rand_reset.3098695851
Short name T620
Test name
Test status
Simulation time 12523857632 ps
CPU time 23.7 seconds
Started Apr 21 04:07:58 PM PDT 24
Finished Apr 21 04:08:22 PM PDT 24
Peak memory 200996 kb
Host smart-49c9c903-b2de-44c4-ba79-fa8ec151e015
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098695851 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all_with_rand_reset.3098695851
Directory /workspace/41.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/41.pwrmgr_wakeup.1185953178
Short name T84
Test name
Test status
Simulation time 289879442 ps
CPU time 1.29 seconds
Started Apr 21 04:07:58 PM PDT 24
Finished Apr 21 04:08:00 PM PDT 24
Peak memory 199268 kb
Host smart-3dae8748-c86f-4e1d-bdcb-e199f4cc9b71
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185953178 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.1185953178
Directory /workspace/41.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/41.pwrmgr_wakeup_reset.583083502
Short name T269
Test name
Test status
Simulation time 123865827 ps
CPU time 0.78 seconds
Started Apr 21 04:07:56 PM PDT 24
Finished Apr 21 04:07:57 PM PDT 24
Peak memory 199016 kb
Host smart-08b9e10b-344c-4b50-adea-24f12fab1e3d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583083502 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.583083502
Directory /workspace/41.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/42.pwrmgr_aborted_low_power.1487853097
Short name T793
Test name
Test status
Simulation time 56215342 ps
CPU time 0.88 seconds
Started Apr 21 04:07:58 PM PDT 24
Finished Apr 21 04:08:00 PM PDT 24
Peak memory 199676 kb
Host smart-f5ebc510-9bd4-4aed-947c-96a6013ecfdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487853097 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.1487853097
Directory /workspace/42.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/42.pwrmgr_disable_rom_integrity_check.2696548330
Short name T470
Test name
Test status
Simulation time 104810332 ps
CPU time 0.72 seconds
Started Apr 21 04:08:06 PM PDT 24
Finished Apr 21 04:08:07 PM PDT 24
Peak memory 198348 kb
Host smart-f0dfeba5-f6f6-4a24-a251-f80008e307fd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696548330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_dis
able_rom_integrity_check.2696548330
Directory /workspace/42.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.2981152520
Short name T681
Test name
Test status
Simulation time 37827519 ps
CPU time 0.67 seconds
Started Apr 21 04:08:00 PM PDT 24
Finished Apr 21 04:08:01 PM PDT 24
Peak memory 197688 kb
Host smart-c3972a2c-b94d-43e9-beda-88d338db324d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981152520 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst
_malfunc.2981152520
Directory /workspace/42.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/42.pwrmgr_escalation_timeout.3506881958
Short name T388
Test name
Test status
Simulation time 627782594 ps
CPU time 1 seconds
Started Apr 21 04:08:00 PM PDT 24
Finished Apr 21 04:08:01 PM PDT 24
Peak memory 198092 kb
Host smart-63d16598-285f-4adb-b27d-d0075ac61339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506881958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.3506881958
Directory /workspace/42.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/42.pwrmgr_glitch.1546005220
Short name T9
Test name
Test status
Simulation time 57932950 ps
CPU time 0.7 seconds
Started Apr 21 04:07:59 PM PDT 24
Finished Apr 21 04:08:00 PM PDT 24
Peak memory 196960 kb
Host smart-0d222e0d-88a3-41b0-8e37-a49c11fe0f8e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546005220 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.1546005220
Directory /workspace/42.pwrmgr_glitch/latest


Test location /workspace/coverage/default/42.pwrmgr_global_esc.2416870370
Short name T45
Test name
Test status
Simulation time 83564742 ps
CPU time 0.64 seconds
Started Apr 21 04:07:57 PM PDT 24
Finished Apr 21 04:07:58 PM PDT 24
Peak memory 197916 kb
Host smart-9685437a-5684-466b-ab41-b0f402bd1ab9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416870370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.2416870370
Directory /workspace/42.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/42.pwrmgr_lowpower_invalid.152606385
Short name T481
Test name
Test status
Simulation time 43537412 ps
CPU time 0.73 seconds
Started Apr 21 04:08:00 PM PDT 24
Finished Apr 21 04:08:01 PM PDT 24
Peak memory 201032 kb
Host smart-187a2075-1daf-4a37-bedb-6fbcb65299d4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152606385 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_invali
d.152606385
Directory /workspace/42.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/42.pwrmgr_lowpower_wakeup_race.3266938601
Short name T953
Test name
Test status
Simulation time 266496136 ps
CPU time 1.29 seconds
Started Apr 21 04:07:59 PM PDT 24
Finished Apr 21 04:08:00 PM PDT 24
Peak memory 199176 kb
Host smart-b7a91d3a-bb8e-4951-97a0-369c916d628e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266938601 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_w
akeup_race.3266938601
Directory /workspace/42.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/42.pwrmgr_reset.3258796931
Short name T761
Test name
Test status
Simulation time 49367641 ps
CPU time 0.77 seconds
Started Apr 21 04:07:59 PM PDT 24
Finished Apr 21 04:08:00 PM PDT 24
Peak memory 198812 kb
Host smart-3e07df3f-cfbd-4b1a-9657-ac45ed5d4596
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258796931 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.3258796931
Directory /workspace/42.pwrmgr_reset/latest


Test location /workspace/coverage/default/42.pwrmgr_reset_invalid.3051423726
Short name T584
Test name
Test status
Simulation time 211812798 ps
CPU time 0.84 seconds
Started Apr 21 04:07:59 PM PDT 24
Finished Apr 21 04:08:00 PM PDT 24
Peak memory 209160 kb
Host smart-aefef8b8-e0a9-4abf-8a61-ace81c15764d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051423726 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.3051423726
Directory /workspace/42.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.1958835617
Short name T428
Test name
Test status
Simulation time 183538494 ps
CPU time 0.93 seconds
Started Apr 21 04:07:57 PM PDT 24
Finished Apr 21 04:07:58 PM PDT 24
Peak memory 199448 kb
Host smart-9263fdd1-cd4b-4167-a6d4-61a028002f41
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958835617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_
cm_ctrl_config_regwen.1958835617
Directory /workspace/42.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4146493138
Short name T957
Test name
Test status
Simulation time 884669638 ps
CPU time 3.18 seconds
Started Apr 21 04:07:56 PM PDT 24
Finished Apr 21 04:07:59 PM PDT 24
Peak memory 200868 kb
Host smart-45e626fd-2a9c-4e47-95a7-46b614c52ac1
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146493138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4146493138
Directory /workspace/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.762062412
Short name T842
Test name
Test status
Simulation time 1207335621 ps
CPU time 2.28 seconds
Started Apr 21 04:07:55 PM PDT 24
Finished Apr 21 04:07:58 PM PDT 24
Peak memory 200792 kb
Host smart-c4633997-0718-43c6-bb9d-e59cfc7941f7
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762062412 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.762062412
Directory /workspace/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.1823601740
Short name T382
Test name
Test status
Simulation time 69211342 ps
CPU time 1 seconds
Started Apr 21 04:08:01 PM PDT 24
Finished Apr 21 04:08:02 PM PDT 24
Peak memory 198812 kb
Host smart-9cfcdb3e-535c-4436-8414-21234ed1c136
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823601740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1823601740
Directory /workspace/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/42.pwrmgr_smoke.1856094342
Short name T765
Test name
Test status
Simulation time 26284536 ps
CPU time 0.72 seconds
Started Apr 21 04:07:56 PM PDT 24
Finished Apr 21 04:07:57 PM PDT 24
Peak memory 198972 kb
Host smart-a459a570-5813-4f1a-bf46-661e53728b9b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856094342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.1856094342
Directory /workspace/42.pwrmgr_smoke/latest


Test location /workspace/coverage/default/42.pwrmgr_stress_all.2978077493
Short name T719
Test name
Test status
Simulation time 1621362038 ps
CPU time 6.65 seconds
Started Apr 21 04:08:06 PM PDT 24
Finished Apr 21 04:08:13 PM PDT 24
Peak memory 200980 kb
Host smart-5eadebd1-31a7-408a-8602-87717a1d7e85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978077493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.2978077493
Directory /workspace/42.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/42.pwrmgr_wakeup.1370152159
Short name T607
Test name
Test status
Simulation time 187978630 ps
CPU time 1.17 seconds
Started Apr 21 04:07:58 PM PDT 24
Finished Apr 21 04:08:00 PM PDT 24
Peak memory 199240 kb
Host smart-7c6dbe1a-0029-4597-8899-71baaf633c12
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370152159 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.1370152159
Directory /workspace/42.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/42.pwrmgr_wakeup_reset.4244635536
Short name T889
Test name
Test status
Simulation time 501072890 ps
CPU time 1.13 seconds
Started Apr 21 04:07:56 PM PDT 24
Finished Apr 21 04:07:57 PM PDT 24
Peak memory 200680 kb
Host smart-7de94af9-5ed9-4910-ad62-1a7dae9e3587
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244635536 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.4244635536
Directory /workspace/42.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/43.pwrmgr_aborted_low_power.3936580972
Short name T315
Test name
Test status
Simulation time 24292988 ps
CPU time 0.88 seconds
Started Apr 21 04:08:00 PM PDT 24
Finished Apr 21 04:08:01 PM PDT 24
Peak memory 199560 kb
Host smart-9005a8a4-1244-4552-b886-95e351c74afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936580972 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.3936580972
Directory /workspace/43.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/43.pwrmgr_disable_rom_integrity_check.1983999194
Short name T840
Test name
Test status
Simulation time 64841800 ps
CPU time 0.75 seconds
Started Apr 21 04:07:57 PM PDT 24
Finished Apr 21 04:07:58 PM PDT 24
Peak memory 198876 kb
Host smart-fdd0bfe0-91e2-4a03-a9c1-8c76e105db46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983999194 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_dis
able_rom_integrity_check.1983999194
Directory /workspace/43.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.3471434442
Short name T883
Test name
Test status
Simulation time 80898237 ps
CPU time 0.6 seconds
Started Apr 21 04:08:00 PM PDT 24
Finished Apr 21 04:08:01 PM PDT 24
Peak memory 197576 kb
Host smart-aabe1b4c-8886-434f-8e18-c9e4958f4772
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471434442 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst
_malfunc.3471434442
Directory /workspace/43.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/43.pwrmgr_escalation_timeout.2575762272
Short name T722
Test name
Test status
Simulation time 631578169 ps
CPU time 0.98 seconds
Started Apr 21 04:08:00 PM PDT 24
Finished Apr 21 04:08:01 PM PDT 24
Peak memory 197800 kb
Host smart-70bfbe01-b3d1-434d-a382-12dc7b775e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575762272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.2575762272
Directory /workspace/43.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/43.pwrmgr_glitch.2390214955
Short name T18
Test name
Test status
Simulation time 54629056 ps
CPU time 0.61 seconds
Started Apr 21 04:08:05 PM PDT 24
Finished Apr 21 04:08:06 PM PDT 24
Peak memory 197044 kb
Host smart-b7dcd12f-d503-4797-bb19-54b89398b2cc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390214955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.2390214955
Directory /workspace/43.pwrmgr_glitch/latest


Test location /workspace/coverage/default/43.pwrmgr_global_esc.764120460
Short name T406
Test name
Test status
Simulation time 58029199 ps
CPU time 0.63 seconds
Started Apr 21 04:08:03 PM PDT 24
Finished Apr 21 04:08:04 PM PDT 24
Peak memory 198084 kb
Host smart-6eb6acd5-b4b0-454d-83e1-3bc39304f21d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764120460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.764120460
Directory /workspace/43.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/43.pwrmgr_lowpower_invalid.1887645213
Short name T949
Test name
Test status
Simulation time 52049862 ps
CPU time 0.7 seconds
Started Apr 21 04:08:06 PM PDT 24
Finished Apr 21 04:08:07 PM PDT 24
Peak memory 200832 kb
Host smart-fdebadf4-f377-4d34-b664-f5976332b493
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887645213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_inval
id.1887645213
Directory /workspace/43.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/43.pwrmgr_lowpower_wakeup_race.2904085182
Short name T86
Test name
Test status
Simulation time 193970252 ps
CPU time 0.78 seconds
Started Apr 21 04:07:57 PM PDT 24
Finished Apr 21 04:07:58 PM PDT 24
Peak memory 198784 kb
Host smart-66e85c07-d0d5-4fc6-b754-bbf0dfbccc34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904085182 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_w
akeup_race.2904085182
Directory /workspace/43.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/43.pwrmgr_reset.778384778
Short name T349
Test name
Test status
Simulation time 68138841 ps
CPU time 0.71 seconds
Started Apr 21 04:07:57 PM PDT 24
Finished Apr 21 04:07:59 PM PDT 24
Peak memory 198328 kb
Host smart-53b51bd5-f943-4ca1-85c4-ef7f6b80fdab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778384778 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.778384778
Directory /workspace/43.pwrmgr_reset/latest


Test location /workspace/coverage/default/43.pwrmgr_reset_invalid.3133236540
Short name T758
Test name
Test status
Simulation time 541409285 ps
CPU time 0.82 seconds
Started Apr 21 04:07:59 PM PDT 24
Finished Apr 21 04:08:01 PM PDT 24
Peak memory 209208 kb
Host smart-f7f2c2d3-d59e-457b-92e9-350c87268c42
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133236540 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.3133236540
Directory /workspace/43.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.3601553331
Short name T263
Test name
Test status
Simulation time 219136182 ps
CPU time 1.31 seconds
Started Apr 21 04:08:06 PM PDT 24
Finished Apr 21 04:08:08 PM PDT 24
Peak memory 200472 kb
Host smart-03dd80ea-51b8-450a-a2e9-96bd9c54b921
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601553331 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_
cm_ctrl_config_regwen.3601553331
Directory /workspace/43.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.500273698
Short name T622
Test name
Test status
Simulation time 907113364 ps
CPU time 2.7 seconds
Started Apr 21 04:07:57 PM PDT 24
Finished Apr 21 04:08:00 PM PDT 24
Peak memory 200776 kb
Host smart-2ddeb1c8-59f3-44b5-9a2a-8473e1b447cb
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500273698 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.500273698
Directory /workspace/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.834090302
Short name T235
Test name
Test status
Simulation time 791555659 ps
CPU time 3.37 seconds
Started Apr 21 04:07:59 PM PDT 24
Finished Apr 21 04:08:03 PM PDT 24
Peak memory 200844 kb
Host smart-7b95a102-0e11-44f5-aa59-292587264711
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834090302 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.834090302
Directory /workspace/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.1554428837
Short name T303
Test name
Test status
Simulation time 89171225 ps
CPU time 0.9 seconds
Started Apr 21 04:07:59 PM PDT 24
Finished Apr 21 04:08:01 PM PDT 24
Peak memory 198868 kb
Host smart-7118c20e-e3cf-4285-97f0-7d9b85bee1f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554428837 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1554428837
Directory /workspace/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/43.pwrmgr_smoke.513558191
Short name T935
Test name
Test status
Simulation time 34403849 ps
CPU time 0.7 seconds
Started Apr 21 04:08:06 PM PDT 24
Finished Apr 21 04:08:07 PM PDT 24
Peak memory 198208 kb
Host smart-00f24239-d7ef-452d-8f0c-5e7a7fb1b40f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513558191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.513558191
Directory /workspace/43.pwrmgr_smoke/latest


Test location /workspace/coverage/default/43.pwrmgr_stress_all.936457529
Short name T720
Test name
Test status
Simulation time 2309242894 ps
CPU time 4.08 seconds
Started Apr 21 04:08:01 PM PDT 24
Finished Apr 21 04:08:06 PM PDT 24
Peak memory 201044 kb
Host smart-12d39870-cf44-48c9-a8fb-ce2a0d5a26c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936457529 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all.936457529
Directory /workspace/43.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/43.pwrmgr_stress_all_with_rand_reset.556966776
Short name T827
Test name
Test status
Simulation time 5934144968 ps
CPU time 19.39 seconds
Started Apr 21 04:07:59 PM PDT 24
Finished Apr 21 04:08:19 PM PDT 24
Peak memory 201076 kb
Host smart-749cf286-7963-48fb-83b6-8e4d7e4619fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556966776 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all_with_rand_reset.556966776
Directory /workspace/43.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/43.pwrmgr_wakeup.3077978121
Short name T572
Test name
Test status
Simulation time 301279382 ps
CPU time 1.13 seconds
Started Apr 21 04:08:00 PM PDT 24
Finished Apr 21 04:08:01 PM PDT 24
Peak memory 199416 kb
Host smart-865f582c-7959-4c6b-a6de-bd232722ed5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077978121 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.3077978121
Directory /workspace/43.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/43.pwrmgr_wakeup_reset.317242277
Short name T507
Test name
Test status
Simulation time 115248347 ps
CPU time 0.67 seconds
Started Apr 21 04:07:57 PM PDT 24
Finished Apr 21 04:07:59 PM PDT 24
Peak memory 198976 kb
Host smart-5d1f4c9d-33e6-4362-9150-c7b8d2e6f1a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317242277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.317242277
Directory /workspace/43.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/44.pwrmgr_aborted_low_power.1083865788
Short name T798
Test name
Test status
Simulation time 35311776 ps
CPU time 1.12 seconds
Started Apr 21 04:08:02 PM PDT 24
Finished Apr 21 04:08:03 PM PDT 24
Peak memory 200532 kb
Host smart-95086104-0dd3-4205-adcc-093ea288499b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083865788 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.1083865788
Directory /workspace/44.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/44.pwrmgr_disable_rom_integrity_check.760424264
Short name T155
Test name
Test status
Simulation time 97411123 ps
CPU time 0.73 seconds
Started Apr 21 04:08:05 PM PDT 24
Finished Apr 21 04:08:06 PM PDT 24
Peak memory 198876 kb
Host smart-af713d32-8cf6-41bf-961b-73177efbb91d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760424264 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_disa
ble_rom_integrity_check.760424264
Directory /workspace/44.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.1360877066
Short name T502
Test name
Test status
Simulation time 43467560 ps
CPU time 0.64 seconds
Started Apr 21 04:08:02 PM PDT 24
Finished Apr 21 04:08:03 PM PDT 24
Peak memory 197640 kb
Host smart-9c098567-49f4-449c-b38e-3813ca1e39e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360877066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst
_malfunc.1360877066
Directory /workspace/44.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/44.pwrmgr_escalation_timeout.2771694014
Short name T333
Test name
Test status
Simulation time 167457800 ps
CPU time 0.98 seconds
Started Apr 21 04:08:07 PM PDT 24
Finished Apr 21 04:08:09 PM PDT 24
Peak memory 197768 kb
Host smart-b9405d0a-d5ae-4dd2-8e99-f72d40fe2865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771694014 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.2771694014
Directory /workspace/44.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/44.pwrmgr_glitch.3893488283
Short name T250
Test name
Test status
Simulation time 54740912 ps
CPU time 0.73 seconds
Started Apr 21 04:08:03 PM PDT 24
Finished Apr 21 04:08:04 PM PDT 24
Peak memory 197748 kb
Host smart-eb32e4fe-04e2-4086-9d85-faf33da03931
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893488283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.3893488283
Directory /workspace/44.pwrmgr_glitch/latest


Test location /workspace/coverage/default/44.pwrmgr_global_esc.4101807311
Short name T742
Test name
Test status
Simulation time 36127594 ps
CPU time 0.64 seconds
Started Apr 21 04:08:03 PM PDT 24
Finished Apr 21 04:08:04 PM PDT 24
Peak memory 197704 kb
Host smart-dc205871-6467-4065-bd4a-1ce3c9d8c2f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101807311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.4101807311
Directory /workspace/44.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/44.pwrmgr_lowpower_invalid.1637614725
Short name T942
Test name
Test status
Simulation time 72878126 ps
CPU time 0.67 seconds
Started Apr 21 04:08:07 PM PDT 24
Finished Apr 21 04:08:08 PM PDT 24
Peak memory 201012 kb
Host smart-f1aa321d-e2d3-4501-a7de-a19fe3063bee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637614725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_inval
id.1637614725
Directory /workspace/44.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/44.pwrmgr_lowpower_wakeup_race.334748055
Short name T590
Test name
Test status
Simulation time 162690706 ps
CPU time 0.81 seconds
Started Apr 21 04:08:07 PM PDT 24
Finished Apr 21 04:08:08 PM PDT 24
Peak memory 197940 kb
Host smart-001cb84c-0edc-4bb9-b0e5-4021fafd8fb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334748055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_wa
keup_race.334748055
Directory /workspace/44.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/44.pwrmgr_reset.2857439705
Short name T692
Test name
Test status
Simulation time 88801202 ps
CPU time 0.98 seconds
Started Apr 21 04:08:00 PM PDT 24
Finished Apr 21 04:08:01 PM PDT 24
Peak memory 198396 kb
Host smart-211380ea-b336-4813-bc87-a6c3173b0046
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857439705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.2857439705
Directory /workspace/44.pwrmgr_reset/latest


Test location /workspace/coverage/default/44.pwrmgr_reset_invalid.1880431424
Short name T635
Test name
Test status
Simulation time 106513430 ps
CPU time 1 seconds
Started Apr 21 04:08:05 PM PDT 24
Finished Apr 21 04:08:06 PM PDT 24
Peak memory 209108 kb
Host smart-95c23b9f-1861-4554-b13e-b89219ed4716
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880431424 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.1880431424
Directory /workspace/44.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.4291669895
Short name T724
Test name
Test status
Simulation time 195897764 ps
CPU time 0.86 seconds
Started Apr 21 04:08:05 PM PDT 24
Finished Apr 21 04:08:07 PM PDT 24
Peak memory 199556 kb
Host smart-93724d1d-0123-4727-a86b-690c5ba38df3
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291669895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_
cm_ctrl_config_regwen.4291669895
Directory /workspace/44.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2633848482
Short name T909
Test name
Test status
Simulation time 793285092 ps
CPU time 3.02 seconds
Started Apr 21 04:08:00 PM PDT 24
Finished Apr 21 04:08:03 PM PDT 24
Peak memory 200708 kb
Host smart-66cb82f8-41b0-46ba-870b-03e82d8eede7
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633848482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2633848482
Directory /workspace/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1163650675
Short name T930
Test name
Test status
Simulation time 771730599 ps
CPU time 3.14 seconds
Started Apr 21 04:08:02 PM PDT 24
Finished Apr 21 04:08:06 PM PDT 24
Peak memory 200816 kb
Host smart-09425189-dcb9-43bd-8924-7cfc823c77e1
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163650675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1163650675
Directory /workspace/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.714920661
Short name T208
Test name
Test status
Simulation time 85701967 ps
CPU time 0.86 seconds
Started Apr 21 04:08:05 PM PDT 24
Finished Apr 21 04:08:06 PM PDT 24
Peak memory 199100 kb
Host smart-ec69802b-1ec4-4d6c-bddf-25d94919e9ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714920661 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig_
mubi.714920661
Directory /workspace/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/44.pwrmgr_smoke.3596486003
Short name T193
Test name
Test status
Simulation time 63496442 ps
CPU time 0.68 seconds
Started Apr 21 04:08:00 PM PDT 24
Finished Apr 21 04:08:01 PM PDT 24
Peak memory 198240 kb
Host smart-a9511faf-7445-4d54-8608-ca84fb12358b
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596486003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.3596486003
Directory /workspace/44.pwrmgr_smoke/latest


Test location /workspace/coverage/default/44.pwrmgr_stress_all.1282648005
Short name T709
Test name
Test status
Simulation time 600892942 ps
CPU time 2.37 seconds
Started Apr 21 04:08:04 PM PDT 24
Finished Apr 21 04:08:07 PM PDT 24
Peak memory 200956 kb
Host smart-a5b7cf18-d2a3-4606-92a1-2ff6655f7a05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282648005 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all.1282648005
Directory /workspace/44.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/44.pwrmgr_stress_all_with_rand_reset.3527222480
Short name T860
Test name
Test status
Simulation time 3980458231 ps
CPU time 17.27 seconds
Started Apr 21 04:08:03 PM PDT 24
Finished Apr 21 04:08:21 PM PDT 24
Peak memory 201032 kb
Host smart-6d072b7a-1c40-412f-859b-36c86ef9d600
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527222480 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all_with_rand_reset.3527222480
Directory /workspace/44.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/44.pwrmgr_wakeup.3081230200
Short name T912
Test name
Test status
Simulation time 252539170 ps
CPU time 1.33 seconds
Started Apr 21 04:08:01 PM PDT 24
Finished Apr 21 04:08:03 PM PDT 24
Peak memory 199192 kb
Host smart-d4daf2cf-69e1-4e11-9af8-b76a377a2ee3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081230200 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.3081230200
Directory /workspace/44.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/44.pwrmgr_wakeup_reset.3971713029
Short name T537
Test name
Test status
Simulation time 267181093 ps
CPU time 0.84 seconds
Started Apr 21 04:08:05 PM PDT 24
Finished Apr 21 04:08:07 PM PDT 24
Peak memory 199804 kb
Host smart-96921efe-7175-41ee-b155-b500ff3d8d03
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971713029 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.3971713029
Directory /workspace/44.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/45.pwrmgr_aborted_low_power.520516833
Short name T465
Test name
Test status
Simulation time 32090711 ps
CPU time 0.68 seconds
Started Apr 21 04:08:02 PM PDT 24
Finished Apr 21 04:08:03 PM PDT 24
Peak memory 198196 kb
Host smart-d7830514-0dbc-4e12-bfe2-232519186876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520516833 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.520516833
Directory /workspace/45.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/45.pwrmgr_disable_rom_integrity_check.2801077232
Short name T159
Test name
Test status
Simulation time 59010546 ps
CPU time 0.77 seconds
Started Apr 21 04:08:06 PM PDT 24
Finished Apr 21 04:08:07 PM PDT 24
Peak memory 198820 kb
Host smart-4a6283a3-6fbf-4c29-8078-ab8f27bcea41
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801077232 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_dis
able_rom_integrity_check.2801077232
Directory /workspace/45.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.3816552462
Short name T300
Test name
Test status
Simulation time 32080808 ps
CPU time 0.62 seconds
Started Apr 21 04:08:07 PM PDT 24
Finished Apr 21 04:08:08 PM PDT 24
Peak memory 197720 kb
Host smart-bd5e366d-0298-4c1d-b438-f619794fad99
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816552462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst
_malfunc.3816552462
Directory /workspace/45.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/45.pwrmgr_escalation_timeout.1432327293
Short name T839
Test name
Test status
Simulation time 638073890 ps
CPU time 0.98 seconds
Started Apr 21 04:08:06 PM PDT 24
Finished Apr 21 04:08:07 PM PDT 24
Peak memory 197956 kb
Host smart-cba89766-1080-4db3-bf4c-c1b9f5dd7d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432327293 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.1432327293
Directory /workspace/45.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/45.pwrmgr_glitch.871157310
Short name T861
Test name
Test status
Simulation time 66503998 ps
CPU time 0.64 seconds
Started Apr 21 04:08:10 PM PDT 24
Finished Apr 21 04:08:11 PM PDT 24
Peak memory 197732 kb
Host smart-e3f3f00b-65fc-4761-b67c-62df3d9a7d96
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871157310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.871157310
Directory /workspace/45.pwrmgr_glitch/latest


Test location /workspace/coverage/default/45.pwrmgr_global_esc.2100154085
Short name T401
Test name
Test status
Simulation time 31272625 ps
CPU time 0.62 seconds
Started Apr 21 04:08:09 PM PDT 24
Finished Apr 21 04:08:10 PM PDT 24
Peak memory 198040 kb
Host smart-374b8f8f-354e-47ed-b467-650a3f1f521c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100154085 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.2100154085
Directory /workspace/45.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/45.pwrmgr_lowpower_invalid.4167361956
Short name T267
Test name
Test status
Simulation time 158845315 ps
CPU time 0.71 seconds
Started Apr 21 04:08:05 PM PDT 24
Finished Apr 21 04:08:06 PM PDT 24
Peak memory 201044 kb
Host smart-3dcde596-7040-47e9-b022-1e78b39d44d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167361956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_inval
id.4167361956
Directory /workspace/45.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/45.pwrmgr_lowpower_wakeup_race.3204840607
Short name T320
Test name
Test status
Simulation time 201733479 ps
CPU time 1.19 seconds
Started Apr 21 04:08:05 PM PDT 24
Finished Apr 21 04:08:07 PM PDT 24
Peak memory 199128 kb
Host smart-d3c7a13d-2ad7-4f72-a7e4-7b291b533e1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204840607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_w
akeup_race.3204840607
Directory /workspace/45.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/45.pwrmgr_reset.2173291183
Short name T615
Test name
Test status
Simulation time 45584961 ps
CPU time 0.81 seconds
Started Apr 21 04:08:08 PM PDT 24
Finished Apr 21 04:08:09 PM PDT 24
Peak memory 198852 kb
Host smart-949f56ec-e58f-4174-b90a-d195ba639321
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173291183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.2173291183
Directory /workspace/45.pwrmgr_reset/latest


Test location /workspace/coverage/default/45.pwrmgr_reset_invalid.3375718372
Short name T222
Test name
Test status
Simulation time 250627415 ps
CPU time 0.84 seconds
Started Apr 21 04:08:06 PM PDT 24
Finished Apr 21 04:08:07 PM PDT 24
Peak memory 209144 kb
Host smart-44a603dd-7e64-461b-ba8a-0248efe5ab77
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375718372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.3375718372
Directory /workspace/45.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.823181834
Short name T637
Test name
Test status
Simulation time 325467699 ps
CPU time 1.14 seconds
Started Apr 21 04:08:10 PM PDT 24
Finished Apr 21 04:08:11 PM PDT 24
Peak memory 199816 kb
Host smart-ddc5ffc0-ead8-4c9b-adbc-2f76b93c466b
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823181834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_c
m_ctrl_config_regwen.823181834
Directory /workspace/45.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1873912624
Short name T691
Test name
Test status
Simulation time 1144718453 ps
CPU time 2.29 seconds
Started Apr 21 04:08:04 PM PDT 24
Finished Apr 21 04:08:06 PM PDT 24
Peak memory 200916 kb
Host smart-4e17236f-3a38-4638-909d-b10bc6af1611
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873912624 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1873912624
Directory /workspace/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.368129280
Short name T582
Test name
Test status
Simulation time 1032899636 ps
CPU time 2 seconds
Started Apr 21 04:08:05 PM PDT 24
Finished Apr 21 04:08:07 PM PDT 24
Peak memory 200964 kb
Host smart-1db35dad-c2bb-4561-ba5d-c4f1b35475cb
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368129280 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.368129280
Directory /workspace/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.1049902763
Short name T468
Test name
Test status
Simulation time 152370197 ps
CPU time 0.87 seconds
Started Apr 21 04:08:07 PM PDT 24
Finished Apr 21 04:08:08 PM PDT 24
Peak memory 198760 kb
Host smart-71b3ddeb-d533-4ce5-aebc-d8c75a3d3abf
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049902763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1049902763
Directory /workspace/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/45.pwrmgr_smoke.253394828
Short name T341
Test name
Test status
Simulation time 33221914 ps
CPU time 0.68 seconds
Started Apr 21 04:08:03 PM PDT 24
Finished Apr 21 04:08:05 PM PDT 24
Peak memory 198980 kb
Host smart-32f72bbc-8b41-44c9-b391-95cfa45487b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253394828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.253394828
Directory /workspace/45.pwrmgr_smoke/latest


Test location /workspace/coverage/default/45.pwrmgr_stress_all.1286448860
Short name T367
Test name
Test status
Simulation time 974113474 ps
CPU time 2.43 seconds
Started Apr 21 04:08:10 PM PDT 24
Finished Apr 21 04:08:13 PM PDT 24
Peak memory 200916 kb
Host smart-1bca3f2e-27e3-44fe-a335-1d369e22188e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286448860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all.1286448860
Directory /workspace/45.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/45.pwrmgr_wakeup.1789150481
Short name T420
Test name
Test status
Simulation time 72778940 ps
CPU time 0.66 seconds
Started Apr 21 04:08:06 PM PDT 24
Finished Apr 21 04:08:07 PM PDT 24
Peak memory 198004 kb
Host smart-760d7c00-315b-4190-afa2-15f92cf750ee
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789150481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup.1789150481
Directory /workspace/45.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/45.pwrmgr_wakeup_reset.1393086459
Short name T317
Test name
Test status
Simulation time 69665683 ps
CPU time 0.74 seconds
Started Apr 21 04:08:06 PM PDT 24
Finished Apr 21 04:08:07 PM PDT 24
Peak memory 198936 kb
Host smart-1f053f21-3fb7-4013-8336-5c8eddbe0b7c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393086459 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.1393086459
Directory /workspace/45.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/46.pwrmgr_aborted_low_power.3103182828
Short name T974
Test name
Test status
Simulation time 38001189 ps
CPU time 0.69 seconds
Started Apr 21 04:08:12 PM PDT 24
Finished Apr 21 04:08:13 PM PDT 24
Peak memory 198372 kb
Host smart-831476f4-7668-40b7-b4ce-39ac450ade59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103182828 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.3103182828
Directory /workspace/46.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/46.pwrmgr_disable_rom_integrity_check.2255352185
Short name T158
Test name
Test status
Simulation time 79594542 ps
CPU time 0.72 seconds
Started Apr 21 04:08:12 PM PDT 24
Finished Apr 21 04:08:13 PM PDT 24
Peak memory 198808 kb
Host smart-d1959ac0-45dc-4378-94fb-3d442969d3c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255352185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_dis
able_rom_integrity_check.2255352185
Directory /workspace/46.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.2897641877
Short name T372
Test name
Test status
Simulation time 28060556 ps
CPU time 0.65 seconds
Started Apr 21 04:08:10 PM PDT 24
Finished Apr 21 04:08:11 PM PDT 24
Peak memory 197604 kb
Host smart-b899d3cc-4c62-4c5c-970c-dfdc98a311ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897641877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst
_malfunc.2897641877
Directory /workspace/46.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/46.pwrmgr_escalation_timeout.1626353607
Short name T856
Test name
Test status
Simulation time 166867158 ps
CPU time 0.96 seconds
Started Apr 21 04:08:11 PM PDT 24
Finished Apr 21 04:08:12 PM PDT 24
Peak memory 197708 kb
Host smart-c9d1901d-1e1c-4d6d-8478-8613c410c171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626353607 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.1626353607
Directory /workspace/46.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/46.pwrmgr_glitch.3133560488
Short name T318
Test name
Test status
Simulation time 63158618 ps
CPU time 0.63 seconds
Started Apr 21 04:08:13 PM PDT 24
Finished Apr 21 04:08:14 PM PDT 24
Peak memory 197776 kb
Host smart-ea7f1621-61be-4e2e-9b8d-2f61eb3ff092
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133560488 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.3133560488
Directory /workspace/46.pwrmgr_glitch/latest


Test location /workspace/coverage/default/46.pwrmgr_global_esc.2597032695
Short name T234
Test name
Test status
Simulation time 80058143 ps
CPU time 0.64 seconds
Started Apr 21 04:08:08 PM PDT 24
Finished Apr 21 04:08:09 PM PDT 24
Peak memory 197764 kb
Host smart-03289067-8cfd-46b0-a72b-01e7d9027efc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597032695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.2597032695
Directory /workspace/46.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/46.pwrmgr_lowpower_invalid.3635141361
Short name T495
Test name
Test status
Simulation time 47068811 ps
CPU time 0.74 seconds
Started Apr 21 04:08:12 PM PDT 24
Finished Apr 21 04:08:14 PM PDT 24
Peak memory 201020 kb
Host smart-5677964d-9ae3-482f-9bae-e4dd7f94da34
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635141361 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_inval
id.3635141361
Directory /workspace/46.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/46.pwrmgr_lowpower_wakeup_race.1649955011
Short name T786
Test name
Test status
Simulation time 66127135 ps
CPU time 0.71 seconds
Started Apr 21 04:08:09 PM PDT 24
Finished Apr 21 04:08:10 PM PDT 24
Peak memory 197900 kb
Host smart-6391aec6-e14c-4ea9-b9f8-181c230f4300
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649955011 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_w
akeup_race.1649955011
Directory /workspace/46.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/46.pwrmgr_reset.3366620164
Short name T795
Test name
Test status
Simulation time 109893439 ps
CPU time 0.76 seconds
Started Apr 21 04:08:04 PM PDT 24
Finished Apr 21 04:08:05 PM PDT 24
Peak memory 198844 kb
Host smart-a7a16052-fc4d-44d5-933e-613e1e1224d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366620164 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.3366620164
Directory /workspace/46.pwrmgr_reset/latest


Test location /workspace/coverage/default/46.pwrmgr_reset_invalid.554067043
Short name T521
Test name
Test status
Simulation time 109003502 ps
CPU time 0.94 seconds
Started Apr 21 04:08:12 PM PDT 24
Finished Apr 21 04:08:14 PM PDT 24
Peak memory 209132 kb
Host smart-83049f75-3b9c-4eee-839d-6c3143c6bc9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554067043 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.554067043
Directory /workspace/46.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.1868526392
Short name T865
Test name
Test status
Simulation time 160519238 ps
CPU time 1.03 seconds
Started Apr 21 04:08:10 PM PDT 24
Finished Apr 21 04:08:11 PM PDT 24
Peak memory 199620 kb
Host smart-6858939a-ed11-4e12-bee0-e729f6914edf
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868526392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_
cm_ctrl_config_regwen.1868526392
Directory /workspace/46.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3126444206
Short name T715
Test name
Test status
Simulation time 925406890 ps
CPU time 3.25 seconds
Started Apr 21 04:08:09 PM PDT 24
Finished Apr 21 04:08:13 PM PDT 24
Peak memory 200764 kb
Host smart-a728d8f6-ac32-4818-bf81-b01b110498bc
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126444206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3126444206
Directory /workspace/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3805733112
Short name T679
Test name
Test status
Simulation time 858981806 ps
CPU time 3.61 seconds
Started Apr 21 04:08:09 PM PDT 24
Finished Apr 21 04:08:12 PM PDT 24
Peak memory 200912 kb
Host smart-2b7b4e8a-5446-405c-af89-5e110dae238e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805733112 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3805733112
Directory /workspace/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.1165400183
Short name T813
Test name
Test status
Simulation time 65905518 ps
CPU time 0.87 seconds
Started Apr 21 04:08:06 PM PDT 24
Finished Apr 21 04:08:08 PM PDT 24
Peak memory 199076 kb
Host smart-1224f58b-b2e8-48b9-8aea-57824bb734c4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165400183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1165400183
Directory /workspace/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/46.pwrmgr_smoke.2453212600
Short name T817
Test name
Test status
Simulation time 128514054 ps
CPU time 0.67 seconds
Started Apr 21 04:08:06 PM PDT 24
Finished Apr 21 04:08:07 PM PDT 24
Peak memory 198232 kb
Host smart-c6fbff6b-5d74-448a-8eff-3f9dcc804f82
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453212600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.2453212600
Directory /workspace/46.pwrmgr_smoke/latest


Test location /workspace/coverage/default/46.pwrmgr_stress_all.130926552
Short name T37
Test name
Test status
Simulation time 926780853 ps
CPU time 1.58 seconds
Started Apr 21 04:08:13 PM PDT 24
Finished Apr 21 04:08:15 PM PDT 24
Peak memory 200792 kb
Host smart-7ceb7ad9-de10-45eb-8510-5fb3cab65419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130926552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all.130926552
Directory /workspace/46.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/46.pwrmgr_stress_all_with_rand_reset.3869089621
Short name T820
Test name
Test status
Simulation time 5838231636 ps
CPU time 9.28 seconds
Started Apr 21 04:08:13 PM PDT 24
Finished Apr 21 04:08:22 PM PDT 24
Peak memory 201028 kb
Host smart-39ceae1d-1754-4e3b-84a1-58c55f565e9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869089621 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all_with_rand_reset.3869089621
Directory /workspace/46.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/46.pwrmgr_wakeup.896061517
Short name T132
Test name
Test status
Simulation time 63761641 ps
CPU time 0.77 seconds
Started Apr 21 04:08:09 PM PDT 24
Finished Apr 21 04:08:10 PM PDT 24
Peak memory 197904 kb
Host smart-af9407a5-10c3-41b2-a68b-ca2170c2cfca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896061517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.896061517
Directory /workspace/46.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/46.pwrmgr_wakeup_reset.3598909419
Short name T203
Test name
Test status
Simulation time 313887267 ps
CPU time 1.21 seconds
Started Apr 21 04:08:12 PM PDT 24
Finished Apr 21 04:08:14 PM PDT 24
Peak memory 200776 kb
Host smart-e2476a45-695f-41e2-b7ff-ac52d1699a70
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598909419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.3598909419
Directory /workspace/46.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/47.pwrmgr_aborted_low_power.3510217120
Short name T128
Test name
Test status
Simulation time 38015843 ps
CPU time 0.85 seconds
Started Apr 21 04:08:12 PM PDT 24
Finished Apr 21 04:08:13 PM PDT 24
Peak memory 199632 kb
Host smart-c3577d4e-f144-4487-b57d-87d61ef21b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510217120 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.3510217120
Directory /workspace/47.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/47.pwrmgr_disable_rom_integrity_check.479928704
Short name T551
Test name
Test status
Simulation time 63565299 ps
CPU time 0.85 seconds
Started Apr 21 04:08:15 PM PDT 24
Finished Apr 21 04:08:16 PM PDT 24
Peak memory 198836 kb
Host smart-46cca99d-591c-43be-ba4d-4ee4e14c1bce
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479928704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_disa
ble_rom_integrity_check.479928704
Directory /workspace/47.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.875991732
Short name T928
Test name
Test status
Simulation time 61411632 ps
CPU time 0.6 seconds
Started Apr 21 04:08:13 PM PDT 24
Finished Apr 21 04:08:14 PM PDT 24
Peak memory 196932 kb
Host smart-8f021422-8db4-4683-818d-a972434ed516
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875991732 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst_
malfunc.875991732
Directory /workspace/47.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/47.pwrmgr_escalation_timeout.2716429645
Short name T275
Test name
Test status
Simulation time 160866094 ps
CPU time 0.98 seconds
Started Apr 21 04:08:13 PM PDT 24
Finished Apr 21 04:08:14 PM PDT 24
Peak memory 197736 kb
Host smart-896a6285-7d7d-48b1-99cb-976657185f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716429645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.2716429645
Directory /workspace/47.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/47.pwrmgr_glitch.1908218059
Short name T736
Test name
Test status
Simulation time 53421111 ps
CPU time 0.65 seconds
Started Apr 21 04:08:18 PM PDT 24
Finished Apr 21 04:08:19 PM PDT 24
Peak memory 197768 kb
Host smart-dfb11525-1431-407f-a694-58e67ed5d8a8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908218059 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.1908218059
Directory /workspace/47.pwrmgr_glitch/latest


Test location /workspace/coverage/default/47.pwrmgr_global_esc.1719818791
Short name T838
Test name
Test status
Simulation time 47177952 ps
CPU time 0.67 seconds
Started Apr 21 04:08:13 PM PDT 24
Finished Apr 21 04:08:14 PM PDT 24
Peak memory 197736 kb
Host smart-020c60eb-7957-4fa2-8d45-a4e5c99f0b19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719818791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.1719818791
Directory /workspace/47.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/47.pwrmgr_lowpower_invalid.1639796620
Short name T829
Test name
Test status
Simulation time 77759545 ps
CPU time 0.69 seconds
Started Apr 21 04:08:16 PM PDT 24
Finished Apr 21 04:08:16 PM PDT 24
Peak memory 200852 kb
Host smart-84290b25-03b7-475c-bb9b-12c64d0248d0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639796620 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_inval
id.1639796620
Directory /workspace/47.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/47.pwrmgr_lowpower_wakeup_race.762158794
Short name T896
Test name
Test status
Simulation time 259929997 ps
CPU time 1.23 seconds
Started Apr 21 04:08:12 PM PDT 24
Finished Apr 21 04:08:14 PM PDT 24
Peak memory 199572 kb
Host smart-6fa1e213-42ae-4259-96b8-5646cbabfcc0
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762158794 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_wa
keup_race.762158794
Directory /workspace/47.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/47.pwrmgr_reset.631978319
Short name T754
Test name
Test status
Simulation time 152995879 ps
CPU time 0.69 seconds
Started Apr 21 04:08:12 PM PDT 24
Finished Apr 21 04:08:12 PM PDT 24
Peak memory 198852 kb
Host smart-155101bf-5d4a-48a3-85b7-3769d970f74e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631978319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.631978319
Directory /workspace/47.pwrmgr_reset/latest


Test location /workspace/coverage/default/47.pwrmgr_reset_invalid.841138819
Short name T205
Test name
Test status
Simulation time 190310872 ps
CPU time 0.83 seconds
Started Apr 21 04:08:16 PM PDT 24
Finished Apr 21 04:08:17 PM PDT 24
Peak memory 209108 kb
Host smart-aa2a3f55-824b-48de-a7a5-f59d145b46e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841138819 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.841138819
Directory /workspace/47.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.419336783
Short name T519
Test name
Test status
Simulation time 216651306 ps
CPU time 1.12 seconds
Started Apr 21 04:08:13 PM PDT 24
Finished Apr 21 04:08:14 PM PDT 24
Peak memory 200524 kb
Host smart-becaf13f-a554-46fd-a6a2-8dc9cf1a78e4
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419336783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_c
m_ctrl_config_regwen.419336783
Directory /workspace/47.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4212451869
Short name T310
Test name
Test status
Simulation time 918543980 ps
CPU time 2.16 seconds
Started Apr 21 04:08:14 PM PDT 24
Finished Apr 21 04:08:16 PM PDT 24
Peak memory 200936 kb
Host smart-98a85d9f-baba-4e25-b13d-277bb3b3f4f4
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212451869 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4212451869
Directory /workspace/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2365636843
Short name T740
Test name
Test status
Simulation time 846806909 ps
CPU time 3.32 seconds
Started Apr 21 04:08:13 PM PDT 24
Finished Apr 21 04:08:17 PM PDT 24
Peak memory 201004 kb
Host smart-fd7471aa-f8e6-4ae8-af82-3fa56e630bd8
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365636843 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2365636843
Directory /workspace/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.4125750131
Short name T251
Test name
Test status
Simulation time 198790956 ps
CPU time 0.88 seconds
Started Apr 21 04:08:15 PM PDT 24
Finished Apr 21 04:08:17 PM PDT 24
Peak memory 198768 kb
Host smart-511c3445-71ec-4212-96b9-8614827a07b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125750131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig
_mubi.4125750131
Directory /workspace/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/47.pwrmgr_smoke.97627301
Short name T204
Test name
Test status
Simulation time 64815525 ps
CPU time 0.66 seconds
Started Apr 21 04:08:12 PM PDT 24
Finished Apr 21 04:08:13 PM PDT 24
Peak memory 198248 kb
Host smart-3869a8b8-2bd1-4426-8ee6-27925cfebae7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97627301 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.97627301
Directory /workspace/47.pwrmgr_smoke/latest


Test location /workspace/coverage/default/47.pwrmgr_stress_all.941311630
Short name T779
Test name
Test status
Simulation time 635748472 ps
CPU time 3 seconds
Started Apr 21 04:08:16 PM PDT 24
Finished Apr 21 04:08:19 PM PDT 24
Peak memory 200960 kb
Host smart-66042ecf-bb25-4ee3-984b-5ed60836db28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941311630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.941311630
Directory /workspace/47.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/47.pwrmgr_stress_all_with_rand_reset.4250448931
Short name T131
Test name
Test status
Simulation time 4532980709 ps
CPU time 16.25 seconds
Started Apr 21 04:08:18 PM PDT 24
Finished Apr 21 04:08:35 PM PDT 24
Peak memory 200972 kb
Host smart-a18ff561-584a-427e-8fc7-9ee9cd158042
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250448931 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all_with_rand_reset.4250448931
Directory /workspace/47.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/47.pwrmgr_wakeup.4039039810
Short name T852
Test name
Test status
Simulation time 68816336 ps
CPU time 0.73 seconds
Started Apr 21 04:08:14 PM PDT 24
Finished Apr 21 04:08:16 PM PDT 24
Peak memory 198124 kb
Host smart-62ccb9f8-63f4-4144-a460-5a6ec3f3d4eb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039039810 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup.4039039810
Directory /workspace/47.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/47.pwrmgr_wakeup_reset.2514247544
Short name T489
Test name
Test status
Simulation time 366771850 ps
CPU time 1.41 seconds
Started Apr 21 04:08:12 PM PDT 24
Finished Apr 21 04:08:14 PM PDT 24
Peak memory 200796 kb
Host smart-afa96168-83ea-4bc3-aebc-d64157b47e75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514247544 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.2514247544
Directory /workspace/47.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/48.pwrmgr_aborted_low_power.3434682055
Short name T899
Test name
Test status
Simulation time 68820587 ps
CPU time 0.86 seconds
Started Apr 21 04:08:19 PM PDT 24
Finished Apr 21 04:08:20 PM PDT 24
Peak memory 199660 kb
Host smart-1c8df599-ed93-4b95-a544-9a4ba4b98db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434682055 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.3434682055
Directory /workspace/48.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/48.pwrmgr_disable_rom_integrity_check.3465363086
Short name T924
Test name
Test status
Simulation time 116746589 ps
CPU time 0.7 seconds
Started Apr 21 04:08:20 PM PDT 24
Finished Apr 21 04:08:21 PM PDT 24
Peak memory 198244 kb
Host smart-ab31fc3b-8784-43bf-bfff-00c41f2cd328
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465363086 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_dis
able_rom_integrity_check.3465363086
Directory /workspace/48.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.2759627710
Short name T480
Test name
Test status
Simulation time 29036696 ps
CPU time 0.64 seconds
Started Apr 21 04:08:19 PM PDT 24
Finished Apr 21 04:08:20 PM PDT 24
Peak memory 197660 kb
Host smart-f4e95c11-c598-4211-8987-e46a504cc112
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759627710 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst
_malfunc.2759627710
Directory /workspace/48.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/48.pwrmgr_escalation_timeout.2836862668
Short name T550
Test name
Test status
Simulation time 627012069 ps
CPU time 0.94 seconds
Started Apr 21 04:08:18 PM PDT 24
Finished Apr 21 04:08:19 PM PDT 24
Peak memory 197804 kb
Host smart-a23daac2-2160-424c-84ae-8d7cb66562ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836862668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.2836862668
Directory /workspace/48.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/48.pwrmgr_glitch.2335600963
Short name T239
Test name
Test status
Simulation time 31454646 ps
CPU time 0.67 seconds
Started Apr 21 04:08:18 PM PDT 24
Finished Apr 21 04:08:19 PM PDT 24
Peak memory 197704 kb
Host smart-32d83153-7de6-44d5-9eec-5ffad1bd1232
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335600963 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.2335600963
Directory /workspace/48.pwrmgr_glitch/latest


Test location /workspace/coverage/default/48.pwrmgr_global_esc.2837033238
Short name T667
Test name
Test status
Simulation time 36981115 ps
CPU time 0.64 seconds
Started Apr 21 04:08:21 PM PDT 24
Finished Apr 21 04:08:22 PM PDT 24
Peak memory 197752 kb
Host smart-946a202b-8b9a-44f0-9a7e-5df5019da950
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837033238 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.2837033238
Directory /workspace/48.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/48.pwrmgr_lowpower_invalid.1433979590
Short name T214
Test name
Test status
Simulation time 80421072 ps
CPU time 0.71 seconds
Started Apr 21 04:08:20 PM PDT 24
Finished Apr 21 04:08:21 PM PDT 24
Peak memory 201032 kb
Host smart-847ee45f-6554-42b0-b74b-b988990d8e79
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433979590 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_inval
id.1433979590
Directory /workspace/48.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/48.pwrmgr_lowpower_wakeup_race.257324719
Short name T478
Test name
Test status
Simulation time 219655493 ps
CPU time 0.86 seconds
Started Apr 21 04:08:16 PM PDT 24
Finished Apr 21 04:08:17 PM PDT 24
Peak memory 198048 kb
Host smart-47c5b471-9c15-4d06-8cb9-92f85213b166
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257324719 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_wa
keup_race.257324719
Directory /workspace/48.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/48.pwrmgr_reset.919664911
Short name T103
Test name
Test status
Simulation time 87817536 ps
CPU time 0.69 seconds
Started Apr 21 04:08:16 PM PDT 24
Finished Apr 21 04:08:17 PM PDT 24
Peak memory 198784 kb
Host smart-93b6e364-e08b-48a2-8cc6-204f8f73e7a5
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919664911 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.919664911
Directory /workspace/48.pwrmgr_reset/latest


Test location /workspace/coverage/default/48.pwrmgr_reset_invalid.1888120397
Short name T602
Test name
Test status
Simulation time 115442227 ps
CPU time 0.88 seconds
Started Apr 21 04:08:20 PM PDT 24
Finished Apr 21 04:08:21 PM PDT 24
Peak memory 209124 kb
Host smart-355b48be-3c95-4ac3-a036-80ec4f91a467
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888120397 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.1888120397
Directory /workspace/48.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.19480974
Short name T613
Test name
Test status
Simulation time 198777694 ps
CPU time 0.82 seconds
Started Apr 21 04:08:25 PM PDT 24
Finished Apr 21 04:08:26 PM PDT 24
Peak memory 199048 kb
Host smart-1b6e2686-4f0f-475e-88b5-a1cb167c3269
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19480974 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_co
nfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm
_ctrl_config_regwen.19480974
Directory /workspace/48.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1061638126
Short name T297
Test name
Test status
Simulation time 769125610 ps
CPU time 3.27 seconds
Started Apr 21 04:08:17 PM PDT 24
Finished Apr 21 04:08:21 PM PDT 24
Peak memory 200836 kb
Host smart-b9cebfb3-1f17-4988-bf77-278a6f1747b2
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061638126 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1061638126
Directory /workspace/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.459854604
Short name T954
Test name
Test status
Simulation time 932477419 ps
CPU time 2.73 seconds
Started Apr 21 04:08:20 PM PDT 24
Finished Apr 21 04:08:23 PM PDT 24
Peak memory 200968 kb
Host smart-825a6663-529d-4cff-984f-ba63993eb463
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459854604 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.459854604
Directory /workspace/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1706923852
Short name T28
Test name
Test status
Simulation time 94015417 ps
CPU time 0.85 seconds
Started Apr 21 04:08:20 PM PDT 24
Finished Apr 21 04:08:21 PM PDT 24
Peak memory 199064 kb
Host smart-af91651d-44d6-490b-8a23-1afa51d32917
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706923852 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig
_mubi.1706923852
Directory /workspace/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/48.pwrmgr_smoke.658904766
Short name T672
Test name
Test status
Simulation time 131442642 ps
CPU time 0.72 seconds
Started Apr 21 04:08:21 PM PDT 24
Finished Apr 21 04:08:22 PM PDT 24
Peak memory 198992 kb
Host smart-f7c076fb-f63d-42ee-9a28-3b0c5a720861
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658904766 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.658904766
Directory /workspace/48.pwrmgr_smoke/latest


Test location /workspace/coverage/default/48.pwrmgr_stress_all.2862321951
Short name T237
Test name
Test status
Simulation time 585037622 ps
CPU time 2.34 seconds
Started Apr 21 04:08:20 PM PDT 24
Finished Apr 21 04:08:22 PM PDT 24
Peak memory 200908 kb
Host smart-0b9dc023-e510-422b-b2e9-5b23da02c73f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862321951 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all.2862321951
Directory /workspace/48.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/48.pwrmgr_stress_all_with_rand_reset.195794358
Short name T760
Test name
Test status
Simulation time 14713828346 ps
CPU time 20.99 seconds
Started Apr 21 04:08:22 PM PDT 24
Finished Apr 21 04:08:43 PM PDT 24
Peak memory 201064 kb
Host smart-44b8a8a9-b11d-4c48-b7df-1d3f01c70624
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195794358 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all_with_rand_reset.195794358
Directory /workspace/48.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/48.pwrmgr_wakeup.403535294
Short name T7
Test name
Test status
Simulation time 50094118 ps
CPU time 0.65 seconds
Started Apr 21 04:08:17 PM PDT 24
Finished Apr 21 04:08:18 PM PDT 24
Peak memory 197868 kb
Host smart-4f68a84f-e8b4-42e9-8338-0f845dabdbef
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403535294 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.403535294
Directory /workspace/48.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/48.pwrmgr_wakeup_reset.121936197
Short name T371
Test name
Test status
Simulation time 308125352 ps
CPU time 1.43 seconds
Started Apr 21 04:08:15 PM PDT 24
Finished Apr 21 04:08:17 PM PDT 24
Peak memory 200716 kb
Host smart-fbcdfe6d-8d9b-4ed8-b655-0dc4fe9e66ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121936197 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.121936197
Directory /workspace/48.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/49.pwrmgr_aborted_low_power.1935115605
Short name T445
Test name
Test status
Simulation time 39023199 ps
CPU time 0.9 seconds
Started Apr 21 04:08:20 PM PDT 24
Finished Apr 21 04:08:22 PM PDT 24
Peak memory 199836 kb
Host smart-a802aa4d-4f5b-485f-a229-6df289efe130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935115605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.1935115605
Directory /workspace/49.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/49.pwrmgr_disable_rom_integrity_check.3383061314
Short name T890
Test name
Test status
Simulation time 73811420 ps
CPU time 0.77 seconds
Started Apr 21 04:08:24 PM PDT 24
Finished Apr 21 04:08:25 PM PDT 24
Peak memory 198768 kb
Host smart-5d046dce-5b52-4d4a-abae-40a68cf48770
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383061314 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_dis
able_rom_integrity_check.3383061314
Directory /workspace/49.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.3742859431
Short name T642
Test name
Test status
Simulation time 38640958 ps
CPU time 0.6 seconds
Started Apr 21 04:08:20 PM PDT 24
Finished Apr 21 04:08:21 PM PDT 24
Peak memory 196996 kb
Host smart-eb4d5064-cd6b-4a45-9201-d95c6e8f2ee1
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742859431 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst
_malfunc.3742859431
Directory /workspace/49.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/49.pwrmgr_escalation_timeout.2615856174
Short name T901
Test name
Test status
Simulation time 158610581 ps
CPU time 0.98 seconds
Started Apr 21 04:08:24 PM PDT 24
Finished Apr 21 04:08:26 PM PDT 24
Peak memory 197784 kb
Host smart-14277981-7eaf-4ab1-a12d-b75b609fcc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615856174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.2615856174
Directory /workspace/49.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/49.pwrmgr_glitch.572816942
Short name T780
Test name
Test status
Simulation time 111066694 ps
CPU time 0.67 seconds
Started Apr 21 04:08:21 PM PDT 24
Finished Apr 21 04:08:22 PM PDT 24
Peak memory 197752 kb
Host smart-27a7894a-b52f-4df3-9f07-446ab2b99954
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572816942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.572816942
Directory /workspace/49.pwrmgr_glitch/latest


Test location /workspace/coverage/default/49.pwrmgr_global_esc.4202301296
Short name T893
Test name
Test status
Simulation time 99604324 ps
CPU time 0.72 seconds
Started Apr 21 04:08:25 PM PDT 24
Finished Apr 21 04:08:26 PM PDT 24
Peak memory 197740 kb
Host smart-44f7dcf1-d747-40af-84b4-eccbe861222b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202301296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.4202301296
Directory /workspace/49.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/49.pwrmgr_lowpower_invalid.4023354691
Short name T903
Test name
Test status
Simulation time 43499493 ps
CPU time 0.74 seconds
Started Apr 21 04:08:23 PM PDT 24
Finished Apr 21 04:08:24 PM PDT 24
Peak memory 201020 kb
Host smart-1dc75e4f-b6c5-420f-bad6-c3b8eef9009a
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023354691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_inval
id.4023354691
Directory /workspace/49.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/49.pwrmgr_lowpower_wakeup_race.2407386292
Short name T734
Test name
Test status
Simulation time 237160936 ps
CPU time 0.84 seconds
Started Apr 21 04:08:25 PM PDT 24
Finished Apr 21 04:08:26 PM PDT 24
Peak memory 198056 kb
Host smart-4f44540a-f103-47bb-8519-2682a6a2ebfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407386292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_w
akeup_race.2407386292
Directory /workspace/49.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/49.pwrmgr_reset.3218754617
Short name T892
Test name
Test status
Simulation time 88707989 ps
CPU time 1.04 seconds
Started Apr 21 04:08:20 PM PDT 24
Finished Apr 21 04:08:21 PM PDT 24
Peak memory 199552 kb
Host smart-6e39917c-12d3-4dee-80cf-1d612ecd49a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218754617 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.3218754617
Directory /workspace/49.pwrmgr_reset/latest


Test location /workspace/coverage/default/49.pwrmgr_reset_invalid.3332797465
Short name T415
Test name
Test status
Simulation time 107877348 ps
CPU time 1.02 seconds
Started Apr 21 04:08:23 PM PDT 24
Finished Apr 21 04:08:25 PM PDT 24
Peak memory 209140 kb
Host smart-042825a0-13cf-44fb-bcab-52990c758cfc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332797465 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.3332797465
Directory /workspace/49.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.4040491879
Short name T247
Test name
Test status
Simulation time 120558283 ps
CPU time 0.89 seconds
Started Apr 21 04:08:21 PM PDT 24
Finished Apr 21 04:08:22 PM PDT 24
Peak memory 198564 kb
Host smart-d2c73d24-efb8-4dfc-b9ce-2cb6c19ba253
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040491879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_
cm_ctrl_config_regwen.4040491879
Directory /workspace/49.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1163476015
Short name T226
Test name
Test status
Simulation time 936709373 ps
CPU time 3.46 seconds
Started Apr 21 04:08:21 PM PDT 24
Finished Apr 21 04:08:24 PM PDT 24
Peak memory 200860 kb
Host smart-705fed82-f38e-4e9b-895d-1102d528cb46
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163476015 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1163476015
Directory /workspace/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.694135740
Short name T195
Test name
Test status
Simulation time 100001971 ps
CPU time 0.92 seconds
Started Apr 21 04:08:26 PM PDT 24
Finished Apr 21 04:08:27 PM PDT 24
Peak memory 198952 kb
Host smart-fb5fbd72-cd17-4413-aef7-4e74eb576629
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694135740 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig_
mubi.694135740
Directory /workspace/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/49.pwrmgr_smoke.2949723916
Short name T448
Test name
Test status
Simulation time 32000358 ps
CPU time 0.67 seconds
Started Apr 21 04:08:19 PM PDT 24
Finished Apr 21 04:08:20 PM PDT 24
Peak memory 198996 kb
Host smart-d3dd1f64-e5e0-4305-89f5-32d194f49d2f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949723916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.2949723916
Directory /workspace/49.pwrmgr_smoke/latest


Test location /workspace/coverage/default/49.pwrmgr_stress_all.4255889539
Short name T882
Test name
Test status
Simulation time 1761195369 ps
CPU time 6.04 seconds
Started Apr 21 04:08:23 PM PDT 24
Finished Apr 21 04:08:30 PM PDT 24
Peak memory 200956 kb
Host smart-a44761e4-49a3-43a2-ae43-1289ee87f0a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255889539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all.4255889539
Directory /workspace/49.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/49.pwrmgr_stress_all_with_rand_reset.545711704
Short name T98
Test name
Test status
Simulation time 10248077039 ps
CPU time 31.74 seconds
Started Apr 21 04:08:25 PM PDT 24
Finished Apr 21 04:08:57 PM PDT 24
Peak memory 201044 kb
Host smart-d64d4730-54a8-4aa5-ad25-cc93836e9dde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545711704 -assert nopost
proc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all_with_rand_reset.545711704
Directory /workspace/49.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/49.pwrmgr_wakeup.3626180102
Short name T884
Test name
Test status
Simulation time 46960991 ps
CPU time 0.7 seconds
Started Apr 21 04:08:23 PM PDT 24
Finished Apr 21 04:08:24 PM PDT 24
Peak memory 197928 kb
Host smart-9df54b8b-88df-4e8c-b9ac-c6c513e8157f
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626180102 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.3626180102
Directory /workspace/49.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/49.pwrmgr_wakeup_reset.2242059565
Short name T712
Test name
Test status
Simulation time 336475115 ps
CPU time 1.21 seconds
Started Apr 21 04:08:24 PM PDT 24
Finished Apr 21 04:08:25 PM PDT 24
Peak memory 200744 kb
Host smart-0e890a29-1c5b-4d3d-8b2c-056fe3798dc4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242059565 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.2242059565
Directory /workspace/49.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/5.pwrmgr_aborted_low_power.1416444584
Short name T845
Test name
Test status
Simulation time 83019439 ps
CPU time 0.77 seconds
Started Apr 21 04:05:36 PM PDT 24
Finished Apr 21 04:05:37 PM PDT 24
Peak memory 198524 kb
Host smart-329eec26-f2d2-4ee1-81ff-1005b278eee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416444584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.1416444584
Directory /workspace/5.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/5.pwrmgr_disable_rom_integrity_check.1649569946
Short name T295
Test name
Test status
Simulation time 47322071 ps
CPU time 0.86 seconds
Started Apr 21 04:05:39 PM PDT 24
Finished Apr 21 04:05:40 PM PDT 24
Peak memory 198828 kb
Host smart-da1bf659-ea83-4731-8ebb-00a1d3475a21
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649569946 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disa
ble_rom_integrity_check.1649569946
Directory /workspace/5.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.3022384747
Short name T688
Test name
Test status
Simulation time 30809002 ps
CPU time 0.68 seconds
Started Apr 21 04:05:40 PM PDT 24
Finished Apr 21 04:05:41 PM PDT 24
Peak memory 197688 kb
Host smart-60729e65-4fb4-45fa-be9b-21dbe2471a86
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022384747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_
malfunc.3022384747
Directory /workspace/5.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/5.pwrmgr_escalation_timeout.1869083860
Short name T408
Test name
Test status
Simulation time 2160232776 ps
CPU time 0.96 seconds
Started Apr 21 04:05:46 PM PDT 24
Finished Apr 21 04:05:47 PM PDT 24
Peak memory 198112 kb
Host smart-52e444cf-5170-40a5-96c0-46e1fd8be094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869083860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.1869083860
Directory /workspace/5.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/5.pwrmgr_glitch.605142003
Short name T455
Test name
Test status
Simulation time 56980097 ps
CPU time 0.58 seconds
Started Apr 21 04:05:42 PM PDT 24
Finished Apr 21 04:05:43 PM PDT 24
Peak memory 197748 kb
Host smart-300e4b14-0e85-4baa-9f55-3104ec838542
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605142003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.605142003
Directory /workspace/5.pwrmgr_glitch/latest


Test location /workspace/coverage/default/5.pwrmgr_global_esc.2138714327
Short name T908
Test name
Test status
Simulation time 23750512 ps
CPU time 0.62 seconds
Started Apr 21 04:05:46 PM PDT 24
Finished Apr 21 04:05:47 PM PDT 24
Peak memory 198048 kb
Host smart-c0f7cdc0-6534-4d60-8cb5-1211dff61067
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138714327 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.2138714327
Directory /workspace/5.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/5.pwrmgr_lowpower_invalid.2292094577
Short name T552
Test name
Test status
Simulation time 58835208 ps
CPU time 0.69 seconds
Started Apr 21 04:05:42 PM PDT 24
Finished Apr 21 04:05:43 PM PDT 24
Peak memory 200852 kb
Host smart-a1086852-6c83-4278-8050-31053e645e56
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292094577 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invali
d.2292094577
Directory /workspace/5.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/5.pwrmgr_lowpower_wakeup_race.2517608241
Short name T236
Test name
Test status
Simulation time 157357190 ps
CPU time 1.05 seconds
Started Apr 21 04:05:35 PM PDT 24
Finished Apr 21 04:05:36 PM PDT 24
Peak memory 198124 kb
Host smart-2d35b870-51cb-4b7c-bdf4-68390ed6b134
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517608241 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wa
keup_race.2517608241
Directory /workspace/5.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/5.pwrmgr_reset.1175132533
Short name T886
Test name
Test status
Simulation time 53416961 ps
CPU time 0.64 seconds
Started Apr 21 04:05:36 PM PDT 24
Finished Apr 21 04:05:37 PM PDT 24
Peak memory 197968 kb
Host smart-3feac36c-6ed1-42bc-b1d5-fed03f3f9899
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175132533 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.1175132533
Directory /workspace/5.pwrmgr_reset/latest


Test location /workspace/coverage/default/5.pwrmgr_reset_invalid.1040196624
Short name T378
Test name
Test status
Simulation time 150426985 ps
CPU time 0.81 seconds
Started Apr 21 04:05:47 PM PDT 24
Finished Apr 21 04:05:48 PM PDT 24
Peak memory 209028 kb
Host smart-670bd734-4f72-4fbb-bec4-cfe9188ad79d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040196624 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.1040196624
Directory /workspace/5.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.723162233
Short name T347
Test name
Test status
Simulation time 86423790 ps
CPU time 0.66 seconds
Started Apr 21 04:05:41 PM PDT 24
Finished Apr 21 04:05:41 PM PDT 24
Peak memory 198204 kb
Host smart-8919ff10-7d41-4b70-908a-28c54a4d14e4
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723162233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm
_ctrl_config_regwen.723162233
Directory /workspace/5.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1344935867
Short name T778
Test name
Test status
Simulation time 1154029967 ps
CPU time 2.04 seconds
Started Apr 21 04:05:38 PM PDT 24
Finished Apr 21 04:05:40 PM PDT 24
Peak memory 200808 kb
Host smart-1a7d29eb-1784-4c55-a2af-e0a004bd6703
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344935867 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1344935867
Directory /workspace/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.410503269
Short name T857
Test name
Test status
Simulation time 1050502792 ps
CPU time 2.1 seconds
Started Apr 21 04:05:46 PM PDT 24
Finished Apr 21 04:05:49 PM PDT 24
Peak memory 200860 kb
Host smart-9561a3fe-90ef-4cc9-ad06-a17ff07492a6
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410503269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.410503269
Directory /workspace/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3268085862
Short name T168
Test name
Test status
Simulation time 50810342 ps
CPU time 0.85 seconds
Started Apr 21 04:05:37 PM PDT 24
Finished Apr 21 04:05:38 PM PDT 24
Peak memory 198788 kb
Host smart-aeafc5d1-d63b-4f26-8ab3-bd9733fe5a16
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268085862 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_
mubi.3268085862
Directory /workspace/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/5.pwrmgr_smoke.3027309829
Short name T447
Test name
Test status
Simulation time 53924232 ps
CPU time 0.65 seconds
Started Apr 21 04:05:36 PM PDT 24
Finished Apr 21 04:05:37 PM PDT 24
Peak memory 198220 kb
Host smart-ef533551-1ec8-4bda-94c2-066dd8f39d50
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027309829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.3027309829
Directory /workspace/5.pwrmgr_smoke/latest


Test location /workspace/coverage/default/5.pwrmgr_stress_all.2937679825
Short name T697
Test name
Test status
Simulation time 1732825327 ps
CPU time 2.72 seconds
Started Apr 21 04:05:43 PM PDT 24
Finished Apr 21 04:05:46 PM PDT 24
Peak memory 200908 kb
Host smart-6da20d2a-1f85-41d3-87f8-6646e5ddec3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937679825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all.2937679825
Directory /workspace/5.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/5.pwrmgr_stress_all_with_rand_reset.1888589892
Short name T631
Test name
Test status
Simulation time 9668690900 ps
CPU time 31.31 seconds
Started Apr 21 04:05:42 PM PDT 24
Finished Apr 21 04:06:14 PM PDT 24
Peak memory 201012 kb
Host smart-7308286e-068e-4dc3-93cc-1c9db2b91fa4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888589892 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all_with_rand_reset.1888589892
Directory /workspace/5.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/5.pwrmgr_wakeup.368186272
Short name T3
Test name
Test status
Simulation time 80618142 ps
CPU time 0.65 seconds
Started Apr 21 04:05:35 PM PDT 24
Finished Apr 21 04:05:36 PM PDT 24
Peak memory 197896 kb
Host smart-ef883fda-70e0-4476-9fed-75e2dca5331e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368186272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.368186272
Directory /workspace/5.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/5.pwrmgr_wakeup_reset.3895013818
Short name T626
Test name
Test status
Simulation time 166927923 ps
CPU time 0.83 seconds
Started Apr 21 04:05:38 PM PDT 24
Finished Apr 21 04:05:39 PM PDT 24
Peak memory 199000 kb
Host smart-03ef1cdd-84fa-41f8-812a-c0ca2c8adb18
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895013818 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.3895013818
Directory /workspace/5.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/6.pwrmgr_aborted_low_power.1177775647
Short name T248
Test name
Test status
Simulation time 36818495 ps
CPU time 1.08 seconds
Started Apr 21 04:05:42 PM PDT 24
Finished Apr 21 04:05:44 PM PDT 24
Peak memory 200616 kb
Host smart-f923cba8-10e6-44e4-a0a1-3d58e5409576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177775647 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.1177775647
Directory /workspace/6.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/6.pwrmgr_disable_rom_integrity_check.3497537517
Short name T646
Test name
Test status
Simulation time 62590035 ps
CPU time 0.75 seconds
Started Apr 21 04:05:47 PM PDT 24
Finished Apr 21 04:05:48 PM PDT 24
Peak memory 198148 kb
Host smart-06761af0-fda6-41d3-ae7f-60986fea6c70
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497537517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_i
ntegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disa
ble_rom_integrity_check.3497537517
Directory /workspace/6.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.1043591363
Short name T279
Test name
Test status
Simulation time 104995067 ps
CPU time 0.61 seconds
Started Apr 21 04:05:44 PM PDT 24
Finished Apr 21 04:05:46 PM PDT 24
Peak memory 197664 kb
Host smart-391918ef-0a78-4180-b34f-559daa71af1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043591363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_
malfunc.1043591363
Directory /workspace/6.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/6.pwrmgr_escalation_timeout.543631780
Short name T801
Test name
Test status
Simulation time 166918800 ps
CPU time 0.99 seconds
Started Apr 21 04:05:49 PM PDT 24
Finished Apr 21 04:05:50 PM PDT 24
Peak memory 198076 kb
Host smart-5a7a44bf-3667-4876-9ec1-3e5c03c70a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543631780 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.543631780
Directory /workspace/6.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/6.pwrmgr_glitch.19102706
Short name T835
Test name
Test status
Simulation time 87789204 ps
CPU time 0.59 seconds
Started Apr 21 04:05:44 PM PDT 24
Finished Apr 21 04:05:45 PM PDT 24
Peak memory 197640 kb
Host smart-faf5e522-1d46-40d3-b624-c3e4afff07df
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19102706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.19102706
Directory /workspace/6.pwrmgr_glitch/latest


Test location /workspace/coverage/default/6.pwrmgr_global_esc.1707675880
Short name T249
Test name
Test status
Simulation time 69085212 ps
CPU time 0.64 seconds
Started Apr 21 04:05:45 PM PDT 24
Finished Apr 21 04:05:46 PM PDT 24
Peak memory 197796 kb
Host smart-e37e885d-6f7f-4443-a2e4-0cdb94ed687a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707675880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.1707675880
Directory /workspace/6.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/6.pwrmgr_lowpower_invalid.467820354
Short name T790
Test name
Test status
Simulation time 44245815 ps
CPU time 0.76 seconds
Started Apr 21 04:05:45 PM PDT 24
Finished Apr 21 04:05:46 PM PDT 24
Peak memory 201028 kb
Host smart-60274c63-2a8c-4dfe-ab50-76daa111b2fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467820354 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inval
id_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invalid
.467820354
Directory /workspace/6.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/6.pwrmgr_lowpower_wakeup_race.1714680224
Short name T929
Test name
Test status
Simulation time 440726643 ps
CPU time 1.05 seconds
Started Apr 21 04:05:41 PM PDT 24
Finished Apr 21 04:05:42 PM PDT 24
Peak memory 199284 kb
Host smart-2034f055-62d7-4e59-a9d2-d04fc699d120
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714680224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wa
keup_race.1714680224
Directory /workspace/6.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/6.pwrmgr_reset.3522257143
Short name T964
Test name
Test status
Simulation time 62774944 ps
CPU time 0.98 seconds
Started Apr 21 04:05:42 PM PDT 24
Finished Apr 21 04:05:44 PM PDT 24
Peak memory 199532 kb
Host smart-7b5855aa-d6e6-41f7-92c6-05757a678084
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522257143 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.3522257143
Directory /workspace/6.pwrmgr_reset/latest


Test location /workspace/coverage/default/6.pwrmgr_reset_invalid.2576093166
Short name T946
Test name
Test status
Simulation time 200621507 ps
CPU time 0.77 seconds
Started Apr 21 04:05:50 PM PDT 24
Finished Apr 21 04:05:51 PM PDT 24
Peak memory 209128 kb
Host smart-8051b941-7d63-4532-8fe1-a5b8c2001c64
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576093166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.2576093166
Directory /workspace/6.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.100957481
Short name T483
Test name
Test status
Simulation time 258066988 ps
CPU time 1.3 seconds
Started Apr 21 04:05:51 PM PDT 24
Finished Apr 21 04:05:53 PM PDT 24
Peak memory 200544 kb
Host smart-a9e54a8a-5ba2-45a3-bf25-68ef6f780d28
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100957481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_c
onfig_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm
_ctrl_config_regwen.100957481
Directory /workspace/6.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.573369552
Short name T588
Test name
Test status
Simulation time 963761491 ps
CPU time 2.13 seconds
Started Apr 21 04:05:43 PM PDT 24
Finished Apr 21 04:05:46 PM PDT 24
Peak memory 200920 kb
Host smart-6b37acc6-a407-40ee-97ef-4ceb48558b71
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573369552 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.573369552
Directory /workspace/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.284105932
Short name T187
Test name
Test status
Simulation time 767744006 ps
CPU time 3.31 seconds
Started Apr 21 04:05:48 PM PDT 24
Finished Apr 21 04:05:51 PM PDT 24
Peak memory 200880 kb
Host smart-4231482e-0a34-4221-a416-bc91e90727bc
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284105932 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.284105932
Directory /workspace/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.1027870224
Short name T825
Test name
Test status
Simulation time 185917592 ps
CPU time 0.89 seconds
Started Apr 21 04:05:46 PM PDT 24
Finished Apr 21 04:05:47 PM PDT 24
Peak memory 198780 kb
Host smart-5ecaa637-0827-4883-bab9-82797bd73e46
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027870224 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_
mubi.1027870224
Directory /workspace/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/6.pwrmgr_smoke.2075226728
Short name T403
Test name
Test status
Simulation time 37853882 ps
CPU time 0.66 seconds
Started Apr 21 04:05:42 PM PDT 24
Finished Apr 21 04:05:43 PM PDT 24
Peak memory 198116 kb
Host smart-eedda383-76e9-4072-a7db-e1a5c49d7e05
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075226728 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.2075226728
Directory /workspace/6.pwrmgr_smoke/latest


Test location /workspace/coverage/default/6.pwrmgr_stress_all.3144054849
Short name T396
Test name
Test status
Simulation time 2403178968 ps
CPU time 6.57 seconds
Started Apr 21 04:05:44 PM PDT 24
Finished Apr 21 04:05:51 PM PDT 24
Peak memory 201020 kb
Host smart-e7114d42-8439-4595-b463-c29db6270c4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144054849 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.3144054849
Directory /workspace/6.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/6.pwrmgr_stress_all_with_rand_reset.2656986185
Short name T412
Test name
Test status
Simulation time 2964881188 ps
CPU time 8.32 seconds
Started Apr 21 04:05:46 PM PDT 24
Finished Apr 21 04:05:54 PM PDT 24
Peak memory 201080 kb
Host smart-c9f6c6bc-4fb6-48c5-a6d3-989527cea0a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656986185 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all_with_rand_reset.2656986185
Directory /workspace/6.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/6.pwrmgr_wakeup.4198893737
Short name T766
Test name
Test status
Simulation time 156174337 ps
CPU time 0.97 seconds
Started Apr 21 04:05:46 PM PDT 24
Finished Apr 21 04:05:47 PM PDT 24
Peak memory 197996 kb
Host smart-53addbdc-a72f-4983-8f7e-26aa7c140bca
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198893737 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.4198893737
Directory /workspace/6.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/6.pwrmgr_wakeup_reset.291156910
Short name T809
Test name
Test status
Simulation time 158726646 ps
CPU time 0.82 seconds
Started Apr 21 04:05:41 PM PDT 24
Finished Apr 21 04:05:43 PM PDT 24
Peak memory 198900 kb
Host smart-0c20c770-a7cb-46fa-b940-515810317c70
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291156910 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.291156910
Directory /workspace/6.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/7.pwrmgr_aborted_low_power.1781761597
Short name T745
Test name
Test status
Simulation time 95645058 ps
CPU time 0.8 seconds
Started Apr 21 04:06:03 PM PDT 24
Finished Apr 21 04:06:04 PM PDT 24
Peak memory 198496 kb
Host smart-9232da81-7bec-421d-82c9-15f80f5019ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781761597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.1781761597
Directory /workspace/7.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/7.pwrmgr_disable_rom_integrity_check.671794666
Short name T832
Test name
Test status
Simulation time 73571685 ps
CPU time 0.78 seconds
Started Apr 21 04:05:51 PM PDT 24
Finished Apr 21 04:05:52 PM PDT 24
Peak memory 198368 kb
Host smart-ab64f57d-77d2-4d58-88bc-01712288d405
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671794666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disab
le_rom_integrity_check.671794666
Directory /workspace/7.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.3995809434
Short name T545
Test name
Test status
Simulation time 39843005 ps
CPU time 0.62 seconds
Started Apr 21 04:05:46 PM PDT 24
Finished Apr 21 04:05:47 PM PDT 24
Peak memory 196928 kb
Host smart-7ad9151b-c9d2-47c5-93b8-6e0f8f38e7f4
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995809434 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_
malfunc.3995809434
Directory /workspace/7.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/7.pwrmgr_escalation_timeout.260697718
Short name T407
Test name
Test status
Simulation time 306597298 ps
CPU time 0.94 seconds
Started Apr 21 04:05:47 PM PDT 24
Finished Apr 21 04:05:48 PM PDT 24
Peak memory 197780 kb
Host smart-2acbc5bf-cac9-4e81-a2d7-473700593efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260697718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.260697718
Directory /workspace/7.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/7.pwrmgr_glitch.3838696538
Short name T738
Test name
Test status
Simulation time 44569465 ps
CPU time 0.64 seconds
Started Apr 21 04:05:49 PM PDT 24
Finished Apr 21 04:05:50 PM PDT 24
Peak memory 197828 kb
Host smart-2085774f-04cc-4ef2-9557-3cf274ea0b75
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838696538 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.3838696538
Directory /workspace/7.pwrmgr_glitch/latest


Test location /workspace/coverage/default/7.pwrmgr_global_esc.3995590211
Short name T981
Test name
Test status
Simulation time 43033678 ps
CPU time 0.66 seconds
Started Apr 21 04:05:47 PM PDT 24
Finished Apr 21 04:05:48 PM PDT 24
Peak memory 197800 kb
Host smart-80867781-81f2-400f-9ef5-029e9e5983bc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995590211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.3995590211
Directory /workspace/7.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/7.pwrmgr_lowpower_invalid.4139825608
Short name T272
Test name
Test status
Simulation time 112659989 ps
CPU time 0.68 seconds
Started Apr 21 04:05:47 PM PDT 24
Finished Apr 21 04:05:48 PM PDT 24
Peak memory 201036 kb
Host smart-5f955fc9-d9a1-4f7c-9d1f-74b8fb9a95fb
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139825608 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invali
d.4139825608
Directory /workspace/7.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/7.pwrmgr_lowpower_wakeup_race.426825741
Short name T457
Test name
Test status
Simulation time 63750604 ps
CPU time 0.64 seconds
Started Apr 21 04:05:47 PM PDT 24
Finished Apr 21 04:05:48 PM PDT 24
Peak memory 197872 kb
Host smart-be87b12c-931f-4ad3-a64c-6b783eb2b5ab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426825741 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wak
eup_race.426825741
Directory /workspace/7.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/7.pwrmgr_reset.2988160758
Short name T629
Test name
Test status
Simulation time 107960136 ps
CPU time 0.79 seconds
Started Apr 21 04:05:45 PM PDT 24
Finished Apr 21 04:05:46 PM PDT 24
Peak memory 198384 kb
Host smart-93147613-f61f-48d6-8ec3-16f333ebb758
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988160758 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.2988160758
Directory /workspace/7.pwrmgr_reset/latest


Test location /workspace/coverage/default/7.pwrmgr_reset_invalid.2532707213
Short name T529
Test name
Test status
Simulation time 96324329 ps
CPU time 0.92 seconds
Started Apr 21 04:05:47 PM PDT 24
Finished Apr 21 04:05:49 PM PDT 24
Peak memory 209140 kb
Host smart-ba5ed68e-9bc9-448e-9ec0-c3e2ea33cbf8
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532707213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.2532707213
Directory /workspace/7.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.3120107161
Short name T451
Test name
Test status
Simulation time 133841618 ps
CPU time 0.77 seconds
Started Apr 21 04:05:45 PM PDT 24
Finished Apr 21 04:05:47 PM PDT 24
Peak memory 198796 kb
Host smart-e9713086-8c4c-452a-acb5-42fde9514224
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120107161 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_c
m_ctrl_config_regwen.3120107161
Directory /workspace/7.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1623436077
Short name T133
Test name
Test status
Simulation time 805752627 ps
CPU time 3.15 seconds
Started Apr 21 04:05:50 PM PDT 24
Finished Apr 21 04:05:53 PM PDT 24
Peak memory 200968 kb
Host smart-a60195cc-c624-49cd-9544-efa3c9e7a7ac
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623436077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1623436077
Directory /workspace/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.433293887
Short name T703
Test name
Test status
Simulation time 855476532 ps
CPU time 3.58 seconds
Started Apr 21 04:06:00 PM PDT 24
Finished Apr 21 04:06:04 PM PDT 24
Peak memory 200856 kb
Host smart-bcbdf616-37d8-4d79-a118-bddbdbcbcd12
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433293887 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.433293887
Directory /workspace/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.2182059628
Short name T353
Test name
Test status
Simulation time 51556037 ps
CPU time 0.89 seconds
Started Apr 21 04:05:45 PM PDT 24
Finished Apr 21 04:05:46 PM PDT 24
Peak memory 198936 kb
Host smart-da4d6e92-cbdb-46bf-ac08-b8fd16a281f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182059628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2182059628
Directory /workspace/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/7.pwrmgr_smoke.2087636296
Short name T166
Test name
Test status
Simulation time 58222603 ps
CPU time 0.67 seconds
Started Apr 21 04:06:01 PM PDT 24
Finished Apr 21 04:06:02 PM PDT 24
Peak memory 198092 kb
Host smart-fad2a446-96ba-49d9-9682-b4d10b080007
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087636296 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.2087636296
Directory /workspace/7.pwrmgr_smoke/latest


Test location /workspace/coverage/default/7.pwrmgr_stress_all.4244805058
Short name T851
Test name
Test status
Simulation time 1574910838 ps
CPU time 2.83 seconds
Started Apr 21 04:05:51 PM PDT 24
Finished Apr 21 04:05:54 PM PDT 24
Peak memory 200972 kb
Host smart-114809bf-e7d3-4bfe-b941-590dfa2ca03a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244805058 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.4244805058
Directory /workspace/7.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/7.pwrmgr_stress_all_with_rand_reset.1050283062
Short name T134
Test name
Test status
Simulation time 19544639513 ps
CPU time 27.12 seconds
Started Apr 21 04:05:50 PM PDT 24
Finished Apr 21 04:06:17 PM PDT 24
Peak memory 201016 kb
Host smart-e58892da-7242-4342-880c-4b2090ddab7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050283062 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all_with_rand_reset.1050283062
Directory /workspace/7.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/7.pwrmgr_wakeup.4221105309
Short name T490
Test name
Test status
Simulation time 165566039 ps
CPU time 0.92 seconds
Started Apr 21 04:05:44 PM PDT 24
Finished Apr 21 04:05:46 PM PDT 24
Peak memory 199204 kb
Host smart-6fca6cb9-b44b-4b54-92ed-694178e40bab
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221105309 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.4221105309
Directory /workspace/7.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/7.pwrmgr_wakeup_reset.4047828229
Short name T292
Test name
Test status
Simulation time 63362156 ps
CPU time 0.77 seconds
Started Apr 21 04:05:44 PM PDT 24
Finished Apr 21 04:05:46 PM PDT 24
Peak memory 198920 kb
Host smart-99f166d1-4667-478b-86ae-57fa7e7254ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047828229 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.4047828229
Directory /workspace/7.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/8.pwrmgr_aborted_low_power.1992316613
Short name T329
Test name
Test status
Simulation time 94803111 ps
CPU time 0.79 seconds
Started Apr 21 04:05:49 PM PDT 24
Finished Apr 21 04:05:50 PM PDT 24
Peak memory 198512 kb
Host smart-39feba5b-7598-45d2-b19b-d958de956a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992316613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.1992316613
Directory /workspace/8.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/8.pwrmgr_disable_rom_integrity_check.915700582
Short name T564
Test name
Test status
Simulation time 68851680 ps
CPU time 0.9 seconds
Started Apr 21 04:05:53 PM PDT 24
Finished Apr 21 04:05:54 PM PDT 24
Peak memory 198792 kb
Host smart-2e568feb-eb14-4297-a492-adaf3d642556
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915700582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disab
le_rom_integrity_check.915700582
Directory /workspace/8.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.531471158
Short name T531
Test name
Test status
Simulation time 38457937 ps
CPU time 0.61 seconds
Started Apr 21 04:05:49 PM PDT 24
Finished Apr 21 04:05:50 PM PDT 24
Peak memory 196984 kb
Host smart-588d8a13-642f-4bf2-9894-4cfaee296f16
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531471158 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_ma
lfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_m
alfunc.531471158
Directory /workspace/8.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/8.pwrmgr_escalation_timeout.3285992019
Short name T878
Test name
Test status
Simulation time 629607257 ps
CPU time 0.93 seconds
Started Apr 21 04:05:51 PM PDT 24
Finished Apr 21 04:05:52 PM PDT 24
Peak memory 197812 kb
Host smart-a94d5b34-083a-4ea3-908f-1219c5acfa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285992019 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.3285992019
Directory /workspace/8.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/8.pwrmgr_glitch.1559276679
Short name T17
Test name
Test status
Simulation time 54725038 ps
CPU time 0.69 seconds
Started Apr 21 04:05:54 PM PDT 24
Finished Apr 21 04:05:55 PM PDT 24
Peak memory 197064 kb
Host smart-3c5fb0bc-13c0-4915-9088-5bf68cdea519
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559276679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.1559276679
Directory /workspace/8.pwrmgr_glitch/latest


Test location /workspace/coverage/default/8.pwrmgr_global_esc.2363742371
Short name T802
Test name
Test status
Simulation time 139858764 ps
CPU time 0.62 seconds
Started Apr 21 04:05:54 PM PDT 24
Finished Apr 21 04:05:55 PM PDT 24
Peak memory 197792 kb
Host smart-6443c6bf-2b79-4ced-98da-b2c1e4033d16
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363742371 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.2363742371
Directory /workspace/8.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/8.pwrmgr_lowpower_invalid.1811508654
Short name T897
Test name
Test status
Simulation time 45093600 ps
CPU time 0.72 seconds
Started Apr 21 04:05:54 PM PDT 24
Finished Apr 21 04:05:55 PM PDT 24
Peak memory 200988 kb
Host smart-c1952364-9763-4310-9849-b3b5f29f56b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811508654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invali
d.1811508654
Directory /workspace/8.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/8.pwrmgr_lowpower_wakeup_race.1120986666
Short name T306
Test name
Test status
Simulation time 266349546 ps
CPU time 0.86 seconds
Started Apr 21 04:05:50 PM PDT 24
Finished Apr 21 04:05:51 PM PDT 24
Peak memory 198188 kb
Host smart-0b6eabfd-79a8-46ae-90d6-061bb3fd758e
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120986666 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wake
up_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wa
keup_race.1120986666
Directory /workspace/8.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/8.pwrmgr_reset.2280010842
Short name T819
Test name
Test status
Simulation time 152542484 ps
CPU time 0.78 seconds
Started Apr 21 04:05:53 PM PDT 24
Finished Apr 21 04:05:54 PM PDT 24
Peak memory 198856 kb
Host smart-ac779856-2a33-41a1-9122-051c79a7af11
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280010842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.2280010842
Directory /workspace/8.pwrmgr_reset/latest


Test location /workspace/coverage/default/8.pwrmgr_reset_invalid.1595599829
Short name T733
Test name
Test status
Simulation time 158817389 ps
CPU time 0.82 seconds
Started Apr 21 04:05:57 PM PDT 24
Finished Apr 21 04:05:58 PM PDT 24
Peak memory 209048 kb
Host smart-17fa17a8-f22c-420f-80f6-4a706fb31084
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595599829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.1595599829
Directory /workspace/8.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.1274348707
Short name T339
Test name
Test status
Simulation time 302811442 ps
CPU time 1.54 seconds
Started Apr 21 04:05:54 PM PDT 24
Finished Apr 21 04:05:56 PM PDT 24
Peak memory 200636 kb
Host smart-8571bc5e-7d56-4027-b83b-d106cbc2509e
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274348707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_c
m_ctrl_config_regwen.1274348707
Directory /workspace/8.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3805419923
Short name T919
Test name
Test status
Simulation time 829259206 ps
CPU time 2.98 seconds
Started Apr 21 04:05:51 PM PDT 24
Finished Apr 21 04:05:54 PM PDT 24
Peak memory 200896 kb
Host smart-f912f46e-4d1a-42a4-9b9a-b0e974f8a747
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805419923 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3805419923
Directory /workspace/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4167483521
Short name T97
Test name
Test status
Simulation time 892635103 ps
CPU time 2.26 seconds
Started Apr 21 04:05:53 PM PDT 24
Finished Apr 21 04:05:55 PM PDT 24
Peak memory 200964 kb
Host smart-68f331a0-30fe-4237-8109-dde15900fd1e
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167483521 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4167483521
Directory /workspace/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.2630860830
Short name T522
Test name
Test status
Simulation time 260405472 ps
CPU time 0.85 seconds
Started Apr 21 04:05:49 PM PDT 24
Finished Apr 21 04:05:51 PM PDT 24
Peak memory 198696 kb
Host smart-06594b10-8097-4c26-a5bc-56733c710612
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630860830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2630860830
Directory /workspace/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/8.pwrmgr_smoke.2111563209
Short name T575
Test name
Test status
Simulation time 42489470 ps
CPU time 0.63 seconds
Started Apr 21 04:05:46 PM PDT 24
Finished Apr 21 04:05:48 PM PDT 24
Peak memory 198088 kb
Host smart-4e173d01-783c-4add-a253-73a7fb2efd88
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111563209 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.2111563209
Directory /workspace/8.pwrmgr_smoke/latest


Test location /workspace/coverage/default/8.pwrmgr_stress_all.2609384948
Short name T201
Test name
Test status
Simulation time 302722936 ps
CPU time 1.82 seconds
Started Apr 21 04:05:51 PM PDT 24
Finished Apr 21 04:05:53 PM PDT 24
Peak memory 200888 kb
Host smart-f3727f89-d921-4346-9883-714d30eaf166
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609384948 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all.2609384948
Directory /workspace/8.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/8.pwrmgr_stress_all_with_rand_reset.2814959661
Short name T89
Test name
Test status
Simulation time 20330576411 ps
CPU time 24.88 seconds
Started Apr 21 04:05:52 PM PDT 24
Finished Apr 21 04:06:17 PM PDT 24
Peak memory 201076 kb
Host smart-1fd67888-df7a-4a31-ac3c-3c64bc68b17a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814959661 -assert nopos
tproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all_with_rand_reset.2814959661
Directory /workspace/8.pwrmgr_stress_all_with_rand_reset/latest


Test location /workspace/coverage/default/8.pwrmgr_wakeup.2420984297
Short name T645
Test name
Test status
Simulation time 254121376 ps
CPU time 0.89 seconds
Started Apr 21 04:05:50 PM PDT 24
Finished Apr 21 04:05:52 PM PDT 24
Peak memory 198772 kb
Host smart-9ba6d374-ca8e-41a7-bdde-41d2281c3fe6
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420984297 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.2420984297
Directory /workspace/8.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/8.pwrmgr_wakeup_reset.297856792
Short name T644
Test name
Test status
Simulation time 92292049 ps
CPU time 0.88 seconds
Started Apr 21 04:05:50 PM PDT 24
Finished Apr 21 04:05:51 PM PDT 24
Peak memory 198724 kb
Host smart-a338b7a5-e648-4198-885b-a1c8e0c1676d
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297856792 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.297856792
Directory /workspace/8.pwrmgr_wakeup_reset/latest


Test location /workspace/coverage/default/9.pwrmgr_aborted_low_power.2979076690
Short name T127
Test name
Test status
Simulation time 55920608 ps
CPU time 0.83 seconds
Started Apr 21 04:05:54 PM PDT 24
Finished Apr 21 04:05:55 PM PDT 24
Peak memory 199664 kb
Host smart-3e7a864b-e11c-4c6b-865c-3fb313a1a3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979076690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.2979076690
Directory /workspace/9.pwrmgr_aborted_low_power/latest


Test location /workspace/coverage/default/9.pwrmgr_disable_rom_integrity_check.317500251
Short name T46
Test name
Test status
Simulation time 68711239 ps
CPU time 0.74 seconds
Started Apr 21 04:05:58 PM PDT 24
Finished Apr 21 04:05:59 PM PDT 24
Peak memory 198792 kb
Host smart-4342dc53-bd93-48a2-a2d2-16d3fa957141
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317500251 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_in
tegrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disab
le_rom_integrity_check.317500251
Directory /workspace/9.pwrmgr_disable_rom_integrity_check/latest


Test location /workspace/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.1126200386
Short name T979
Test name
Test status
Simulation time 39029116 ps
CPU time 0.59 seconds
Started Apr 21 04:05:53 PM PDT 24
Finished Apr 21 04:05:54 PM PDT 24
Peak memory 197740 kb
Host smart-a99de4fc-f960-41d2-bb76-e0c370c0d6d2
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126200386 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_m
alfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_
malfunc.1126200386
Directory /workspace/9.pwrmgr_esc_clk_rst_malfunc/latest


Test location /workspace/coverage/default/9.pwrmgr_escalation_timeout.539648895
Short name T542
Test name
Test status
Simulation time 168470174 ps
CPU time 1 seconds
Started Apr 21 04:05:53 PM PDT 24
Finished Apr 21 04:05:54 PM PDT 24
Peak memory 197748 kb
Host smart-21ffad0e-4372-4076-a5ba-d7c5aa98d0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539648895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.539648895
Directory /workspace/9.pwrmgr_escalation_timeout/latest


Test location /workspace/coverage/default/9.pwrmgr_glitch.2004406370
Short name T683
Test name
Test status
Simulation time 58334291 ps
CPU time 0.72 seconds
Started Apr 21 04:05:58 PM PDT 24
Finished Apr 21 04:06:00 PM PDT 24
Peak memory 197788 kb
Host smart-fc844163-843d-487f-9294-605770359bbd
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004406370 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.2004406370
Directory /workspace/9.pwrmgr_glitch/latest


Test location /workspace/coverage/default/9.pwrmgr_global_esc.774069336
Short name T717
Test name
Test status
Simulation time 51930229 ps
CPU time 0.67 seconds
Started Apr 21 04:05:57 PM PDT 24
Finished Apr 21 04:05:58 PM PDT 24
Peak memory 197720 kb
Host smart-5f3f15c3-71e5-4aad-aa96-77fe434d95bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774069336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.774069336
Directory /workspace/9.pwrmgr_global_esc/latest


Test location /workspace/coverage/default/9.pwrmgr_lowpower_invalid.1472493549
Short name T589
Test name
Test status
Simulation time 41043794 ps
CPU time 0.76 seconds
Started Apr 21 04:05:54 PM PDT 24
Finished Apr 21 04:05:55 PM PDT 24
Peak memory 201020 kb
Host smart-c1ca983e-2aeb-4430-8696-a5b47ece8250
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472493549 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_inva
lid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invali
d.1472493549
Directory /workspace/9.pwrmgr_lowpower_invalid/latest


Test location /workspace/coverage/default/9.pwrmgr_lowpower_wakeup_race.216353372
Short name T769
Test name
Test status
Simulation time 322200411 ps
CPU time 1.22 seconds
Started Apr 21 04:05:51 PM PDT 24
Finished Apr 21 04:05:53 PM PDT 24
Peak memory 199240 kb
Host smart-44420d52-c481-42eb-80af-75de5db20c43
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216353372 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeu
p_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wak
eup_race.216353372
Directory /workspace/9.pwrmgr_lowpower_wakeup_race/latest


Test location /workspace/coverage/default/9.pwrmgr_reset.2379957582
Short name T172
Test name
Test status
Simulation time 44472972 ps
CPU time 0.84 seconds
Started Apr 21 04:05:52 PM PDT 24
Finished Apr 21 04:05:53 PM PDT 24
Peak memory 198880 kb
Host smart-0b1a0015-97d1-405e-bc5b-0b6d41282d89
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379957582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.2379957582
Directory /workspace/9.pwrmgr_reset/latest


Test location /workspace/coverage/default/9.pwrmgr_reset_invalid.4035724922
Short name T501
Test name
Test status
Simulation time 124373446 ps
CPU time 0.89 seconds
Started Apr 21 04:05:55 PM PDT 24
Finished Apr 21 04:05:56 PM PDT 24
Peak memory 209056 kb
Host smart-0bc47f3f-a275-44fc-894e-cc639b12a59c
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035724922 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.4035724922
Directory /workspace/9.pwrmgr_reset_invalid/latest


Test location /workspace/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.1262754216
Short name T513
Test name
Test status
Simulation time 330604699 ps
CPU time 1.25 seconds
Started Apr 21 04:05:56 PM PDT 24
Finished Apr 21 04:05:58 PM PDT 24
Peak memory 200652 kb
Host smart-f0d3e62b-47ef-4890-87c2-04fce8f314de
User root
Command /workspace/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262754216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_
config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_c
m_ctrl_config_regwen.1262754216
Directory /workspace/9.pwrmgr_sec_cm_ctrl_config_regwen/latest


Test location /workspace/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3101221571
Short name T380
Test name
Test status
Simulation time 965394882 ps
CPU time 2.82 seconds
Started Apr 21 04:05:53 PM PDT 24
Finished Apr 21 04:05:57 PM PDT 24
Peak memory 200816 kb
Host smart-d9895d1e-1d9b-4654-9ab5-ee1d967178e6
User root
Command /workspace/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101221571 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test
+UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3101221571
Directory /workspace/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3799756560
Short name T276
Test name
Test status
Simulation time 935198302 ps
CPU time 3.54 seconds
Started Apr 21 04:05:52 PM PDT 24
Finished Apr 21 04:05:56 PM PDT 24
Peak memory 200956 kb
Host smart-2f357fea-d295-420b-ae5a-f526c1b1c66f
User root
Command /workspace/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799756560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_tes
t +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3799756560
Directory /workspace/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest


Test location /workspace/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2395312675
Short name T221
Test name
Test status
Simulation time 67453077 ps
CPU time 0.96 seconds
Started Apr 21 04:05:55 PM PDT 24
Finished Apr 21 04:05:56 PM PDT 24
Peak memory 198948 kb
Host smart-1fa55da0-6a99-42a4-8e9a-b44a045a7522
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395312675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_
mubi.2395312675
Directory /workspace/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest


Test location /workspace/coverage/default/9.pwrmgr_smoke.2122681174
Short name T394
Test name
Test status
Simulation time 54474347 ps
CPU time 0.71 seconds
Started Apr 21 04:05:54 PM PDT 24
Finished Apr 21 04:05:55 PM PDT 24
Peak memory 198996 kb
Host smart-86ee695a-77eb-400f-9865-c11bf7cab604
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122681174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.2122681174
Directory /workspace/9.pwrmgr_smoke/latest


Test location /workspace/coverage/default/9.pwrmgr_stress_all.2553816721
Short name T405
Test name
Test status
Simulation time 925436626 ps
CPU time 3.68 seconds
Started Apr 21 04:05:59 PM PDT 24
Finished Apr 21 04:06:03 PM PDT 24
Peak memory 200996 kb
Host smart-6128bc56-6726-4528-9095-54b9a05eb7f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553816721 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.2553816721
Directory /workspace/9.pwrmgr_stress_all/latest


Test location /workspace/coverage/default/9.pwrmgr_wakeup.1131639185
Short name T474
Test name
Test status
Simulation time 183291762 ps
CPU time 0.85 seconds
Started Apr 21 04:05:52 PM PDT 24
Finished Apr 21 04:05:54 PM PDT 24
Peak memory 198252 kb
Host smart-789cfee8-0129-4827-818e-63f1c75b5469
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131639185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.1131639185
Directory /workspace/9.pwrmgr_wakeup/latest


Test location /workspace/coverage/default/9.pwrmgr_wakeup_reset.3712099886
Short name T459
Test name
Test status
Simulation time 88554725 ps
CPU time 0.83 seconds
Started Apr 21 04:05:52 PM PDT 24
Finished Apr 21 04:05:53 PM PDT 24
Peak memory 198720 kb
Host smart-d68ba983-13ad-4b14-b9e3-946996f48dea
User root
Command /workspace/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712099886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.3712099886
Directory /workspace/9.pwrmgr_wakeup_reset/latest
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