Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	64	0	64	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
core_cp	2	0	2	100.00	100	1	1	2
io_cp	2	0	2	100.00	100	1	1	2
main_pd_n_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2
usb_active_cp	2	0	2	100.00	100	1	1	2
usb_lp_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
control_cross	64	0	64	100.00	100	1	1	0

Summary for Variable core_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for core_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26484

1

T1

2

T2

16

T3

54

auto[1]

25388

1

T2

18

T3

46

T4

8

---

Summary for Variable io_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for io_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26725

1

T1

2

T2

20

T3

52

auto[1]

25147

1

T2

14

T3

48

T4

2

---

Summary for Variable main_pd_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for main_pd_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25672

1

T2

14

T3

40

T4

4

auto[1]

26200

1

T1

2

T2

20

T3

60

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29640

1

T1

1

T2

28

T3

50

auto[1]

22232

1

T1

1

T2

6

T3

50

---

Summary for Variable usb_active_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_active_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25608

1

T2

16

T3

48

T4

6

auto[1]

26264

1

T1

2

T2

18

T3

52

---

Summary for Variable usb_lp_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for usb_lp_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26536

1

T1

2

T2

21

T3

36

auto[1]

25336

1

T2

13

T3

64

T4

4

---

Summary for Cross control_cross

Samples crossed: core_cp io_cp usb_lp_cp usb_active_cp main_pd_n_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for control_cross

Bins

core_cp

io_cp

usb_lp_cp

usb_active_cp

main_pd_n_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

932

1

T2

1

T6

3

T9

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

700

1

T6

3

T9

1

T37

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

897

1

T2

1

T3

2

T6

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

658

1

T2

1

T3

2

T6

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

918

1

T3

1

T6

1

T9

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

679

1

T3

1

T6

1

T9

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1445

1

T1

1

T2

2

T6

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

1215

1

T1

1

T6

1

T9

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

860

1

T2

1

T6

1

T9

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

658

1

T6

1

T9

1

T38

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

894

1

T3

5

T4

1

T6

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

687

1

T3

5

T4

1

T6

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

926

1

T3

3

T6

2

T37

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

697

1

T3

3

T6

2

T37

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

928

1

T2

2

T3

4

T6

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

710

1

T3

4

T6

2

T36

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

916

1

T3

1

T6

1

T9

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

692

1

T3

1

T6

1

T9

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

928

1

T3

2

T6

2

T36

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

668

1

T3

2

T6

2

T36

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

874

1

T2

1

T3

2

T6

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

674

1

T3

2

T6

1

T14

15

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

894

1

T2

1

T3

1

T9

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

667

1

T2

1

T3

1

T9

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

905

1

T38

1

T39

1

T56

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

678

1

T38

1

T39

1

T56

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

904

1

T2

1

T3

4

T6

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

668

1

T3

4

T6

1

T9

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

974

1

T2

1

T3

1

T36

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

715

1

T3

1

T36

1

T37

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

885

1

T2

3

T3

1

T6

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

638

1

T3

1

T6

3

T9

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

952

1

T2

2

T3

1

T6

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

715

1

T2

1

T3

1

T6

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

977

1

T2

2

T3

2

T4

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

727

1

T3

2

T4

1

T6

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

927

1

T2

2

T4

1

T6

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

690

1

T2

1

T4

1

T6

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

895

1

T2

1

T3

1

T4

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

657

1

T2

1

T3

1

T4

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

979

1

T2

1

T6

1

T38

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

724

1

T6

1

T38

1

T39

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

888

1

T6

3

T36

2

T38

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

673

1

T6

3

T36

2

T38

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

909

1

T2

1

T3

3

T6

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

692

1

T3

3

T6

1

T9

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

878

1

T3

4

T6

2

T39

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

638

1

T3

4

T6

2

T39

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

918

1

T2

1

T3

3

T6

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

697

1

T3

3

T6

2

T36

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

900

1

T2

1

T37

1

T38

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

671

1

T2

1

T37

1

T38

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

901

1

T3

1

T6

4

T37

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

665

1

T3

1

T6

4

T37

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

855

1

T3

1

T6

3

T9

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

632

1

T3

1

T6

3

T9

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

880

1

T2

1

T3

2

T4

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

658

1

T3

2

T4

1

T6

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

920

1

T2

1

T3

2

T6

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

684

1

T3

2

T6

1

T9

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

895

1

T3

2

T6

4

T9

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

672

1

T3

2

T6

4

T9

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

886

1

T2

1

T3

1

T6

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

633

1

T3

1

T6

1

T9

1