Unified Coverage Report :: Group :: pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg

Group : pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_env_0.1/pwrmgr_env_cov.sv

---

Summary for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00
Crosses	6	0	6	100.00

Variables for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_cp	2	0	2	100.00	100	1	1	2
sleep_cp	2	0	2	100.00	100	1	1	2

Crosses for Group pwrmgr_env_pkg::pwrmgr_env_cov::hw_reset_1_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
reset_cross	6	0	6	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13923

1

T3

33

T4

4

T6

44

auto[1]

20776

1

T1

1

T3

55

T4

6

---

Summary for Variable reset_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for reset_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29376

1

T1

1

T2

6

T3

69

auto[1]

7871

1

T1

1

T3

19

T4

3

---

Summary for Variable sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sleep_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15126

1

T1

1

T3

38

T4

5

auto[1]

22121

1

T1

1

T2

6

T3

50

---

Summary for Cross reset_cross

Samples crossed: reset_cp enable_cp sleep_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	6	0	6	100.00
Automatically Generated Cross Bins	6	0	6	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for reset_cross

Bins

reset_cp

enable_cp

sleep_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

3404

1

T3

10

T4

1

T6

9

auto[0]

auto[0]

auto[1]

7882

1

T3

21

T4

2

T6

27

auto[0]

auto[1]

auto[0]

3592

1

T3

9

T4

1

T6

3

auto[0]

auto[1]

auto[1]

11950

1

T3

29

T4

3

T6

23

auto[1]

auto[0]

auto[0]

2637

1

T3

2

T4

1

T6

8

auto[1]

auto[1]

auto[0]

5234

1

T1

1

T3

17

T4

2

User Defined Cross Bins for reset_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
illegal	0	Illegal